WO2012105740A1 - Tap tape for electronic devices with reinforced lead crack and method of manufacturing the same - Google Patents

Tap tape for electronic devices with reinforced lead crack and method of manufacturing the same Download PDF

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Publication number
WO2012105740A1
WO2012105740A1 PCT/KR2011/007580 KR2011007580W WO2012105740A1 WO 2012105740 A1 WO2012105740 A1 WO 2012105740A1 KR 2011007580 W KR2011007580 W KR 2011007580W WO 2012105740 A1 WO2012105740 A1 WO 2012105740A1
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WO
WIPO (PCT)
Prior art keywords
lead
electronic devices
tap tape
pattern
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2011/007580
Other languages
French (fr)
Inventor
Dae Sung Yoo
Han Mo Koo
Jun Young Lim
Ki Tae Park
Tae Ki Hong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Priority to JP2013551886A priority Critical patent/JP6109078B2/en
Priority to CN201180066521.1A priority patent/CN103348460B/en
Priority to US13/982,658 priority patent/US20130308289A1/en
Publication of WO2012105740A1 publication Critical patent/WO2012105740A1/en
Anticipated expiration legal-status Critical
Priority to US15/153,970 priority patent/US10020248B2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H10W70/24—Conductive package substrates serving as an interconnection, e.g. metal plates characterised by materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/453—Leadframes comprising flexible metallic tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/456—Materials
    • H10W70/457—Materials of metallic layers on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/124—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed the encapsulations having cavities other than that occupied by chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/077—Connecting of TAB connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors

Definitions

  • the present invention relates to a tap tape for electronic components with reinforced lead crack and a method of manufacturing the tap tape.
  • a tape carrier film has been widely used, on which wiring patterns are formed on a thin film tape material as a wiring substrate used for mounting semiconductor chips.
  • a semiconductor chip is mounted on a tape carrier film and packaged, and it refers to as a tape carrier package (TCP).
  • TCP tape carrier package
  • TAB tape automated bonding
  • a wiring pattern connected from an inner lead to an outer lead has a narrow wiring width and thus cracks are formed due to a weak bending property.
  • the technical problem to be solved by the present invention relates to provide a tap tape for electronic devices and a method of manufacturing the tap tape in which with respect to a connecting configuration, by forming a cut- part (hereinafter, refer to as cutting portion ) on a narrow circuit pattern and forming the cutting portion within a resin application portion and without being a bending portion, lead crack problem may be solved.
  • cutting portion a cut- part
  • the technical solutions are solved by forming a cutting portion on a narrow circuit pattern to be connected from a first lead to a second lead and forming the cutting portion within a resin application portion and without being a bending portion, crack occurred on a narrow wiring width can be solved.
  • a cutting portion is formed on a circuit pattern to be connected from the first lead to the second lead of a dielectric substrate wherein at least one or more of portions of different intervals between lead patterns are provided.
  • FIG. 1 is a partly exploded plain view of a wiring pattern of a tap tape according to an embodiment of the present invention.
  • FIG. 2 is a partly exploded plain view of the wiring pattern as shown in FIG. 1.
  • FIG. 1 is a partly exploded plain view of a wiring pattern of a tap tape according to an embodiment of the present invention
  • FIG. 2 is a partly exploded plain view of the wiring pattern as shown in FIG. 1.
  • a tap tape according to the present invention may include a first lead 121 and a second lead 122 formed on a dielectric substrate 110, and a cutting portion 140 formed on one of the first lead and the second lead.
  • the cutting portion 140 according to the present invention refers to as a cutting-form connecting pattern (143 in FIG. 2) on a connecting portion of the first lead 121 and the second lead 122.
  • the dielectric substrate 110 may use a base film formed with dielectric material such as polyimide resin.
  • a tap tape according to the present invention may include a portion for a chip to be mounted and a resin application portion 130 for burying an electronic device chip.
  • the cutting portion 140 according to the present invention may be arranged on the resin application portion.
  • FIGS. 1 and 2 Further, detailed configurations of the tap tape according to the present invention will be described, referring to FIGS. 1 and 2.
  • a conductive thin film such as cupper foil may be formed on a dielectric substrate 110 and then a wiring pattern may be formed using a photo etching.
  • a plurality of sprocket holes 111 may be formed at a predetermined distance on both edges of the dielectric substrate 110.
  • the wiring pattern 120 may include a second lead 122 to be connected electrically to a semiconductor chip using an inner lead bonding (ILB), a first lead 121 for connecting electrically to a terminal outside the substrate, and a connection portion 123 formed as a connecting pattern for connection the first lead 121 and the second lead 122.
  • ILB inner lead bonding
  • the second lead 122 is formed to have relatively narrow width in a consideration of being connected to connecting terminals of a fine pitch of a semiconductor chip and the first lead 121 is formed to have a relatively wide width in a consideration of being connected to a terminal outside a substrate, not corresponding directly to fine pitches of a semiconductor chip.
  • the connecting portion 123 may be formed as a cut-form to have a predetermined length for connecting the second lead 122 having a narrow width and the first leads 121 having a wide width.
  • the second lead 122 may be formed as a wiring pattern to be connected from an inner lead to an outer lead, having a narrow wiring width. Accordingly, in a case where the wiring pattern is formed straightly for connecting directly the first lead and the second lead, as in the prior art, a bending property may be weak and thereby creating cracks.
  • the crack problem may be solved or avoided.
  • a second lead pattern 142 formed to have relatively narrower width than that of a first lead pattern 141, a first lead pattern 141 formed to have relatively wider width than that of the second lead pattern 142 and a connection pattern 143 for connecting a portion between the first lead pattern 141 and the second lead pattern 142 as a cutting form based on the cutting portion 140 are provided.
  • the cutting portion 140 may be formed within the resin application portion 130 and without being a bending portion.
  • the cutting portion By forming the cutting portion in a place where a wiring width is relatively narrower than other places, that is, a circuit pattern of the second lead 122 to be connected from the first lead (for example, inner lead) to the second lead (for example, outer lead), and forming it within the resin application portion after an IC bonding, and designing a lead wiring pattern of two times as an existing lead wiring pattern in a case of an outer part of the resin application portion not to be IC bonded, lead crack can be avoided.
  • a circuit pattern can be protected and conductivity of the lead wiring pattern can be improved.
  • FIGS. 1 and 2 a manufacturing method of a tap tape for electronic devices will be described.
  • a conductive thin film may be formed on one surface of a dielectric substrate 110.
  • the conductive thin film may be formed as a sputtered-metal layer on a whole surface of the dielectric film.
  • the metal layer may be formed by sputtering one of Cu, Ni, Pd, Au, Sn, Ag, Co.
  • a plating treatment layer may be further formed as a single layer or multi layer using one, binary alloy or ternary alloy of Cu, Ni, Pd, Au, Sn, Ag, Co.
  • a wiring pattern may be formed by etching selectively the conductive thin film wherein a cutting portion 140 may be formed on a circuit pattern to be connected from the firs lead (inner lead) to the second lead (outer lead), having relatively a narrow wiring width.
  • the circuit pattern may be separated into the first lead pattern 141 and the second lead pattern 142, based on the cutting portion 140, and may include a connecting pattern for cutting and connecting a portion between the first and second leads 141, 142, based on the cutting portion 140.
  • a wiring width of the first lead pattern 141 may be wider than that of the second lead pattern 142.
  • the cutting portion 140 may be formed within the resin application portion and without being a bending portion.
  • a tap tape for electronic devices and a method of the tap tape of the present invention by forming a cutting portion on a narrow circuit pattern to be connected from a first lead to a second lead and forming the cutting portion within a resin application portion and without being a bending portion, the technical object of the present invention can be achieved.
  • the tap tape according to the present invention may be packaged by applying resin on an electronic device chip to be mounted within the resin application portion 130.
  • the resin to be applied on the resin application portion 130 may be potting material having viscosity, comprising epoxy, epoxy resin, curing material, or inorganic filler.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)

Abstract

Provided is a tap tape for electronic devices with lead crack and a method of manufacturing the tap tape. According to the present invention, by forming a cutting portion on a narrow circuit pattern to be connected from an inner lead to an outer lead and further forming the cutting portion within a resin application portion and without being a bending portion, crack occurred in a narrow wiring width can be avoided. The tap tape may includes a first lead and a second lead formed on a dielectric substrate and a cutting portion formed on one of the first lead and the second lead wherein the cutting portion is formed within a resin application portion.

Description

TAP TAPE FOR ELECTRONIC DEVICES WITH REINFORCED LEAD CRACK AND METHOD OF MANUFACTURING THE SAME
The present invention relates to a tap tape for electronic components with reinforced lead crack and a method of manufacturing the tap tape.
Recently, in a technical field of a semiconductor device, there have been trends of thinning, miniaturizing, high-integrating, high-speeding and multi-pinning. For these objects, a tape carrier film has been widely used, on which wiring patterns are formed on a thin film tape material as a wiring substrate used for mounting semiconductor chips.
A semiconductor chip is mounted on a tape carrier film and packaged, and it refers to as a tape carrier package (TCP). In a case where the tape carrier package is manufactured using a tape carrier film, it is possible to use a technology of tape automated bonding (TAB) when connecting consistently a semiconductor chip and a lead on the tape carrier film, and thus it refers to as a tap tape.
In a prior tap tape for electronic components, a wiring pattern connected from an inner lead to an outer lead has a narrow wiring width and thus cracks are formed due to a weak bending property.
The technical problem to be solved by the present invention relates to provide a tap tape for electronic devices and a method of manufacturing the tap tape in which with respect to a connecting configuration, by forming a cut- part (hereinafter, refer to as cutting portion ) on a narrow circuit pattern and forming the cutting portion within a resin application portion and without being a bending portion, lead crack problem may be solved.
The technical solutions are solved by forming a cutting portion on a narrow circuit pattern to be connected from a first lead to a second lead and forming the cutting portion within a resin application portion and without being a bending portion, crack occurred on a narrow wiring width can be solved.
In addition, a cutting portion is formed on a circuit pattern to be connected from the first lead to the second lead of a dielectric substrate wherein at least one or more of portions of different intervals between lead patterns are provided.
According to the present invention, by forming a cutting portion on a narrow circuit pattern to be connected from a first lead to a second lead and forming the cutting portion within a resin application portion and without being a bending portion, crack occurred on a narrow wiring width can be solved.
The technical advantageous effects are not limited thereto and it has to be understood that other effects not set forth in the forgoing are obvious to a person who has ordinary skill in the art.
The above and other aspects, features and advantages of certain exemplary embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a partly exploded plain view of a wiring pattern of a tap tape according to an embodiment of the present invention; and
FIG. 2 is a partly exploded plain view of the wiring pattern as shown in FIG. 1.
<Reference Numerals>
110: base film
111: sprocket hole
120: wiring pattern
121: first lead
122: second lead
123: connecting portion
130: resin application portion
140: cutting portion (pattern inflection point formation portion)
141: first lead pattern
142: second lead pattern
143: connecting pattern
Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used to refer to the same elements throughout the specification, and a duplicated description thereof will be omitted. It will be understood that although the terms first , second , etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.
FIG. 1 is a partly exploded plain view of a wiring pattern of a tap tape according to an embodiment of the present invention, and FIG. 2 is a partly exploded plain view of the wiring pattern as shown in FIG. 1.
A tap tape according to the present invention, as shown FIG. 1, may include a first lead 121 and a second lead 122 formed on a dielectric substrate 110, and a cutting portion 140 formed on one of the first lead and the second lead. The cutting portion 140 according to the present invention refers to as a cutting-form connecting pattern (143 in FIG. 2) on a connecting portion of the first lead 121 and the second lead 122. The dielectric substrate 110 may use a base film formed with dielectric material such as polyimide resin.
Furthermore, referring to a partly exploded a wiring pattern 120 as shown in FIG. 1, a tap tape according to the present invention may include a portion for a chip to be mounted and a resin application portion 130 for burying an electronic device chip. Specially, the cutting portion 140 according to the present invention may be arranged on the resin application portion.
Further, detailed configurations of the tap tape according to the present invention will be described, referring to FIGS. 1 and 2.
A conductive thin film such as cupper foil may be formed on a dielectric substrate 110 and then a wiring pattern may be formed using a photo etching. Here, a plurality of sprocket holes 111 may be formed at a predetermined distance on both edges of the dielectric substrate 110.
Meanwhile, the wiring pattern 120 may include a second lead 122 to be connected electrically to a semiconductor chip using an inner lead bonding (ILB), a first lead 121 for connecting electrically to a terminal outside the substrate, and a connection portion 123 formed as a connecting pattern for connection the first lead 121 and the second lead 122.
Additionally, the second lead 122 is formed to have relatively narrow width in a consideration of being connected to connecting terminals of a fine pitch of a semiconductor chip and the first lead 121 is formed to have a relatively wide width in a consideration of being connected to a terminal outside a substrate, not corresponding directly to fine pitches of a semiconductor chip. The connecting portion 123 may be formed as a cut-form to have a predetermined length for connecting the second lead 122 having a narrow width and the first leads 121 having a wide width.
Here, the second lead 122 may be formed as a wiring pattern to be connected from an inner lead to an outer lead, having a narrow wiring width. Accordingly, in a case where the wiring pattern is formed straightly for connecting directly the first lead and the second lead, as in the prior art, a bending property may be weak and thereby creating cracks.
In order to solve this drawback, in the present invention, by forming the cutting portion 140 on a circuit pattern of the second lead 122 to widen a wiring width and by forming the cutting portion 140 within the resin application portion 130 and without being a bending portion, the crack problem may be solved or avoided.
In more detailed description of the circuit pattern of the second lead 122, as shown in FIG. 2, a second lead pattern 142 formed to have relatively narrower width than that of a first lead pattern 141, a first lead pattern 141 formed to have relatively wider width than that of the second lead pattern 142 and a connection pattern 143 for connecting a portion between the first lead pattern 141 and the second lead pattern 142 as a cutting form based on the cutting portion 140 are provided. At this time, the cutting portion 140 may be formed within the resin application portion 130 and without being a bending portion.
By forming the cutting portion in a place where a wiring width is relatively narrower than other places, that is, a circuit pattern of the second lead 122 to be connected from the first lead (for example, inner lead) to the second lead (for example, outer lead), and forming it within the resin application portion after an IC bonding, and designing a lead wiring pattern of two times as an existing lead wiring pattern in a case of an outer part of the resin application portion not to be IC bonded, lead crack can be avoided.
Furthermore, by forming further a plating treatment layer as a single layer or multi layer on a circuit pattern surface of the first lead and the second lead, using one, binary alloy or ternary alloy of Cu, Ni, Pd, Au, Sn, Ag, Co, a circuit pattern can be protected and conductivity of the lead wiring pattern can be improved.
-Manufacturing method of a tap tape for electronic devices
Referring to FIGS. 1 and 2, a manufacturing method of a tap tape for electronic devices will be described.
First, a conductive thin film may be formed on one surface of a dielectric substrate 110. At this time, the conductive thin film may be formed as a sputtered-metal layer on a whole surface of the dielectric film. The metal layer may be formed by sputtering one of Cu, Ni, Pd, Au, Sn, Ag, Co. Further, a plating treatment layer may be further formed as a single layer or multi layer using one, binary alloy or ternary alloy of Cu, Ni, Pd, Au, Sn, Ag, Co.
Next, a wiring pattern may be formed by etching selectively the conductive thin film wherein a cutting portion 140 may be formed on a circuit pattern to be connected from the firs lead (inner lead) to the second lead (outer lead), having relatively a narrow wiring width.
Here, the circuit pattern may be separated into the first lead pattern 141 and the second lead pattern 142, based on the cutting portion 140, and may include a connecting pattern for cutting and connecting a portion between the first and second leads 141, 142, based on the cutting portion 140. At this time, a wiring width of the first lead pattern 141 may be wider than that of the second lead pattern 142. The cutting portion 140 may be formed within the resin application portion and without being a bending portion.
According to a tap tape for electronic devices and a method of the tap tape of the present invention, by forming a cutting portion on a narrow circuit pattern to be connected from a first lead to a second lead and forming the cutting portion within a resin application portion and without being a bending portion, the technical object of the present invention can be achieved.
The tap tape according to the present invention may be packaged by applying resin on an electronic device chip to be mounted within the resin application portion 130. The resin to be applied on the resin application portion 130 may be potting material having viscosity, comprising epoxy, epoxy resin, curing material, or inorganic filler.
While the invention has been shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the scope of the invention is defined not by the detailed description of the invention but by the appended claims, and all differences within the scope will be construed as being included in the present invention.

Claims (18)

  1. A tap tape for electronic devices:
    A first lead and a second lead formed on a dielectric substrate; and
    cutting portion formed on one of the first lead and the second lead.
  2. The tap tape for electronic devices of claim 1, wherein the cutting portion is formed on a connecting portion of the first lead and the second lead.
  3. The tap tape for electronic devices of claim 2, wherein at least one or more of different intervals between patterns are provided in the first lead and the second lead.
  4. The tap tape for electronic devices of claim 2, wherein a resin application portion corresponding to a chip mounting portion to be formed on the dielectric substrate is provided and the cutting portion is included in the resin application portion.
  5. The tap tape for electronic devices of claim 4, wherein the cutting portion comprises a connecting pattern for connecting the fist lead and the second lead as a cutting-form.
  6. The tap tape for electronic devices of claim 5, wherein in the first lead and the second lead a pattern width of the first lead is wider than that of the second lead.
  7. The tap tape for electronic devices of claim 6, wherein the tap tape for electronic devices further comprises an electronic device chip to be mounted on the chip mounting portion and resin to be applied for burying a circumference of the electronic devices in the resin application portion.
  8. The tap tape for electronic devices of claim 7, wherein the dielectric substrate is polyimide film.
  9. The tap tape for electronic devices of claim 8, wherein the resin comprises epoxy.
  10. The tap tape for electronic devices of claim 8, wherein a plating treatment layer as a single layer or multi layer is formed further on the circuit pattern surface of the first lead and the second lead, using one, binary alloy or ternary alloy of Cu, Ni, Pd, Au, Sn, Ag, Co.
  11. A method of manufacturing a tap tape for electronic devices, comprising:
    forming a conductive thin film on one surface of a dielectric film;
    etching selectively the conductive thin film to form a wiring pattern; and
    forming a cutting portion on a connecting portion to be connected from the first lead to the second lead.
  12. The method of manufacturing a tap tape for electronic devices of claim 11, wherein the forming a cutting portion comprises etching selectively a conductive thin film and forming a connecting pattern for connecting the first lead and the second lead as a cutting-form.
  13. The method of manufacturing a tap tape for electronic devices of claim 12, wherein the forming a cutting portion comprises patterning the connecting portion for the connecting pattern to be included in the resin application portion for resin to be applied on which an electronic device is mounted.
  14. The method of manufacturing a tap tape for electronic devices of claim 12, wherein the etching selectively a conductive thin film to form a wiring pattern comprises forming a wiring width of the first lead pattern to be wider than that of the second lead pattern, based on the cutting portion.
  15. The method of manufacturing a tap tape for electronic devices of claim 14, wherein the etching selectively a conductive thin film to form a wiring pattern comprises applying photo resist on the conductive thin film and etching it after an exposure development as a photolithography method.
  16. The method of manufacturing a tap tape for electronic devices of claim 13, which further comprises mounting an electronic device chip within the resin application portion and applying resin for burying the electronic device chip, after forming a cutting portion on a connecting portion to be connected from the first lead to the second lead.
  17. The method of manufacturing a tap tape for electronic devices of claim 11, wherein the forming a conductive thin film on one surface of a dielectric film comprises forming further a plating treatment layer as a single layer or multi layer, using one, binary alloy or ternary alloy of Cu, Ni, Pd, Au, Sn, Ag, Co.
  18. The method of manufacturing a tap tape for electronic devices of claim 17, wherein the conductive thin film is formed by sputtering one of Cu, Ni, Pd, Au, Sn, Ag, Co.
PCT/KR2011/007580 2011-01-31 2011-10-12 Tap tape for electronic devices with reinforced lead crack and method of manufacturing the same Ceased WO2012105740A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2013551886A JP6109078B2 (en) 2011-01-31 2011-10-12 Electronic device tape with enhanced lead cracks
CN201180066521.1A CN103348460B (en) 2011-01-31 2011-10-12 There is the tap band for electronic installation of the lead-in wire crackle of enhancing
US13/982,658 US20130308289A1 (en) 2011-01-31 2011-10-12 Tape for electronic devices with reinforced lead crack
US15/153,970 US10020248B2 (en) 2011-01-31 2016-05-13 Tape for electronic devices with reinforced lead crack

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2011-0009610 2011-01-31
KR1020110009610A KR101259844B1 (en) 2011-01-31 2011-01-31 Tap Tape for Electronic Components Reinforced Lead Crack And Method of Manufacture The Same

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US13/982,658 A-371-Of-International US20130308289A1 (en) 2011-01-31 2011-10-12 Tape for electronic devices with reinforced lead crack
US15/153,970 Division US10020248B2 (en) 2011-01-31 2016-05-13 Tape for electronic devices with reinforced lead crack

Publications (1)

Publication Number Publication Date
WO2012105740A1 true WO2012105740A1 (en) 2012-08-09

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PCT/KR2011/007580 Ceased WO2012105740A1 (en) 2011-01-31 2011-10-12 Tap tape for electronic devices with reinforced lead crack and method of manufacturing the same

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US (2) US20130308289A1 (en)
JP (1) JP6109078B2 (en)
KR (1) KR101259844B1 (en)
CN (1) CN103348460B (en)
TW (1) TW201232733A (en)
WO (1) WO2012105740A1 (en)

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KR102144378B1 (en) 2013-08-27 2020-08-13 삼성전자주식회사 Chip-on-film package and display device including the same
KR102251684B1 (en) 2014-09-03 2021-05-14 삼성디스플레이 주식회사 Chip on film package and display apparatus having the same
US10317018B2 (en) * 2015-09-01 2019-06-11 Lg Innotek Co., Ltd. Lighting device
KR102466918B1 (en) 2017-12-27 2022-11-15 삼성디스플레이 주식회사 Chip on film package and display device including the chip on film package
KR20210026659A (en) * 2019-08-30 2021-03-10 엘지이노텍 주식회사 Driving apparatus of image sensor

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KR20120088332A (en) 2012-08-08
US10020248B2 (en) 2018-07-10

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