WO2012105106A1

WO2012105106A1 - Method for manufacturing solid-state imaging element, solid-state imaging element, and imaging device

Info

Publication number: WO2012105106A1
Application number: PCT/JP2011/076325
Authority: WO
Inventors: 崇後藤
Original assignee: 富士フイルム株式会社
Priority date: 2011-02-04
Filing date: 2011-11-15
Publication date: 2012-08-09
Also published as: KR101590687B1; KR20140015308A; JP5501262B2; JP2012164780A

Abstract

Provided is a method for manufacturing a layered solid-state imaging element having a high yield and a low dark current. This solid-state imaging element comprises a plug (20) electrically connected to a pixel electrode (3), a connector (11) connected to the plug (20), and a signal reader for reading a signal corresponding to an electrical charge that has been generated on a light-receiving layer (4) and transferred to the connector (11). This method for manufacturing a solid-state imaging element includes: a step for forming the connector (11) on a surface of a substrate (1); a step for forming an insulating film (2) above the substrate (1) on which the signal reader and the connector (11) have been formed, and forming, on the insulating film (2), an opening (k) that is smaller than the connector (11) at a position further inward than the connector (11) in plan view; a step for embedding an electroconductive material in the opening (k) and forming the plug (20); and a step for forming the pixel electrode (3) on the plug (20). In terms of design, the opening (k) and the connector (11) are formed such that the center of the connector (11) and the opening (k) coincide with each other, and that the distance from the end of the opening (k) to the end of the connector (11) in any direction that passes through the center is from 20% to 50%, inclusive, of the width of the opening (k) in this direction.

Description

Solid-state imaging device manufacturing method, solid-state imaging device, and imaging apparatus

According to the present invention, a plurality of light receiving portions having a pixel electrode, a counter electrode facing the pixel electrode, and a light receiving layer including a photoelectric conversion layer provided between the pixel electrode and the counter electrode are arranged above the semiconductor substrate. The present invention relates to a solid-state imaging device, a method for manufacturing the solid-state imaging device, and an imaging device including the solid-state imaging device.

In recent years, the miniaturization of solid-state imaging devices has progressed, and the limits of resolution and sensitivity are approaching. Accordingly, attention is paid to a stacked solid-state imaging device that can further increase sensitivity and resolution.

In this stacked solid-state imaging device, generally, a light receiving unit including a pair of electrodes and a photoelectric conversion layer sandwiched between them is stacked above a semiconductor substrate, and the photoelectric conversion layer of the light receiving unit is formed on the semiconductor substrate. A charge storage unit for storing the generated charge and a signal readout circuit for converting the charge stored in the charge storage unit into a signal and reading the signal to the outside are provided. One of the pair of electrodes constituting the light receiving unit and the charge storage unit are electrically connected by a conductive plug formed above the semiconductor substrate, and the charge generated in the photoelectric conversion layer passes through the conductive plug and is charged. Accumulated in the accumulator.

Patent Documents

1 and 2 disclose a pnp structure as a structure of an electric junction region for connecting a charge storage portion in a semiconductor substrate and a conductive plug. The pnp structure has a low-concentration n-type impurity layer constituting a charge storage portion, a p-type impurity layer formed on the surface of the low-concentration n-type impurity layer, and a low penetration through the p-type impurity layer. A high-concentration n-type impurity layer reaching the high-concentration n-type impurity layer is formed, and a conductive plug is connected to the high-concentration n-type impurity layer.

According to such a pnp structure, since the low-concentration n-type impurity layer is pinned by the p-type impurity layer provided on the surface of the low-concentration n-type impurity layer, darkness caused by the low-concentration n-type impurity layer is caused. The current can be reduced. In addition, since an ohmic contact can be obtained by connecting a conductive plug to the high-concentration n-type impurity layer, signal charges can be smoothly transported from the photoelectric conversion layer to the charge storage portion.

Japanese Unexamined Patent Publication No. 2009-164604 Japanese Unexamined Patent Publication No. 2009-117802

However, in the above-described pnp structure, dark current tends to occur due to surface defects in the high-concentration n-type impurity layer connected to the conductive plug. In order to reduce this dark current, it is considered effective to reduce the area of the high-concentration n-type impurity layer.

In order to minimize the area of the high-concentration n-type impurity layer, in

Patent Documents

1 and 2, after forming an interlayer insulating film on the semiconductor substrate, an opening for embedding a conductive plug is formed in the interlayer insulating film. Discloses a method of forming a high-concentration n-type impurity layer by implanting ions into a semiconductor substrate through the opening, and then filling a conductive material in the opening to form a conductive plug.

According to this method, the areas of the high-concentration n-type impurity layer and the conductive plug can be made substantially the same, and the area of the high-concentration n-type impurity layer can be reduced. However, in this method, since the high-concentration n-type impurity layer is ion-implanted after the formation of the interlayer insulating film, the high-concentration n-type impurity layer is not sufficiently formed deep in the semiconductor substrate. The variation in the size increases and the yield decreases.

In order to prevent such a decrease in yield, a high concentration n-type impurity layer is formed by ion implantation before forming the interlayer insulating film, and then an interlayer insulating film is formed on the high concentration n-type impurity layer. It is considered that a method of forming an opening above the high-concentration n-type impurity layer of the interlayer insulating film and embedding a conductive material in the opening to form a conductive plug is considered to be adopted.

However, in this method, it is necessary to make the area of the high-concentration n-type impurity layer larger than that of the conductive plug in consideration of misalignment between the high-concentration n-type impurity layer and the conductive plug. The problem is how to reduce this.

Such a problem is not limited to the pnp structure, but includes a connection portion (including a case where charge is accumulated in the connection portion itself) for forming an ohmic contact between the conductive plug and the semiconductor substrate in the semiconductor substrate. It occurs when it is provided. In a solid-state image sensor having a connection part that forms an ohmic contact with such a conductive plug, how to reduce the dark current generated near the connection part is a practical use of a high-sensitivity and high-resolution stacked solid-state image sensor. It becomes important in becoming.

The present invention has been made in view of the above circumstances, and provides a manufacturing method of a stacked solid-state imaging device capable of high yield and reduction of dark current, a solid-state imaging device, and an imaging apparatus including the same. Objective.

The solid-state imaging device manufacturing method of the present invention includes a pixel electrode, a counter electrode facing the pixel electrode, and a light receiving layer including a photoelectric conversion layer provided between the pixel electrode and the counter electrode. Is a method of manufacturing a plurality of solid-state imaging devices arranged above a semiconductor substrate, wherein the solid-state imaging device is formed above the semiconductor substrate and electrically connected to the pixel electrode, and the semiconductor A connection portion formed on the surface of the substrate and formed of an impurity layer that forms an ohmic contact with the conductive plug; and a charge generated in the light receiving layer and transferred to the connection portion through the pixel electrode and the conductive plug. And a signal readout portion formed on the semiconductor substrate for reading out a corresponding signal, and the connection portion is formed on the surface of the semiconductor substrate by impurity implantation using a mask. And forming an insulating layer above the semiconductor substrate on which the signal readout section and the connection section are formed, and forming an opening in the insulating layer that is smaller than the area of the connection section and reaches the connection section. A step of forming the conductive plug by embedding a conductive material in the opening, and a step of forming the pixel electrode on the conductive plug. The distance from the end of the opening to the end of the connection in all directions that coincides with the center and is parallel to the surface of the semiconductor substrate and passes through the center of the connection is the opening in the direction. The opening and the connecting portion are formed so as to be 20% or more and 50% or less of the width.

This method can achieve both improvement in yield and reduction in dark current.

In the solid-state imaging device according to the present invention, a light receiving unit including a pixel electrode, a counter electrode facing the pixel electrode, and a light receiving layer including a photoelectric conversion layer provided between the pixel electrode and the counter electrode is a semiconductor substrate. A plurality of solid-state imaging devices arranged above, a conductive plug formed above the semiconductor substrate and electrically connected to the pixel electrode, and formed on the surface of the semiconductor substrate, the ohmic contact with the conductive plug Formed on the semiconductor substrate for reading out a signal corresponding to the electric charge generated in the light receiving layer and transferred to the connection through the pixel electrode and the conductive plug. And in the plan view, the area of the conductive plug is smaller than the area of the connection part, and the conductive plug is disposed inside the connection part. A distance from one end of the connecting portion to one end of the conductive plug in all directions parallel to the surface of the semiconductor substrate and passing through the center of the conductive plug; The average value of the distance from the other end of the connecting portion in the direction to the other end of the conductive plug is 20% to 50% of the width of the conductive plug in the direction. Is.

This configuration can achieve both improvement in yield and reduction in dark current.

The imaging device of the present invention includes the solid-state imaging device.

According to the present invention, it is possible to provide a method for manufacturing a stacked solid-state imaging device capable of high yield and reduction of dark current, a solid-state imaging device, and an imaging apparatus including the same.

1 is a schematic cross-sectional view illustrating a schematic configuration of one pixel 100 of a stacked solid-state imaging device for explaining an embodiment of the present invention. The figure which shows the shape and positional relationship in the planar view of the connection part 11 of the pixel 100 in the design of the solid-state image sensor shown in FIG. The figure explaining the manufacturing process of the solid-state image sensor shown in FIG. The figure which shows the relationship between the breadth d of the connection part 11 in the solid-state image sensor shown in FIG. 1, and the dark current of a solid-state image sensor. The figure which shows the relationship between the ratio of the breadth d with respect to the width h of the conductive plug 20 in the solid-state image sensor shown in FIG. 1, and the dark current of a solid-state image sensor. 1 is a diagram showing the relationship between the ratio of the spread d to the width h of the conductive plug 20 and the dark current in the solid-state imaging device shown in FIG. The figure which shows the relationship between the said breadth ratio and manufacturing yield in the solid-state image sensor shown in FIG. The figure which shows the modification of the pixel shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic cross-sectional view showing a schematic configuration of one pixel 100 of a stacked solid-state imaging device for explaining an embodiment of the present invention. The stacked solid-state imaging device is used by being mounted on an imaging device such as a digital camera or a digital video camera, an imaging module mounted on an electronic endoscope, a camera-equipped mobile phone, or the like. Further, this stacked solid-state imaging device has a configuration in which a plurality of pixels 100 shown in FIG. 1 are arranged in a one-dimensional or two-dimensional manner.

As shown in FIG. 1, a light receiving portion P is formed on a p-type silicon substrate 1 common to all the pixels 100 via an insulating layer 2.

The light receiving portion P includes a pixel electrode 3 formed above the p-type silicon substrate 1, a counter electrode 5 formed above the pixel electrode 3, and a light receiving layer 4 provided between the pixel electrode 3 and the counter electrode 5. including.

Light enters the counter electrode 5 from above. Since the counter electrode 5 needs to make light incident on the light receiving layer 4, the counter electrode 5 is made of a conductive material such as ITO that is transparent to the incident light. The counter electrode 5 has a single configuration common to all the pixels 100 of the solid-state imaging device, but may be provided separately for each pixel 100.

The pixel electrode 3 is a thin film electrode divided for each pixel 100 and is made of a transparent or opaque conductive material (ITO, aluminum, titanium nitride, or the like).

The light receiving layer 4 is a layer including at least a photoelectric conversion layer configured to include an organic or inorganic photoelectric conversion material that absorbs a specific wavelength region of incident light and generates a charge corresponding to the absorbed light amount. is there. The light receiving layer 4 is suppressed from injecting electric charges from the electrodes into the photoelectric conversion layer between the photoelectric conversion layer and the counter electrode 5 included therein or between the photoelectric conversion layer and the pixel electrode 3. A charge blocking layer may be provided. Further, the light receiving layer 4 may be provided with other functional layers. The light receiving layer 4 has a single configuration common to all the pixels 100 of the solid-state imaging device.

In this embodiment, a bias voltage is applied to the counter electrode 5 so that electrons out of the charges generated in the light receiving layer 4 move to the pixel electrode 3 and holes move to the counter electrode 5. The configuration of the light receiving layer 4 and the bias voltage to be applied may be set so that holes move to the pixel electrode 3 and electrons move to the counter electrode 5.

On the surface of the p-type silicon substrate 1, a connection portion 11 made of a high-concentration n-type impurity layer that is electrically connected to the pixel electrode 3 of the light-receiving portion P is formed. A conductive plug 20 made of a conductive material that penetrates the insulating layer 2 is formed on the connection portion 11. The concentration of the connection portion 11 is adjusted so as to form an ohmic contact with the conductive plug 20. On the conductive plug 20, the pixel electrode 3 is formed, and the conductive plug 20 and the pixel electrode 3 are electrically connected.

In the p-type silicon substrate 1, the charge generated in the light receiving layer 4 and moved to the connection portion 11 via the pixel electrode 3 and the conductive plug 20 is accumulated at a position slightly separated from the surface of the p-type silicon substrate 1. Therefore, a charge storage portion 13 made of an n-type impurity layer having a lower concentration than the connection portion 11 is formed. The charge storage unit 13 is in contact with the connection unit 11, and the charge that has moved to the connection unit 11 is stored in the charge storage unit 13. In plan view, the connection portion 11 is formed inside the charge storage portion 13.

In order to prevent dark current generated on the surface of the charge storage unit 13 between the region other than the region in contact with the connection unit 11 of the charge storage unit 13 and the surface of the p-type silicon substrate 1, a p-type impurity layer is used. A dark current reducing layer 12 is provided. The connection part 11 is formed so as to penetrate the dark current reduction layer 12 and to contact the charge storage part 13.

A floating diffusion (FD) 16 made of an n-type impurity to which the accumulated charge of the charge accumulation unit 13 is transferred is formed on the right side of the dark current reducing layer 12. A gate electrode 15 is formed on the p-type silicon substrate 1 between the dark current reducing layer 12 and the FD 16 via a gate insulating film (not shown). The gate electrode 15 functions as a charge transfer unit that transfers the accumulated charge of the charge accumulation unit 13 to the FD 16.

On the p-type silicon substrate 1, a MOS circuit 17 is formed as a signal reading unit for outputting a signal according to the amount of charge transferred to the FD 16 to the outside. The MOS circuit 17 includes a reset transistor that resets the FD 16, an output transistor that outputs a signal corresponding to the potential of the FD 16, and a selection transistor that selectively outputs an output signal of the output transistor to an output signal line.

FIG. 2 is a diagram showing the shape and positional relationship in plan view when the connection portion 11 and the conductive plug 20 of the pixel 100 shown in FIG. 1 are designed without deviation. The connecting portion 11 and the conductive plug 20 have a rectangular shape (in the example of FIG. 2, a square shape) in plan view, and the conductive plug 20 has a smaller area than the connecting portion 11 and the center of the connecting portion 11. Arranged to coincide with the center.

In FIG. 2, the distance from one end of the connecting portion 11 to one end of the conductive plug 20 in all directions passing through the center of the connecting portion 11, and the other end of the connecting portion 11 in all directions. The distance from this part to the other end of the conductive plug 20 is the same.

For example, the distance from one end portion (left end portion or upper end portion) of the connection portion 11 to the one end portion (left end portion or upper end portion) of the conductive plug 20 in the left-right direction or the vertical direction passing through the center of the connection portion 11 The distance from the other end (right end or lower end) of the connecting portion 11 in the direction to the other end (right end or lower end) of the conductive plug 20 is d. Further, the width of the conductive plug 20 in the horizontal direction or the vertical direction in FIG. 2 is h. Hereinafter, the distance d is referred to as a spread d of the connecting portion 11 from the conductive plug 20.

FIG. 3 is a diagram for explaining a manufacturing process of the solid-state imaging device shown in FIG.

First, a dark current reduction layer 12, a charge storage unit 13, a gate electrode 15, an FD 16, a MOS circuit 17, and an element isolation layer are usually provided on a p-type silicon substrate 1 on which a gate insulating film such as a silicon oxide film is formed. The CMOS process is used.

For example, the dark current reduction layer 12 and the charge storage unit 13 are selectively formed using a photomask having openings at positions where the dark current reduction layer 12 and the charge storage unit 13 are to be formed above the p-type silicon substrate 1. It is formed by performing ion implantation (FIG. 3A).

Next, selectively using a photomask having an opening at a position where the connection portion 11 on the charge storage portion 13 is to be formed (a position inside the charge storage portion 13 in plan view) above the p-type silicon substrate 1. Are ion-implanted to form the connecting portion 11 (FIG. 3B). After the connection portion 11 is formed in the same manner as other high-concentration impurity regions, the connection portion 11 is salicided.

In the above description, for convenience, the gate electrode 15, the FD 16, the MOS circuit 17, and the element isolation layer are formed first, and finally the connection portion 11 is formed. However, the order is not limited. It is desirable to form these circuits by an appropriate procedure according to the CMOS process.

Next, an insulating layer 2 is formed above the p-type silicon substrate 1, and an opening k is formed by etching on the connecting portion 11 of the insulating layer 2 (FIG. 3C). The opening k takes into account misalignment with the connecting portion 11, and the relationship with the connecting portion 11 is the same as the shape and positional relationship in plan view of the connecting portion 11 and the conductive plug 20 shown in FIG. 2. Designed and formed as follows.

Next, a conductive material is formed on the insulating layer 2, the conductive material is embedded in the opening k, and excess conductive material that has not been embedded in the opening k is removed by planarization, and the conductive plug 20 is removed. Is formed (FIG. 3D).

Thereafter, the pixel electrode 3 is formed on the conductive plug 20, the light receiving layer 4 and the counter electrode 5 are sequentially formed to provide the light receiving portion P on the insulating layer 2 to complete the solid-state imaging device. .

When the inventor manufactures the stacked solid-state imaging device by the process as described above, the conductive plug 20 at a distance between the connection portion 11 and the conductive plug 20 in all directions passing through the center of the connection portion 11. Even if a solid-state imaging device is manufactured by any process rule, the area and the formation position of the connection portion 11 and the conductive plug 20 are designed so that the ratio (spreading ratio) to the width of the solid-state imaging device is 50% or less. It has been found that the current can be reduced.

For example, in FIG. 2, the area of the connection portion 11 (for forming the connection portion 11) is set so that the ratio of the spread d to the width h of the conductive plug 20 (unit:%; hereinafter referred to as spread ratio) is 50% or less. Opening area of the photomask), the area of the opening k (the opening area of the photolithographic mask when forming the hard mask for forming the opening k (synonymous with the area of the conductive plug 20)), the connection portion 11 and the conductivity By designing the position where the plug 20 is formed, the dark current can be reduced when the solid-state imaging device is manufactured by any process rule.

The spread ratio is preferably as small as possible from the viewpoint of dark current. However, if the spread ratio is too small, the connection portion 11 causes the dark current reduction layer 12 and the charge accumulation due to misalignment between the connection portion 11 and the conductive plug 20. It protrudes to the outside of the part 13, and the yield in manufacturing decreases. As a result of the study, the inventor has found that a reduction in yield can be prevented by designing and forming the connection portion 11 and the conductive plug 20 with the lower limit of the spread ratio being 20%.

Hereinafter, the basis of the numerical range of the spread ratio in the present invention will be described.

FIG. 4 is a diagram showing a result of studying the relationship between the spread d of the connecting portion 11 and the dark current of the solid-state imaging device. FIG. 4 shows the examination result of the change in dark current when the spread d is changed for three types of solid-state imaging devices having different process rules. The width h of the conductive plug 20 is uniquely determined according to the process rule. Here, as a process rule, three generations in which the width h of the conductive plug 20 is 0.12 μm, 0.18 μm, and 0.24 μm were examined.

From the results shown in FIG. 4, it can be seen that the dark current increases when the width h of the conductive plug 20 is smaller when the dark current in the same spread d is compared.

If the spread d is the same, the plane area of the connection part 11 in the solid-state image sensor with the small width h of the conductive plug 20 is larger than the plane area of the connection part 11 in the solid-state image sensor with the large width h of the conductive plug 20. small.

Therefore, it is considered that the dark current is lower in the solid-state imaging device having a smaller plane area of the connection portion 11, but this is not the case in the result of FIG. This is considered to be caused by the fact that the process rule with a narrower minimum line width has a higher concentration of the connecting portion 11 and more defects.

From these results, it can be seen that even if only the width of the connecting portion 11 is simply reduced, the dark current is rather increased depending on the process rule.

As a result of examining the graph of FIG. 4, the inventor found that the dark current of the solid-state imaging device is not the plane area of the connection portion 11 and the size of the connection portion 11 and the conductive plug 20 regardless of the process rule. We thought that it was decided by the relationship of size.

Therefore, the ratio of the spread d to the width h of the conductive plug 20 (the spread ratio = (d / h) × 100) is calculated as an index for defining the size of the connection portion 11 and the conductive plug 20, and FIG. FIG. 5 was created by replacing the horizontal axis of the graph shown in FIG. In FIG. 5, the reference level of dark current, which is generally not a practical problem as a solid-state imaging device, is indicated by a broken line.

In the graph of FIG. 5, the relationship between the spreading ratio and the dark current is almost the same for any process rule. Therefore, from the result shown in FIG. 5, if the connection portion 11 and the conductive plug 20 are formed by designing the spread ratio to be 50% or less, the dark current is at a level that does not cause a problem in practice regardless of the process rule. It was found that it can be reduced.

Next, for a solid-state imaging device having a conductive plug 20 with a width h of 0.18 μm, it was examined whether or not there was a difference in dark current between when the connecting portion 11 was salicided and when not salicided. Although there is a concern that the operation speed is lowered by not using salicide, an effect of reducing dark current can be expected. The examination results are shown in FIG. The spreading ratio is plotted on the horizontal axis and the dark current is plotted on the vertical axis.

From the results shown in FIG. 6, it can be seen that the dark current can be reduced by not making the connecting portion 11 salicide than when the connecting portion 11 is salicided. Such a non-salicide effect can be similarly obtained for a solid-state imaging device in which the width h of the conductive plug 20 is 0.12 μm and 0.24 μm. The graphs of FIGS. 4 and 5 are obtained when the connecting portion 11 is salicided.

FIG. 7 is a diagram showing the results of studying the relationship between the spread ratio and the yield of the solid-state imaging device. FIG. 7 shows the results of examining the yield when the spread ratio is changed for three types of solid-state imaging devices having different process rules in which the width h of the conductive plug 20 is 0.12 μm, 0.18 μm, and 0.24 μm. Show.

When the conductive plug 20 is formed so as to protrude from the inside of the connection portion 11 in plan view, the solid-state imaging device is NG (failed) as a product, and the conductive plug 20 is formed inside the connection portion 11. If so, the solid-state imaging device was determined as OK (accepted) as a product, and the yield was determined.

From the graph of FIG. 7, by designing the spread ratio to be 20% or more and forming the connecting portion 11 and the conductive plug 20, it is possible to obtain a high yield generally required (acceptable) in manufacturing a solid-state imaging device. I understand. In addition, about the yield, even if it did not salicide the connection part 11, it became a simulation result which is not different from the case where it salicided.

As described above, from the results shown in FIGS. 5 and 7, the spread ratio is designed to be 20% or more and 50% or less to form the connection portion 11 and the conductive plug 20, so that the solid-state imaging device can be formed by any process rule. It can be seen that even when manufactured, both low dark current and high yield can be achieved.

Even when a solid-state imaging device is manufactured by designing the spread ratio to 20% or more and 50% or less, the positional relationship between the connection portion 11 and the conductive plug 20 is as designed as shown in FIG. 2 due to manufacturing variations. May not be the value of. However, in a solid-state imaging device that is OK as a product, the conductive plug 20 is formed inside the connection portion 11.

That is, in the solid-state imaging device that is OK as a product, one of the connection portions 11 in the direction with respect to the width H of the conductive plug 20 in all directions (for example, left and right directions) passing through the center of the conductive plug 20 in plan view. The distance A from one end (left end) of the conductive plug 20 to one end (left end) of the conductive plug 20 and the other end (right end) of the connecting portion 11 in the direction to the other end of the conductive plug 20 The ratio of the average value D ((A + B) / 2) of the distance B to the part (right end part) is 20% or more and 50% or less.

Therefore, according to the manufacturing method of the present invention, a solid-state imaging device that has passed as a product in which the ratio of the average value D to the width H in all directions passing through the center of the conductive plug 20 in a plan view is 20% to 50%. It can be manufactured with a high yield.

FIG. 8 is a schematic cross-sectional view of a pixel 200 which is a modification of the pixel 100 shown in FIG. In FIG. 8, the same components as those in FIG.

The pixel 200 shown in FIG. 8 is arranged so that the charge storage unit 13 and the connection part 11 partially overlap with each other in a plan view without the charge storage part 13 being completely overlapped with the connection part 11. Except for this point, the configuration is the same as that of the pixel 100 shown in FIG. With the pixel configuration shown in FIG. 8, the area on the left side of the connection portion 11 can be narrowed, and the pixel size can be reduced.

In the embodiment described above, the planar view shapes of the conductive plug 20 and the connection portion 11 are rectangular, but the planar view shapes of the conductive plug 20 and the connection portion 11 are not limited thereto. For example, the conductive plug 20 and the connecting portion 11 may have a circular shape in plan view, one may be a rectangle, and the other may be a circle.

Further, the charge accumulated in the charge accumulating unit 13 may be read out to the CCD, the charge is transferred to the output amplifier by the CCD, and a signal corresponding to the charge is output from the output amplifier.

Further, although electrons are stored in the charge storage unit 13, holes may be stored and a signal corresponding to the amount of holes may be read out. In this case, the polarity of the signal readout circuit may be changed as appropriate.

As described above, the following items are disclosed in this specification.

The disclosed method for manufacturing a solid-state imaging device includes a pixel electrode, a counter electrode facing the pixel electrode, and a light receiving layer including a photoelectric conversion layer provided between the pixel electrode and the counter electrode. Is a method of manufacturing a plurality of solid-state imaging devices arranged above a semiconductor substrate, wherein the solid-state imaging device is formed above the semiconductor substrate and electrically connected to the pixel electrode, and the semiconductor A connection portion formed on the surface of the substrate and formed of an impurity layer that forms an ohmic contact with the conductive plug; and a charge generated in the light receiving layer and transferred to the connection portion through the pixel electrode and the conductive plug. A signal readout portion formed on the semiconductor substrate for reading out a corresponding signal, and forming the connection portion on the surface of the semiconductor substrate by impurity implantation using a mask. And forming an insulating layer above the semiconductor substrate on which the signal readout section and the connection section are formed, and forming an opening in the insulating layer that is smaller than the area of the connection section and reaches the connection section. A step of forming the conductive plug by embedding a conductive material in the opening, and a step of forming the pixel electrode on the conductive plug. The distance from the end of the opening to the end of the connection in all directions that coincides with the center and is parallel to the surface of the semiconductor substrate and passes through the center of the connection is the opening in the direction. The opening and the connecting portion are formed so as to be 20% or more and 50% or less of the width.

The disclosed method for manufacturing a solid-state imaging device does not salicide the connecting portion in the step of forming the connecting portion.

This method can further reduce the dark current.

According to the disclosed method for manufacturing a solid-state imaging device, the solid-state imaging device has the same conductivity type as the connection portion formed in contact with the connection portion in the semiconductor substrate and has a lower concentration than the connection portion. A charge storage part for storing the charge transferred to the connection part, and an impurity layer of a conductivity type opposite to the charge storage part formed between the charge storage part and the semiconductor substrate surface, In the step of forming the connection portion, the connection portion is formed by implanting impurities into the semiconductor substrate on which the impurity layer having the opposite conductivity type to the charge storage portion is formed.

By this method, since the charge storage part is pinned by the impurity layer provided between the charge storage part and the semiconductor substrate surface, dark current caused by the charge storage part can be reduced. Further, since the complete transfer is possible when the charge is transferred from the charge storage portion to another portion, it is possible to suppress the occurrence of an afterimage.

In the disclosed method for manufacturing a solid-state imaging device, in the step of forming the connection portion, the connection portion is formed inside the charge storage portion in plan view, and the charge storage portion and the surface of the semiconductor substrate are formed. It is formed so as to penetrate through the impurity layer of the opposite conductivity type formed between and in contact with the charge storage portion.

This method improves the sensitivity because the charges move smoothly from the connection portion to the charge storage portion.

In the disclosed method for manufacturing a solid-state imaging device, the signal readout unit includes a transfer transistor that transfers charges accumulated in the charge accumulation unit, and a second charge accumulation unit that accumulates charges transferred by the transfer transistor. Is included.

By this method, the charge can be completely transferred from the charge storage unit to the second charge storage unit, and the occurrence of afterimage can be suppressed.

In the disclosed solid-state imaging device, a light receiving unit including a pixel electrode, a counter electrode facing the pixel electrode, and a light receiving layer including a photoelectric conversion layer provided between the pixel electrode and the counter electrode is a semiconductor substrate. A plurality of solid-state imaging devices arranged above, a conductive plug formed above the semiconductor substrate and electrically connected to the pixel electrode, and formed on the surface of the semiconductor substrate, the ohmic contact with the conductive plug Formed on the semiconductor substrate for reading out a signal corresponding to the electric charge generated in the light receiving layer and transferred to the connection through the pixel electrode and the conductive plug. And the area of the conductive plug is smaller than the area of the connection part in plan view, and the conductive plug is arranged on the inner side of the connection part. A distance from one end of the connecting portion to one end of the conductive plug in all directions parallel to the surface of the semiconductor substrate and passing through the center of the conductive plug; The average value of the distance from the other end of the connecting portion in the direction to the other end of the conductive plug is 20% to 50% of the width of the conductive plug in the direction. Is.

The disclosed solid-state imaging device is one in which the connecting portion is not salicided.

This configuration can further reduce the dark current.

The disclosed solid-state imaging device is an impurity layer having the same conductivity type as the connection portion formed in contact with the connection portion in the semiconductor substrate and having a lower concentration than the connection portion, and has moved to the connection portion A charge storage section for storing charge; and an impurity layer having a conductivity type opposite to the charge storage section formed between the charge storage section and the surface of the semiconductor substrate.

With this configuration, since the charge storage unit is pinned by the impurity layer provided between the charge storage unit and the semiconductor substrate surface, dark current caused by the charge storage unit can be reduced. Further, since the complete transfer is possible when the charge is transferred from the charge storage portion to another portion, it is possible to suppress the occurrence of an afterimage.

In the disclosed solid-state imaging device, the connection portion is formed inside the charge storage portion in a plan view, and the impurity layer of the opposite conductivity type formed between the charge storage portion and the surface of the semiconductor substrate is provided. It is formed so as to penetrate and contact the charge storage portion.

This configuration improves the sensitivity because the charges move smoothly from the connection portion to the charge storage portion.

In the disclosed solid-state imaging device, the signal readout unit includes a transfer transistor that transfers the charge accumulated in the charge accumulation unit, and a second charge accumulation unit that accumulates the charge transferred by the transfer transistor. It is a waste.

With this configuration, charges can be completely transferred from the charge storage unit to the second charge storage unit, and the occurrence of afterimages can be suppressed.

The disclosed imaging device includes the solid-state imaging device.

Although the present invention has been described in detail and with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.
This application is based on a Japanese application (Japanese Patent Application No. 2011-23411) filed on Feb. 4, 2011, the contents of which are incorporated herein by reference.

100 pixel 1 p-type silicon substrate 2 insulating layer 3 pixel electrode 4 light receiving layer 5 counter electrode 11 connection portion 12 dark current reducing layer 13 charge storage portion 20 conductive plug k opening P light receiving portion

Claims

Solid-state imaging in which a plurality of light-receiving portions having a pixel electrode, a counter electrode facing the pixel electrode, and a light-receiving layer including a photoelectric conversion layer provided between the pixel electrode and the counter electrode are arranged above the semiconductor substrate A method for manufacturing an element, comprising:
The solid-state imaging device includes a conductive plug formed above the semiconductor substrate and electrically connected to the pixel electrode, and an impurity layer formed on the surface of the semiconductor substrate and forming an ohmic contact with the conductive plug. And a signal readout unit formed on the semiconductor substrate for reading out a signal corresponding to the charge generated in the light receiving layer and moved to the connection unit through the pixel electrode and the conductive plug. Is,
Forming the connection portion on the surface of the semiconductor substrate by impurity implantation using a mask;
Forming an insulating layer above the semiconductor substrate on which the signal readout unit and the connection unit are formed, and forming an opening in the insulating layer that is smaller than the area of the connection unit and reaches the connection unit;
Forming the conductive plug by embedding a conductive material in the opening;
Forming the pixel electrode on the conductive plug,
In design, the center of the opening coincides with the center of the connection part, and is parallel to the surface of the semiconductor substrate, and is connected from the end of the opening in all directions passing through the center of the connection part. A method of manufacturing a solid-state imaging device in which the opening and the connection portion are formed so that the distance to the end of the portion is 20% to 50% of the width of the opening in the direction.
It is a manufacturing method of the solid-state image sensing device according to claim 1,
In the step of forming the connection portion, a method of manufacturing a solid-state imaging device in which the connection portion is not salicided.
It is a manufacturing method of the solid-state image sensing device according to claim 1 or 2,
The solid-state imaging device has the same conductivity type as the connection portion formed in contact with the connection portion in the semiconductor substrate and is formed of an impurity layer having a lower concentration than the connection portion, and the electric charge transferred to the connection portion. A charge storage section for storing; and an impurity layer of a conductivity type opposite to the charge storage section formed between the charge storage section and the semiconductor substrate surface,
In the step of forming the connection portion, a method for manufacturing a solid-state imaging device, wherein the connection portion is formed by implanting impurities into the semiconductor substrate on which the impurity layer having the opposite conductivity type to the charge storage portion is formed.
It is a manufacturing method of the solid-state image sensing device according to claim 3,
In the step of forming the connection portion, the connection portion is formed inside the charge accumulation portion in a plan view, and the opposite conductivity type formed between the charge accumulation portion and the surface of the semiconductor substrate. A method for manufacturing a solid-state imaging device, wherein the solid-state imaging device is formed so as to penetrate the impurity layer and contact the charge storage portion.
It is a manufacturing method of the solid-state image sensing device according to claim 3 or 4,
The method of manufacturing a solid-state imaging device, wherein the signal readout unit includes a transfer transistor that transfers charges accumulated in the charge accumulation unit, and a second charge accumulation unit that accumulates charges transferred by the transfer transistor.
Solid-state imaging in which a plurality of light-receiving portions having a pixel electrode, a counter electrode facing the pixel electrode, and a light-receiving layer including a photoelectric conversion layer provided between the pixel electrode and the counter electrode are arranged above the semiconductor substrate An element,
A conductive plug formed above the semiconductor substrate and electrically connected to the pixel electrode;
A connection portion formed on the surface of the semiconductor substrate and made of an impurity layer forming an ohmic contact with the conductive plug;
A signal readout unit formed on the semiconductor substrate for reading out a signal corresponding to the charge generated in the light receiving layer and moved to the connection unit through the pixel electrode and the conductive plug;
In a plan view, the area of the conductive plug is smaller than the area of the connection portion, and the conductive plug is disposed inside the connection portion,
The distance from one end of the connecting portion to one end of the conductive plug in all directions parallel to the surface of the semiconductor substrate and passing through the center of the conductive plug, and the direction in the direction A solid-state imaging device in which an average value of the distance from the other end of the connection portion to the other end of the conductive plug is 20% or more and 50% or less of the width of the conductive plug in the direction.
The solid-state imaging device according to claim 6,
A solid-state imaging device in which the connecting portion is not salicided.
The solid-state imaging device according to claim 6 or 7,
A charge storage portion that is an impurity layer of the same conductivity type as the connection portion formed in contact with the connection portion in the semiconductor substrate and has a lower concentration than the connection portion, and stores the charge that has moved to the connection portion; ,
A solid-state imaging device comprising: an impurity layer having a conductivity type opposite to the charge storage portion formed between the charge storage portion and the surface of the semiconductor substrate.
The solid-state imaging device according to claim 8,
The connection part is formed inside the charge storage part in a plan view and penetrates the opposite conductivity type impurity layer formed between the charge storage part and the surface of the semiconductor substrate. A solid-state imaging device formed so as to contact the
The solid-state imaging device according to claim 8 or 9,
The solid-state imaging device, wherein the signal readout unit includes a transfer transistor that transfers charges accumulated in the charge accumulation unit, and a second charge accumulation unit that accumulates charges transferred by the transfer transistor.
An imaging apparatus comprising the solid-state imaging device according to any one of claims 6 to 10.