WO2012100647A1 - 缓解铟镓铝氮薄膜应力的半导体器件的制造方法 - Google Patents

缓解铟镓铝氮薄膜应力的半导体器件的制造方法 Download PDF

Info

Publication number
WO2012100647A1
WO2012100647A1 PCT/CN2012/000062 CN2012000062W WO2012100647A1 WO 2012100647 A1 WO2012100647 A1 WO 2012100647A1 CN 2012000062 W CN2012000062 W CN 2012000062W WO 2012100647 A1 WO2012100647 A1 WO 2012100647A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
indium gallium
layer
gallium aluminum
aluminum nitride
Prior art date
Application number
PCT/CN2012/000062
Other languages
English (en)
French (fr)
Inventor
熊传兵
赵汉民
江风益
Original Assignee
晶能光电（江西）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201110026143.6A external-priority patent/CN102610707B/zh
Application filed by 晶能光电（江西）有限公司 filed Critical 晶能光电（江西）有限公司
Publication of WO2012100647A1 publication Critical patent/WO2012100647A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to an indium gallium aluminum nitride based semiconductor light emitting device.
  • the commercial indium gallium aluminum nitride light-emitting device has a growth substrate which is a heterogeneous growth substrate, and there are mainly three kinds: a sapphire substrate, a silicon carbide substrate and a silicon substrate; although other substrates can also be used for Epitaxial indium gallium aluminum nitride film, but has not yet formed a commercial device; homogenous growth substrate can also be used as a light-emitting device, but the cost of homogenous growth substrate is very high, and commercialization is not yet mature.
  • the temperature of the epitaxially grown indium gallium aluminum nitride film is generally about 1000 ° C, and is reduced to room temperature after the epitaxial growth of the indium gallium aluminum nitride film is completed. There is a large stress in the indium gallium aluminum nitride film due to the mismatch in the thermal expansion coefficient.
  • gallium nitride of the (0001) plane when it is epitaxially grown on a sapphire substrate, the film is subjected to compressive stress at room temperature: when it is epitaxially grown on a silicon carbide substrate and a silicon substrate, it is subjected to tensile stress at room temperature. .
  • the silicon substrate since the thermal expansion coefficient between the gallium nitride and the silicon of the (0001) plane differs greatly, the epitaxial film is liable to cause cracks and defects at room temperature.
  • the indium gallium aluminum nitride film is a very polar material.
  • the energy band structure of the ⁇ layer of the indium gallium aluminum nitride film changes correspondingly, so that the photoelectric properties of the device change accordingly.
  • the stress state of the indium gallium aluminum chloride film is different, the internal energy of the atom will be different, and the ability of the atom to migrate during the operation of the device will be different.
  • the stress of the film will directly affect the reliability of the device.
  • a non-polar or semi-polar indium gallium aluminum nitride film although it can solve the problem of the effect of stress on luminous efficiency, it introduces a new thermal expansion and contraction stress problem.
  • the thermal mismatch problem between non-polar gallium arsenide on a sapphire substrate and the substrate is a problem of epitaxial stress that is more prominent than gallium nitride on a silicon substrate. Only when there is stress, the ability of the atom to diffuse and migrate during the operation of the device will be affected, and the reliability of the device will be affected.
  • the indium gallium aluminum nitride film epitaxially grown on the substrate is bonded to the new supporting substrate, and then the growth substrate is removed to realize the transfer of the indium gallium aluminum nitride film from the growth substrate to the supporting substrate.
  • the main effect of this technical solution is to improve the heat dissipation of the device, and transfer the epitaxial indium gallium aluminum nitride film on the sapphire substrate to the silicon substrate or the metal substrate to realize the vertical structure, the silicon and the gold substrate.
  • the heat dissipation is much stronger than the sapphire substrate. Effective heat dissipation has improved the electro-optic conversion efficiency and reliability of such devices. However, the reliability of the device obtained by this one-time transfer technique is still not satisfactory.
  • the technical problem solved by the present invention is: providing a method for manufacturing a semiconductor device for relieving the stress of an indium gallium aluminum nitride film, which is used for releasing the stress of adjusting the indium gallium aluminum nitride film, and making the photoelectric performance and reliability of the device Get improved.
  • the present invention provides a method of fabricating a semiconductor device for alleviating the stress of an indium gallium aluminum nitride film, comprising:
  • the substrate is grown prior to epitaxial indium gallium aluminum nitride film.
  • the patterned groove structure acts to adjust the telescopic space during the transfer of the substrate.
  • the indium gallium aluminum nitride film is in a state of free-stretching release stress after being transferred to the flexible adhesive.
  • a flexible adhesive is used to bond an indium gallium aluminum nitride film and a transfer substrate, including some soft metals such as lead, zinc, silver, tin, indium, gold, aluminum, copper, etc. at room temperature, and some softness Rarely, it also includes metals that become softer at elevated manufacturing temperatures.
  • some organic colloids including those which harden for a long time, have an effect of adjusting the stress of the indium gallium aluminum nitride film during the unhardened time.
  • the indium gallium aluminum nitride film is attached to the transfer substrate by a flexible adhesive, and the stress generated during the growth process is gradually reduced to subsided under the tension-free and compressive stress environment provided by the flexible adhesive. Even if these flexible adhesives are themselves in thermal expansion and contraction, because they are soft materials themselves, they will well decompose the stress by stretching deformation, and will not transmit the thermal expansion and contraction stress to indium gallium aluminum. Nitrogen film.
  • the indium gallium aluminum nitride film is subjected to two substrate transfer successively, and the substrate transfer twice is the following transfer mode: bond bonding, deposition or a mixture thereof.
  • Deposition includes arc ion plating, magnetron sputtering, electron beam evaporation, thermal evaporation, thermal spraying, electroplating, electroless plating, vacuum plating, and the like.
  • the indium gallium aluminum nitride film is transferred to another substrate by a bonding material, and the stress of the indium gallium aluminum nitride film is adjusted by thermal expansion and contraction of the bonding material curing. When the bonding material is cured, its volume changes due to thermal expansion and contraction.
  • This change will stress the indium gallium aluminum nitride film, such as the stress effect and the growth of indium gallium and aluminum.
  • the opposite stress generated by the substrate can serve to adjust the stress of the indium gallium aluminum nitride film. If the indium gallium aluminum nitride film is subjected to tensile stress (silicon carbide, silicon substrate) at room temperature after epitaxy, a material having a smaller expansion coefficient than indium gallium aluminum nitride is used; if the indium gallium aluminum nitride film is subjected to compressive stress after epitaxy (Sapphire substrate), a material having a larger expansion coefficient than indium gallium aluminum nitride is used.
  • the indium gallium aluminum nitride film is transferred to another substrate by a bonding material, and the stress adjustment of the indium gallium aluminum nitride film is achieved by the temperature at which the bonding material is cured. According to the expansion coefficient of the bonding material, an appropriate curing temperature environment is selected to adjust the stress of the indium gallium aluminum nitride film.
  • the indium gallium aluminum nitride film is transferred to another substrate by bonding pressure welding, and the stress adjustment of the indium gallium aluminum nitride film is realized by the fusion temperature control of the bonding pressure metal.
  • the indium gallium aluminum alloy film is transferred to another substrate by bonding pressure welding, and the stress adjustment of the indium gallium aluminum nitride film is realized by controlling the elastic modulus of the pressure bonding metal layer.
  • the composition of the pressure-welded metal has different elastic moduli.
  • the indium gallium aluminum nitride film is transferred to another substrate by deposition, and the stress adjustment of the indium gallium aluminum ammonia film is realized by the stress formed by the deposition layer S in the deposition process of the other substrate.
  • the indium gallium aluminum nitride film is transferred to another substrate, and stress adjustment of the indium gallium aluminum nitride film is achieved by deposition preparation conditions, wherein the preparation conditions include: temperature, thickness, density distribution, group A combination of any one or more of the points or structures.
  • the indium gallium aluminum nitride film is transferred under the selected temperature conditions, so that the stress of the indium gallium aluminum nitride film releases a certain stress at this temperature.
  • the thickness of the transfer substrate also affects the indium gallium aluminum nitride film. In the same case, the thicker transfer substrate makes it easier for the indium gallium aluminum nitride film to undergo deformation or deformation, thereby generating stress, thus adjusting the thickness of the substrate.
  • the stress on the indium gallium aluminum nitride film can be adjusted.
  • the higher the density of a substance in a general substrate the larger the coefficient of expansion, and thus the density can also be used to adjust the stress of the indium gallium aluminum nitride film.
  • the substance contained in the substrate determines its expansion coefficient, so that the stress of the indium gallium aluminum nitride film can be adjusted according to the composition of the substrate.
  • the structure of the substrate such as hollowing, voids, grooves, layers, etc., all change the thermal expansion and contraction effect, and these structures can be used to adjust the stress of the indium gallium aluminum nitride film.
  • the method comprises the steps of: fabricating a constituent device on the indium gallium aluminum nitride thin strand, and constituting the device comprises: an electrode and a pad and an ohmic contact layer.
  • the constituting device further includes:
  • the passivation layer one or more of a patterning layer that increases light emission (i.e., roughening of the light-emitting surface), a light-reflecting layer, a light-reflecting layer, or a complementary structure to the electrode.
  • the electrode complementary structure refers to a structure in which the electrode has no ohmic contact in the projection position of the indium gallium aluminum nitride film.
  • One or all of the elements constituting the device are fabricated on the indium gallium aluminum ammonia film prior to the last substrate transfer.
  • the fabrication of the constituent elements of the indium gallium aluminum nitride film results in a change in the coefficient of thermal expansion of the indium gallium aluminum nitride film, and the stress is also adjusted during the manufacturing process.
  • the intrinsic stress adjustment of the indium gallium aluminum nitride film containing all the elements can be performed by transferring the substrate for the last time; if the substrate is transferred after the last transfer If the material is manufactured, the stress state of the entire device will change again or again. Even if the stress condition of the device is known again, it is not satisfactory, and there is no way to adjust it. For example, a roughened surface can release stress. Therefore, the way in which all the elements are produced before the last substrate transfer is generally better than the latter.
  • the growth substrate is a sapphire substrate, a silicon carbide substrate, a silicon substrate, MgAl 2 0 4 , MgO, LiGa0 2 , Y-LiA10 2 , NdGa0 3 , ScAlMg0 4 , Ga 8 La 2 (P0 4 6 0 2 , MoS 2 , LaAI0 3 , (Mn, Zn)Fe 2 0 4 , Hf, Zr, ZrN, Sc, ScN, NbN, TiN or a solid material (a three-dimensional shape having a first predetermined thickness). Any of GaN or AI substrates.
  • deposited on the growth substrate Si, GaAs, Ge, AlP, AlAs, AlSb, GaP, GaAs, GaSb, InP, InAs InSb, ZnO, ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgSe, HgTePbS, PbSe, PbTe, GaP x As, x > Ga x Ai,.
  • the method comprises the following steps:
  • the substrate Before epitaxial indium gallium aluminum nitride film, the substrate is patterned to form a growth structure between the growth platform and the platform of the indium gallium aluminum nitride film; a passivation layer is formed, and a passivation layer is patterned in the indium gallium aluminum nitride film.
  • Edge and in-slot equalization between indium gallium aluminum nitride thin film units a patterned passivation layer for blocking the plating current, a gap between the passivation layer at the edge of the indium gallium aluminum film and the patterned passivation layer in the trench;
  • thermally conductive metal layer (copper, good thermal conductivity) at a substrate position below the removed passivation layer, and patterning the thermally conductive metal layer to expose the passivation layer in the trench;
  • the prepared epitaxial wafer is subjected to filming, and the joined substrate is removed to complete the dicing.
  • the purpose of patterning the passivation layer is to achieve electroplating of a transfer substrate on the thermally conductive metal.
  • the electroplated transfer substrate has been naturally patterned during deposition, so that it does not require cutting. After the joint substrate is removed, the plated transfer substrate is naturally separated to complete the dicing.
  • This method is designed for metal substrates. This is a special solution based on the problem that the metal substrate is difficult to cut.
  • the indium gallium aluminum film is transferred at least twice, and the coefficient of thermal expansion of the second transfer substrate matches the coefficient of thermal expansion of the first transfer substrate.
  • the two transfer substrates are formed on the indium gallium aluminum nitride film after the first transfer substrate, and they act together on the indium gallium aluminum nitride film before the first transfer substrate is peeled off.
  • the matching of the expansion coefficients of the two transfer substrates can well realize the excessive transfer of the indium gallium aluminum nitride film, and avoid the crack caused by the stress imbalance during the transfer process.
  • the transfer substrate is made to have its thermal expansion coefficient matched to the indium gallium aluminum nitride film by a hollow structure.
  • the hollow structure can change its expansion coefficient.
  • the expansion coefficient of the material itself is insufficient to meet the stress of releasing the indium gallium aluminum nitride film, the effect of thermal expansion and contraction can be changed by hollowing, hole, groove and other structures. Effect.
  • the bonding material is an organic material or an inorganic non-metal material.
  • the organic substance is a hot glue type adhesive, a hot melt type adhesive, a room temperature curing type adhesive, a pressure sensitive type adhesive, and a light curing organic glue.
  • the bonding material is a two-layer structure of two or more layers, and the laminated structure includes at least two materials.
  • the binder material is a cellulose ester, an olefin polymer (polyvinyl acetate, polyvinyl alcohol, perchloroethylene, polyisobutylene, etc.), a polyester, a polyether, a polyamide, a polyacrylate, A-cyanoacrylate, polyvinyl acetal, ethylene-vinyl acetate copolymer, epoxy resin, phenolic resin, urea resin, melamine-formaldehyde resin, silicone resin, furan resin, unsaturated polyester, acrylic acid Resin, polyimide, polybenzimidazole, phenolic-polyvinyl acetal, phenolic-polyamide, phenolic-epoxy resin, epoxy-polyamide, synthetic rubber, neoprene, styrene butadiene rubber, butyl Rubber, sodium butadiene rubber, isoprene rubber, polysulfide rubber, urethane rubber, chlorosulfon
  • the inorganic non-metallic material is an air-drying inorganic adhesive, a water-curable inorganic adhesive, a hot-melt inorganic adhesive or a chemically reactive inorganic adhesive.
  • the inorganic non-golden material is gypsum, cement, water glass, clay, low melting glass, low melting glass ceramic or sulfur, or silicate adhesive, phosphate adhesive, colloidal alumina Adhesive, dental cement adhesive; the bonding material is a combination of one or more of the above inorganic non-metallic materials.
  • a P-side passivation layer is deposited on the P-side of the indium gallium aluminum nitride film, and the P-side passivation layer is patterned to have a patterned P-side passivation layer on the edge of each of the final discrete devices.
  • the thickness of the P-side passivation layer is thin, and there is basically no significant stress on the surface of the indium gallium aluminum nitride film, and its main function is to prevent oxidation of the film.
  • the transfer substrate is a composite substrate, which is divided into three layers, the first layer is in contact with the indium gallium aluminum nitride film, and the second layer and the third layer are sequentially; the thermal expansion coefficient of the first layer is The indium gallium aluminum nitride film is matched, the third layer has a coefficient of thermal expansion matching the growth substrate, and the second layer is a pressure bonding layer that connects the first layer and the third layer together.
  • the first layer can reduce the thermal shock damage of the substrate to the indium gallium aluminum nitride film during the chip processing; the third layer can prevent the crack of the epitaxial wafer from the substrate bow after the completion of the first transfer.
  • the method comprises:
  • the patterning of the plating layer is consistent with the patterning of the growth substrate, and the plating layer has a slit extending along the groove of the patterned growth substrate, wherein the growth substrate For the sapphire substrate:
  • This structure is advantageous for the discharge of gaseous substances generated when the laser is peeled off from the substrate, thereby reducing the damage to the indium gallium aluminum nitride film.
  • the number of film transfer times is greater than three times, the device with the first type of conductive nitride layer facing upward is obtained by an even number of times, and the light-emitting device with the second type of conductive layer facing upward is obtained by an odd number of times, and the constituent elements of the light-emitting device can be transferred at any time. Prepared and added.
  • the present invention proposes a solution for releasing the stress generated by the growth substrate on the indium gallium aluminum nitride film due to the difference in thermal expansion coefficient after at least two substrate transfers.
  • the growth substrate will have a large stress on the epitaxial layer due to the difference in thermal expansion coefficient.
  • This stress may be tensile stress or compressive stress. This stress can cause changes in the energy band in the device, even physical cracking.
  • Transfer of the substrate is generally considered to transfer the epitaxial layer from the hot poor conductor substrate to the hot good conductor to enhance heat dissipation, so the transfer substrate is often used for heat dissipation from high power chips.
  • the transfer of the epitaxial layer can alleviate the stress inside the epitaxial layer, but the effect of the first transfer is not obvious, or the research in this area is not paid attention to or be ignored.
  • the present invention is directed to stress generated by the difference in thermal expansion coefficient between the growth substrate and the indium gallium aluminum nitride film, and proposes a scheme for continuously releasing stress, by at least two transfers, even three times, four times, and the like.
  • a scheme for continuously releasing stress by at least two transfers, even three times, four times, and the like.
  • the surface of the indium gallium aluminum nitride film in contact with the growth substrate (referred to as the lower surface, corresponding to the upper surface) is liberated, so that the surface and the lower portion thereof are
  • the elastic recovery state especially under the action of the first transfer substrate, has a significant recovery effect on the surface and the lower portion, and the degree of recovery effect is related to the selected first transfer substrate.
  • the first transfer of the substrate directly releases the stress of the upper surface of the indium gallium aluminum nitride film and its adjacent lower portion.
  • the lower surface does not have a strong upper surface.
  • the substrate is transferred a second time, and the first transfer substrate is peeled off.
  • the second transfer substrate directly releases the lower surface of the indium gallium aluminum nitride film and its adjacent lower portion stress, while the upper surface has no effect on the lower surface.
  • the substrate can be further transferred.
  • the process of transferring the substrate multiple times may be used to release stress not every transfer. For example, a transfer substrate fabricated at a high temperature may be used to adjust stress, and a transfer substrate fabricated at normal temperature may not be used to adjust stress.
  • the invention can fully and effectively release and adjust the stress state of the indium gallium aluminum nitride film, and can gradually adjust the stress of the indium gallium aluminum nitride film, wherein the stress is fully or partially released, thereby improving the photoelectric performance and reliability of the device. .
  • Figure 1 is a device structure obtainable by the method of the present invention.
  • FIGS 4-01 through 4-11 are used to illustrate the implementation of Embodiments 4, 5, and 6.
  • FIGS 5-01 through 515 are used to illustrate the implementation of Embodiments 7, 8.
  • 6-01 to 6-14 are for explaining the implementation process of the embodiment 9.
  • FIGS 9-01 through 9-13 are used to illustrate the implementation of Embodiment 12.
  • Figure 12 is one of the typical device structures that can be obtained using the method of the present invention. '
  • Figure 13 is one of another exemplary device configurations that can be obtained using the method of the present invention.
  • Figure 14 is one of another exemplary device configurations that can be obtained using the method of the present invention.
  • Figure 15 is one of another exemplary device configurations that can be obtained using the method of the present invention.
  • Figure 16 is one of another exemplary device configurations that can be obtained using the method of the present invention.
  • Figure 17 is one of another exemplary device configurations that can be obtained using the method of the present invention.
  • Figure 18 is one of another exemplary device configurations that can be obtained using the method of the present invention.
  • Figure 19 is one of another exemplary device configurations that can be obtained using the method of the present invention. detailed description
  • the invention provides a method for manufacturing a semiconductor device for relieving stress of an indium gallium aluminum nitride film, comprising: epitaxial indium gallium aluminum nitride film on a growth substrate; and aiming at a difference in thermal expansion coefficient between the growth substrate and the indium gallium aluminum nitride
  • the generated stress is transferred at least twice to transfer the indium gallium aluminum nitride film from the current substrate to the substrate on the other substrate, and the substrate transfer release adjusts the stress accumulated during the growth process of the indium gallium aluminum nitride film.
  • Embodiments of the present invention are suitable for transferring epitaxially grown indium gallium aluminum nitride thin films on silicon substrates, sapphire substrates, silicon carbide substrates, and other prior art substrates onto a new substrate and preparing corresponding luminescence Device.
  • the invention adopts a process of transferring a film twice or more, so that the stress of the indium gallium aluminum nitride film is fully or partially released during the first transfer, the second transfer or more than two transfer processes, in the indium gallium.
  • the invention can be embodied in practicality, novelty and inventiveness by the following embodiments.
  • 2-01 to 24-1 are used to illustrate the process of obtaining the stress and the structure of the device for releasing and adjusting the indium gallium aluminum nitride film by the three-transfer method, and also illustrating the mentioned figure.
  • the passivation layer is patterned, and a patterned passivation layer for blocking the plating current is distributed in the groove between the edge of the indium gallium aluminum nitride film and the indium gallium aluminum nitride thin film unit, and is blunt at the edge of the indium gallium aluminum nitride film. There is a gap between the layer and the patterned passivation layer in the trench;
  • a metal bonded substrate bonded to the third transfer substrate is bonded to the third transfer substrate by a conductive bonding material, and the second transfer substrate is removed:
  • 2-01 is a schematic cross-sectional view of a feature of an epitaxial wafer, in which Ol is a growth substrate (also referred to as an epitaxial substrate), 202 is a groove on the growth substrate, and the groove 202 divides the growth substrate 20 into
  • the periodic flat region array, the indium gallium aluminum nitride film 203 grown on the independent flat regions, is also a periodic array.
  • the growth substrate 201 in the drawing may be a sapphire substrate, a silicon carbide substrate, a silicon substrate, MgAI 2 0 4 , MgO, LiGa0 2 , Y -LiA10 2 , NdGa0 3 , ScAlMg0 4 , Ga 8 La 2 (P0 4 ) 6 0 2 , MoS 2 , LaA10 3 , (Mn, Zn)Fe 2 0 4 , Hf, Zr, ZrN, Sc, ScN, NbN, TiN or a steric material (three-dimensional shape having a first predetermined thickness) of GaN or Any of the A1N substrates.
  • Si, GaAs, Ge, A1P, AlAs, AlSb, GaP, GaAs, GaSb, lnP, InAs, InSb, ZnO, ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgSe, HgTePbS may be deposited.
  • the growth substrate 201 of this example is exemplified by a silicon substrate.
  • the growth substrate 201 is divided by the groove 202 into separate flat regions for preventing thermal mismatch between the indium gallium aluminum nitride film and the silicon substrate.
  • the laminate produces cracks.
  • the depth of the groove 202 is greater than 3 microns
  • the width of the groove 202 is greater than 3 microns and less than 100 microns
  • the optimum parameter for the groove width is 10 microns
  • the groove depth optimum is 20 microns.
  • the shape of the independent flat region divided by the groove may be a square, a rectangle, a diamond, a triangle, or the like, and the optimal shape of the shape is a square.
  • the independent flat area is greater than 100 square microns.
  • 203 is an indium gallium aluminum nitride film epitaxially grown on a growth substrate which is divided into individual flat regions by a recess.
  • the indium gallium aluminum nitride film 203 is obtained by chemical vapor deposition (MOCVD), first in the lining. Forming a buffer layer on the bottom, and then depositing at least an N-type gallium nitride layer, an indium gallium nitride/gallium nitride multi-quantum well light-emitting layer, a P-type gallium nitride layer, and finally depositing or not depositing a layer on the P-type layer.
  • Indium gallium nitride cap layer of nanometer thickness.
  • the buffer layer of the indium gallium aluminum nitride film 203 in the figure may also be an alternating stack of aluminum nitride and gallium nitride, and the gallium nitride in the buffer layer may be in a stoichiometric ratio or a deviation ratio.
  • the impurity of the n-type layer of the indium gallium aluminum film 203 is generally silicon, and the impurity of the p-type layer is generally magnesium, and the quantum well may or may not be doped.
  • a layer of indium gallium nitride capping less than 5 nanometers is deposited on the P-type layer.
  • the purpose is to use the indium gallium nitride to exert a tensile stress on the surface of the gallium nitride, so that the polarization electric field of the P-type surface changes. , the hole concentration of the P-type surface is increased, thereby improving the performance of the P-type ohmic contact.
  • the indium gallium nitride cap layer may or may not be doped with magnesium, and the indium gallium nitride cap layer is optional, and the P-type layer is The cap layer may or may not be present, and the indium gallium nitride cap layer is considered to be part of the P-type layer.
  • Fig. 2-02 is a schematic cross-sectional view showing the p-type ohmic contact layer and the reflective layer 204 deposited on the epitaxial wafer.
  • the epitaxial wafer may be annealed to activate the Mg impurity to increase the hole concentration; or the ITO, the nickel oxide gold, the platinum-palladium nickel alloy, or the platinum may be first prepared on the epitaxial wafer. Any one of palladium nickel is alloyed, first ohmic contact is formed and a certain interfacial reaction occurs, and then removed, and then the reflective contact layer of the p-type ohmic contact layer and the reflective layer 204 is deposited.
  • the reflective contact layer may be pure silver; or may be a laminated structure composed of nickel and silver, the nickel layer may be continuous or discontinuous; or may be two or two of metals such as silver palladium platinum, lanthanum zinc, and the like.
  • the above alloy may also be an elemental metal; or an ohmic contact region may be regularly distributed on the surface of the epitaxial film, and the ohmic contact region other than the ohmic contact region may be a regional laminated structure, that is, adjacent to the p-type GaN.
  • the layers are regional array patterns, and then a metal reflective layer is deposited thereon which together form the p-type ohmic contact layer and reflective layer 204 shown in the figures; in summary the 204 layer has the dual effect of an ohmic contact layer and a reflective layer.
  • Fig. 2-03 is a schematic view showing the preparation of the first etching mask layer 205 after the 204 reflective contact layer is formed on the epitaxial wafer, which may be a photoresist or other photosensitive material.
  • the second-04 is a schematic view of the first etch mask layer 205 after the mask pattern is obtained, and the etched reflective layer is generally subjected to an oxygen plasma treatment to obtain a uniform and uniform mask effect after the mask pattern is obtained.
  • the mask complementary region 206 is to achieve a masking effect of the complementary electrode.
  • the first etch mask layer 205 has a mask rim region 207 near the recess 202.
  • Fig. 2-05 is a schematic view after etching the reflective contact layer. Since the mask complementary region 206 is not masked, the ohmic contact complementary region 208 is realized after the etching, thereby facilitating the improvement of the device luminous efficiency.
  • the p-type ohmic contact layer and the reflective layer 204 have an ohmic contact edge region 209 near the recess 202.
  • Fig. 2-06 is a schematic view showing the pattern of the p-type ohmic contact layer and the reflective layer required for the device after the mask layer is removed.
  • 2-07 are schematic views after the p-type ohmic contact layer and the reflective layer 204 are patterned on the epitaxial wafer, and then the deposited first transfer substrate 210 is formed thereon.
  • Fig. 2-08 is a schematic view showing the removal of the growth substrate, and thus the first transfer of the indium gallium aluminum nitride film from the growth substrate to the first transfer substrate 210 has been achieved.
  • the first transfer substrate 210 in the figure may be metal, non-metallic or organic. Only the first transfer substrate 210 is shown as a single layer structure in the drawing, which may be a laminated structure during actual fabrication. In this transfer, the stress from the growth substrate is completely released by the indium gallium aluminum nitride film, and partial release of the film stress can be achieved, and the film stress can also be adjusted.
  • the first transfer substrate 210 in the figure comprises a support substrate and a soft bonding material, and after the growth substrate is removed, the film can be freely stretched thereon, thereby obtaining stress Full release; to achieve partial release can be achieved by adjusting the elastic modulus of the bond material and its aging or solidification shrinkage, or by adjusting the self-stress of the electrochemical deposition or vacuum deposition substrate.
  • the adjustment of the film stress can be achieved.
  • the illuminating heat is simultaneously performed, and part of the input electric power is converted into heat, and the device has a certain junction temperature, which is bound to cause the supporting substrate (the final substrate) and the indium gallium aluminum. Thermal expansion of the nitrogen film.
  • L the stress of the LED during operation and when it is not: L (refer to the current, the same below) will be different.
  • the stress when the device is not working is also called the initial stress, and the stress when the device is working is also called the working stress.
  • the indium gallium aluminum nitride film will be under pressure due to the junction temperature during operation.
  • the stress has a certain effect on the luminous efficiency and reliability of the LED.
  • the indium gallium aluminum nitride film is a very polar material, and its polarization electric field changes when the stress changes.
  • the band gap of the LED light-emitting well layer, the tilt of the energy band, the surface charge distribution of the front and back sides of the LED indium gallium aluminum film, the interface charge distribution of the LED multilayer structure, the corresponding device operating voltage, wavelength, Luminous efficiency and reliability will change.
  • the first transfer substrate 210 may be formed into a gold-plated substrate, and the metal substrate may be realized by an electrochemical method or a vacuum deposition method.
  • the metal substrate layer is required to withstand corrosion of the silicon etching solution whether it is an elemental metal or an alloy.
  • the metal substrate may have different composition distributions in the thickness direction, or may have different density distributions. Different composition distributions and density distributions are mainly used to obtain different thermal expansion coefficient distributions in the thickness direction.
  • the metal substrate may be elemental chromium or an alloy containing chromium if it is an alloy that is resistant to corrosion by silicon etching solutions.
  • the metal substrate is considered to be an alloy composed of elemental chromium and stainless steel from the viewpoint of process simplicity.
  • the metal substrate may be deposited by one or a combination of methods such as arc ion plating, magnetron sputtering, electron beam evaporation, thermal evaporation, thermal spraying, and electroplating.
  • the optimal deposition method is multi-target arc ion plating and magnetron sputtering.
  • the most typical metal substrate deposition T. Art is as follows: On the rotating sample stage of the multi-arc ion plating system, an epitaxial wafer of a passivation layer and an ohmic contact layer is prepared on the chuck, so that the chip face is placed outward, making it tight Paste the sample rotary table.
  • the sample stage is provided with a water-cooling device, and the ambient temperature during the coating process can be placed continuously.
  • the system is pumped with the same ', and when the vacuum is lower than ⁇ 8 X 10 - 3 Pa, Ar gas is introduced into the vacuum chamber to maintain the vacuum at 0.5 Pa. Then, with the bias voltage, a piece of stainless steel with a thickness of 100 nanometers or more is plated on the epitaxial wafer. The purpose is because the thermal expansion coefficient of the stainless steel is larger than that of the indium gallium aluminum nitride film, so it will have a film of indium gallium and aluminum nitride.
  • a certain compressive stress acts so that the stress of the indium gallium aluminum nitride film which is originally subjected to tensile stress on the epitaxial wafer can be partially relaxed or even transformed into compressive stress after being transferred to a new gold substrate.
  • pure Cr and 316L stainless steel are simultaneously plated to form an alloy of pure Cr and 316L stainless steel.
  • the ambient temperature of the vacuum chamber will continuously increase. If the composition and density of the alloy substrate are uniform in the thickness direction, it will cause the metal substrate after etching the silicon substrate. bending. Elemental chromium and stainless steel have different coefficients of thermal expansion. The coefficient of thermal expansion of stainless steel is greater than the coefficient of thermal expansion of elemental chromium.
  • the coefficient of thermal expansion of R-density material is greater than the coefficient of thermal expansion of loose material. Therefore, by changing the composition distribution and density of the substrate, the coefficient of thermal expansion in the thickness direction can be changed, thereby changing the stress state and size of the indium gallium aluminum nitride film.
  • the change of composition is mainly achieved by the arc current of the two targets, and the change of the density is achieved by changing the conditions of the arc current and the bias voltage.
  • the tantalum metal substrate may also be elemental chromium, and the curvature and expansion coefficient of the substrate are controlled by changing the density in the thickness direction.
  • a relatively loose gold substrate can be plated to make the coefficient of thermal expansion substantially the same as the coefficient of thermal expansion of Ga, thereby improving the reliability of the device.
  • the metal substrate can be plated with dense plating. Slightly high and stainless; slightly higher substrate to achieve the large tensile stress experienced by the relaxed film. The film stress can be adjusted again in the next two steps or it can be no longer adjusted.
  • FIG. 2-09 is a schematic view of the substrate filler filled in the substrate recess 202, the purpose of which is to achieve contact exposure in the subsequent steps, thereby obtaining a more accurate pattern of the indium gallium aluminum nitride film.
  • the optimization scheme of the primary transfer substrate is an alloy substrate deposited on the epitaxial wafer with a thermal expansion coefficient matching the indium gallium aluminum nitride film, and it is a substrate obtained by co-depositing chromium and stainless steel. It can withstand various chemical and vacuum etchings in the subsequent chip processing.
  • Figure 2-10 shows the schematic diagram of the de-edge patterned mask layer deposited on the indium gallium aluminum nitride film after removing the recessed filler. It can be silicon dioxide, silicon nitride, silicon oxynitride or metal.
  • FIGS. 2-11 are schematic views of the second mask 212 after the photoresist is applied to the surface of the wafer to form other photosensitive materials.
  • 2-12 is a schematic view after the completion of the pattern lithography, in which the ⁇ 213 is the indium gallium aluminum nitride region to be removed, and the luminescent film of the region is affected by the groove boundary effect, if not removed, the device is required to be removed. Photoelectric performance and reliability are reduced.
  • 2-13 is a schematic view showing the pattern of the mask layer after the pattern lithography is completed, so that the indium gallium aluminum nitride film of the fourth region 214 is exposed.
  • FIGS. 2-14 are schematic views showing that the indium gallium aluminum nitride film in the vicinity of the fifth region 215 forms a sharp boundary after the edge indium gallium aluminum nitride film is removed, which effectively blocks the n-type layer and the p-type layer of the film from being opened.
  • the device is not connected by the thin film of the boundary to cause leakage of the device.
  • the method of removing the edge nitride is reactive ion etching, which may also be wet etching.
  • the reactive ion etched gas may be a gas containing chlorine or may contain other gases commonly used for etching gallium nitride.
  • the wet etching corrosive liquid may be phosphoric acid, sodium hydroxide or potassium hydroxide. When corroded, it may be irradiated with ultraviolet light or without ultraviolet light.
  • Figure 2-15 shows the schematic lik after removing the photoresist layer and the mask layer.
  • 2-16 is a schematic view after the passivation layer 216 is deposited on the surface of the chip pattern, and the passivation layer may be any one or a combination of the passivation layers described in the claims.
  • the passivation material may be It is one or more of silicon dioxide, silicon nitride, aluminum oxide, polyimide, and other common semiconductor passivation materials.
  • FIGS. 2-17 are schematic views after the passivation layer 216 is deposited on the surface of the chip pattern and then the third photoresist layer 217 is applied.
  • FIGS. 2-18 are schematic diagrams after the second photoresist layer 2 is patterned, in which the right ⁇ mask 218 and the left mask 220 are both etch mask layers of the chip side passivation layer, and the intermediate mask 219 is a patterned mask pattern that facilitates pattern plating in a subsequent step, and a gap 221 is a pattern that separates the left mask 220, the intermediate mask 219, and the right mask 218 from each other.
  • FIGS. 2-19 are schematic views of the passivation layer 216 after being patterned and etched.
  • FIGS. 2-20 are schematic views after removing the photoresist mask layer, the right passivation layer 222 and the left passivation layer 224 are side passivation patterns, and the intermediate passivation layer 223 is a pattern set for subsequent pattern plating. .
  • Fig. 2-21 is a schematic view of a patterned textured layer obtained by adding light to the surface of the indium gallium aluminum nitride film, also called roughening
  • the roughened surface 225 is a schematic view of the nitride film after roughening.
  • the surface roughened shape may be a hexagonal pyramid shape, a hexagonal prism shape, a cylindrical shape, a conical shape, and a columnar ring shape.
  • the method of forming the surface roughening may be one of photoelectrochemical etching and ICP etching, or a combination of the two methods. If photoelectrochemical etching is used, the etchant may be phosphoric acid or potassium hydroxide or sodium hydroxide.
  • the method of obtaining the roughened pattern is selected so as not to damage the passivation layer. For example, if polyimide or silicon dioxide is used as the passivation layer, the nitride cannot be roughened with alkali.
  • I I 2-22 is a schematic view of the n-type electrode and the pad layer 226 after the indium gallium aluminum nitride film is subjected to roughening treatment.
  • the most preferable ⁇ of the n-type electrode and the pad layer 226 is Al/Ti/Au, and may be a structure of an ohmic contact electrode of a common n-type Ga such as Al Ni/Au or Cr/Au, and a structure of a disk, or may be only There is a layer of elemental aluminum, which may be a gold-nickel alloy, a gold-silicon alloy, a titanium nitride, an alloy containing titanium aluminum, or a gold-nickel-nickel, a gold-silicon, a titanium nitride, or Two or more combinations of titanium aluminum.
  • the n-type electrode and the pad layer 226 may be formed by evaporation or sputtering, or may be formed by electrochemical methods such as electroplating and electroless plating.
  • 2-23 are schematic views of the fourth photoresist layer 227 coated on the n-type drain pad layer 226.
  • FIGS. 2-24 are schematic views after the photoresist layer 227 is patterned, and a fourth patterned photoresist layer 228 is obtained, which will serve as a mask layer for the etching electrode layer in the subsequent process.
  • the four patterned photoresist layer 228 has its position on the chip corresponding to the ohmic contact complementary regions 208 of the P-type ohmic contact layer and reflective layer 204.
  • Fig. 2-25 is a schematic view after the photoresist layer is patterned and a turbulent conduction layer 229 is deposited thereon.
  • 2-26 are schematic views of the first transfer substrate 210 after the spin coating of the protective layer 230.
  • the preferred embodiment of the current conducting layer 229 is a nickel layer.
  • the preferred embodiment of the protective layer 230 is a photoresist.
  • Fig. 2-27 is a schematic view of electroplating a second transfer substrate 231 on a vacuum deposited layer, and a preferred embodiment is electroplating nickel and nickel plating using a nickel sulfate system.
  • the composition of the ruthenium plating solution is: 270 g/L of nickel sulfate, 60 g/L of nickel chloride, 45 g/L of boric acid, 0.5.ml/L of brightener, 20 ml/L of sizing agent, I.5 ml/L of humectant; 3 ⁇ 4 plating conditions
  • the temperature is 60 °C
  • the pH is 4.5
  • the cathode current density is 5 A/dm2
  • the deposition rate is 0.6 ⁇ m/min
  • the anode is a seesaw.
  • 2-28 are schematic views after the second transfer substrate 231 of metallic nickel is plated, and then the first transfer substrate 210 and the protective layer 230 are removed.
  • the acetone is boiled for 5 minutes, the alcohol is bubbled for lmin, and the ionized water is washed for 10 minutes to remove the protective layer 230.
  • the first transfer substrate 210 is deplated by electrochemical method, and the deplating solution is: sodium carbonate 250 g/L, phosphoric acid Disodium hydrogenation 10g / L, deplating conditions are: anode current density 10A / dm2, temperature is room temperature, the cathode is a low carbon steel plate.
  • the indium gallium aluminum nitride film realizes the second transfer.
  • the secondary transfer can adjust the stress or not adjust the stress.
  • the method of adjusting the stress is to change the second transfer liner of the electroplated nickel.
  • the plating conditions of the bottom 231 are achieved. .
  • 2-29 are schematic views after deplating the first transfer substrate 210 and then vacuum depositing the copper metal layer 232 on the p-type side of the chip array.
  • FIG. 2-30 is a schematic view of the fifth photoresist layer 233 patterned on the copper gold layer 232.
  • Fig. 2-31 is a schematic view after the fifth photoresist layer 233 is patterned, and the sixth region 234 is a patterned region where the copper layer is exposed.
  • Fig. 2-32 is a schematic view showing the copper metal layer 232 obtained by patterning, and the seventh region 235 is a region for patterning the copper layer corresponding to the reserved region of the intermediate passivation layer 223.
  • Figure 2-33 is a schematic view showing the removal of the fifth photoresist layer 233.
  • 2-34 is a schematic view after the second photoresist protective layer 236 is applied on the 3 ⁇ 4 side of the second transfer substrate 231.
  • Figure 2-35 is a schematic view of the patterned copper-gold buckling layer 232 after the second transfer substrate 237 is plated.
  • the passivation material at the intermediate passivation layer 223 during the ruthenium plating process has a barrier to the erbium-plated Lti flow. So that the area is not plated with metal, so that the third transfer liner is electroplated
  • the bottom 237 becomes a separate array, and the eighth region 238 indicates that the plating substrates of the respective chips are independent of each other. If individual areas are stuck together during the plating process, they can be ground to separate and flatten each pattern substrate, or lithographically etch the adhesion sites apart.
  • the patterned substrate may be a ruthenium-plated elemental copper substrate, a "copper/nickel/copper” laminate substrate, a nickel-cobalt alloy plating substrate, or a seed crystal. 3 ⁇ 4 layer combination of plating. After the substrate plating is completed, a gold layer of 0.2 ⁇ m or more is finally plated as a protective layer for the substrate oxidation prevention.
  • Figure 2-36 is a schematic view of a chip array of a plated patterned substrate bonded to another support substrate 240 by a bonding material 239, wherein the bonding material 239 is a conductive conductive material.
  • the support substrate 240 is a metal substrate having electrical conductivity, for example, a stainless steel substrate or a copper substrate or the like.
  • Figure 2-37 is a schematic view of the second photoresist protective layer 236 on the second transfer substrate 231, and the second transfer substrate 231 is deplated, and the electrode pattern is etched.
  • Figure 2-38 is a schematic view of the fourth patterned photoresist layer 228 on the electrode, wherein 241 is an electrode-formed n-type electrode and pad layer.
  • 241 is an electrode-formed n-type electrode and pad layer.
  • the indium gallium aluminum nitride film has completed the entire secondary transfer and releases and adjusts the stress transfer process.
  • the photoelectric array ⁇ moving point measurement can be performed on the chip array.
  • Figure 2-39 is a schematic view of a blue or white film 242 bonded to a chip array.
  • the blue or white film 242 can also be assimilated with a wax or rosin or hot sol or other thermal light using a support substrate.
  • the glue is replaced by a support substrate.
  • FIGS. 2-40 are schematic views of the bonding material (conductive paste) 239 and the supporting substrate 240.
  • Fig. 2-41 is a schematic view of the chip after conventional film tumbling and sorting, in which the sorting film 243 represents a sorting film carrying the chip. At this point, the entire chip processing process is completed, and the stress on the chip's indium gallium aluminum nitride film is released.
  • This embodiment adopts a method of pattern plating a substrate to avoid the problem that the gold substrate is difficult to cut.
  • the processes and methods for the first and second film transfer in the present embodiment are the same as those in the first embodiment, but the mode of the third transfer is different from that of the first embodiment.
  • the next step is to deposit a barrier layer and a pressure-welded metal layer on the p-type ohmic contact layer and reflective layer 204, and then bond it together with a substrate. Instead of graphic plating.
  • the barrier layer is composed of a laminate or alloy of one or more of several metals such as titanium, calcium, nickel, platinum, gold, palladium, chromium, vanadium, zirconium, molybdenum, etc., which are evaporated or sputtered in a p-type ohmic contact.
  • a pressure-welded metal layer is deposited on the barrier layer.
  • the pressure-welded metal may be a common reflow solder paste material, or a common eutectic gold-zinc evaporation or sputtering layer, or may contain palladium, indium, or the like.
  • An alloy consisting of gold, tin, lead, platinum, nickel, silver, etc. ⁇ , the copper metal layer 232 of Figures 2-28 in this embodiment is replaced by a metal layer S layer composed of a barrier layer and a pressure solder layer.
  • the second transfer substrate is removed, and then the bonding substrate is cut to perform dicing.
  • Fig. 3-01 to Fig. 3-10 are diagrams for explaining the method of obtaining the stress of releasing and adjusting the indium gallium aluminum nitride film according to the present invention by the three-transfer method and the process of obtaining the structure of the light-emitting device.
  • the present embodiment differs from the previous two embodiments in that: the third transfer of the first embodiment and the second embodiment is to transfer the indium gallium aluminum nitride film onto the difficult-to-cut metal substrate, and the present embodiment is a film. Transferring on a easily secritable substrate; in this embodiment, the film is transferred onto a continuous flat substrate, and the chip is formed after the chip patterning process is completed.
  • the first transfer of the present embodiment is the same as that of the embodiment and the second embodiment except that the passivation layer pattern which is advantageous for blocking the plating current, that is, the intermediate passivation layer 223 in the first embodiment, is not required.
  • the description of the present embodiment begins with the steps of completing one transfer, and has completed the steps of nitride de-edge patterning, passivation layer patterning, and surface roughening.
  • 3-01 is completed a transfer, that is, the indium gallium aluminum nitride film is transferred from the growth substrate to the first transfer substrate 305, and the patterning of the nitride side, the patterning of the passivation layer, and the roughening of the surface are completed.
  • 301 is an indium gallium aluminum nitride film
  • 302 is an ohmic contact reflective layer
  • 303 is a passivation layer
  • 304 is a roughened pattern. The basic requirements of these constructs have been explained in Embodiment 1 and Embodiment 2, and the description thereof will not be repeated here.
  • FIG. 3-02 is a schematic view showing a metal conduction layer 306 deposited on the surface of the chip pattern array, and the gold-conducting layer may be a high melting point, It may also be a low melting point metal or an alloy. It may be one or more of platinum, palladium, gold, silver, copper, iron, titanium, zinc, tin, tungsten, molybdenum, vanadium, zirconium, indium, nickel, aluminum, magnesium, chromium, and the like. a laminate, or an alloy layer composed of two or more of them.
  • the deposition method may be one or a combination of sputtering, evaporation, spraying, electroplating, electroless plating.
  • Figure 3-03 is a schematic view of the back side of the first transfer substrate 305 coated with an anti-plating protective layer 307.
  • the thermal expansion coefficient of the second transfer substrate 308 is either the second of the third transfer.
  • the thermal expansion coefficient of the transfer substrate 31 i is matched or matched to the thermal expansion coefficient of the indium gallium aluminum nitride film 301.
  • the second transfer substrate 308 can also be obtained by other germanium chemical methods and vacuum deposition methods other than electroplating. If the vacuum method is obtained and prepared, the protective layer 307 in the previous step is not necessary.
  • the coefficient of thermal expansion of the second transfer substrate 308 can be adjusted by controlling the composition and density of the substrate preparation, or it can be patterned to adjust the macroscopic thermal expansion coefficient, for example, if the second transfer substrate 308 is copper.
  • the substrate can then be hollowed out through two-thirds of the area of the substrate to achieve a coefficient of thermal expansion that matches the gallium nitride.
  • a preferred preparation of the second transfer substrate 308 is electroplating and is a hollow plated substrate.
  • Figure 3-05 is a schematic diagram after completion of the preparation of the second transfer substrate 308 and removal of the first transfer substrate 305 and its protective layer 307. After completing this step, the indium gallium aluminum nitride film achieved the second transfer.
  • 3-06 is a schematic view of the diffusion barrier layer and the pressure-welded metal layer 309 after the surface of the chip array is prepared.
  • the basic features and requirements of the diffusion barrier layer and the pressure-welded metal layer 309 have been described in Embodiment 2. This is not repeated.
  • Figure 3-07 is a schematic view of the chip array after pressure bonding the third transfer substrate.
  • reference numeral 310 denotes a bonding soldering gold layer which is fused together between the chip and the substrate.
  • the layer includes a diffusion barrier layer on the side of the indium gallium aluminum nitride film and a third layer in addition to the soldering gold layer.
  • the 3 12 layers in the figure are the second protective layer of the back metal of the third transfer substrate, which is ohmic contact with the substrate.
  • the second transfer substrate can be a silicon substrate, a germanium substrate, a graphite substrate, a gallium arsenide substrate, and other non-gold-bending substrates that are easily cut and guided.
  • Figure 3-08 is a schematic illustration of the removal of the second transfer substrate 308 and the metal conduction layer 306.
  • FIG. 3-09 is a schematic diagram of the n-type electrode and the pad 313 after the chip array is prepared. The basic characteristics and requirements of the n-type electrode and the pad have been described in the embodiment 1, and the description will not be repeated here. .
  • Figure 3-10 is a schematic diagram of the chip array after cutting the discrete devices.
  • the cutting method can be common mechanical cutting, laser cutting, waterjet cutting, water jet waveguide laser cutting, water column blasting, multi-line sawing with sand cutting, or It is a silicon carbide scratch cleavage cutting, or it can be an electric spark cutting, or a chopping chip cutting, or a combination of the above several cutting methods.
  • a preferred method of cutting is mechanical cutting.
  • Fig. 4-01 to Fig. 4-1 1 illustrate a method for obtaining stress for releasing and adjusting an indium gallium aluminum nitride film according to the present invention by a three-time transfer method, and a method and a process for obtaining a structure of the light-emitting device.
  • the difference from the several embodiments described above is that the step of de-edge, roughening, and n-thinning of the indium gallium aluminum nitride film is performed after the completion of the third transfer, that is, except p
  • the patterning of the ohmic contact electrode is performed on the epitaxial wafer prior to transfer, and other graphical work is performed after the completion of the third transfer step.
  • Figure 4-01 is a schematic cross-sectional view showing the transfer of the indium gallium aluminum nitride film from the growth substrate to the first transfer substrate 403 after a transfer is completed.
  • 401 is an indium gallium aluminum nitride film
  • 402 is an ohmic contact reflective layer
  • 404 is a metal conduction layer deposited on the surface of the chip array.
  • 4-02 is a schematic view showing the deposition of a second transfer substrate 405 on the conduction layer 404 of the on current.
  • the basic features and basic requirements of the conductive layer 404 and the second transfer substrate have been described in the foregoing embodiments, and the description thereof will not be repeated here.
  • Figure 4-03 is a schematic view after completion of the preparation of the second transfer substrate 405 and removal of the first transfer substrate 403. After completing this step, the indium gallium aluminum nitride film achieved the second transfer.
  • FIG. 4-04 is a schematic diagram after the diffusion barrier layer and the bonding metal layer 406 are prepared on the surface of the chip array.
  • the basic features and requirements of the diffusion barrier layer and the bonding bonding metal layer 406 have been carried out in the foregoing embodiments. Note, the description will not be repeated here.
  • 4-05 is a schematic view of the chip array and the second transfer substrate after pressure bonding.
  • Reference numeral 407 in the figure denotes a bonding weld gold layer which is fused together between the chip and the substrate.
  • 408 denotes a third transfer substrate.
  • the protective layer 409 in the figure is the back metal protection of the third transfer substrate. The sheath, which is required to be in ohmic contact with the substrate.
  • 4-06 is a schematic view of the second transfer substrate 405 and the conduction layer 404 after removal. After completing this step, the indium gallium aluminum nitride film achieved the third transfer.
  • Figure 4-07 is a schematic diagram of a roughened pattern formed on the chip array to facilitate light extraction.
  • 4]0 represents a roughened pattern.
  • the basic features and basic requirements for forming the roughened graphics 410 have been described in the previous embodiments, and the description thereof will not be repeated here.
  • 4-08 is a schematic view after removing the nitride at the edge of the chip array, where the position indicated by the first region 41 1 is the position after the edge nitride is removed, and the basic features and basic requirements of the method and process for removing the edge nitride are shown. It has been explained in the previous embodiment, and the description will not be repeated here.
  • Figure 4-09 is a schematic diagram showing the formation of a passivation antireflection layer on the surface of the chip array, in which 412 is a passivation antireflection layer.
  • the position indicated by the second region 413 in the figure is the position where the passivation layer is not passivated, and the passivation layer of the bit S is removed for the purpose of forming the n-electrode metal and the wire bonding pad.
  • the basic features and basic teachings of the method and process for forming the passivation anti-reflection layer 412 have been described in the previous embodiments and will not be repeated here.
  • FIGS. 4-10 are schematic views showing the formation of the n-electrode and the lead pad 414 on the surface of the chip array.
  • the basic features and basic requirements have been described in the foregoing embodiments, and the description thereof will not be repeated here.
  • Figure 4-1 1 is a schematic view after the chip array is cut into discrete components, the third region 415 is the location where the incision is located, the method of forming the third region 415 and the basic features and basic requirements of the implementation are implemented in the foregoing. It has been explained in the manner, and the description will not be repeated here.
  • the present embodiment is the same as the method described in the fourth embodiment in that the patterning step of de-edge, roughening, and n-electrode of the indium gallium aluminum nitride film is performed after the completion of the third transfer, and the difference is as follows.
  • the conductive layer 404 used for the second transfer is not a metal layer, but an organic substance capable of effectively releasing or adjusting the stress state of the indium gallium aluminum nitride film.
  • the basic characteristics of the organic material are: wax, hot melt adhesive, rosin, UV curable adhesive, bonding gel, resin, and other one-component or two-component or multi-component organic glue, which can be thermal assimilation
  • the organic matter may also be a hot-melt organic substance, a photocurable organic substance, or an organic substance that can be reacted and cured. It may be a thermosetting adhesive, a hot melt adhesive, a room temperature curing adhesive, or a pressure sensitive adhesive.
  • the conductive layer 404 may be an organic layer as described above, or a laminated structure composed of two organic materials, or a multilayer laminated structure of two or more organic materials, or may be a mixture of a plurality of organic substances.
  • a curable bond or binder is prepared.
  • the conductive layer 404 may be such that the stress of the indium gallium aluminum nitride film is released because the layer is soft; or the indium gallium aluminum may be formed because the organic layer has a certain curing shrinkage rate or curing expansion ratio during curing.
  • the tensile stress of the nitrogen thin film becomes smaller or larger (the compressive stress becomes larger or smaller), thereby realizing the adjustment or release of the stress of the indium gallium aluminum nitride film.
  • Embodiment 6 ' is a diagrammatic representation of Embodiment 6 .
  • the present embodiment differs from the methods described in Embodiments 4 and 5 in that the conduction layer 404 used for the second transfer is neither a metal layer nor a physical layer, but a curable inorganic non-metal. material.
  • the basic feature of the inorganic non-gold-based bonding material used for the conductive layer 404 is that it is one or a mixture of a silicate, a phosphate, an oxide, a sulfate, a borate, and the like. It can be an air-drying type of inorganic adhesive, depending on the solvent or solvent to volatilize or lose moisture, such as water glass and clay; it can also be a water-curing inorganic adhesive, which uses water as a curing agent, adding water. Produces a chemical reaction to cure, such as gypsum and cement; it can also be a hot melt inorganic adhesive, such as low melting glass, low melting glass ceramics and sulfur, and other common inorganic hot melt adhesives.
  • Adhesive can also be an inorganic binder of chemical reaction, assimilated by the addition of an anabolic agent to produce a chemical reaction, such as silicate-based adhesives, phosphate-based adhesives, colloidal alumina, and dental Glue adhesive, etc. It may be a combination of cement, gypsum, water glass, lime, clay, inorganic salts (phosphates and silicates) composed of low molecular compounds, etc., which may be composed of an inorganic adhesive.
  • the single-layer structure of the composition may also be a 3 ⁇ 4 layer structure composed of a plurality of inorganic binders, or a laminate or a single layer structure of a mixture of them.
  • the conduction layer 404 may be adjusted or released by stress or contraction of the indium gallium aluminum nitride film due to shrinkage or expansion when the layer is assimilated.
  • This embodiment differs from the first embodiment already described above in that, in the process of patterning the chip before the first transfer, in addition to forming a p-type ohmic contact reflective layer, a pattern is formed thereon.
  • Surface passivation layer the effect of this layer may not be completely designed to passivate the p-plane, it may be to maintain the stress state of indium gallium aluminum nitrogen, or increase stress recovery, or reduce stress recovery, or reduce Substrate transfer over 3 ⁇ 4 of the substrate preparation ⁇ : the effect of the art on the stress of the film is set, or may be used to enhance the chip manufacturing yield to enhance the mechanical strength of the indium gallium aluminum nitride film and set S, This layer can be present in the device last or not in the device.
  • Figure 5-01 is a schematic diagram of the patterning of the p-side passivation layer on the epitaxial wafer.
  • 501 is a growth substrate
  • 502 is a groove for dividing the growth substrate into independent flat regions
  • 503 is an indium gallium aluminum nitride film layer
  • 504 is a p-plane passivation layer
  • Fig. 5-02 is a schematic view after the ohmic contact reflective layer 505 is patterned on the epitaxial wafer.
  • the basic features and basic requirements of the ohmic contact reflective layer 505 have been described in the foregoing embodiments, and the description thereof will not be repeated here.
  • Fig. 5-03 is a schematic view showing the formation of a gold-plated layer 506 on the epitaxial wafer. The basic features and basic requirements of this layer have been described in the previous embodiments, and will not be repeated here.
  • the substrate may be bond bonded to the epitaxial wafer, or plated on the epitaxial wafer, or adhered to the epitaxial wafer with an adhesive.
  • the basic requirements of the first transfer substrate 507 and the protective layer 508 on the back side thereof are in accordance with the basic requirements of the substrate and back protective layer in the related embodiments already described. If it is a bonding metal substrate, the basic requirements of the bonding layer and the back protective layer are also in line with the related content already described above:
  • the gold substrate can also be a metallurgical layer 506 without metal, but The relevant adhesive bond has been described previously.
  • the pressure-welded metal layer 506 may be a low-melting gold yt, or may be an adhesive, or may directly heat the organic substrate and the epitaxial wafer together without using an adhesive. The substrate melts to soften at the bonding interface, and then cools the condensation between the epitaxial wafer.
  • Figure 5-05 is a schematic view of the growth substrate after the epitaxial wafer is bonded or bonded to the first transfer substrate.
  • the method of removing the substrate may be a combination of one or more of laser lift-off, chemical etching, mechanical polishing, chemical mechanical polishing, ion physical etching, and reflection ion etching.
  • the most preferred solution for removing the substrate for silicon substrates is chemical etching, and the most optimized solution for sapphire substrates is laser lift-off. So far the chip has completed a transfer.
  • Figure 5-06 is a schematic illustration of bonding the chip array to the second transfer substrate 510 through the bonding layer 509 after removing the transfer substrate once.
  • the bonding layer 509 may be a deposited gold layer, and the second transfer substrate 510 is a plating substrate on the metal layer, and the stress is adjusted by a substrate plating process: the bonding layer 509 may be a metal bonding layer.
  • the second transfer substrate 510 is a pressure-bonded substrate, and the stress is adjusted by the bonding temperature, the thermal expansion coefficient of the substrate, the melting point and composition of the bonding layer; the bonding layer 509 may be an adhesive, and the second transfer liner
  • the bottom 510 may be an organic, inorganic or inorganic non-metallic substrate, and its stress on the indium gallium aluminum nitride film 503 is adjusted by a combination of a shrinkage ratio or a chemical expansion ratio or an assimilation temperature of the adhesive or several conditions.
  • Figure 5-07 is a schematic view after removing the secondary transfer substrate.
  • the indium gallium aluminum nitride film realizes the secondary transfer and the stress release and adjustment.
  • ISI 5-08 is a schematic diagram of the chip array and the three transfer substrates are pressure bonded together.
  • 5 ⁇ denotes a three-transfer bonding layer
  • 512 denotes a second transfer substrate
  • a second protective layer 513 denotes a protective layer on the back surface of the substrate.
  • Pressure bonding layer 511, third transfer substrate 512, and The basic design and basic features of the two protective layers 513, and the method of adjusting the stresses thereof have been described in the foregoing embodiments, and the description thereof will not be repeated here.
  • Figure 5-09 is a schematic view showing the removal of the second transfer substrate 510 and the bonding layer 509. After completing this step, the indium gallium aluminum nitride film achieved the third transfer. .
  • 5-10 are schematic views of the chip array with the groove fill at the location of the first region 514 removed.
  • 5-11 are schematic views after roughening the surface of the chip array, wherein 515 represents a roughened pattern, and the forming method and basic features and basic requirements have been explained in the foregoing embodiments, and no longer fi ' Repeat instructions.
  • FIG. 5-12 are schematic views of the chip array edge nitride after removing the second region 516 bits S.
  • the formation method, basic features and basic requirements have been described in the previous embodiments, and are not described here.
  • 5-13 are schematic views showing the formation of a passivation antireflection layer on the surface of the chip array, and 517 in the figure indicates a passivation antireflection layer.
  • the position indicated by the third region 518 in the figure is the position where the passivation layer is not passivated, and the passivation layer of this position is removed for the purpose of forming the n-electrode metal and the wire bonding pad.
  • FIG. 5-14 are schematic views showing the formation of n 3 ⁇ 4 poles and lead pads 519 on the surface of the chip array, the basic features and basic requirements of which have been described in the previous embodiments, and are not described here.
  • 5-15 are schematic views after the chip array is cut into discrete components, the fourth region 520 is the location where the incision is located, the method of forming the fourth region 520, and the basic features and basic requirements of the claim are in the foregoing embodiments. It has been explained that the description will not be repeated here.
  • the embodiment is different from the previously described embodiment in that the element referred to in the P-side passivation layer 504 in FIG. 5-01 is replaced by a metal layer having a thermal expansion coefficient larger than that of GaN, and the thermal expansion coefficient may be smaller than A non-metallic layer of GaN.
  • first transfer and the second transfer are both transferred by an adhesive, by adjusting the fouling expansion rate or the ISI shrinkage rate of the adhesive.
  • the flexible adhesive can achieve stress adjustment and release
  • the third transfer can be achieved by common bonding technology or electroplating technology.
  • the 6-01 is a schematic view of the indium gallium aluminum gas epitaxial film (i.e., indium gallium aluminum nitride film) 602 formed on the growth substrate 601.
  • the growth substrate 601 is a uniform continuous substrate which is not divided by grooves or projections, and the indium gallium aluminum nitride epitaxial film 602 is a uniformly associated epitaxial film formed on the growth substrate.
  • Fig. 6-02 is a schematic view showing the indium gallium aluminum film on the epitaxial wafer being etched into an array, and the p-side passivation layer 603 is formed.
  • the basic features and basic requirements of the p-face passivation layer 603 have been explained in the foregoing embodiments, and the description thereof will not be repeated here.
  • Fig. 6-03 is a schematic view showing the formation of the adhesive layer 604 on the epitaxial wafer.
  • the choice of the type of adhesive used in the adhesive layer 604 is selected according to the stress of the indium gallium aluminum nitride layer. If the indium gallium aluminum nitride epitaxial film 602 is subjected to tensile stress, the assimilated shrinkage adhesive is selected, if indium gallium aluminum The nitrogen epitaxial film 602 is subjected to compressive stress to select an adhesive which is expanded, and the flexible adhesive may be selected irrespective of the stress applied to the indium gallium aluminum nitride epitaxial film 602.
  • the basic features and basic requirements of the adhesive have been described in the foregoing embodiments, and the description thereof will not be repeated here.
  • Figure 6-04 is a schematic view of the first transfer substrate 606 after the epitaxial wafer is bonded to the substrate by the cured adhesive layer 605.
  • Figure 6-05 is a schematic view of the growth substrate after removal. The basic features and basic requirements of the method of removing the substrate have been described in the previous embodiments and will not be described again here. At this point, the chip has been transferred once, and the stress of the indium gallium aluminum nitride epitaxial film 602 is adjusted or released by the adhesive being cured by shrinkage or expansion or because it is flexible.
  • Figure 6-06 is a schematic illustration of the bonding of the chip array to the second transfer substrate 608 by bonding layer 607 after removal of the transfer substrate.
  • the bonding layer 607 can also adjust and release the stress of the indium gallium aluminum nitride epitaxial film 602 by selective expansion or l?r
  • Figure 6-07 is a schematic illustration of the removal of the second transfer substrate. At this point, the indium gallium aluminum nitride film achieves secondary transfer and the stress release and adjustment described.
  • Figure 6-08 is a schematic diagram of the chip array and the second transfer substrate are pressed together.
  • 609 denotes a three-transfer bonding layer
  • 610 denotes a third transfer substrate
  • 61 1 denotes a protective layer on the back surface of the substrate.
  • the basic design and basic features of the bonding layer 609, the third transfer substrate 610, and the protective layer 611, and the method of adjusting the stress thereof have been described in the foregoing embodiments, and the description thereof will not be repeated here.
  • Figure 6-09 is a schematic & I after removing the second transfer substrate. After completing this step, the indium gallium aluminum nitride film achieved the third transfer.
  • 6-10 is a schematic diagram after the surface roughening treatment of the chip array, and the forming method, basic features and basic requirements have been described in the foregoing embodiments, and will not be described again here.
  • 6-11 are schematic diagrams showing the removal of nitride at the edge of the chip array.
  • the forming method, basic features and basic requirements have been described in the previous embodiments, and will not be described here.
  • 6-12 are schematic views showing the formation of a passivation antireflection layer on the surface of the chip array, and 612 represents a passivation antireflection layer.
  • the position indicated by the first region 613 in the figure is the position where the passivation layer is not passivated, and the passivation layer of this position is removed for the purpose of forming the n-electrode metal and the wire bonding pad.
  • the basic features and basic requirements of the method and process for forming the passivation antireflection layer have been described in the foregoing embodiments, and the description thereof will not be repeated here.
  • FIG. 6-13 are schematic views showing the formation of the n-pole and the lead pad 614 on the surface of the chip array.
  • the basic features and basic requirements have been described in the foregoing embodiments, and will not be described again here.
  • FIGS. 6-14 are schematic views after the chip array is cut into discrete components, the second region 615 is where the incision is located, the method of forming the second region 615, and the basic features and basic requirements of the claim are in the previous embodiment. It has been explained that the description will not be repeated here.
  • Embodiment 10' The embodiment of the present embodiment described above differs in that: in order to make the device have high light-emitting efficiency, the p-side passivation layer and the ohmic contact reflective layer are after the completion of the second transfer, ⁇ ⁇ 3 times before the bonding, so the indium gallium aluminum nitride film of the device has a reflective layer to increase the light output effect, and the reflective layer does not need to be patterned.
  • Figure 7-01 is a schematic diagram of an epitaxial wafer.
  • the growth substrate 701 is divided by the groove 703 into an array of independent flat regions, and 702 is an indium gallium aluminum nitride epitaxial film.
  • the basic features and basic requirements of the growth substrate 701, the indium gallium aluminum aluminide epitaxial film 702 and the recess 703 have been explained in the foregoing embodiments, and the description thereof will not be repeated here.
  • Fig. 7-02 is a schematic view showing the formation of a ⁇ 3 ⁇ 4 ohm contact sacrificial layer 704 on the epitaxial wafer.
  • the layer may be one or more alloys of nickel, nickel oxide gold, ruthenium or an alloy thereof, platinum or an alloy thereof, indium tin oxide, or the like, which may be passed after completion of depositing a p-type ohmic contact sacrificial layer 704 layer. Alloy annealing treatment achieves ohmic contact.
  • Fig. 7-03 is a schematic view after the filling 705 is prepared at the groove of the epitaxial wafer.
  • the filler may be a metal or an organic material such as a photoresist.
  • Fig. 7-04 is a schematic view showing the formation of the ruthenium-plated conductive layer 706 on the epitaxial wafer.
  • FIG. 7-05 shows a schematic diagram of the first transfer substrate 707 and the back surface protection layer 708 after the epitaxial wafer is plated on the epitaxial wafer.
  • the basic features and basic requirements have been explained in the foregoing embodiments, and the ffi complex is no longer used here. Description.
  • Figure 7-06 is a schematic illustration of the removal of the growth substrate 70! and the recess fill 705.
  • the basic features and basic requirements of the method of removing the substrate have been described in the previous embodiments and will not be repeated here.
  • the chip has completed a transfer.
  • the stress of the indium gallium aluminum nitride film can be adjusted by changing the plating conditions of the substrate, or it can be adjusted.
  • 7-07 is a schematic view of the chip array bonded to the second transfer substrate 710 by the bonding layer 709 after the transfer substrate is removed once.
  • the stress of the indium gallium aluminum nitride layer is adjusted and released by selecting the swell expansion ratio of the bonding layer 709 to the iodine shrinkage rate or the flexible adhesive.
  • Figure 7-08 is a schematic illustration of the removal of the first transfer substrate 707, the removal of the protective layer 708 of the transfer substrate, the removal of the transfer bonding layer 709, and the removal of the P-type ohmic contact sacrificial layer 704.
  • the indium gallium aluminum nitride film achieves secondary transfer and the stress release and adjustment described.
  • Fig. 7-09 is a schematic view showing the formation of the p-side passivation layer 71 1 on the indium gallium aluminum thin film.
  • Fig. 7-10 is a schematic view showing the formation of the composite layer 712 on the indium gallium aluminum nitride film.
  • the layer includes an ohmic contact reflective layer, a diffusion barrier layer, and a pressure-welded adhesive layer, the basic features and basic teachings of which have been described in the foregoing embodiments, and the description thereof will not be repeated here.
  • Figure 7- 1 1 is a schematic view of the chip array and the second transfer substrate after pressure bonding.
  • 713 denotes a three-transfer bonding layer
  • 714 denotes a second transfer substrate
  • 715 denotes two protective layers on the back surface of the substrate.
  • the basic requirements and basic features of the bonding layer 713, the three transfer substrates 714 and the second protective layer 715, and the method of adjusting the stresses thereof have been described in the foregoing embodiments and will not be repeated here.
  • FIG. 7 to 12 are schematic views showing the removal of the second transfer substrate 710 and the adhesive layer 709 jfj. After this step, the indium gallium aluminum nitride film achieved the third transfer.
  • Figure 7-13 is a schematic diagram of the surface roughening process of the chip array.
  • 716 represents a roughened figure, and its formation method and basic characteristics The claim has been explained in the foregoing embodiments, and the description will not be repeated here.
  • Fig. 7-14 is a schematic view showing the removal of nitride at the position of the first region 717 of the edge of the chip array, and the basic features and requirements of the method for forming the same have been described in the previous embodiments, and the description thereof will not be repeated.
  • FIG. 7-15 are schematic views of the passivation antireflection layer 718 and the n-type electrode and pad 719 formed on the surface of the chip array.
  • the basic features and basic teachings of the methods and processes for forming 718 and 719 are illustrated in the previous embodiments and will not be repeated here.
  • Embodiment 1 1 is a diagrammatic representation of Embodiment 1 1
  • Embodiment 9 differs from Embodiment 9 in that both the first transfer and the second transfer are bonded by the adhesive to the substrate, and the third plating is transferred.
  • Figure 8-01 is a schematic diagram of an epitaxial wafer.
  • the growth substrate 801 is divided by the groove 803 into an array of independent flat regions, and 802 is an indium gallium aluminum nitride epitaxial film.
  • the basic features and basic requirements of the growth substrate 801, the recess 802, and the indium gallium aluminum nitride epitaxial film 803 have been described in the foregoing embodiments, and the description thereof will not be repeated here.
  • Fig. 8-02 is a schematic view showing the p-type ohmic contact sacrificial layer 804 formed on the epitaxial wafer. The basic features and basic requirements of this layer have been explained in the previous embodiments, and the description will not be repeated here.
  • FIG. 8-03 is a schematic view of the epitaxial wafer bonded to the first transfer substrate 806 by the adhesive layer 805.
  • the basic features and basic requirements have been explained in the foregoing embodiments, and will not be repeated here. Description.
  • Figure 8-04 is a schematic view of the growth substrate 801 after removal. So far the chip has completed a transfer.
  • the basic features and basic requirements of the method of removing the substrate and the method of adjusting the stress have been explained in the foregoing embodiments, and the description thereof will not be repeated here.
  • FIG. 8-05 is a schematic view of the chip array bonded to the second transfer substrate 808 by the bonding layer 807 after the first transfer substrate is removed.
  • the stress of the indium gallium aluminum nitride layer is adjusted and released by selecting the adhesion ratio or curing shrinkage of the bonding layer 807 or the flexible adhesive.
  • Figure 8-06 is a schematic illustration of the removal of the first transfer substrate 806 and the adhesive layer 805. At this point, the indium gallium aluminum nitride film achieves the stress transfer and regulation described in the second transfer and power book.
  • Figure 8-07 is a schematic illustration of the removal of the p-type ohmic contact sacrificial layer 804.
  • Fig. 8-08 is a schematic view showing the formation of the p-side passivation layer 809 on the indium gallium aluminum nitride film.
  • Figure 8-09 is a schematic view of the ohmic contact reflective layer 810 and the pressure bonding adhesion and diffusion barrier layer 81 1 formed on the indium gallium aluminum nitride film.
  • the basic features and basic requirements have been explained in the foregoing embodiments. This is not repeated.
  • 8-10 are schematic views of the chip array and the third support substrate after pressure bonding.
  • 812 denotes a three-transfer bonding layer
  • 813 denotes a third transfer substrate
  • 814 denotes a protective layer on the back side of the substrate.
  • 8- 1 1 is a schematic view after removing the second transfer substrate 808 and the bonding layer 807. After this step, the indium gallium aluminum nitride film achieved the third transfer.
  • 8-12 are schematic views after surface roughening of the chip array.
  • 815 denotes a roughened figure, and its formation method and basic features and requirements have been explained in the foregoing embodiments, and the description thereof will not be repeated here.
  • Fig. 8-13 is a schematic view of the nitride at the position of the edge 816 of the chip array.
  • FIGS. 8-14 are schematic views showing the formation of a passivation antireflection layer 817 on the surface of the chip array, and forming an n-type electrode and a pad S19 at a position where the passivation layer is not provided at the first region 818.
  • the basic features and requirements of the method and process for the passivation of the antireflection layer 817, the first region 818 and the n-type electrode and the pad 8] 9 have been described in the previous embodiments, and the description thereof will not be repeated here.
  • Embodiment 12 differs from the previously described embodiments in that: the chip patterning process is completed before the first transfer, and it is completed on a substrate having a coefficient of thermal expansion matching GaN; Sub-transfer uses electroplating or bonding or adhesive transfer; the third time uses pattern plating to achieve dicing.
  • Figure 9-01 is a schematic diagram of an epitaxial wafer.
  • 901 is a growth substrate
  • 902 is an indium gallium aluminum nitride epitaxial film.
  • Fig. 9-02 is a schematic view showing the formation of a p-type ohmic contact reflective layer 903 on the epitaxial wafer, a low work function gold flex passivation layer 904, a pressure solder diffusion barrier layer 905, and a pressure bonding adhesive layer 906.
  • the basic features and basic requirements have been explained in the foregoing embodiments, and the description thereof will not be repeated here.
  • Figure 9-03 is a schematic view of the epitaxial wafer and the first transfer substrate after pressure bonding.
  • the first transfer substrate is a composite® layer structure substrate, the germanium layer 907 of the substrate has a coefficient of thermal expansion matching the GaN; the third layer 909 of the substrate has a phase opposite to the growth substrate Matched Thermal Expansion Coefficient:
  • the second layer 908 layer is a pressure bonding layer that bonds the first layer 907 layer and the third layer 909 layer together.
  • the first layer of layer 907 can reduce the thermal shock damage of the indium gallium aluminum nitride film during the processing of the chip; the third layer of 909 can prevent the epitaxial wafer from being broken by the substrate after the primary transfer is completed.
  • Figure 9-04 is a schematic view of the growth substrate 901 with the protective layer 910 on the back side. At this point, the chip has completed a transfer.
  • Fig. 9-05 is a schematic view showing the surface roughening treatment of the indium gallium aluminum nitride epitaxial film 902, and 911 is a roughened pattern.
  • 9-06 is a schematic view of the indium gallium aluminum nitride epitaxial film 902 after etching into a chip array, and the first region 912 is an etched position.
  • Figure 9-07 is a schematic diagram showing the formation of a passivation anti-reflection layer 13, an n-electrode and pad 914 and a chip array slit 915 on the chip array.
  • the conductive layer 916 is formed on the surface of the chip array.
  • the conductive layer 916 may be an electroplated conductive layer, or may be a substrate bonding layer or an adhesive.
  • FIG-9 is a schematic view after the second transfer substrate 917 is plated on the conduction layer 916, and the second protection layer 918 is a back surface protection layer.
  • the second transfer substrate in this step may be an adhesive.
  • the cemented substrate can also be a bonded bonded substrate.
  • Figure 9-10 is a schematic illustration of the removal of the first transfer substrate. So far the chip has achieved a second transfer. '
  • Figure 9 - ⁇ is a schematic diagram of a patterned electro-resistive photoresist pattern formed on the surface of the chip array, and 919 represents a photoresist pattern.
  • 9-12 are schematic views of the surface of the chip array after the pattern substrate 920 and the substrate protective layer 921 are plated.
  • FIG-13 are schematic views of the second transfer substrate 917, the second protective layer 918, and the conduction layer 916, and 922 is a blue film carrying the chip discrete device. At this point, the chip is added: .1.: The process is completed.
  • the substrate to be transferred for the first time is a patterned electroplated substrate, which is bonded to another substrate, and then laser stripped to remove the substrate, so that It is beneficial to the discharge of vaporized substances during laser, thereby reducing the damage of the indium gallium aluminum nitride film.
  • 10-01 is a schematic view of an epitaxial wafer
  • 1001 is a growth substrate
  • 002 is an indium gallium aluminum nitride epitaxial film.
  • Fig. 10-02 is a schematic view showing the patterning of the indium gallium aluminum nitride film pattern, and the first region 1003 is a grooved position of the nitride film.
  • 0-03 is a schematic view after forming a passivation layer on the edge of the chip array, and 1004 is a passivation layer.
  • Figure 10-04 is a schematic view of the p-type ohmic contact reflective layer 1005.
  • Fig. 10-05 is a schematic view of the diffusion barrier layer and the pressure bonding layer 1006.
  • the diffusion barrier layer and the pressure bonding layer 1006 are capable of conducting turbulence with each other throughout the surface of the wafer.
  • Fig. 0-06 is a schematic diagram of a patterned photoresist 1007 on which a germanium-plated pattern is formed on the chip array.
  • Figure 10-07 is a schematic illustration of a patterned substrate on a chip array, the first transfer substrate 1008.
  • Figure 10-08 shows the completion of the plating on the patterned substrate; ⁇ , removes the patterned photoresist 1007, and passes it through the adhesive 1009 and the bonded substrate.
  • Fig. 10-09 is a schematic view after the growth substrate 1001 is removed. So far, one transfer of the indium gallium aluminum nitride film has been achieved. Especially for the epitaxial wafer of the sapphire substrate, due to the existence of a gap between the patterned electroplated substrate arrays, it can remove the vaporized material of the nitride during laser stripping in time, thereby reducing the damage of the indium gallium aluminum nitride film.
  • ⁇ 10-10 is a schematic diagram of the second adhesive layer 1012 of the chip after bonding the second transfer substrate 1012 of the chip array.
  • a secondary transfer substrate is prepared by plating a substrate or bonding a bond pad.
  • 10-11 are schematic views after removing the joint 1010 of the first transfer substrate 1008 and the adhesive 1009 of the adhesive layer.
  • 10-12 are schematic views after the first transfer substrate 1008 is removed.
  • 10-13 are schematic views showing the bonding of the chip array and the third transfer substrate 1014 together, wherein 1013 is a pressure-bonded metal layer on the front surface of the substrate, and 015 is a metal layer protective layer on the back surface of the substrate. .
  • Fig. 10-14 is a schematic view showing the removal of the two transfer substrates 1012 and the second adhesive 1011 after the bonding is completed.
  • 1016 denotes a bonding metal layer 013 and a bonding metal layer after the diffusion barrier layer and the pressure bonding layer 1006 are welded to each other.
  • the three transfer of the indium gallium aluminum nitride film was achieved.
  • Figure 10-16 is a schematic diagram showing the formation of an n-type drain and pad 1018 on the surface of the chip array.
  • Figure 10-17 is a schematic diagram of the chip array after it has been cut into discrete devices.
  • the present embodiment differs from the previously described embodiments in that: a groove of 1 to 300 micrometers deep is formed on the substrate at a gap between the chip arrays of the epitaxial wafer before the first transfer: Then, Bonding it to the substrate: The substrate is then ground to the recess to separate the chip arrays from each other; then the remaining growth substrate is removed and other processing is performed.
  • This method can not only reduce the damage of the indium gallium aluminum nitride film when the laser is peeled off, but also avoid the problem that some substrates are difficult to cut the dicing.
  • Figure 11-01 is a schematic view of the first transfer substrate 1308 and the epitaxial wafer bonded together with an adhesive 1309.
  • the indium gallium aluminum nitride thin threat 1302 on the growth substrate 1301 is etched into an array, and a p-side passivation layer 1303, a p-plane complementary passivation layer 1304, an ohmic contact reflective layer 1305,
  • the diffusion barrier layer 1306 and the metal bonding layer 1307 are pressure bonded.
  • Figure 1 1 -02 is a schematic view of a transfer substrate 1308 epitaxial wafer bonded together.
  • Fig. 1 1 -03 is a schematic diagram of the growth substrate being polished and thinned by ⁇ .
  • 1310 is a growth substrate after polishing and thinning.
  • Figure -04 is a schematic view of the remaining substrate 1310 after removing the remaining thinned germanium. At this point, a single transfer of the indium gallium aluminum nitride film is achieved.
  • Fig. 11 -05 is a schematic view showing the bonding of the chip array to the second transfer substrate 13 ⁇ with the adhesive 1312. A schematic view of the remaining thinned growth substrate 1310 is removed. At this point, a single transfer of the indium gallium aluminum nitride film is achieved.
  • 11-06 is a schematic view after removing the first transfer substrate 1308 and the adhesive 1309. At this point, the indium gallium aluminum film achieved secondary transfer.
  • Figure 1 1 - 07 is a schematic diagram of the chip array and the secondary transfer substrate before bonding.
  • 13 ⁇ is the third transfer substrate
  • 1314 is the front metal layer of the substrate
  • 1315 is the metal layer on the back side of the substrate.
  • Figure 11-08 is a schematic diagram of the chip array and the three transfer substrate bonding.
  • 1316 is a metal layer after pressure welding.
  • Fig. 11-09 is a schematic view showing the removal of the two transfer substrates 131 1 and the second adhesive 1312. At this point, the indium gallium aluminum nitride film achieved three transfers.
  • Figures 1 - 10 are prepared by roughening the pattern 1317 on the surface of the chip array, removing the nitride at the edge of the array edge 13 8 , preparing the passivation anti-reflection layer 1319, and having no passivation anti-reflection layer in the first region 1320.
  • S is a schematic view of the n-type electrode and the pad 1321.
  • Figure 1-11 is a schematic diagram of a diced split chip array after obtaining a discrete device.
  • Figure 12 is one of the typical device structures that can be obtained using the method of the present invention.
  • 1401 is a surface-intensified indium gallium aluminum nitride film
  • 1402 is a device edge passivation antireflection layer
  • 1403 is a passivation antireflection layer on the lower surface edge of the device
  • 1404 is an ohmic contact reflection layer of the device
  • 1405 is diffusion.
  • the barrier layer, 1406 is a pressure-welded metal layer, 1407 is a p-side electrode complementary passivation anti-reflection layer, 1408 is a substrate of the device, 1409 is a metal layer on the back side of the substrate, 1410 is an ohmic contact gold refraction layer and a gold-strength wire bonding plate.
  • Figure 13 is one of the other typical device structures that can be obtained by the method of the present invention.
  • the device differs from the device described above in that the surface of the indium gallium aluminum nitride film is free from roughened surfaces.
  • 1501 is an indium gallium aluminum gas dragon
  • 1502 is a device edge passivation antireflection layer
  • 503 is a passivation antireflection S of the lower surface edge of the device
  • 1504 is an ohmic contact reflection layer of the device
  • 1505 is a diffusion barrier layer
  • 1506 For the pressure-welded gold flex layer, 1507 is a p-plane dipole complement passivation layer, 1508 is the substrate of the device, 1509 is the gold layer on the back side of the substrate, 1510 is the n-type ohmic contact metal layer and the metal lead plate .
  • the basic requirements and basic features of each key element of the device have been described in the relevant parts of the specification, and the description will not be repeated here.
  • Figure 14 is one of another exemplary device configurations obtainable by the method of the present invention which differs from the previously described device in that it does not have a complementary drain corresponding to the n electrode site ffi.
  • 1601 is a roughened indium gallium aluminum nitride film
  • 1602 is a device edge passivation antireflection layer
  • 1603 is a passivation antireflection layer on the lower surface edge of the device
  • 1604 is an ohmic contact reflection layer of the device
  • 1605 is The diffusion barrier layer
  • 1606 is a pressed metal layer
  • 1607 is a ohmic contact metal layer and a metal lead pad
  • 1608 is a substrate of the device
  • 1609 is a metal layer on the back side of the substrate.
  • FIG. 15 is a diagram showing another typical device structure obtainable by the method of the present invention.
  • the device is different from the device described above in that its ohmic contact reflective layer and diffusion barrier layer may not pass through the light during processing of the device.
  • 1701 is a roughened indium gallium aluminum nitride film
  • 1702 is a device edge passivation antireflection layer
  • 1703 is a passivation antireflection layer on the lower surface edge of the device
  • 1704 is an ohmic contact reflection layer of the device
  • 1705 is
  • 1706 is a pressure-welded metal layer
  • 1707 is an n-type ohmic contact metal layer and a metal lead pad
  • 1708 is a substrate of the device
  • 1709 is a metal layer on the back side of the substrate.
  • Figure 16 is a diagram showing another typical device structure which can be obtained by the method of the present invention by the method of the present invention.
  • the device differs from the device described above in that the substrate of the device can be a substrate of a germanium plating or a bonding multilayer structure.
  • 1801 is a roughened indium gallium aluminum nitride film
  • 1802 is a passivation antireflection layer on the upper surface of the device.
  • 1803 is a passivation antireflection layer on the lower surface of the device
  • 1804 is an ohmic contact reflection layer of the device, 1805.
  • 1806 is a gold-bonded layer
  • 1807 is the first layer of the substrate
  • 180S is the second layer of the substrate
  • 18(]9 is the third layer of the substrate
  • 1810 is the metal layer of the back surface of the substrate
  • 181 1 is n ohmic contact gold refraction layer and metal lead pad.
  • Figure 17 is a diagram showing another typical device structure obtainable by the method of the present invention, which is different from the device described above in that the passivation of the lower surface of the device is achieved by a gold work layer having a low work function, and The area of the ohmic contact reflective layer is smaller than the mesa of the indium gallium aluminum nitride film.
  • 1901 is a roughened indium gallium aluminum 3 ⁇ 4 film
  • 1902 is a passivation antireflection layer on the upper surface of the device
  • 1903 is a passivation metal layer on the lower surface of the device
  • 1904 is a pressure
  • 1905 is the supporting substrate
  • 1906 is the metal layer on the back side of the supporting substrate
  • 1907 is an n-type ohmic contact metal layer and a metal lead pad.
  • the device 18 is one of the other typical device structures that can be obtained by the method of the present invention.
  • the device is different from the device described above in that the ohmic contact reflective layer of the device is not subjected to I-shaped processing, and its area is indium.
  • the gallium aluminum nitride film has a large mesa area, and there is no passivation layer on the lower surface of the device.
  • 2001 is a roughened indium gallium aluminum nitride film
  • 2002 is a surface passivation antireflection layer on the device
  • 2003 is an ohmic contact reflection layer
  • 2004 is a diffusion barrier layer
  • 2005 is a pressure welding gold layer
  • 2006 is The supporting substrate
  • 2007 is the metal layer on the back side of the supporting substrate
  • the 2008 is an n-type ohmic contact metal layer and a gold bent bow I-line disk.
  • Figure 19 is a diagram showing another typical device structure obtainable by the method of the present invention.
  • the device differs from the device described above in that its complementary i3 ⁇ 4 pole corresponding to the position of the n-electrode is not realized by a passivation antireflection layer. , but by the metal layer of the low work function.
  • 2101 is a roughened indium gallium aluminum nitride film 2102 which is a passivation antireflection layer on the upper surface of the device
  • 2103 is a passivation metal layer and a diffusion barrier layer on the lower surface of the device and the complementary electrode
  • 2104 is a pressed metal layer.
  • 2105 is an ohmic contact reflective layer
  • 2i 06 is a supporting substrate
  • 2107 is a supporting substrate back metal layer
  • 2108 is an n ⁇ ohmic contact gold layer and a metal lead pad.
  • a growth substrate 701 an indium gallium nitride epitaxial strand 702, a groove 703, a p-type ohmic contact sacrificial layer 704, a filler 705, a conduction layer 706, a first transfer substrate 707, a protective layer 708, a bonding layer 709, ⁇ two transfer substrates 710, a passivation layer 711, a composite layer 712, a solder layer 713, a third transfer substrate 714, a first protective layer 715, a roughened pattern 716, a first region 717, blunt An anti-reflection layer 718, an n-type electrode and a tray 719;
  • Growth substrate 901 indium gallium aluminum 3 ⁇ 4 epitaxial lift 902, ⁇ 3 ⁇ 4 ohm contact reflective layer 903, passivation layer 904, diffusion barrier layer 905, pressure bond layer 906, first layer 907, second layer 908, third Layer 909, protective layer 910, roughened pattern 911, first region 912, passivation antireflection layer 913, n-drain and pad 914, slit 91 5, evanescent layer 916, second transfer substrate 917, Two protective layers 918, a photoresist pattern 919, a pattern substrate 920, a substrate protection layer 921, and a blue film 922:
  • Growth substrate 1001 indium gallium aluminum nitride epitaxial strip 1002, first region 1003, passivation layer 1004, p-type ohmic contact reflective layer 1005, diffusion barrier layer and pressure solder layer 1006, photoresist 1007, first transfer liner Bottom painting, adhesive 1009, connected substrate 1010, second adhesive 101 1 , second transfer substrate 1012, metal layer 1013, third transfer substrate 1014, protective layer 1015, bonding Metal layer 1016, roughened pattern 1017, n-type drain and pad 1018 ;
  • Indium gallium aluminum nitride film 1501 edge passivation antireflection layer 1 502, passivation antireflection layer 1503 on the lower surface edge, ohmic contact reflection layer 1504, diffusion barrier layer 1505, pressure welding gold flex ⁇ 1 506, p surface complement Passivation antireflection layer 1507, substrate 1508, metal layer 1509, n-type ohmic contact gold refraction layer and metal lead pad 1510;
  • 1601 is an indium gallium aluminum film
  • 1602 is an edge passivation antireflection layer
  • 1603 is a passivation antireflection layer on the lower surface edge
  • 1604 is an ohmic contact reflection layer
  • 1605 is a diffusion barrier layer
  • 1606 is a compression metal layer
  • 1607 For the n-type ohmic contact metal layer and metal lead pad, 1608 for the substrate, 1609 for the gold layer:
  • 1701 is an indium gallium aluminum nitride film
  • 1702 is an edge passivation antireflection layer
  • 1703 is a passivation antireflection layer on the lower surface edge
  • 1704 is an ohmic contact reflection layer
  • 1705 is a diffusion barrier layer
  • ⁇ 06 is a pressure bonding metal layer
  • 1707 An n-type ohmic contact metal layer and a metal lead pad
  • 1708 is a substrate
  • ⁇ 09 is a metal layer
  • 1801 is an indium gallium aluminum 3 ⁇ 4 film
  • 1802 is an upper surface passivation antireflection layer
  • 1803 is a passivation antireflection layer on the lower surface edge
  • 1804 is an ohmic connection.
  • the touch reflective layer 1805 is a diffusion barrier layer
  • 1806 is a pressure-welded gold layer
  • 1807 is a substrate first layer
  • 1808 is a substrate second layer
  • 1809 is a substrate third layer
  • 1901 is an indium gallium aluminum nitride film
  • 1902 is a surface passivation antireflection layer on the device
  • 1903 is a passivation metal layer and a diffusion barrier layer for pressure bonding
  • 1904 is a pressure bonding metal layer
  • 1905 is a support substrate
  • 1906 is a support liner.
  • 1907 is an n-type ohmic contact metal layer and a metal lead pad
  • 2001 is an indium gallium aluminum nitride film
  • 2002 is a surface passivation antireflection layer on the device
  • 2003 is an ohmic contact reflection layer
  • 2004 is a diffusion barrier layer
  • 2005 is a pressure bonding metal layer
  • 2006 is a support substrate
  • 2007 is a support substrate.
  • 2008 is an n-type ohmic contact metal layer and a metal lead pad;
  • 2101 is an indium gallium aluminum nitride film
  • 2102 is a surface passivation antireflection layer on the device
  • 2103 is a passivation metal layer and a diffusion barrier layer
  • 2104 is a solder metal layer
  • 2105 is an ohmic contact reflection
  • 2 106 is a support substrate.
  • 2107 is a metal layer on the back side of the support substrate
  • 2108 is an n-type ohmic contact metal layer and a metal lead pad.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Led Devices (AREA)

Description

缓解铟镓铝氮薄膜应力的半导体器件的制造方法 技术领域
本发明涉及一种半导体器件的制造方法， 特别是涉及铟镓铝氮基半导体发光器件。
mm
目前商品化的铟镓铝氮发光器件， 其生长衬底均是异质生长衬底， 主要有 3种： 蓝宝石衬底、 碳化硅 衬底和硅衬底； 其他衬底上虽然也可以用于外延铟镓铝氮薄膜， 但目前还没有形成商品化的器件； 同质生 长衬底虽然也可以做成发光器件， 然而同质生长衬底成本非常高， 商品化尚不成熟。
铟镓铝氮薄膜与异质衬底之间存在线性热膨胀系数的差异， 外延生长铟镓铝氮薄膜的温度一般都在 lOOO'C左右， 当外延生长铟镓铝氮薄膜完成以后降到室温时会由于热膨胀系数的不匹配导致在铟镓铝氮薄 膜里面存在很大的应力。 对于 （0001 )面的氮化镓而言， 当它外延在蓝宝石衬底上时， 在室温状态薄膜受 到压应力： 当它外延在碳化硅衬底和硅衬底时， 在室温状态受到张应力。 尤其是硅衬底， 由于 (0001)面的 氮化镓与硅之间的热膨胀系数相差很大， 丙而室温状态时外延薄膜极易产生裂纹和缺陷增加。 铟镓铝氮薄 膜， 是一种极性很强的材料， 应力状态发生变化时， 会使得铟镓铝氮薄膜 §层的能带结构发生相应的变 化， 从而使得器件的光电性能发生相应的变化； 另外， 铟镓铝氯薄膜的应力状态不同， 原子的内能会不同， 在器件工作时， 其原子发生迁移的能力会不同， H此薄膜应力也会直接影响到器件的可靠性。
非极性或半极性的铟镓铝氮簿膜， 虽然它可以解决应力对发光效率的影响问题， 但它会引入新的热胀 冷缩的应力问题。 例如， 蓝宝石衬底上的非极性 a化镓与衬底之间的热失配问题是一个比硅衬底氮化镓还 突出的外延应力问题。 只耍有应力存在， 在器件工作过程中其原子的扩散迁移能力就会受到影响， 从而器 件的可靠性就会受到影响。
目前已有将衬底上外延生长的铟镓铝氮薄膜与新的支撑衬底邦定压焊在一起， 然后去除生长衬底， 实 现铟镓铝氮薄膜从生长衬底到支撑衬底的转移。 该技术方案最主耍的效果是可以改善器件的散热， 将蓝宝 石衬底上外延的铟镓铝氮薄膜转移到硅衬底或者金属衬底上， 可以实现垂直结构， 硅以及金厲衬底的散热 大大强于蓝宝石衬底。 有效的散热使得这类器件的电光转换效率和可靠性均得到一定改善。 然而， 这种一 次转移的技术获得的器件可靠性仍然不理想。
发明内容
本发明所耍解决的技术问题是： 提供-一种缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 该方法用 于释放调节铟镓铝氮薄膜的应力， 使器件的光电性能和可靠性获得提高。
为了解决本发明的技术问题， 本发明提出一种缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其包括：
在生长衬底上外延铟镓铝氮薄膜；
针对由于生长衬底与铟镓铝氣的热膨胀系数的差异而产生的应力， 而进行至少两次将铟镓铝氮 薄膜由当前衬底转移到另一个衬底上的衬底转移， 该次衬底转移释放调节铟镓铝氮薄膜在生长过程 中积存的应力。
优选地： 在外延铟镓铝氮薄膜之前， 先图形化生长衬底。 图形化的槽结构在转移衬底的过程中起 到调节伸缩空间的作用。
优选地： 所述铟镓铝氮薄膜转移到柔性胶黏剂上后处于自由伸展的释放应力状态。 柔性胶黏剂 用于粘接铟镓铝氮薄膜和转移衬底， 其包括一些常温下的软金属诸如， 铅、 锌、 银、 锡、 铟、 金、 铝、 铜等金厲， 以及一些柔软的稀有金厲， 也包括在提高制造环境温度下变得柔软的金属。 除此以 为还包括一些有机胶体， 包括在较长时间才硬化的有机胶， 在其未硬化的时间内， 其具有调节铟镓 铝氮薄膜应力的效果。 铟镓铝氮薄膜通过柔性胶黏剂附着在转移衬底上， 其在生长过程中产生的应 力在柔性胶黏剂提供的无张应力和压应力环境下， 逐步减小至消退。 即使这些柔性胶黏剂本身的热 胀冷缩， 由于它们自身为柔软材质， 其会很好的通过延展形变来消解应力， 而不会将这种热胀冷缩 的应力外传给到铟镓铝氮薄膜。
优选地： 将所述铟镓铝氮薄膜先后进行两次衬底转移， 两次的衬底转移均为以下转移方式： 邦定压焊、 沉积或者它们的混合方式。 沉积包括电弧离子镀、 磁控溅射、 电子束蒸发、 热蒸发、 热 喷涂、 电镀、 化学镀、 真空镀等等。 优选地： 所述铟镓铝氮薄膜通过粘结材料转移到另一个衬底上， 通过粘结材料固化的热胀冷缩 对铟镓铝氮薄膜的应力进行调节。 粘接材 ^在固化的时候， 由于热胀冷缩， 其体积会发生变化， 这 种变化， 会给对铟镓铝氮薄膜产生应力作用， 如 这种应力作用与铟镓铝氮本身由生长衬底产生的 应力相反， 则可以起到调节铟镓铝氮薄膜应力的效果。 如果铟镓铝氮薄膜外延后室温下受到的是张 应力 （碳化硅、 硅衬底）， 则选用膨胀系数比铟镓铝氮小的材料； 如果铟镓铝氮薄膜外延后受到的是 压应力 （蓝宝石衬底）， 则选用膨胀系数比铟镓铝氮大的材料。
优选地： 所述铟镓铝氮薄膜通过粘结材料转移到另一个衬底上， 期间通过粘结材料固化的温度 来实现对铟镓铝氮薄膜的应力调节。 根据粘接材料的膨胀系数， 选择合适的固化温度环境来调节铟 镓铝氮薄膜的应力。
优选地： 所述铟镓铝氮薄膜通过邦定压焊方式转移到另一个衬底上， 期间通过邦定压焊金属的 融合温度控制来实现对铟镓铝氮薄膜的应力调节。
优选地： 所述铟镓铝藏薄膜通过邦定压焊方式转移到另一个衬底上， 期间通过控制压焊金属层 的弹性模量来实现对铟镓铝氮薄膜的应力调节。 压焊金属的成份不同， 其具有不同的弹性模量。
优选地： 所述铟镓铝氮薄膜通过沉积方式转移到另一个衬底上， 通过另一个衬底在沉积过程中 沉积层 S身形成的应力来实现对铟镓铝氨薄膜的应力调节。
优选地： 所述铟镓铝氮薄膜转移到另一个衬底上， 期间通过沉积的制备条件来实现对铟镓铝氮 薄膜的应力调节， 其中制备条件包括： 温度、 厚度、 致密度分布、 组分或结构中的任一项或多项的 组合。 在选定的温度条件下转移铟镓铝氮薄膜， 使铟镓铝氮薄膜的应力在该温度下释放一定的应力。 转移衬底的厚度也会对铟镓铝氮薄膜产生影响， 同等情况下， 较厚的转移衬底更容易使铟镓铝氮薄 膜随其形变或形变趋势， 产生应力， 因此调节衬底的厚度可以调节铟镓铝氮薄膜所受到的应力。 一 般衬底中物质致密度越大， 其膨胀系数也越大， 因此致密度也可以用于调节铟镓铝氮薄膜的应力。 衬底所含物质决定了其膨胀系数， 因此可以根据衬底组分来调节铟镓铝氮薄膜的应力。 衬底的结构 例如镂空、 空隙、 槽、 层等结构均会改变其热胀冷缩的效果， 可以利用这些结构来调节铟镓铝氮薄 膜的应力。
优选地： 包括在铟镓铝氮薄股上制造构成器件的耍素， 构成器件的耍素包括： 电极及焊盘和欧 姆接触层。
优选地， 所述构成器件的耍素还包括：
钝化层、 增加出光的图形组构层 （即出光表面的粗化）、 反光层、 光增透层或与电极的互补结构 中的一种或多种。 其中电极互补结构指的是电极在铟镓铝氮薄膜中投影位置没有欧姆接触的结构。
优选地： 在外延铟镓铝氮薄膜之前， 先图形化生长衬底：
进行最后一次衬底转移之前， 在铟镓铝氨薄膜上制造构成器件的耍素中的一种或者全部要素。 在铟镓铝氮薄膜上制造构成器件的要素会导致铟镓铝氮薄膜的热膨胀系数发生变化， 其应力也 会在该制造过程中得以调整。 如果全部耍素均在最后一次衬底转移之前完成， 则可以通过最后一次 转移衬底， 对包含所有耍素的铟镓铝氮薄膜进行整体性应力调整； 如果在最后一次转移衬底之后再 进行耍素制造， 会使整个器件的应力状态再次或多次发生变化， 即使再次获知器件的应力情况， 对 其不满意， 也没有办法进行调整。 例如， 粗化的表面可以释放应力。 故在最后一次衬底转移之前完 成所有耍素的制作的方式一般耍优于之后的方式。
优选地： 所述生长衬底为蓝宝石衬底、 碳化硅衬底、 硅衬底、 MgAl204、 MgO、 LiGa02、 Y -LiA102、 NdGa03、 ScAlMg04、 Ga8La2(P04)602、 MoS2、 LaAI03、 （Mn,Zn)Fe204、 Hf、 Zr、 ZrN、 Sc、 ScN、 NbN、 TiN或立体材料 （具有第一定厚度的三维立体形状). 的 GaN或 AI 衬底中的任一种衬底。
优选地： 在所述生长衬底上沉积有： Si、 GaAs、 Ge、 A1P、 AlAs、 AlSb、 GaP、 GaAs、 GaSb、 InP、 InAs InSb、 ZnO、 ZnS、 ZnSe、 ZnTe、 CdS、 CdSe、 CdTe、 HgSe、 HgTePbS、 PbSe、 PbTe、 GaPxAs,.x> GaxAi,.xAs> MgAl204、 MgO、 LiGa02、 y -LiAI02、 NdGa<¾、 ScAlMg〇4、 GasLa2(P04)602、 MoS2、 LaAI03> (Vjn,Zn)Fe204 > Hf、 Zr、 Ζι·Ν、 Sc、 ScN、 NbN或 TiN中的一种或几种薄层， 它们构成复合衬底。
优选地， 包括以下步骤：
在外延铟镓铝氮薄膜之前， 图形化生长衬底， 形成铟镓铝氮薄膜的生长平台和平台之间的槽结构； 制作钝化层， 并图形化钝化层， 在铟镓铝氮薄膜的边缘以及铟镓铝氮薄膜单元之间的槽内均分 布有用于阻断电镀电流的图形化钝化层， 在铟镓铝氣薄膜边缘的钝化层与槽内的图形化钝化层之间 存在间隙；
在钝化层的上面制作转移衬底， 并去除钝化层下面的衬底；
在上述被去除掉的钝化层下面的衬底位置上沉积导热金属层 （铜， 导热性能好）， 并图形化导热金 属层， 使所述槽内的钝化层露出；
在导热金属层上电镀另一个位于钝化层下面的转移衬底， 形成与导热金属层一致的图形构造； 在上述位于钝化层下面的转移衬底上通过导电的粘结材料粘接一个与其连体的金属连体衬底，并去 除钝化层上面的转移衬底；
将制成的外延片进行贴膜， 并去除连体衬底， 完成分片。
上述钝化层的图形化， 其目的就是为了实现在所述导热金属上电镀转移衬底， 该电镀的转移衬底在沉 积的过程中， 己经自然图形化， 因此， 其不需要切割， 在将连体衬底去除后， 该电镀的转移衬底自然而然 分开， 从而完成分片。 这种方法是针对金属衬底而设计的。 这是基于金属衬底难于切割的问题而采用的特 别方案。
优选地： 将铟镓铝氣薄膜至少进行两次转移，第二个转移衬底的热膨胀系数与第一个转移衬底的热膨 胀系数相匹配。 笫二个转移衬底是在第一个转移衬底之后制作在铟镓铝氮薄膜上的， 在第一个转移衬底被 剥离之前， 它们共同作用铟镓铝氮薄膜。 两个转移衬底的膨胀系数相匹配可以很好的实现铟镓铝氮薄膜的 转移过度， 避免在转移过程中发生应力失衡造成的破裂。
优选地： 转移衬底通过镂空结构实现其热膨胀系数与铟镓铝氮薄膜相匹配。镂空结构可以改变其膨胀 系数， 当材料本身的膨胀系数不足以满足释放铟镓铝氮薄膜应力需耍的时候， 可以通过镂空、 孔、 槽等结 构改变其热胀冷缩的效果， 能够达到预期的效果。
优选地： 所述粘结材料为有机物、 无机非金属材料。
优选地： 所述有机物为热阇型胶黏剂、 热熔型胶黏剂、 室温固化型胶黏剂、 压敏型胶黏剂、 光固化有 机胶。
优选地： 所述粘接材料为两层以及以上的 ¾层结构， 该叠层结构包括至少两种材料。
优选地： 所述粘结材料为纤维素酯、烯类聚合物（聚乙酸乙烯酯、聚乙烯醇、过氯乙烯、聚异丁烯等）、 聚酯、 聚醚、.聚酰胺、 聚丙烯酸酯、 a-氰基丙烯酸酯、 聚乙烯醇缩醛、 乙烯 -乙酸乙烯酯共聚、 环氧树脂、 酚醛树脂、 脲醛树脂、 三聚氰 -甲醛树脂、 有机硅树脂、 呋喃树脂、 不饱和聚酯、 丙烯酸树脂、 聚酰亚胺、 聚苯并咪唑、 酚醛-聚乙烯醇缩醛、 酚醛-聚酰胺、 酚醛 -环氧树脂、 环氧-聚酰胺、 合成橡胶、 氯丁橡胶、 丁 苯橡胶、 丁基橡胶、 丁钠橡胶、 异戊橡胶、 聚硫橡胶、 聚氨酯橡胶、 氯磺化聚乙烯弹性体、 硅橡胶、 酚醛 -丁腈胶、 酚醛-氯丁胶、 酚醛 -聚氨酡胶、 环氧-丁腈胶、 环氧-聚硫胶等中的一种或几种的组合。 其中烯类 聚合物可以是聚乙酸乙烯酯、 聚乙烯醇、 过氯乙烯、 聚异丁烯等
优选地： 所述无机非金属材料为空气干燥型无机胶黏剂、水固化型无机胶黏剂、热熔型无机胶黏剂或 化学反应型无机胶黏剂。
优选地： 所述无机非金屈材料为石膏、 水泥、 水玻璃、 粘土、 低熔点玻璃、 低熔点玻璃陶瓷或硫磺， 或者硅酸盐类胶黏剂、 磷酸盐类胶黏剂、 胶体氧化铝胶黏剂、 牙科胶泥胶黏剂； 所述粘结材料为上述无机 非金属材料中的一种或多种的组合。
优选地： 在铟镓铝氮薄膜 P面上沉积 P面钝化层， 并图形化 P面钝化层， 使每个最终的分立器件的 边缘存在图形化的 P面钝化层。 P面钝化层厚度报薄， 对铟镓铝氮薄膜的表面基本上没有特别明显的应力 作用， 其主耍是其防止薄膜氧化的作用。
优选地： 转移衬底为复合衬底， 其分为三层， 与铟镓铝氮薄膜接触的为第一层， 其它依次为第二层和 第三层； 所述第一层的热膨胀系数与铟镓铝氮薄膜的相匹配， 所述第三层的热膨胀系数与生长衬底的相匹 配， 第二层为将第一层和第三层连接在一起的压焊层。 第一层可以减少芯片加工过程中衬底对铟镓铝氮薄 膜的冷热冲击损伤； 第三层可以防止一次转移完成后衬底弓 I起的外延片的破裂现象。
优选地， 包括：
在包括生长衬底的外延片上制作图形化电镀层， 电镀层的图形化与生长衬底的图形化一致， 电镀层中 有沿图形化生长衬底的凹槽延伸出来的缝隙， 其中生长衬底为蓝宝石衬底：
在电镀层上制作第一个转移衬底； 激光剥离生长衬底。
该结构有利于激光剥离衬底时， 产生的气体物质的排放， 从而减小铟镓铝氮薄膜所受到的损伤。 薄膜转移次数大于三次时， 偶数次转移获得第 1型导电性氮化物层朝上的器件， 奇数次转移获得第 2 型导电层朝上的发光器件， 发光器件的构成要素可以在任意一次转移过程中制备和增加。
本发明的有益效果：
相比现有技术， 本发明提出经过至少两次衬底转移来释放由于热膨胀系数差异造成的生长衬底对铟镓 铝氮薄膜产生的应力的方案。 在外延层生长完成后， 由于热膨胀系数的差异， 恢复到常温下， 生长衬底会 外延层有很大的应力作用， 这种应力或为张应力或为压应力。 这种应力会导致器件中的能带发生变化， 甚 至是物理上的开裂。
转移衬底的通常是认为将外延层从热的不良导体衬底上转移到热的良导体上， 以加强散热， 因此转移 衬底常被用于大功率芯片的散热。
对外延层进行一次转移， 特别是没有针对性的一般性为了达到芯片散热而进行的转移， 可以缓解外延 层内部的应力， 但是一次转移由于效果不明显， 导致这方面的研究得不到重视或被忽略。
本发明针对由于生长衬底与铟镓铝氮薄膜的热膨胀系数的差异而产生的应力， 提出一种持续释放应力 的方案， 通过至少两次的转移， 甚至三次、 四次等更多次的转移， 来释放铟镓铝氮薄膜中的应力。 第一次 转移衬底， 剥离掉生长衬底后， 铟镓铝氮薄膜与生长衬底接触的面（简称为下表面， 与其对应的为上表面） 被解放， 使该面及其下部分处于弹性恢复状态， 特别是在第一次转移衬底的作用下， 该面及其下部分， 会 有明显恢复效果， 恢复效果的程度与选择的第一次转移衬底有关。 第一次转移衬底最直接释放铟镓铝氮薄 膜的上表面及其邻近的下部分的应力， 鉴于铟镓铝氮薄膜的厚度， 下表面作用没有上表面强。
然后再进行第二次转移衬底， 并剥离掉第一个转移衬底。 第二次转移衬底最直接释放铟镓铝氮薄膜的 下表面及其邻近的下部分应力， 而上表面的作用没有下表面的强。
但是经过两次转移后， 铟镓铝氮上表面部分和下表面部分均得到应力释放， 此时铟镓铝氮薄膜整体应 力释放会变得更加均衡。 两次转移后， 如果应力效果仍然达不到产品耍求， 可以进一步转移衬底。 或者多 次转移衬底的过程， 可以不是每次转移都用于释放应力， 例如， 在高温下制作的转移衬底可以用于调节应 力， 在常温下制作的转移衬底可以不用于调节应力。
本发明能够充分有效的释放和调节铟镓铝氮薄膜的应力状态， 可以逐步对铟镓铝氮薄膜进行应力调 节， 其中的应力得以充分或部分释放， 从而使器件的光电性能和可靠性得到提高。
附图说明
图 1是运用本发明的方法可以获得的一种器件结构。
图 2-01至图 2-41用于说明实施方式 1和 2的实现过程。
. 图 3-01至图 3-10用于说明实施方式 3的实现过程。
图 4-01至图 4-11用于说明实施方式 4、 5、 6的实现过程。
图 5-01至图 5 15用于说明实施方式 7、 8的实现过程。
图 6-01至图 6-14用于说明实施方式 9的实现过程。
图 7-01至图 7- 16用于说明实施方式 10的实现过程。
图 8-01至图 8-15用于说明实施方式 11的实现过程。
.图 9-01至图 9-13用于说明实施方式 12的实现过程。
图 10-01至图 10-17用于说明实施方式 13的实现过程。
图 11-01至图 11-11用于说明实施方式 1 的实现过程。
图 12是运用本发明的方法可以获得的典型器件结构之一。 '
图 13是运用本发明的方法可以获得的另一典型器件结构之一。
图 14是运用本发明的方法可以获得的另一典型器件结构之一。
图 15是运用本发明的方法可以获得的另一典型器件结构之一。
图 16是运用本发明的方法可以获得的另一典型器件结构之一。
图 17是运用本发明的方法可以获得的另一典型器件结构之一。
图 18是运用本发明的方法可以获得的另一典型器件结构之一。
图 19是运用本发明的方法可以获得的另一典型器件结构之一。 具体实施方式
本发明提供一种缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其包括： 在生长衬底上外延 铟镓铝氮薄膜； 针对由于生长衬底与铟镓铝氮的热膨胀系数的差异而产生的应力， 而进行至少两次 将铟镓铝氮薄膜由当前衬底转移到另一个衬底上的衬底转移， 该次衬底转移释放调节铟镓铝氮薄膜 在生长过程中积存的应力。
本发明所保护的具体内容不仅仅限于以下所描述的各种实施方式， 对以下实施方式所做的任何显而易 见的修改或各种实施形态关键耍素的重新组合都是受本发明所保护的。
概述
本发明的实施方式适合于将硅衬底、 蓝宝石衬底、 碳化硅衬底上及其他现有技术领域的衬底上外延生 长的铟镓铝氮薄膜转移到新的衬底上并制备相应发光器件。 本发明采用两次或两次以上转移薄膜的工艺， 使铟镓铝氮薄膜所受应力在第 1次转移、 第 2次转移或 2次以上的转移过程中得到充分或部分释放， 在铟镓 铝氮薄膜转移前或转移后或转移过程中制备构成器件的欧姆接触层、反光层、提高出光效率的图形织构层、 引线焊盘和钝化层等发光器件所必须的构成耍素， 从而获得铟镓铝氮薄膜应力得到充分或部分释放的发光 器件， 改善了器件的可靠性能和提高了制造良品率。通过以下实施方式， 可以体现本发明专利具有实用性、 新颖性和创造性。
实施方式 1
图 2-01至图 2-41用于说明采用三次转移方法获得所述的释放和调节铟镓铝氮薄膜所受应力的途径及 其器件结构的实现过程， 同时还说明了所提及的图形电镀免划片的实现过程和方法。 整个过程简述如下： 图形化生长衬底；
外延铟镓铝氮薄膜：
沉积 P型欧姆接触层和反射层， 并图形化处理， 使其与电极焊盘具有互补结构；
制作第一个转移衬底， 并去除掉生长衬底； .
铟镓铝氮薄膜的去边处理；
钝化层图形化， 在铟镓铝氮薄膜的边缘以及铟镓铝氮薄膜单元之间的槽内均分布有用亍阻断电 镀电流的图形化钝化层， 在铟镓铝氮薄膜边缘的钝化层与槽内的图形化钝化层之间存在间隙；
铟镓铝氮薄膜的表面粗化处理；
制作电极掩膜；
电镀第二个转移衬底， 并去除第一个转移衬底；
在 P型欧姆接触层和反射层上沉积导热金属层， 并图形化导热金属层， 使所述槽内的钝化层露出； . 在导热金属层上电镀第三个转移衬底， 形成与导热金属层一致的图形构造；
在第三个转移衬底上通过导电的粘结材料粘接一个与第三个转移衬底连体的金属连体衬底， 并去 除第二个转移衬底：
制作电极及焊盘；
将制成的外延片进行贴膜， 并去除连体衬底. 完成分片；
再进行翻膜。） - 详细说明如下所述。
图 2-01是外延片特征的剖面示意图， 图中 Ol为生长衬底 （也称为外延衬底）， 202为在生长衬底上 的凹槽， 凹槽 202将生长衬底 20]分割成周期性的平坦区域阵列， 生长在独立平坦区域上的铟镓铝氮薄膜 203也相应的为周期性的阵列。 图中生长衬底 201 可以是蓝宝石衬底、 碳化硅衬底、 硅衬底、 MgAI204、 MgO、 LiGa02、 Y -LiA102、 NdGa03、 ScAlMg04、 Ga8La2(P04)602、 MoS2、 LaA103、 （Mn,Zn)Fe204、 Hf、 Zr、 ZrN、 Sc、 ScN、 NbN、 TiN或立体材料 （具有第一定厚度的三维立体形状） 的 GaN或 A1N衬底中的 任一种衬底。 在生长衬底上可以沉积有： Si、 GaAs、 Ge、 A1P、 AlAs、 AlSb、 GaP、 GaAs、 GaSb、 lnP、 InAs、 InSb、 ZnO、 ZnS、 ZnSe、 ZnTe、 CdS、 CdSe、 CdTe、 HgSe、 HgTePbS, PbSe、 PbTe、 GaPxAsi.x、 GaxAl,-xAs、 MgAl204、 MgO、 LiGa02、 Y -LiAI02、 NdGa03、 ScAlMg。4、 Ga8La2(P04)602、 MoS2、 LaAl。3、 (Mn,Zn)Fe204, Hf、 Zr、 ZrN、 Sc、 ScN、 Nb 或 TiN中的一种或几种薄层， 它们构成复合衬底。 本例生 长衬底 201以硅衬底为例。
生长衬底 201被凹槽 202分割成独立的平坦区域， 用于防止铟镓铝氮薄膜与硅衬底之间的热失配导致 叠层产生裂紋。凹槽 202的深度大于 3微米， 凹槽 202的宽度耍求大于 3微米小于 100微米,凹槽宽度的最 优参数是 10微米， 凹槽深度最优方案是 20微米。 被凹槽分割成的独立平坦区域的形状可以是正方形、 矩 形、 菱形、 三角形等形状， 形状的最优方案是正方形。 独立平坦区域面积大于 100平方微米。 图中 203是 在被凹槽分割成独立平坦区域的生长衬底上外延生长的铟镓铝氮薄膜， 图中铟镓铝氮薄膜 203是用化学气 相沉积 (MOCVD)法获得的， 首先在衬底上形成缓冲层， 然后至少依次沉积 N型氮化镓层、 铟镓氮 /氮化镓 多量子阱发光层、 P型氮化镓层， 最后在 P型层上面沉积或不沉积一层 2纳米左右厚度的铟镓氮盖层。 图 中铟镓铝氮薄膜 203的缓冲层也可以是氮化铝和氮化镓的交替叠层， 缓冲层里的氮化镓可以是符合计量比 的也可以是偏离计量比的。 图中铟镓铝氣薄膜 203的 n型层的杂质一般为硅、 p型层的杂质一般为镁， 量 子阱里面可以掺杂也可以不摻杂。 P型层上面沉积或不沉积一层小于 5纳米厚度的铟镓氮盖层， 其目的是 利用铟镓氮对氮化镓表面有张应力的作用， 从而使 P型表面的极化电场发生变化， 使得 P型表面的空穴浓 度增加， 从而改善 P型欧姆接触的性能， 该铟镓氮盖层可以掺镁也可以不掺镁， 该铟镓氮盖层是可选的， P型层上可以有该盖层， 也可以没有该该盖层， 该铟镓氮盖层的视为 P型层的一部分。
图 2-02是在外延片上沉积了 p型欧姆接触层和反射层 204后的剖面示意图。在沉积了 p型欧姆接触层 和反射层 204之前可以对外延片进行退火处理激活 Mg杂质使空穴浓度提高； 也可以先在外延片上先制备 ITO、 氧化镍金、 铂钯镍的合金、 铂钯镍中的任意一种并合金， 先使其形成欧姆接触并发生一定界面反应， 然后将其去除， 然后再沉积 ρ型欧姆接触层和反射层 204的反射接触层。 该反射接触层可以是纯银； 也可 以是镍和银组成的叠层结构， 镍层可以是连续的也可以是不连续的； 也可以是银钯铂铑锌镁等金属中两种 或两种以上的合金， 也可以是单质金属； 也可以是在外延膜表面规则的分布着欧姆接触区域， 欧姆接触区 域以外不是欧姆接触， 屑于区域性的叠层结构， 也即紧邻 ρ型 GaN的层是区域性的阵列图形， 然后在其上 沉积金属反射层， 它们共同构成图中所示的 p型欧姆接触层和反射层 204; 总之该 204层具有欧姆接触层 和反射层的双重功效。
图 2-03是在外延片上制备了 204反射接触层后制备了第一腐蚀掩膜层 205后的示意图，它可以光刻胶 也可以是其他感光材料。
图 2-04是第一腐蚀掩膜层 205获得掩膜图形后的示意图，在获得掩膜图形后腐蚀反射层之前一般需对 其进行氧等离子体处理， 用于获得整齐均匀的掩膜效果， 掩膜互补区域 206是为了实现互补电极的掩膜效 果。 第一腐蚀掩膜层 205侧边靠近凹槽 202处有一个掩膜边沿区域 207。
图 2-05是腐蚀反射接触层后的示意图， 由于掩膜互补区域 206不被掩膜，所以腐蚀后实现了欧姆接触 互补区域 208, 从而有利于器件发光效率的提高。 p型欧姆接触层和反射层 204侧边靠近凹槽 202处有一 个欧姆接触边沿区域 209。
图 2-06是去除掩膜层后， 获得了器件所需的 p型欧姆接触层和反射层的图形后的示意图。
图 2-07是在外延片上完成了 p型欧姆接触层和反射层 204图形化后接着在其上制备沉积的第一个转移 衬底 210后的示意图。
图 2-08是将生长衬底去除后的示意图， 至此已经实现铟镓铝氮薄膜从生长衬底到第一个转移衬底 210 的第 1次转移。 图中第一个转移衬底 210可以是金属,的， 也可以是非金属的， 也可以是有机的。 在图中仅 将第一个转移衬底 210表示成一个单层结构， 在实际制备过程中它可以是一个叠层结构。 在此次转移中可 以是铟镓铝氮薄膜所受的来自生长衬底的应力完全释放， 也可以实现薄膜应力的部分释放， 也可以对薄膜 应力进行调节。 若耍实现完全释放， 则图中的第一个转移衬底 210包含一个支撑衬底和一种柔软的粘结材 料， 在生长衬底去除后， 薄膜可以在其上自由伸展， 从而使应力得到充分释放； 若要实现部分释放则可以 通过调节粘结材料的弹性模量和其闹化或凝固收缩率实现， 也可以通过调节电化学沉积或真空沉积衬底的 自身应力实现部分释放。 在此第 1实施方式中着 '说明对薄膜应力进行调节可以如何实现。
LED工作时（指通有一定正向电流）发光发热同时进行， 输入的电功率一部分转变成了热， 器件存在 一定的结温， 这势必引起支撑衬底 （最终的一个衬底） 和铟镓铝氮薄膜的热膨胀。 当支撑衬底和铟镓铝氮 薄膜的热膨胀系数不匹配时， LED在工作时和非:. L作时（指没通电流， 下同）所受的应力会有所不同。 器 件非工作时的应力也称起始应力， 器件工作时的应力也称工作应力。 假如， 垂直结构 LED 非工作时的应 力状态为无应力状态， 且其支撑衬底热膨胀系数比铟镓铝氮薄膜小， 则工作时受其结温的影响， 铟镓铝氮 薄膜会处在压应力状态下工作；假如支撑衬底的热膨胀系数比 GaN大，则铟镓铝氮薄膜会处在张应力状态 下工作； 假如支撑衬底的热膨胀系数与铟镓铝氮薄膜相匹配， 则铟镓铝氮薄膜仍然会基本在无应力状态下 工作。 应力对 LED 的发光效率和可靠性 A有至关 ffi耍的影响， 这是因为铟镓铝氮薄膜是一种极性很强的 材料， 当应力发生变化时其极化电场会发生变化， 从而导致 LED的发光阱层的禁带宽度、 能带倾斜情况、 LED铟镓铝 ¾薄膜正反两面的表面电荷分布、 LED多层结构的界面电荷分布发生变化，所对应的器件工作 电压、 波长、 发光效率和可靠性等均会发生变化。 冈而， 在实际的器件制备中很有必要根据支撑衬底的热 膨胀系数来选择器件薄膜的应力状态， 所以很有必耍对薄膜的应力状态进行调节。 例如， 可以将第一个转 移衬底 210制各成金厲衬底， 金属衬底可以是电化学的方法实现的， 也可以是真空沉积的方法实现的。 如 果本实施方案中所用的外延片是硅衬底外延片， 则该金属衬底层无论是单质金属还是合金， 它都要求能耐 受硅腐蚀液的腐蚀。 该金属衬底在厚度方向可以具有不同的成分分布， 也可以有不同的致密度分布， 不同 的成分分布和致密度分布主耍是为了获得在厚度方向具有不同的热膨胀系数分布。 该金属衬底可以是单质 铬， 也可以是含有铬的合金， 如果它是合金耍求它能耐受硅腐蚀液的腐蚀。 该金属衬底从工艺简单的角度 考虑， 它的最佳选择是单质铬和不锈钢所组成的合金。 该金属衬底的沉积方式可以是： 电弧离子镀、 磁控 溅射、 电子束蒸发、 热蒸发、 热喷涂和电镀等方法中的一种或几种方法的组合。 最优的沉积方式是多靶的 电弧离子镀和磁控溅射。 最典型的金属衬底沉积 T.艺如下： 在多弧离子镀系统的旋转样品台上， 装夹上制 备了钝化层和欧姆接触层的外延片， 使芯片面朝外放置， 使其紧贴样品旋转台。 样品台设置水冷装置，可以 放置镀膜过程中环境温度不断升高。 在样品装夹好后， 然后装配一半数量的单质铬靶和一半数量的 316不 锈钢靶。 先对系统抽真仝'， 待真空度低于 · 8 X 10— 3Pa时， 向真空室通入 Ar气， 使其真空度保持在 0.5Pa。 然后， 加上偏压， 先在外延片上镀一层厚度 100纳米厚度以上的不锈钢， 目的是因为不锈钢的热膨胀系数 比铟镓铝氮薄膜的热膨胀系数大， 所以它对铟镓铝氮薄膜会有一定的压应力作用， 使得本来在外延片上受 到张应力的铟镓铝氮薄膜的应力在转移到新的金厲衬底后可以部分受到驰豫， 甚至转变为受到压应力。 然 后同时镀制纯 Cr及 316L不锈钢， 形成纯 Cr及 316L不锈钢的合金。在镀制合金的过程中真空腔室的环境 温度会不断的升高， 如果在厚度方向合金衬底的成分和致密度是一致的， 它就会引起在腐蚀完硅衬底后， 金属衬底弯曲。 单质铬与不锈钢具有不同的热膨胀系数， 不锈钢的热膨胀系数大于单质铬的热膨胀系数； 对于同一种材料而 R致密材质的热膨胀系数大于疏松材质的热膨胀系数。 所以通过改变衬底的成分分布和 致密度可以改变其在厚度方向的热膨胀系数， 从而可以改变铟镓铝氮薄膜的应力状态和大小。 改变成分主 要是通过两种靶材的弧流实现， 改变致密度主耍是通过改变弧流和偏压两个条件实现。 铍制的金属衬底也 可以是单质铬， 通过改变厚度方向的致密度控制衬底的曲率和膨胀系数。 同时可以镀制比较疏松的金厲衬 底使其热膨胀系数与 Ga 的热膨胀系数基本一致，从而使得器件的可靠性提高。在转移铟镓铝氮薄膜的过 程中由于薄膜受到生长衬底所带来的张应力， 独立台面越大的薄膜受到的张应力越大， 对于这样的薄膜它 的金属衬底可以镀制致密镀稍微偏高和不锈 含; 稍微偏高的衬底， 以达到驰豫薄膜受到的巨大的张应力 的作用。 在后继的两个步骤中可以对薄膜应力进行再次调整， 也可以不再调整。
图 2-09是在将填充在衬底凹槽 202里面的衬底填充物淸理后的示意图，其目的是为了后继步骤中可以 实现接触式曝光， 从而获得铟镓铝氮薄膜更加精准的图形化。 在本实施方案中， 一次转移衬底的优化方案 为沉积在外延片上一种热膨胀系数与铟镓铝氮薄膜相匹配的合金衬底， 并且它是铬和不锈钢共沉积所获得 的衬底。 它能经受后继芯片加工图形化过程中的各种化学腐蚀和真空刻蚀。
图 2-10去除了凹槽填充物后， 再在铟镓铝氮薄膜上沉积了薄膜图形化所需的去边掩膜层后的示意图， 图中 211是去边图形化的掩膜层， 它可以是二氧化硅、 氮化硅、 氮氧硅、 也可以是金属。
图 2-11是在片子表面涂布光刻胶成其他感光材料的第二掩膜 212后的示意图。
图 2-12是图形化光刻完成后的示意图， 图中笫三冈域 213是需要去除的铟镓铝氮区域， 该区域的发光 薄膜受凹槽边界效应的影响如果不去除势必使得器件的光电性能和可靠性降低。
图 2-13是图形化光刻完成后，获得掩膜层图形化后的示意图， 使得第四区域 214的铟镓铝氮薄膜被暴 露。
图 2-14是去除边缘铟镓铝氮薄膜后的示意 此时第五区域 215的附近的铟镓铝氮薄膜形成清晰的边 界， 它有效的使得薄膜的 n型层和 p型层阻断开来而不被边界的薄膜相连导致器件漏电。 去除边缘氮化物 的方法的是反应离子刻蚀， 也可以是湿法腐蚀。 反应离子刻蚀的气体可以是含有氯气的气体， 也可以是含 有其它常见的用于刻蚀氮化镓的气体。 湿法腐蚀的腐蚀液可以是磷酸， 也可以是氢氧化钠， 也可以是氢氧 化钾， 腐蚀时可以加紫外光照射， 也可以不加紫外光照射。
图 2-15是去除光刻胶层和掩膜层后的示意 lik 图 2- 16是在芯片图形表面沉积了钝化层 216后的示意图，该钝化层可以是权利耍求书中所述的钝化层 的任意一种或儿种的组合， 钝化材料可以是二氧化硅、 氮化硅、 三氧化二铝、 聚酰亚氨及其它常见半导体 钝化材料中的一种或几种。
图 2-17是在芯片图形表面沉积了钝化层 216后接着涂布第三光刻胶层 217后的示意图。
图 2-18是在第二光刻胶层 2 获得图形化后的示意图，图中右恻掩膜 218和左侧掩膜 220均为芯片侧 边钝化层的腐蚀掩膜层， 中间掩膜 219是为后继步骤中对图形电镀有帮助的图形化的掩膜图形， 间隙 221 将左侧掩膜 220、 中间掩膜 219和右侧掩膜 218相互隔开的图形。
图 2-19是钝化层 216经过图形化蚀刻后的示意图。
图 2-20是去除光刻胶掩膜层后的示意图，右侧钝化层 222和左侧钝化层 224是侧边钝化图形， 中间钝 化层 223是为后继图形电镀而设置的图形。
图 2-21是在铟镓铝氮薄膜表面获得增加出光的图形织构层后的示意图，也叫做粗化，粗化面 225是氮 化物薄膜经过粗化处理后的示意图。 表面粗化的形状可以是六棱锥形、 六棱柱形、 圆柱形、 圆锥形和柱环 形等形状。 表面粗化形成的方法可以是光电化学腐蚀和 ICP刻蚀中的一种， 也可是两种方法的结合。 如果 用光电化学腐蚀， 其腐蚀剂可以是磷酸也可以是氢氧化钾或氢氧化钠。 获得粗化图形的方法选择上， 要不 破坏钝化层， 比如若用聚酰亚胺或二氧化硅做钝化层则不能用碱粗化氮化物。
I I 2-22是在铟镓铝氮薄膜经过粗化处理后， 在其上蒸发的 n型电极及焊盘层 226后的示意图。 n型电 极及焊盘层 226的最优选抒是 Al/Ti/Au, 也可以是 Al Ni/Au、 Cr/Au等常见的 n型 Ga 的欧姆接触电极和 烨盘的结构， 也可以是仅有一层单质铝， 也可以是金锗镍合金， 也可以是金硅合金， 也可以是氮化钛， 也 可以是含有钛铝的合金， 也可以是金锗镍、 金硅、 氮化钛、 钛铝的两种或两种以上的组合。 n型电极及焊 盘层 226形成的方法可以是蒸发， 也可以是溅射， 也可以是电镀和化学镀等电化学的方法形成的。
图 2-23是在 n型屯极焊盘层 226上涂布第四光刻胶层 227后的示意图。
图 2-24是在光刻胶层 227获得图形化后的示意图， 得到第四图形化光刻胶层 228, 它将在后继的工序 中作为腐蚀电极层的掩膜层， 该图形化的第四图形化光刻胶层 228其在芯片上的位置是与 P型欧姆接触层 和反射层 204的欧姆接触互补区域 208相对应的。
图 2-25是在光刻胶层完成图形化后， 再在其上沉积一层屯流导通层 229后的示意图。
图 2-26是在第一转移衬底 210的 ¾面旋涂保护层 230后的示意图，电流导通层 229的优选方案是镍层， 保护层 230的优选方案是光刻胶。
图 2-27是在锞真空沉积层上电镀金厲的第二转移衬底 231后的示意图， 1尤选方案是电镀镍， 并且采用 硫酸镍体系镀镍。屯镀液组成为：硫酸镍 270g/L，氯化镍 60g/L，硼酸 45g/L，光亮剂 0.5.ml/L，走位剂 20ml/L， 湿润剂 I.5ml/L; ¾镀条件为： 温度 60 °C , pH值 4.5， 阴极电流密度 5A/dm2， 沉积速率 0.6 μ m/min，阳极 为锞板。
图 2-28是在完成金属镍的第二转移衬底 231电镀后，然后去除第一转移衬底 210和保护层 230后的示 意图。 本步骤先 丙酮煮 5min， 酒精泡 lmin, 冲去离子水 lOmin, 以去除保护层 230; 然后用电化学的方 法退镀第一转移衬底 210， 退镀液为： 碳酸钠 250g/L、 磷酸氢二钠 10g/L， 退镀条件为： 阳极电流密度 10A/dm2、 温度为室温、 阴极为低碳钢板。 完成此步骤后， 铟镓铝氮薄膜就实现了第 2次转移， 二次转移 可以对其应力进行调整， 也可以不对其应力进行调整， 调整应力的方法是通过改变电镀镍的第二转移衬底 231的电镀条件实现的。 .
图 2-29是在退镀去除第一转移衬底 210后，然后在芯片阵列 p型一侧上真空沉积铜金属层 232后的示 意图。
图 2-30是在铜金厲层 232上涂布使其图形化的第五光刻胶层 233后的示意图。 图 2-31是在第五光刻 胶层 233获得图形化后的示意图， 第六区域 234是使铜层暴露的图形化区域。
图 2-32是铜金属层 232获得图形化后的示意图，第七区域 235是使铜层图形化的区域， 该区域与中间 钝化层 223预留区相对应。
图 2-33是去掉第五光刻胶层 233的示意图。
图 2-34是在第二转移衬底 231的¾面涂布第二光刻胶保护层 236后的示意图。
图 2-35是图形化的铜金屈层 232上屯镀第二转移衬底 237后的示意图， 屯镀过程中中间钝化层 223 处的钝化材料具有阻断屯镀 Lti流的作 W , 从而使得该区域电镀不上金属， 从而使得电镀出来的第三转移衬 底 237成为各自分开的阵列， 第八区域 238表示各个芯片的镀层衬底相互独立。 如果在电镀的过程中出现 个别区域粘连在一起， 则可以研磨使其分开并使每个图形衬底平整， 或者用光刻腐蚀的办法使粘连部位分 开。 该图形化的芯片最终衬底可以是屯镀的单质铜衬底， 也可以是"铜 /镍 /铜 "叠层结构的衬底， 也可以是 镍钴合金电镀衬底， 也可以是这儿种镀层的¾层组合。 在衬底电镀完成后， 最后再镀一层 0.2微米以上的 金层作为衬底防氧化的保护层。
图 2-36是用一种粘结材料 239将电镀完图形化衬底的芯片阵列与另一支撑衬底 240粘合在一起后的示 意图，其中粘结材料 239是一种具有导电能力的导电胶，支撑衬底 240是具有导电能力的金属衬底，例如， 不锈钢衬底或铜衬底等。
图 2-37是去除第二转移衬底 231上的第二光刻胶保护层 236， 以及退镀掉第二转移衬底 231， 以及腐 蚀出电极图形后的示意图。第二转移衬底 231的退镀优化条件为：退镀液为盐酸 /水 = 1/19,退镀电压 6伏， 退镀温度室温。
图 2-38是去除电极上的第四图形化光刻胶层 228后的示意图，图中 241为经过电极化处理的 n型电极 及焊盘层。 至此， 铟镓铝氮薄膜已经完成整个二次转移并释放和调节应力的三次转移工艺， 此时可以对芯 片阵列进行光电参数 β动点测。
图 2-39是用蓝膜或白膜 242将其与芯片阵列粘合在一起后的示意图，蓝膜或白膜 242也可以用一块支 撑衬底用蜡或松香或热溶胶或其他热光同化之类的胶与一支撑衬底粘结来替换。
图 2-40是去除粘结材料 （导电胶） 239和支撑衬底 240后的示意图。
图 2-41是芯片经过常规翻膜和分选后的示意图， 图中分选膜 243表示承载芯片的分选膜。至此整个芯 片加工过程全部完成， 且芯片的铟镓铝氮的薄膜所受的应力得到释放。 本实施方式采用图形电镀衬底的方 法避免金厲衬底难切割的问题。
对本实施方式所做的任何显而易见的修改， 关键步骤显而易见的重新罗列组合， 关键耍素的重新拼凑 都是受本发明所保护的。
实施方式 2
本实施方式的第 1次和第 2次薄膜转移的工艺和方法与实施方式 1一致， 但第 3次转移的方式与实施方式 1有所不同。在完成图 2-28中所示的歩骤后，接下来的步骤是在 ρ型欧姆接触层和反射层 204上沉积阻挡层和 压焊金属层， 然后与一个衬底邦定压焊在一起， 而不是图形电镀。
阻挡层由钛、 钙、 镍、 铂、 金、 钯、 铬、 钒、 锆、 钼等几种金属中的一种或几种的叠层或合金构成， 它蒸发或溅射在 ρ型欧姆接触层和反射层204上。 同时在阻挡层上沉积压焊金属层， 压焊金属可以是常见的 回流焊的锡膏材料， 也可以是常见的共晶焊的金锡蒸发或溅射层， 也可以是含有钯、 铟、 金、 锡、 铅、 铂、 镍、银等金厲中的一种或儿种组成的合金。 ^此， 此实施方案中图 2-28中的铜金属层 232则替换为由阻挡层 和压焊层组成的金属层 S层。
上述邦定完成后， 去除第二个转移衬底， 然后切割邦定衬底进行分片。
实施方式 3
图 3-01至图 3-10用于说明采用三次转移方法获得本发明所述的释放和调节铟镓铝氮薄膜所受应力的 方法及获得发光器件结构的过程。 本实施方式与前面两个实施方式的不同之处在于： 实施方式 1和实施方 式 2的第 3次转移是将铟镓铝氮薄膜转移在难切割的金属衬底上， 本实施方式是将薄膜转移在易切割的衬 底上； 本实施方式是将薄膜转移在连续平整的衬底上， 待芯片图形化加工全部完成后再切割芯片^成分立 器件。
本实施方式的第〗次转移， 与实施方式〗和实施方式 2相同， 只是该实施方式不需设置有利于阻断电 镀电流的钝化层图形， 即实施例 1 中的中间钝化层 223。 因而对本实施方式的说明从完成了一次转移的相 关步骤， 并已经完成了氮化物去边图形化、 钝化层图形化、 以及表面粗化等步骤幵始对本实施方式进行说 明。
3-01是完成了一次转移即铟镓铝氮薄膜从生长衬底转移到了第一个转移衬底 305， 并且完成了氮化 物 ¾边图形化、 钝化层图形化和表面粗化等儿个工艺步骤后的剖面示意图。 301 是铟镓铝氮薄膜， 302是 欧姆接触反射层， 303是钝化层， 304是粗化图形。 这些构造耍素的基本要求在实施方式 1和实施方式 2 中已经给予了说明， 在此不再重复说明。
图 3-02是在芯片图形阵列表面沉积了金属导通层 306后的示意图， 该金屈导通层可以是高熔点金屈， 也可以是低熔点金属， 也可以是合金。 它可以是铂、 钯、 金、 银、 铜、 铁、 钛、 锌、 锡、 钨、 钼、 钒、 锆、 铟、镍、铝、镁、铬等儿种金属中的一种或几种组成的叠层， 或它们中两种或两种以上金属组成的合金层。 沉积方法可以是溅射、 蒸发、 喷涂、 电镀、 化学镀 ^方法中的一种或几种的组合。
图 3-03是在第一个转移衬底 305背面涂布了防电镀的保护层 307后的示意图。
图 3-04是在金属导通层 306上屯镀金属的第二个转移衬底 308后的示意图，优选方案是第二个转移衬 底 308的热膨胀系数要么与第 3次转移的第二个转移衬底 31 i的热膨胀系数匹配，要么与铟镓铝氮薄膜 301 的热膨胀系数匹配。 该第二个转移衬底 308也可以是电镀以外的其他屯化学方法和真空沉积方法获得的， 若是真空方法获得和制备的则上一步骤中的保护层 307不是必须的。第二个转移衬底 308的热膨胀系数可 以通过控制衬底制备的组分和致密程度进行调节， 也可以使其图形化进行宏观热膨胀系数的调节， 例如， 如果第二个转移衬底 308是铜衬底则可以通过衬底有三分之二的区域是镂空的从而实现其热膨胀系数与氮 化镓匹配。 第二转移衬底 308的优选制备方案是电镀， 且是镂空的电镀衬底。
图 3-05是在完成第二个转移衬底 308制备后，并去除了第一个转移衬底 305及其保护层 307后的示意 图。 完成此步骤后， 铟镓铝氮薄膜就实现了第 2次转移。
图 3-06是在芯片阵列表面制备了扩散阻挡层和压焊金属层 309后的示意图，扩散阻挡层和压焊金属层 309的基本特征和耍求在实施方式 2中已经进行了说明， 在此不再重复说明。
图 3-07是将芯片阵列与第三个转移衬底压焊在一起后的示意图。图中 310表示芯片和衬底之间的融合 在一起的邦定焊接金屈层， 该层中除了包括焊接金厲层外， 还包括铟镓铝氮薄膜一侧的扩散阻挡层和第三 个转移衬底 311—侧的扩散阻挡层。 图中 3 12层是第三个转移衬底的背面金属的第二个保护层， 它与衬底 之间耍求是欧姆接触。 第二个转移衬底可以是硅衬底、 锗衬底、 石墨衬底、 砷化镓衬底、 以及其他易于切 割且导 的非金屈衬底。
图 3-08是去除第二个转移衬底 308和金属导通层 306后的示意图。
图 3-09是在芯片阵列上制备了 n型电极和焊盘 313后的示意图， n型电极和焊盘的基本特征和要求在 实施方案 1中已经进行了说明， 在此不再 S复说明。
图 3-10是在芯片阵列切割成分立器件后的示意图。切割方式可以是常见的机械切割， 也可以是激光切 割， 也可以是水刀切割， 也可以是水柱波导激光切割， 也可以是水柱喷砂切割， 也可以是多线锯带砂切割， 也可以是金刚砂划痕解理切割， 也可以是电火花切割， 也可以是砍片裂解切割， 也可以是以上几种切方式 的组合。 优选的切割方式为机械切割。
对本实施方式所做的任何显而易见的修改， 关键步骤显而易见的重新罗列组合， 关键耍素的重新拼凑 都是受本发明所保护的。
实施方式 4
图 4-01至图 4-1 1 于说明釆用 3次转移方法获得本发明所述的释放和调节铟镓铝氮薄膜所受应力的 方法及获得发光器件结构的制造方法和过程。 与前面所述的几个实施方式的不同之处在于， 对铟镓铝氮薄 膜的去边、 粗化、 n屯极 ^图形化步骤是在完成第 3次转移后进行的， 也即除了 p型欧姆接触电极的图形 化工作是在转移之前在外延片上完成的， 其他图形化的工作均是在第 3次转移步骤完成之后进行的。
本实施方式的第 1次转移的实现方法与途径的基本特征和要求与前面己经说明的实施方式 1的基本特 征和基本耍求基本一致， 在此不再 ffi复说明。
图 4-01是完成了一次转移即铟镓铝氮薄膜从生长衬底转移到了第一个转移衬底 403后的剖面示意图。
401是铟镓铝氮薄膜， 402是欧姆接触反射层， 404是在芯片阵列表面沉积的金属导通层。 这些构造耍素的 基本要求在前面的施方式中已经给予了说明， 在此不再 ffi复说明。
图 4-02是导通电流的导通层 404上沉积了第二个转移衬底 405后的示意图。该导通层 404及第二个转 移衬底的基本特征和基本耍求在前面实施方式中已经说明， 在此不再重复说明。
图 4-03是在完成第二个转移衬底 405制备后， 并去除了第一个转移衬底 403后的示意图。完成此步骤 后 ' 铟镓铝氮薄膜就实现了第 2次转移。
4-04是在芯片阵列表面制备了扩散阻档层和压焊金属层 406后的示意图，扩散阻挡层和邦定压焊金 属层 406的基本特征和耍求在前面的实施方式中已经进行了说明， 在此不再重复说明。
图 4-05是将芯片阵列与第二个转移衬底压焊在一起后的示意图。图中 407表示芯片和衬底之间的融合 在一起的邦定焊接金屈层。 图中 408表示第三个转移衬底。 图中保护层 409是第三转移衬底的背面金属保 护层， 它与衬底之间要求是欧姆接触。
图 4-06是去除第二转移衬底 405和导通层 404后的示意图。完成此步骤后，铟镓铝氮薄膜就实现了第 3次转移。
图 4-07是在芯片阵列上形成了有利于出光的粗化图形后的示意图， 图中 4】0表示粗化图形。形成粗化 图形 410的基本特征和基本耍求在前面实施方式中已经说明， 在此不再重复说明。
图 4-08是在去除芯片阵列边缘的氮化物后的示意图，图中第一区域 41 1所指的位置是边缘氮化物去除 后的位置， 去除边缘氮化物方法和过程的基本特征和基本要求在前面实施方式中已经说明， 在此不再重复 说明。
图 4-09是在芯片阵列表面形成钝化增透层后的示意图， 图中 412为钝化增透层。 图中第二区域 413 所指的位置是没有钝化增透层的位置， 将此位 S的钝化增透层去除的目的是为了形成 n电极金属及引线焊 盘。 形成钝化增透层 412的方法和过程的基本特征和基本耍求在前面实施方式中已经说明， 在此不再重复 说明。
图 4-10是在芯片阵列表面形成了 n电极及引线焊盘 414后的示意图，其基本特征和基本耍求在前面实 施方式中己经说明， 在此不再重复说明。
图 4-1 1是在芯片阵列被切割成分立器件后的示意图， 第三区域 415是切痕所在的位置，形成第三区域 415的方法和耍求的其基本特征和基本耍求在前面实施方式中己经说明， 在此不再重复说明。
对本实施方式所做的任何显而易见的修改， 关键步骤显而易见的重新罗列组合， 关键要素的重新拼凑 都是受本发明所保护的。
实施方式 5
本实施方式与实施方式 4所述的方法的相同之处在于： 对铟镓铝氮薄膜的去边、 粗化、 n电极等图形 化步骤是在完成第 3次转移后进行的， 不同之处在于： 第二转移所用的导通层 404不是金属层， 而是一种 有机物， 该有机物能够有效的释放或调节铟镓铝氮薄膜的应力状态。 该有机材料的基本特征是： 可以是 蜡、 热熔胶、 松香、 紫外固化胶、 邦定胶、 树脂、 以及其他单组分或双组分或多组分的有机胶水， 它可以 是热同化的有机物、 也可以热熔有机物、 也可以是光固化的有机物、 也可以反应固化的有机物。 它可以是 热固型的胶黏剂、 也可以是热熔型的胶黏剂、 还可以是室温固化型的胶黏剂、 还可以是压敏型的胶點剂。 它可以是纤维素酯、 烯类聚合物 〔聚乙酸乙烯酯、 聚乙烯醇、 过氯乙烯、 聚异丁烯等）、 聚酯、 聚醚、 聚 酰胺、 聚丙烯酸酯、 a-氰基丙烯酸酯、 聚乙烯醇缩醛、 乙烯 -乙酸乙烯酯共聚、 环氧树脂、 酚醛树脂、 脲醛 树脂、 三聚氰 -甲醛树脂、 有机硅树脂、 呋喃树脂、 不饱和聚酯、 丙烯酸树胎、 聚酰亚胺、 聚苯并咪唑、 酚 醛-聚乙烯醇缩醛、 酚醛-聚酰胺、 酚醛 -环氧树脂、 环氧-聚酰胺、 合成橡胶、 氯丁橡胶、 丁苯橡胶、 丁基橡 胶、 丁钠橡胶、 异戊橡胶、 聚硫橡胶、 聚氨酯橡胶、 氯磺化聚乙烯弹性体、 硅橡胶、 酚醛-丁腈胶、 酚醛- 氯丁胶、 酚醛 -聚氮酯胶、 环氧-丁腈胶、 环氧-聚硫胶等中的一种或几种的组合。 .导通层 404可以整层是前 面所说明的某种有机物， 也可以两种有机物组成的叠层结构， 也可以是两种有机物以上的多层叠层结构， 还可以是多种有机物相互混合所制备的可以固化的粘结物或粘结剂。 该导通层 404可以是因为该层柔软而 使得铟镓铝氮薄膜所受的应力得到释放； 也可以是因为该有机层在固化中具有一定的固化收缩率或固化膨 胀率而使得铟镓铝氮薄膜的张应力变小或变大 （压应力变大或变小）， 从而实现对铟镓铝氮薄膜的应力进 行调整或释放。
在用前面所述的有机物完成铟镓铝氮薄膜的二次转移后， 其余的加工制造的工艺步骤的耍求和特征与 实施方式 4基本一致， 在此不再重复说明。
对本实施方式所做的任何显而易见的修改， 关键步骤显而易见的重新罗列组合， 关键要素的重新拼^ 都是受本发明所保护的。
实施方式 6 ' .
本实施方式与实施方式 4和 5所述的方法的不同之处在于： 第 2次转移所用的导通层 404既不是金属 层也不是有^物层， 而是一种可以固化的无机非金属材料。
该导通层 404所用的无机非金厲粘结材料的基本特征是： 它是硅酸盐、 磷酸盐、 氧化物、 硫酸盐和硼 酸盐等中的一种或儿种。 它可以是仝气干燥型的无机胶黏剂， 依赖 Τ·溶剂挥发或失去水分而固化， 比如水 玻璃和粘土； 也可以是水固化型的无机胶黏剂， 它以水为固化剂， 加水产生化学反应而固化， 比如石膏和 水泥； 它也可以是热熔 的无机胶黏剂， 比如低熔点玻璃、 低熔点的玻璃陶瓷和硫黄等常见的无机热熔胶 黏剂； 它还可以是化学反应 ^的无机胶黏剂， 通过加入同化剂来产生化学反应而同化， 比如硅酸盐类胶黏 剂、 磷酸盐类胶黏剂、 胶体氧化铝赚翻、 牙科胶泥胶黏剂等。 它可以是水泥、 石膏、 水玻璃、 石灰、 粘土、 低分子化合物组成的无机盐 （磷酸盐和硅酸盐）等中的一种或儿种的组合， 它可以是由一种无机胶 黏剂组成的单层结构， 也可以是多种无机胶黏剂组成的 ¾层结构， 也可以是它们组成的混合物的叠层或单 层结构。 该导通层 404可以是因为该层同化的时候产生收缩或膨胀来对铟镓铝氮薄膜的应力进行调整或释 放。
在用前面所述的无机胶黏剂完成铟镓铝氮薄膜的二次转移后， 其余的加工制造的工艺步骤的要求和特 征与实施方式 4和 5的一致， 在此不再 ffi复说明。
对本实施方式所做的任何显而易见的修改. 关键步骤显而易见的重新罗列组合， 关键要素的重新拼凑 都是受本发明所保护的。
实施方式 7
本实施方式与前面已经说明的实施方式 1的不同之处在于： 第 1次转移前的芯片图形化的工艺里面， 它除了形成 p型欧姆接触反射层外， 还在其上图形化形成了 p面钝化层， 该层的作用也可以不完全是为了 钝化 p面而设 ¾， 它可以是为了维持铟镓铝氮的应力状态、 或增加应力回复、 或减小应力回复、 或减小后 继转移过 ¾中的衬底制备 Ί :艺对薄膜的应力产生影响而设置的， 也可以是为了提高芯片制造良率而设置的 用来加强铟镓铝氮薄膜的机械强度而设 S的， 该层可以最后在器件里面存在， 也可以最后不在器件里面存 在。
图 5-01是在外延片上完成了 p面钝化层图形化后的示意图。 图中 501是生长衬底， 502是将生长衬底 分割成独立平坦区域的凹槽， 503是铟镓铝氮薄膜层， 504是 p面钝化层， 以上各层的基本特征和基本耍 求在前面的实施方式中己经给予了说明， 在此不再重复说明。
图 5-02是在外延片上完成了欧姆接触反射层 505图形化后的示意图。欧姆接触反射层 505的基本特征 和基本耍求在前面的实施方案中已经给予说明， 在此不再重复说明。
图 5-03是在外延片上形成了压焊金厲层 506后的示意图。该层的基本特征和基本耍求在前面实施方式 中已经说明， 在此不再 ffl复说明。
5-04是在压焊金属层 506上制备了第一个转移衬底 507和衬底背面保护层 508后的示意图。该衬底 可以是邦定压焊在外延片上的， 也可以是电镀在外延片上的， 也可以是用胶黏剂胶黏在外延片上的。 如果 是电镀金厲衬底， 则第一个转移衬底 507及其背面的保护层 508的基本要求与前面已经说明的相关实施方 式中的衬底和背面保护层的基本耍求一致。 如果是邦定金属衬底， 则其邦定层与背面保护层的基本要求也 与前面已经说明的相关内容耍求一致： 金屈衬底也可以是压焊金厲层 506不用金属， 而用前面已经说明过 的相关胶黏剂粘结。 如果是蓝宝^ '片、 玻璃片、 陶瓷片等非金属衬底， 则 506可以是金属层也可以是胶黏 剂层， 其耍求与前面已经说明过的相关内容和耍求基本一致。 如果是有机衬底， 则压焊金属层 506可以是 低熔点的金屈， 也可以是胶黏剂， 也可以是不耍胶黏剂而直接将有机衬底与外延片热压在一起使有机衬底 在粘结界面处发生熔化成软化， 然后冷却凝 |Α|实现与外延片之间的粘合。
图 5-05是在外延片与第一个转移衬底实现了粘结或捍.接后，将生长衬底去除后的示意图。去除衬底的 方法可以是激光剥离、 化学腐蚀、 机械研磨、 化学机械磨抛、 离子物理刻蚀、 反映离子刻蚀等方法中的一 种或几种的结合。 对于硅衬底而言去除衬底的最优化方案是化学腐蚀， 对蓝宝石衬底而言最优化的方案是 激光剥离。 至此芯片已经完成一次转移。 . 图 5-06是去除一次转移衬底后，通过粘结层 509将芯片阵列与第二个转移衬底 510粘合在一起的示意 图。 粘接层 509可以是沉积的金厲层， 第二个转移衬底 510是在金属层上的电镀衬底， 通过衬底电镀工艺 对应力进行调节： 粘接层 509可以是金属压焊层， 第二个转移衬底 510是压焊衬底， 通过压焊温度、 衬底 热膨胀系数、 压焊层的熔点和组分来调节应力； 粘接层 509可以是胶黏剂， 第二个转移衬底 510可以是有 机、 无机、 无机非金属衬底， 通过胶黏剂的 化收缩率或 化膨胀率或同化温度或几个条件的结合来调节 其对铟镓铝氮薄膜 503的应力。
图 5-07是去除二次转移衬底后的示意图》至此铟镓铝氮薄膜就实现了二次转移和所述的应力释放和调
•P。
ISI 5-08是将芯片阵列与笫三个转移衬底压焊在一起后的示意图。图中 5 Π表示三次转移的压焊层， 512 表示第 ΞΞ个转移衬底， 第二个保护层 513表示衬底背面的保护层。 压焊层 511、 第三个转移衬底 512和第 二个保护层 513的基本耍求和基本特征， 及其调节应力的方法在前面的实施方案中已经进行了说明， 在此 不再重复说明。
图 5-09是去除第二个转移衬底 510、 粘结层 509后的示意图。 完成此步骤后， 铟镓铝氮薄膜就实现了 第 3次转移。 . ，.
图 5-10是在芯片阵列上去除了处在笫一区域 514位置的凹槽填充物后的示意图。
图 5-11是在对芯片阵列进行表面粗化处理后的示意图， 图中 515表示粗化图形， 其形成方法和基本特 征及基本耍求在前面实施方式中已经说明， 在此不再 fi '复说明。
图 5-12是去除第二区域 516位 S的芯片阵列边缘氮化物后的示意图，其形成方法和基本特征及基本要 求在前面实施方式中已经说明， 在此不再―道复说明。
图 5-13是在芯片阵列表面形成钝化增透层后的示意图， 图中 517表示钝化增透层。 图中第三区域 518 所指的位置是没有钝化增透层的位置， 将此位置的钝化增透层去除的目的是为了形成 n电极金属及引线焊 盘。形成钝化增透层的方法和过程的基本特征和¾本要求在前面实施方式中已经说明，在此不再重复说明。
图 5-14是在芯片阵列表面形成了 n ¾极及引线焊盘 519后的示意图，其基本特征和基本要求在前面实 施方式中已经说明， 在此不再 £复说明。
图 5-15是在芯片阵列被切割成分立器件后的示意图， 第四区域 520是切痕所在的位置， 形成第四区域 520的方法和耍求的基本特征和基本耍求在前面实施方式中已经说明， 在此不再重复说明。
对本实施方式所做的任何显而易见的修改， 关键步骤显而易见的重新罗列组合， 关键要素的重新拼凑 都是受本发明所保护的。
实施方式 8
本实施方式与前面已经说明的实施方式的不同之处在于：在图 5-01中的 P面钝化层 504所指的要素替 换成一个热膨胀系数大于 GaN的金属层， 也可以是热膨胀系数小于 GaN的非金属层。
实施方式 9 '
本实施方式与前面已经说明的实施方式的不同之处在于： 第 1次转移和第 2次转移均是用胶黏剂实现 转移的， 通过调节胶黏剂的闹化膨胀率或 ISI化收缩率或柔性胶黏剂实现应力调节和释放的， 第 3次转移可 以用常见的邦定技术或电镀技术实现芯片转移。
图 6-01是在生长衬底 601上形成了铟镓铝氣外延膜（即铟镓铝氮薄膜） 602后的的示意图。 生长衬底 601是没有被凹槽或凸起分割的均匀连续的衬底， 铟镓铝氮外延膜 602是在生长衬底上形成的均匀联系的 外延薄膜。
图 6-02是在外延片上的铟镓铝 ¾薄膜被刻蚀成阵列， 以及形成了 p面钝化层 603后的示意图。 p面钝 化层 603的基本特征和基本耍求在前面的实施方案中已经给予说明， 在此不再重复说明。
图 6-03是在外延片上形成了胶黏层 604后的示意图。胶黏层 604所用胶黏剂种类的选择根据铟镓铝氮 层所受的应力进行选择， 若铟镓铝氮外延膜 602受到的是张应力则选择同化收缩的胶黏剂， 若铟镓铝氮外 延膜 602受到的是压应力则选择^化膨胀的胶黏剂， 也可以不考虑铟镓铝氮外延膜 602所受的应力而选择 柔性胶黏剂。 胶黏剂的基本特征和基本耍求在前面实施方式中已经说明， 在此不再重复说明。
图 6-04是将第一个转移衬底 606通过固化了的胶黏层 605实现了外延片与衬底胶结后的示意图。 图 6-05是将生长衬底去除后的示意图。去除衬底的方法的基本特征和基本要求在前面实施方式中已经 说明， 在此不再 S复说明。 至此芯片已经完成一次转移， 铟镓铝氮外延膜 602的应力会受胶黏剂固化收缩 或膨胀或因为是柔性的而对其应力进行调节或释放。
图 6-06是去除一次转移衬底后，通过粘结层 607将芯片阵列与第二个转移衬底 608粘合在一起的示意 图。粘结层 607同样可以通过选抒 M化膨胀或 l?r|化收缩或柔性胶黏剂对铟镓铝氮外延膜 602的应力进行调 节和释放。
图 6-07是去除第二个转移衬底后的示意图。至此铟镓铝氮薄膜就实现了二次转移和所述的应力释放和 调节。
图 6-08是将芯片阵列与第二个转移衬底压焯在一起后的示意图。图中 609表示三次转移的压焊层， 610 表示第三个转移衬底， 61 1表示衬底背面的保护层。 压焊层 609、 第三个转移衬底 610和保护层 611 的基 本耍求和基本特征， 及其调节应力的方法在前面的实施方案中已经进行了说明， 在此不再重复说明。
图 6-09是去除第二个转移衬底后的示意& I。 完成此步骤后， 铟镓铝氮薄膜就实现了第 3次转移。 6-10是在对芯片阵列进行表面粗化处理后的示意图，其形成方法和基本特征及基本耍求在前面实施 方式中己经说明， 在此不再 S复说明。
图 6-11是去除芯片阵列边缘氮化物后的示意图，其形成方法和基本特征及基本要求在前面实施方式中 已经说明， 在此不再 ffi复说明。
图 6-12是在芯片阵列表面形成钝化增透层后的示意图， 图中 612表示钝化增透层。 图中第一区域 613 所指的位置是没有钝化增透层的位置， 将此位置的钝化增透层去除的目的是为了形成 n电极金属及引线焊 盘。形成钝化增透层的方法和过程的基本特征和基本耍求在前面实施方式中已经说明，在此不再重复说明。
图 6-13是在芯片阵列表面形成了 n屯极及引线焊盘 614后的示意图，其基本特征和基本要求在前面实 施方式中己经说明， 在此不再 S复说明。
图 6-14是在芯片阵列被切割成分立器件后的示意图，第二区域 615是切痕所在的位置，形成第二区域 615的方法和耍求的基本特征和基本耍求在前面实施方式中已经说明， 在此不再重复说明。
对本实施方式所做的任何显而易见的修改， 关键步骤显而易见的重新罗列组合， 关键要素的重新拼凑 都是受本发明所保护的。
实施方式 10 ' 本实施方式 前面己经说明的实施方式的不同之处在于： 为了使器件具有高的出光效率， 其 p面钝化 层和欧姆接触反射层是在完成第 2次转移后， Τ·笫 3次邦定前制备的， 因而器件的铟镓铝氮薄膜整个台面 都有反射层增加出光效果， 并且反射层无需图形化处理。
图 7-01是外延片的示意图。 生长衬底 701被凹槽 703分割成独立平坦区域阵列， 702是铟镓铝氮外延 膜。 生长衬底 701、 铟镓铝铽外延膜 702和凹槽 703的基本特征和基本耍求在前面的实施方案中已经给予 说明， 在此不再重复说明。
图 7-02是在外延片上形成了 ρ ¾欧姆接触牺牲层 704后的示意图。该层可以是镍、氧化镍金、铑或其 合金、 铂或其合金、 氧化铟锡等中的一种或一种以上的合金， 可以通过完成沉积 ρ型欧姆接触牺牲层 704 层后， 通过合金退火处理实现欧姆接触。
图 7-03是在外延片的凹槽处制备了填充物 705后的示意图。该填充物可以是金属、也可以是光刻胶等 有机物。
图 7-04是在外延片上形成了屯镀导通层 706后的示意图，其基本特征和基本要求在前面实施方式中已 经说明， 在此不再 复说明。
图 7-05 ¾在外延片上屯镀了第一个转移衬底 707和衬底背面保护层 708后的示意图，其基本特征和基 本耍求在前面实施方式中已经说明， 在此不再 ffi复说明。
图 7-06是去除生长衬底 70!和凹槽填充物 705后的示意图。去除衬底方法的基本特征和基本要求在前 面实施方式中已经说明， 在此不再 ffi复说明。 至此芯片已经完成一次转移， 在此次转移中可以通过改变衬 底的电镀条件对铟镓铝氮薄膜的应力进行调节， 也可以不对其进行调节。
图 7-07是去除一次转移衬底后，通过粘结层 709将芯片阵列与第二个转移衬底 710粘合在一起后的示 意图。通过选择粘接层 709的阇化膨胀率成 I l化收缩率或柔性胶黏剂对铟镓铝氮层的应力进行调节和释放。
图 7-08是去除第一个转移衬底 707、 去除一次转移衬底的保护层 708、 去除一次转移粘结层 709、 去 除 P型欧姆接触牺牲层 704后的示意图。 至此铟镓铝氮薄膜就实现了二次转移和所述的应力释放和调节。
图 7-09是在铟镓铝挺薄膜上形成了 p面钝化层 71 1后的示意图，其基本特征和基本耍求在前面实施方 式中已经说明， 在此不再 S复说明。
图 7-10是在铟镓铝氮薄膜上形成了复合层 712后的示意图。 该层包括欧姆接触反射层、 扩散阻挡层、 压焊粘结层， 其基本特征和基本耍求在前面实施方式中已经说明， 在此不再重复说明。
图 7- 1 1是将芯片阵列与第二个转移衬底压焊在一起后的示意图。图中 713表示三次转移的压焊层， 714 表示第二个转移衬底， 715表示衬底背面的笫二个保护层。 压焊层 713、 笫三个转移衬底 714和第二个保 护层 715的基本要求和基本特征， 及其调节应力的方法在前面的实施方案中已经进行了说明， 在此不再重 复说明。
图 7- 12是去除第二个转移衬底 710和粘结层 709 jfj的示意图。完成此步骤后，铟镓铝氮薄膜就实现了 第 3次转移。
图 7-13是在对芯片阵列进行表面粗化处理后的示意图。图中 716表示粗化图形，其形成方法和基本特 征及耍求在前面实施方式中已经说明， 在此不再重复说明。
图 7-14是去除芯片阵列边缘第一区域 717位置处的氮化物后的示意图，其形成方法的基本特征及要求 在前面实施方式中己经说明， 在此不再重复说明。
图 7-15是在芯片阵列表面形成钝化增透层 718和 n型电极及焊盘 719后的示意图。 形成 718和 719 的方法和过程的基本特征和基本耍求在前面实施方式中已 ¾说明， 在此不再重复说明。
图 7-16是在芯片阵列被切割成分立器件后的示意图，切割芯片阵列的方法和耍求的基本特征和基本要 求在前面实施方式中巳经说明， 在此不再重复说明。
对本实施方式所做的任何显而易见的修改， 关键步骤显而易见的重新罗列组合， 关键要素的重新拼凑 都是受本发明所保护的。
实施方式 1 1
本实施方式与实施方式 9的不同之处在于:第 1次转移和第 2次转移均用胶黏剂与衬底粘结实现转移， 第 3次电镀衬底实现转移。
图 8-01是外延片的示意图。 生长衬底 801被凹槽 803分割成独立平坦区域阵列， 802是铟镓铝氮外延 膜。 生长衬底 801、 凹槽 802和铟镓铝氮外延膜 803的基本特征和基本要求在前面的实施方案中已经给予 说明， 在此不再重复说明。
图 8-02是在外延片上形成了 p型欧姆接触牺牲层 804后的示意图。该层的基本特征和基本要求在前面 的实施方案中已经给予说明， 在此不再重复说明。
图 8-03是用胶黏剂层 805把外延片与第一个转移衬底 806粘结在一起后的示意图，其基本特征和基本 耍求在前面实施方式中已经说明， 在此不再重复说明。
图 8-04是去除生长衬底 801后的示意图。至此芯片已经完成一次转移。去除衬底方法及调整应力的方 法的基本特征和基本耍求在前面实施方式中已经说明， 在此不再重复说明。
8-05是去除第一个转移衬底后，通过粘结层 807将芯片阵列与第二个转移衬底 808粘合在一起后的 示意图。 通过选择粘接层 807的 |?;|化膨胀率或固化收缩率或柔性胶黏剂对铟镓铝氮层的应力进行调节和释 放。
图 8-06是去除第一个转移衬底 806和胶黏剂层 805后的示意图。至此铟镓铝氮薄膜就实现了二次转移 和权力耍求书中所述的应力释放和调节。
图 8-07是去除 p型欧姆接触牺牲层 804后的示意图。
图 8-08是在铟镓铝氮薄膜上形成了 p面钝化层 809后的示意图，其基本特征和基本要求在前面实施方 式中己经说明， 在此不再重复说明。
图 8-09是在铟镓铝氮薄膜上形成了欧姆接触反射层 810和压焊粘结及扩散阻挡层 81 1后的示意图，其 基本特征和基本耍求在前面实施方式中已经说明， 在此不再重复说明。
图 8-10是将芯片阵列与第三支撑衬底压焊在一起后的示意图。 图中 812表示三次转移的压焊层， 813 表示第三个转移衬底， 814表示衬底背面的保护层。
8- 1 1是去除第二个转移衬底 808和粘结层 807后的示意图。完成此步骤后，铟镓铝氮薄膜就实现了 第 3次转移。
图 8-12是在对芯片阵列进行表面粗化处理后的示意图。图中 815表示粗化图形，其形成方法和基本特 征及要求在前面实施方式中已经说明， 在此不再重复说明。
图 8- 13是去除芯片阵列边缘 816位置处的氮化物后的示意图，其形成方法的基本特征及要求在前面实 施方式中已经说明， 在此不再重复说明。
图 8-14是在芯片阵列表面形成钝化增透层 817， 和在第一区域 818处没有钝化增透层的位置形成 n型 电极及焊盘 S19后的示意图。 形钝化增透层 817、 第一区域 818和 n型电极及焊盘 8] 9的方法和过程的基 本特征和耍求在前面实施方式中已经说明 , 在此不再重复说明。
图 8-15是在芯片阵列被切割成分立器件后的示意图， 第二区域 820是切痕所在的位置。切割芯片阵列 的方法和要求的基本特征和基本要求在前面实施方式中已经说明， 在此不再重复说明。
对本实施方式所做的任何显而易见的修改， 关键步骤显而易见的重新罗列组合， 关键要素的重新拼凑 都是受本发明所保护的。
实施方式 12 本实施方式与前面已经说明的实施方式的不同之处在于： 芯片图形化的加工工序在第 1次转移前全部 完成,并且它是在一个热膨胀系数与 GaN匹配的衬底上完成的；第 2次转移采用电镀或邦定或胶黏剂转移； 第 3次采用图形电镀实现免划片。
图 9-01是外延片的示意图。 901是生长衬底， 902是铟镓铝氮外延膜， 其基本特征和基本要求在前面 的实施方案中已经给予说明 . 在此不再; 2复说明。
图 9-02是在外延片上形成了 p型欧姆接触反射层 903、 芯片边缘的低功函数的金屈钝化层 904、 压焊 扩散阻挡层 905和压焊粘结层 906后的示意图。其基本特征和基本要求在前面的实施方案中已经给予说明， 在此不再重复说明。
图 9-03是用将外延片和第一个转移衬底压焊在一起后的示意图。该第一个转移衬底是一个复合的 ®层 结构的衬底，该衬底的笫一层 907具有与 GaN相匹配的热膨胀系数；该衬底的第三层 909是具有与生长衬 底相匹配的热膨胀系数： 第二层 908层是将第一层 907层和第三层 909层粘在一起的压焊层。 第一层 907 层可以减少芯片加工过程中衬底对铟镓铝氮薄膜的冷热冲击损伤； 第三层 909层可以防止一次转移邦定完 成后衬底引起的外延片破裂。
图 9-04是去除生长衬底 901后的示意图， 背面有保护层 910。 至此芯片巳经完成一次转移。
图 9-05是对铟镓铝氮外延膜 902进行了表面粗化处理后的示意图， 911是粗化图形。
图 9-06是将铟镓铝氮外延膜 902刻蚀成芯片阵列后的示意图， 第一区域 912是刻蚀位置。
图 9-07是在芯片阵列上形成了钝化增透层 13 , n电极及焊盘 914和芯片阵列缝隙 915后的示意图。
9-08是在芯片阵列表面形成了屮」镀导通层 916后的的示意图。导通层 916可以是电镀导通层，也可 以是衬底压焊层、 也可以是胶黏剂 )S， 其基本特征和基本耍求在前面实施方式中己经说明， 在此不再重复 说明。
图 9-09是在导通层 916上电镀了第二个转移衬底 917后的示意图，第二个保护层 918是衬底背面保护 层 此步骤中第二个转移衬底可以是 胶黏剂胶结的衬底， 也可以是压焊邦定的衬底。
图 9-10是去除第一个转移衬底后的示意图。 至此芯片已经实现二次转移。 '
图 9-Π是在芯片阵列表面形成了图形电铍光刻胶图形后的示意图， 919表示光刻胶图形。
图 9-12是在芯片阵列表面屯镀了图形衬底 920和衬底保护层 921后的示意图。
图 9-13是去除第二个转移衬底 917、 第二个保护层 918和导通层 916后的示意图， 922是承载芯片分 立器件的蓝膜。 至此芯片加 :.1.：工序全部完成。
对本实施方式所做的任何显而易见的修改， 关键步骤显而易见的重新罗列组合， 关键要素的重新拼凑 都是受本发明所保护的。
实施方式 13
本实施方式与前面已经说明的实施方式的不同之处在于： 第 1次转移的衬底是图形电镀的衬底， 将其 粘结在另一块衬底上， 然后激光剥离移除衬底, 这样有利于激光时气化物质的排放， 从而减小铟镓铝氮薄 膜所受的损伤。
图 10-01是外延片的示意图， 1001是生长衬底， 〗002是铟镓铝氮外延膜。
图 10-02是实现了铟镓铝氮薄膜图形阵列化后的示意图，第一区域 1003是刻穿氮化物薄膜的刻槽位置。 图】0-03是形成芯片阵列边缘的钝化层后的的示意图， 1004是钝化层。
图 10-04是制备了 p型欧姆接触反射层 1005后的示意图。
图 10-05是制备了扩散阻挡层和压焊层 1006后的示意图， 该扩散阻挡层和压焊层 1006在整个片子表 面耍求是能相互能导通屯流的。
图】0-06是芯片阵列上形成了屯镀图形 W底的图形化的光刻胶 1007后的示意图。
图 10-07是在芯片阵列上 镀了图形衬底——第一个转移衬底 1008后的示意图。
图 10-08是在图形衬底屯镀完成； Γτ, 将图形光刻胶 1007去除后， 并将其通过胶黏剂 1009与连体衬底
10 i 0粘结在一起后的示意图。
图 10-09是移除生长衬底 1001后的示意图。 至此， 已经实现铟镓铝氮薄膜的一次转移。尤其对于蓝宝 石衬底的外延片， 由于有图形电镀衬底阵列间的缝隙存在， 它可以将激光剥离时氮化物的气化物质及时排 除， 从而减小铟镓铝氮薄膜所受的冲 损伤。
^ 10-10是川第二胶黏剂 10 ! 1将芯片阵列 第二个转移衬底 1012粘结在一起后的示意图。 也可以用 电镀衬底或邦定压焊衬底制备二次转移衬底。
图 10-11是去除第一个转移衬底 1008的连体 1010和粘结层的胶黏剂 1009后的示意图。
图 10-12是去除第一个转移衬底 1008后的示意图。
图 10-13是将芯片阵列与第三个转移衬底 1014邦定压焊在一起后的示意图， 图中 1013是衬底正面的 压焊金属层， 】015是衬底背面的金属层保护层。
图 10-14是完成邦定压焯后， 将笫二个转移衬底 1012及第二胶黏剂 1011去除后的示意图。 图中 1016 表示压焊金属层】013和扩散阻挡层和压焊层 1006相互熔焊连接后的邦定金属层。 至此， 就实现了铟镓铝 氮薄膜的三次转移。
图 10-15是在芯片阵列表面形成了粗化图形 1017后的示意图。
图 10-16是在芯片阵列表面形成了 n型屯极及焊盘 1018后的示意图。
图 10-17是在芯片阵列被切割成分立器件后的示意图。
对本实施方式所做的任何显而易见的修改， 关键步骤显而易见的重新罗列组合， 关键要素的重新拼凑 都是受本发明所保护的。
实施方式 14
本实施方式与前面己经说明的实施方式的不同之处在于： 第 1次转移之前在外延片的芯片阵列之间的 缝隙位 在衬底上制备 1 ~300微米深皮的凹槽: 然后， 将其与衬底邦定在一起: 然后研磨减薄衬底至凹 槽使芯片阵列相互分幵各 ΰ独立； 然后再移除剩下的生长衬底及进行其他加工。 本方式不但可以减小激光 剥离生长衬底时对铟镓铝氮薄膜的冲 1损伤， 而且可以避免有些衬底很难切割划片的问题。
图 11 -01是用胶黏剂 1309将第一次转移衬底 1308和外延片粘结在一起前的示意图。 图中的外延片， 其生长衬底 1301上的铟镓铝氮薄脇 1302被刻蚀成阵列，并制备了 ρ面钝化层 1303、ρ面互补钝化层 1304、 欧姆接触反射层 1305、 压焊扩散阻挡层 1306和金属压焊层 1307。
图 1 1 -02是将一次转移衬底 1308 外延片粘结在一起后的示意图。
' 图 1 1 -03是将生长衬底研磨减薄 β动分开后的示意图， 图中 1310是研磨减薄后的生长衬底。
图 Π -04是移除剩下的减薄ή的生 衬底 1310后的示意图。 至此， 实现了铟镓铝氮薄膜的一次转移。 图 11 -05是用胶黏剂 1312将芯片阵列与第二个转移衬底 13 Π粘合在一起后的示意图。 移除剩下的减 薄后的生长衬底 1310后的示意图。 至此， 实现了铟镓铝氮薄膜的一次转移。
11-06是去除第一个转移衬底 1308和胶黏剂 1309后的示意图。 至此， 铟镓铝氣薄膜实现了二次转 移。
图 1 1 - 07是将芯片阵列与二次转移衬底邦定压焊前的示意图。 13 Π是第三个转移衬底， 1314是衬底正 面金属层， 1315是衬底背面金属层。
图 11 -08是将芯片阵列与三次转移衬底邦定压焯在一起后的示意图。 1316是压焊熔合后的金属层。 图 11-09是去除笫二个转移衬底 131 1和笫二胶黏剂 1312后的示意图。 至此， 铟镓铝氮薄膜实现了三 次转移。
图〗1 - 10是在芯片阵列表面制备了粗化图形 1317、 去除了阵列边缘 13】8位置的氮化物、 制备了钝化 增透层 1319、 在第一区域 1320无钝化增透层位 S制备了 n型电极及焊盘 1321后的示意图。
图〗1 -11是划片分割芯片阵列获得分立器件后的示意图。
对本实施方式所做的任何显而易见的修改， 关键步骤显而易见的重新罗列组合， 关键要素的重新拼凑 都是受本发明所保护的。 ' - 以上实施方式可以获得的典 ¾器件结构例举如下： '
图 12是运用本发明的方法可以获得的典型器件结构之一。图中 1401为经过表面粗化的铟镓铝氮薄膜， 1402为器件边缘钝化增透层， 1403为器件下表面边缘的钝化增透层， 1404为器件的欧姆接触反射层， 1405 为扩散阻挡层， 1406为压焊金属层， 1407为 p面电极互补钝化增透层， 1408为器件的衬底， 1409为衬底 背面的金属层， 1410为 欧姆接触金屈层及金厲引线焊盘。本器件各关键要素的基本要求和基本特征在 本说明书的相关部分己经说明， 在此不再 ΪΕ复说明。
图 13 是运) ·《本发明的方法可以获得的另一典型器件结构之一， 该器件与前面所述器件不同之处在于 其铟镓铝氮薄膜的表面是可以没冇经过粗化的表面。 图中 1501为铟镓铝氣龍, 1502为器件边缘钝化增 透层， 】503为器件下表面边缘的钝化增透 S, 1504为器件的欧姆接触反射层， 1505为扩散阻挡层， 1506 为压焊金屈层， 1507为 p面屯极 补钝化增透层, 1508为器件的衬底， 1509为衬底背面的金厲层, 1510 为 n型欧姆接触金属层及金属引线焯盘。 本器件各关键耍素的基本耍求和基本特征在本说明书的相关部分 己经说明， 在此不再重复说明。
图 14是运用本发明的方法可以获得的另一典型器件结构之一， 该器件与前面所述器件不同之处在于 它没有与 n电极位 ffi相对应的互补屯极。 图中 1601为经过了粗化处理的铟镓铝氮薄膜， 1602为器件边缘 钝化增透层， 1603为器件下表面边缘的钝化增透层， 1604为器件的欧姆接触反射层， 1605为扩散阻挡层， 1606为压焯金属层， 1607为 ^型欧姆接触金属层及金属引线焊盘， 1608为器件的衬底， 1609为衬底背面 的金属层。本器件各关键耍素的基本耍求和基本特征在本说明书的相关部分己经说明，在此不再重复说明。
图 15是运用本发明的方法可以获得的另一典型器件结构之一， 该器件与前面所述器件不同之处在于 它的欧姆接触反射层及扩散阻挡层可以是在器件加工过程中没有经过光刻的层。 图中 1701 为经过了粗化 处理的铟镓铝氮薄膜， 1702为器件边缘钝化增透层， 1703为器件下表面边缘的钝化增透层， 1704为器件 的欧姆接触反射层， 1705为扩散阻挡层， 1706为压焊金属层， 1707为 n型欧姆接触金属层及金属引线焊 盘， 1708 为器件的衬底， 1709 为衬底背面的金属层。 本器件各关键要素的基本要求和基本特征在本说明 书的相关部分已经说明， 在此不再 i£g说明。
图 16是运川本发明的方法可以获得的另一典型器件结构之一， 该器件与前面所述器件不同之处在于 该器件的衬底可以是屯镀或邦定的多层结构的衬底。 图中 1801 为经过了粗化处理的铟镓铝氮薄膜， 1802 为器件上表面钝化增透层. 1803 为器件下表面边缘的钝化增透层， 1804为器件的欧姆接触反射层， 1805 为扩散阻挡层， 1806 压焊金屈层， 1807为衬底第一层， 180S为衬底第二层， 18(]9为衬底第三层， 1810 为衬底背面金属层， 181 1为 n 欧姆接触金屈层及金属引线焊盘。本器件各关键耍素的基本耍求和基本特 征在本说明书的相关部分已经说明， 在此不再重复说明。
图 17是运用本发明的方法可以获得的另一典型器件结构之一， 该器件与前面所述器件不同之处在于 该器件下表面的钝化是用低功函数的金屈层实现的， 而且欧姆接触反射层的面积比铟镓铝氮薄膜的台面 小。 图中 1901为经过了粗化处理的铟镓铝 ¾簿膜， 1902为器件上表面钝化增透层， 1903为器件下表面边 缘的钝化金属层和压焊的扩散阻挡层， 1904为压焊金厲层， 1905为支撑衬底， 1906为支撑衬底背面金属 层, 1907为 n型欧姆接触金属层及金属引线焊盘。本器件各关键耍素的基本要求和基本特征在本说明书的 相关部分己经说明， 在此不再 ffifi说明。
18 是运 i+j本发明的方法可以获得的另一典型器件结构之一， 该器件与前面所述器件不同之处在于 该器件的欧姆接触反射层没有经过 I形化处理， 其面积比铟镓铝氮薄膜台面面积大， 器件下表面边缘没有 钝化层。 图中 2001为经过了粗化处理的铟镓铝氮薄膜， 2002为器件上表面钝化增透层， 2003为欧姆接触 反射层， 2004为扩散阻挡层， 2005为压焊金屈层， 2006为支撑衬底， 2007为支撑衬底背面金属层， 2008 为 n型欧姆接触金属层及金屈弓 I线烊盘。本器件各关键耍素的基本耍求和基本特征在本说明书的相关部分 已经说明， 在此不再重复说明。
图 19是运用本发明的方法可以获得的另一典型器件结构之一， 该器件与前面所述器件不同之处在于 它与 n电极位置相对应的互补 i¾极不是靠钝化增透层实现的， 而是靠低功函数的金属层实现的。 图中 2101 为经过了粗化处理的铟镓铝氮薄膜 2102 为器件上表面钝化增透层， 2103 为器件下表面及互补电极处钝 化金属层及扩散阻挡层， 2104为压焯金属层， 2105为欧姆接触反射层， 2i 06为支撑衬底， 2107为支撑衬 底背面金属层， 2108为 n ^欧姆接触金厲层及金属引线焊盘。本器件各关键耍素的基本要求和基本特征在 本说明书的相关部分己经说明， 在此不再 复说明。
对上述器件所做的任何显而易见的修改， 关键耍素显而易见的重新罗列组合都是受本发明所保护的。 本发明说明书附图的标识说明：
生长衬底 201、 凹槽 202、 铟镓铝氮薄膜 203、 p型欧姆接触层和反射层 204、 第一腐蚀掩膜层 205、 掩膜互补区域 206、 掩膜边沿 域 207、 欧姆接触互补区域 208、 欧姆接触边沿区域 209、 第一个转移衬底 210、 去边图形化的掩膜层 21 1、 第二掩膜 212、 第三区域 213、 第四区域 214、 第五区域 215、 钝化层 216、 第三光刻胶层 217、 右侧掩膜 218、 中间掩膜 219、 左侧掩膜 220、 间隙 221、 右侧钝化层 222、 中间钝化 层 223、 左侧钝化层 224、 粗化面 225、 n型屯极及焊盘层 226、 第四光刻胶层 227、 第四图形化光刻胶层 228、 电流导通层 229、 保护层 230、 第二转移衬底 231、 铜金属层 232、 第五光刻胶层 233、 第六区域 234、 第七区域 235、 第二光刻胶保护层 236、 笫二转移衬底 237、 第八区域 238、 粘结材料 239、 支撑衬底 240、 经过刻蚀的 n型电极及焊盘层 241、 蓝股成白膜 242、 分选膜 243 ;
铟镓铝氮薄膜 301、 欧姆接触反射层 302、 钝化层 303、 粗化图形 304、 第一个转移衬底 305、 金属导 通层 306、 保护层 307、 第二个转移衬底 308、 扩散阻挡层和压焊金属层 309、 融合在'一起的邦定压焊金属 层 310、 笫三个转移衬底 31 1、 第二个保护层 312、 n型电极和焊盘 313 ;
铟镓铝氮薄膜 401、 欧姆接触反射层 402、 第一个转移衬底 403、 导通层 404、 第二个转移衬底 405、 扩散阻挡层和压焊金厲层 406、 融合在一起的邦定压焊金属层 407、 第三个转移衬底 408、 保护层 409、 粗 化图形 410、 第一区域 41 1、 钝化增透 jg 412、 笫二区域 413、 n电极及引线焊盘 414、 第三区域 415 ; 生长衬底 501、凹槽 502、铟镓 簿膜 503、 P面钝化层 504、欧姆接触反射层 505、压焊金属层 506、 第一个转移衬底 507、 保护层 508、 粘结层 509、 第二个转移衬底 510、 压焊层 511、 第三个转移衬底 512、 第二个保护层 513、 第一区域 514、 粗化图形 515、 第二区域 516、 钝化增透层 517、 第三区域 518、 n电极 及引线焊盘 519、 第四区域 520;
生长衬底 601、 铟镓铝挺外延股 602、 p面钝化层 603、 胶黏层 604、 固化了的胶黏层 605、 第一个转 移衬底 606、 粘结层 607、 第二个转移衬底 608、 压焊层 609、 第三个转移衬底 610、 保护层 61 1、 钝化增 透层 612、 第一区域 613、 n屯极及引线焊盘 614、 第二区域 615 ;
生长衬底 701、 铟镓 氮外延股 702、 凹槽 703、 ρ型欧姆接触牺牲层 704、 填充物 705、 导通层 706、 第一个转移衬底 707、 保护层 708、 粘结层 709、 笫二个转移衬底 710、 ρ面钝化层 711、 复合层 712、 压焊 层 713、 第三个转移衬底 714、 第―个保护层 715、 粗化图形 716、 第一区域 717、 钝化增透层 718、 η型电 极及悍盘 719;
生长衬底 801、 铟镓铝氨外延股 802、 凹槽 803、 ρ型欧姆接触牺牲层 804、 胶黏剂层 805、 第一个转 移衬底 806、 粘结层 807、 第—个转移衬底 808、 ρ面钝化层 809、 欧姆接触反射层 810、 扩散阻挡层 811、 压焊层 812、第三个转移衬底 813、 保护 S 814、粗化图形 815、边缘 816、钝化增透层 817、第一区域 818、 η型电极及焊盘 819、 第二区域 820：
生长衬底 901、 铟镓铝 ¾外延脱 902、 卩 ¾欧姆接触反射层 903、 钝化层 904、 扩散阻挡层 905、 压焊 粘结层 906、 第一层 907、 第二层 908、 第三层 909、 保护层 910、 粗化图形 911、 第一区域 912、 钝化增透 层913、 η屯极及焊盘 914、 缝隙 91 5、 导逝层 916、 第二个转移衬底 917、 第二个保护层 918、 光刻胶图形 919、 图形衬底 920、 衬底保护 ϋ 921、 蓝膜 922:
生长衬底 1001、 铟镓铝氮外延脱 1002、 第一区域 1003、 钝化层 1004、 ρ型欧姆接触反射层 1005、 扩 散阻挡层和压焊层 1006、 光刻胶 1007、 第一个转移衬底画、 胶黏剂 1009、 连体衬底 1010、 第二胶黏剂 101 1、 第二个转移衬底 1012、 压^金属层 1013、 第三个转移衬底 1014、 保护层 1015、 邦定金属层 1016、 粗化图形 1017、 η型屯极及焊盘 1018 ;
生长衬底 1301、 铟镓铝 ¾ 膜 1302、 p面钝化层 1303、 p面互补钝化层 1304、 欧姆接触反射层 1305、 压焊扩散阻挡层 1306、 压焊层 1307、 '第一次转移衬底 1308、 胶黏剂 1309、 减薄后的生长衬底 1310、 第二 个转移衬底 131 1、 第二胶黏剂 13 12、 第二个转移衬底 1313、 正面金属层 1314、 背面金属层 1315、 合后 的金屈层 1316、 粗化图形 13 17、 边缘 1318、 钝化增透层 1319、 第一区域 1320、 n型电极及焊盘 1321 ; 铟镓铝氮薄膜 1401、 边缘钝化增透层 1402、 下表面边缘的钝化增透层 1403、 欧姆接触反射层 1404、 扩散阻挡层 1405、 压焊金属层 1406、 p面 极互补钝化增透层 1407、 衬底 1408、 金属层 1409、 n型欧姆 接触金属层及金属弓 I线焊盘 10 ;
铟镓铝氮薄膜 1501、 边缘钝化增透层 1 502、 下表面边缘的钝化增透层 1503、 欧姆接触反射层 1504、 扩散阻挡层 1505、 压焊金屈 β 1 506、 p面 极互补钝化增透层 1507、 衬底 1508、 金属层 1509、 n型欧姆 接触金屈层及金属引线焊盘 1510 ;
1601为铟镓铝氣薄膜、 1602为边缘钝化增透层、 1603为下表面边缘的钝化增透层、 1604为欧姆接触 反射层、 1605为扩散阻挡层、 1606为压烨金属层、 1607为 n型欧姆接触金属层及金属引线焊盘、 1608为 衬底、 1609为金屈层：
1701为铟镓铝氮薄膜、 1702为边缘钝化增透层、 1703为下表面边缘的钝化增透层、 1704为欧姆接触 反射层、 1705为扩散阻挡层、 Π06为压焊金属层、 1707为 n型欧姆接触金属层及金属引线焊盘、 1708为 衬底、 Π09为金属层；
1801为铟镓铝 ¾薄膜、 1802为上表面钝化增透层、 1803为下表面边缘的钝化增透层、 1804为欧姆接 触反射层、 1805为扩散阻挡层、 1806为压焊金厲层、 1807为衬底第一层、 1808为衬底第二层、 1809为衬 底第三层、 1810为衬底背面金屈层、 181 1为 n型欧姆接触金属层及金属引线焊盘；
1901为铟镓铝氮薄膜、 1902为器件上表面钝化增透层、 1903为钝化金属层和压焊的扩散阻挡层、 1904 为压焊金属层、 1905为支撑衬底、 1906为支撑衬底背面金属层、 1907为 n型欧姆接触金属层及金属引线 焊盘；
2001为铟镓铝氮薄膜、 2002为器件上表面钝化增透层、 2003为欧姆接触反射层、 2004为扩散阻挡层、 2005为压焊金属层、 2006为支撑衬底、 2007为支撑衬底背面金属层、 2008为 n型欧姆接触金属层及金属 引线焊盘；
2101为铟镓铝氮薄膜、 2102为器件上表面钝化增透层、 2103为钝化金属层及扩散阻挡层、 2104为压 焊金属层、 2105为欧姆接触反射展、 2 106为支撑衬底、 2107为支撑衬底背面金属层、 2108为 n型欧姆接 触金属层及金属引线焊盘。

Claims

权 利 要 求 书
1、 一种缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其包括- 在生长衬底上外延铟镓铝氮薄膜；
针对由于生 · ϊ衬底与铟镓铝弒的热膨胀系数的差异而产生的应力， 而进行至少两次将铟镓铝氨 薄膜由当前衬底转移到另一个衬底上的衬底转移， 该次衬底转移释放调节铟镓 ^氮薄膜在生长过程 中积存的应力。
2、 根据权利耍求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 在外 延铟镓铝氮薄膜之前， 先图形化生长衬底。
3、 根据权利要求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 所述 铟镓铝氮薄膜转移到柔性胶黏剂上后处于自由伸展的释放应力状态。
4、 根据权利耍求 3所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 将所述铟镓铝氮薄膜先后进行两次衬底转移， 两次的衬底转移均为以下转移方式- 邦定压焊、 沉积或者它们的混合方式。
5、 根据权利要求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 所述铟镓铝氮薄膜通过粘结材料转移到另一个衬底上， 通过粘结材料固化的热胀冷缩对铟镓铝 氮薄膜的应力进行调节。
6、 根据权利耍求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于- 所述铟镓铝氮薄膜通过粘结材料转移到另一个衬底上， 期间通过粘结材料固化的温度来实现对 铟镓铝氮薄膜的应力调节。
7、 根据权利耍求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 所述铟镓铝氮薄膜通过邦定压焊方式转移到另一个衬底上， 期间通过邦定压焊金属的融合温度 控制来实现对铟镓铝氮薄膜的应力调节。
8、 根据权利要求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 所述铟镓铝氮薄膜通过邦定压焊方式转移到另一个衬底上， 期间通过控制压焊金属层的弹性模 量来实现对铟镓铝氮薄膜的应力调节。
9、 根据权利要求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 所述铟镓铝氮薄膜通过沉积方式转移到另一个衬底上， 通过另一个衬底在沉积过程中沉积层自 身形成的应力来实现对铟镓铝氮薄膜的应力调节。
10、 根据权利耍求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 所述铟镓铝氮薄膜转移到另一个衬底上， 期间通过沉积的制备条件来实现对铟镓铝氮薄膜的应 力调节， 其中制备条件包括： 温度、 厚度、 致密度分布、 组分或结构中的任一项或多项的组合。
11、 根据权利要求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 包括在铟镓铝氮薄膜上制造构成器件的耍素， 构成器件的耍素包括： 电极及焊盘和欧姆接触层。
12、 根据权利耍求 11所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于所述 构成器件的耍素还包括： ' .
钝化层、 增加出光的图形组构层、 反光层、 光增透层或与电极的互补结构中的一种或多种。
13、 根据权利耍求 11或 12所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在 于： 在外延铟镓铝氮薄膜之前， 先图形化生长衬底；
进行最后一次衬底转移之前， 在铟镓铝氮薄膜上制造构成器件的要素中的一种或者全部耍素。
14、 根据权利要求 1 所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 所 述生长衬底为蓝宝石衬底、碳化硅衬底、硅衬底、 MgAl204、 MgO、 LiGa02、 y -LiAlO2、NdGa03、 ScAlMgO Ga8La2(P04)602、 MoS2、 LaAI03、 （Mn，Zn)Fe204、 Hf、 Zr、 ZrN、 Sc、 ScN、 NbN、 TiN或立体材料的 GaN 或 A1N衬底中的任一种衬底。
15、 根据权利要求 14所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 在所述生长衬底上沉积有： Si、 GaAs、 Ge、 A1P, AIAs, AlSb, GaP、 GaAs、 GaSb、 InP、 InAs、 InSb、
ZnO、 ZnS、 ZnSe、 ZnTe、 CdS、 CdSe、 CdTe、 HgSe、 HgTePbS> PbSe、 PbTe、 GaPxAs,.x, GaxAl,.xAs, ■MgAl204、 MgO、 LiGa02、 Y -LiA102、 NdGa。3、 ScAlMg04、 GasLa2(P04)602、 MoS2、 LaA103、（Mn，Zn)Fe204、 Hf、 Zr、 ZrN、 Sc、， ScN、 NbN或 TiN中的一种或几种薄层， 它们构成复合衬底。
16、 根据权利要求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于包括以下步 骤： 在外延铟镓铝氮薄膜之前， 图形化生长衬底， 形成铟镓铝氮薄膜的生长平台和平台之间的槽结构； 制作钝化层， 并图形化钝化层， 在铟镓铝氮薄膜的边缘以及铟镓铝氮薄膜单元之间的槽内均分 布有用于阻断电镀电流的图形化钝化层， 在铟镓铝氮薄膜边缘的钝化层与槽内的图形化钝化层之间 存在间隙；
在钝化层的上面制作转移衬底， 并去除钝化层下面的衬底；
在上述被去除掉的钝化层下面的衬底位置上沉积导热金属层， 并图形化导热金属层， 使所述槽内的 钝化层露出；
在导热金厲层上电镀另一个位于钝化层下面的转移衬底， 形成与导热金屑层一致的图形构造； 在上述位于钝化层下面的转移衬底上通过导电的粘结材料粘接一个与其连体的金属连体衬底，并去 除钝化层上面的转移衬底；
将制成的外延片进行贴膜， 并去除连体衬底， 完成分片。
17、 根据权利耍求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 将铟镓铝 氮薄膜至少进行两次转移， 第二个转移衬底的热膨胀系数与第一个转移衬底的热膨胀系数相匹配。
1 8、 根据权利耍求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于. · 转移衬底 通过镂空结构实现其热膨胀系数与铟镓铝氮薄膜相匹配。
19、 根据权利耍求 5所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 所述粘结 材料为有机物、 无机非金属材料。
20、 根据权利耍求 19所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 所述有 机物为热固型胶黏剂、 热熔型胶黏剂、 室温固化型胶黏剂、 压敏型胶黏剂、 光固化有机胶。
21、 根据权利耍求 5所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 所述粘接 材料为两层以及以上的叠层结构， 该叠层结构包括至少两种材料。
22、 根据权利要求 5所述的缓解铟镓铝氣薄膜应力的半导体器件的制造方法， 其特征在于： 所述粘结 材料为纤维素酯、 烯类聚合物、 聚酯、 聚醚、 聚酷胺、 聚丙烯酸酯、 a-氰基丙烯酸酯、 聚乙烯醇缩醛、 乙 烯 -乙酸乙烯酯共聚、 环氧树脂、 酚醛树脂、 脲醛树脂、 三聚氰 -甲醛树脂、 有机硅树脂、 呋喃树脂、 不饱 和聚酯、 丙烯酸树脂、 聚酰亚胺、 聚苯并咪唑、 酚醛-聚乙烯醇缩醛、 酚醛-聚酰胺、 酚醛 -环氧树脂、 环氧 -聚酰胺、 合成橡胶、 氯丁橡胶、 丁苯橡胶、 丁基橡胶、 丁钠橡胶、 异戊橡胶、 聚硫橡胶、 聚氨酯橡胶、 氯 磺化聚乙烯弹性体、 硅橡胶、 酚醛-丁腈胶、 酚醛-氯丁胶、 酚醛 -聚氨酯胶、 环氧-丁腈胶、 环氧-聚硫胶等 中的一种或几种的组合。
23、 根据权利耍求 19所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于所述无机 非金属材料为空气干燥型无机胶黏剂、'水固化型无机胶黏剂、热熔型无机胶黏剂或化学反应型无机胶黏剂。
24、 根据权利要求 19所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 所述无 机非金属材料为石脅、 水泥、 水玻璃、 粘土、低熔点玻璃、低熔点玻璃陶瓷或硫磺， 或者硅酸盐类胶黏剂、 磷酸盐类胶黏剂、 胶体氧化铝胶黏剂、 牙科胶泥胶黏剂： 所述粘结材料为上述无机非金属材料中的一种或 多种的组合。
25、 根据权利要求 1所述的缓解铟镓铝氣薄膜应力的半导体器件的制造方法， 其特征在于包括： 在铟镓铝氮薄膜 P面上沉积 P面钝化层， 并图形化 P面钝化层， 使每个最终的分立器件的边缘存在图 形化的 P面钝化层。
26、 根据权利耍求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于： 转移衬底 为复合衬底， 其分为三层， 与铟镓铝氮薄膜接触的为第一层， 其它依次为第二层和第三层； 所述第一层的 热膨胀系数与铟镓铝氮薄膜的相匹配， 所述第三层的热膨胀系数与生长衬底的相匹配， 第二层为将第一层 和第三层连接在一起的压焊层。
27、 根据权利耍求 1所述的缓解铟镓铝氮薄膜应力的半导体器件的制造方法， 其特征在于包括： 在包括生长衬底的外延片上制作图形化电镀层， 电镀层的图形化与生长衬底的图形化一致， 电镀层中 有沿图形化生长衬底的凹槽延伸出来的缝隙， 其中生长衬底为蓝宝石衬底；
在电镀层上制作第一个转移衬底；
激光剥离生长衬底。
PCT/CN2012/000062 2011-01-24 2012-01-13 缓解铟镓铝氮薄膜应力的半导体器件的制造方法 WO2012100647A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110026143.6A CN102610707B (zh) 2011-01-24 缓解铟镓铝氮薄膜应力的半导体器件的制造方法
CN201110026143.6 2011-01-24

Publications (1)

Publication Number Publication Date
WO2012100647A1 true WO2012100647A1 (zh) 2012-08-02

Family

ID=46527960

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/000062 WO2012100647A1 (zh) 2011-01-24 2012-01-13 缓解铟镓铝氮薄膜应力的半导体器件的制造方法

Country Status (1)

Country Link
WO (1) WO2012100647A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538304A (zh) * 2014-12-24 2015-04-22 中国科学院半导体研究所 倒装结构的氮化镓基高电子迁移率晶体管的制作方法
CN104538303A (zh) * 2014-12-24 2015-04-22 中国科学院半导体研究所 转移衬底的氮化镓基高电子迁移率晶体管制作的方法
TWI790155B (zh) * 2021-04-07 2023-01-11 全新光電科技股份有限公司 半導體磊晶晶圓

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101449400A (zh) * 2006-05-23 2009-06-03 阿尔卑斯电气株式会社 半导体发光元件的制造方法
CN101840967A (zh) * 2009-05-08 2010-09-22 晶能光电（江西）有限公司 铟镓铝氮半导体发光器件及其制备方法
CN101919075A (zh) * 2008-03-25 2010-12-15 晶能光电（江西）有限公司 制备大功率led阵列的方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101449400A (zh) * 2006-05-23 2009-06-03 阿尔卑斯电气株式会社 半导体发光元件的制造方法
CN101919075A (zh) * 2008-03-25 2010-12-15 晶能光电（江西）有限公司 制备大功率led阵列的方法
CN101840967A (zh) * 2009-05-08 2010-09-22 晶能光电（江西）有限公司 铟镓铝氮半导体发光器件及其制备方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538304A (zh) * 2014-12-24 2015-04-22 中国科学院半导体研究所 倒装结构的氮化镓基高电子迁移率晶体管的制作方法
CN104538303A (zh) * 2014-12-24 2015-04-22 中国科学院半导体研究所 转移衬底的氮化镓基高电子迁移率晶体管制作的方法
TWI790155B (zh) * 2021-04-07 2023-01-11 全新光電科技股份有限公司 半導體磊晶晶圓

Also Published As

Publication number Publication date
CN102610707A (zh) 2012-07-25

Similar Documents

Publication Publication Date Title
TWI344706B (en) Method of fabricating vertical structure compound semiconductor devices
TW513818B (en) Method to produce GaN-based semiconductor elements and thin layer semiconductor elements
TWI559572B (zh) 使用中間電傳導性接合層來製造及傳遞微裝置及微裝置陣列的方法
TWI300277B (en) Method for manufacturing gallium nitride light emitting diode devices
CN102637784B (zh) 发光二极管封装基板及其制作方法
TW201349556A (zh) 形成具有自對準金屬化堆疊之微發光二極體裝置的方法
TW200924249A (en) Light emitting diode with bonded semiconductor wavelength converter
CN101465402B (zh) 一种基于无缝隙平面键合的薄膜led芯片器件制造方法
US20140147987A1 (en) Method for manufacturing gallium nitride-based film chip
TW201044641A (en) Controlling edge emission in package-free LED die
TW201121110A (en) Method of forming vertical structure light emitting diode with heat exhaustion structure
JP5232975B2 (ja) 発光ダイオードの製造方法及び発光ダイオード、並びにランプ
JPWO2007136064A1 (ja) 半導体発光素子及びその製造方法
JP2007134388A (ja) 窒化物系半導体素子とその製造方法
JP2009099675A (ja) 発光ダイオードの製造方法及び発光ダイオード、並びにランプ
JP2005026291A (ja) 窒化物系半導体発光装置およびその製造方法
WO2012100647A1 (zh) 缓解铟镓铝氮薄膜应力的半导体器件的制造方法
JP6462029B2 (ja) 基板を半導体発光素子に接合する方法
WO2013038964A1 (ja) Ｌｅｄ発光素子保持基板用クラッド材及びその製造方法
CN104953006A (zh) 半导体发光装置
CN102683517A (zh) 薄膜led芯片器件及其制造方法及应用
CN106463596B (zh) 发光器件的成形方法
CN103443940B (zh) 发射光的半导体器件
TW201318236A (zh) 具增大面積之氮化鎵發光二極體及其製造方法
CN108365058A (zh) 一种led衬底转移方法及其应用

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12739692

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12739692

Country of ref document: EP

Kind code of ref document: A1