WO2012098182A1 - Cellule de mémoire volatile et non volatile combinée - Google Patents

Cellule de mémoire volatile et non volatile combinée Download PDF

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Publication number
WO2012098182A1
WO2012098182A1 PCT/EP2012/050768 EP2012050768W WO2012098182A1 WO 2012098182 A1 WO2012098182 A1 WO 2012098182A1 EP 2012050768 W EP2012050768 W EP 2012050768W WO 2012098182 A1 WO2012098182 A1 WO 2012098182A1
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Prior art keywords
transistor
coupled
storage node
resistance switching
supply voltage
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PCT/EP2012/050768
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English (en)
Inventor
Yoann GUILLEMENET
Lionel Torres
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Centre National De La Recherche Scientifique
Universite Montpellier 2
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Publication of WO2012098182A1 publication Critical patent/WO2012098182A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material

Definitions

  • the present invention relates to a programmable volatile/non-volatile memory cell, and to a method of reading a programmable non-volatile memory cell .
  • FIG. 1 illustrates a typical static random access memory (SRAM) cell 100.
  • a first inverter is formed of an N- channel MOS (NMOS) transistor 102 and P-channel MOS (PMOS) transistor 103 coupled in series between a supply voltage Vpp and a ground voltage.
  • a second inverter is formed of an NMOS transistor 104 and a PMOS transistor 105 also coupled in series between the supply voltage Vpp and the ground voltage.
  • the gates of transistors 104 and 105 are coupled to a node 106 coupled to the drains of transistors 102 and 103, while the gates of transistors 102 and 103 are coupled to a node 108 coupled to the drains of transistors 104 and 105, such that the inverters form a latch.
  • the nodes 106 and 108 store complementary voltage states Q and Q , permitting one bit of data to be memorized by the cell.
  • Node 106 is coupled to a bit line BL via a P-channel MOS (PMOS) transistor 110, while node 108 is coupled to a complementary bit line BLB via a PMOS transistor 112.
  • the gates of transistors 110 and 112 are coupled to a word line WL, and are activated by a low signal allowing data to be written to or read from the cell 100.
  • the circuit 100 has advantage of being relatively quick to access during read and write operations.
  • a disadvantage is that, as with all volatile memory cells, the stored data is lost if the supply voltage Vpp is removed.
  • Flash memory is an example of a programmable non ⁇ volatile memory.
  • a disadvantage with flash memory is that it is relatively slow to access when compared to the SRAM cell of Figure 1, and requires a relatively high supply voltage. Furthermore, the Flash technology is difficult to integrate with CMOS, and has relatively low endurance.
  • a memory device comprising at least one memory cell comprising: a first inverter comprising a first transistor coupled between a first storage node and a first supply voltage; a second inverter comprising a second transistor coupled between a second storage node and said first supply voltage, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; a first resistance switching element coupled between said first storage node and a first access line; and a second resistance switching element coupled between said second storage node and a second access line, wherein said first transistor is the only transistor of said first inverter, and said second transistor is the only transistor of said second inverter.
  • the first resistance switching element is programmed to have a first resistance and said second resistance switching element is programmed to have a second resistance, and further comprising: control circuitry adapted to store a data value at said first and second storage nodes by coupling said first and second access lines to a second supply voltage while said access lines are coupled to said first and second storage nodes respectively, the data value being determined by the relative resistances of the first and second resistance switching elements.
  • the memory device further comprises a third transistor coupled between said first storage node and said first resistance switching element; and a fourth transistor coupled between said second storage node and said second resistance switching element, wherein said control circuitry is adapted to control said third and fourth transistors to connect said first and second storage nodes to said first and second access lines respectively.
  • control circuitry is further adapted to isolate said first and second storage nodes from said second supply voltage after a time delay.
  • the third and fourth transistors are adapted to have a lower threshold voltage than said first and second transistors.
  • the memory device further comprises programming circuitry adapted to program the resistances of said first and second resistance switching elements based on input data.
  • the first and second resistance switching elements are one of: oxide resistive elements; conductive bridging elements; phase change elements; programmable metallization elements; spin-torque-transfer elements; and field-induced magnetic switching elements.
  • the first and second resistance switching elements are thermally assisted switching elements
  • the memory device further comprising heating circuitry arranged to heat said first and second resistance switching elements by passing a current through them.
  • the heating circuitry is adapted to couple a third supply voltage to said first and second bit lines.
  • a random access memory comprising an array of the above memory devices .
  • a field programmable gate array comprising at least one multiplexer comprising an input coupled to at least one of the above memory devices.
  • a field programmable gate array comprising: a plurality of configurable logic blocks; and at least one switching block adapted to interconnect said plurality of configurable logic blocks, wherein said at least one switching block comprises the above memory device.
  • a method of transferring a data value from non-volatile storage of a memory cell to first and second volatile storage nodes of said memory cell wherein the memory cell comprises a first inverter comprising a first transistor coupled between said first storage node and a first supply voltage; a second inverter comprising a second transistor coupled between said second storage node and said first supply voltage, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; a first resistance switching element coupled between said first storage node and a first access line; and a second resistance switching element coupled between said second storage node and a second access line, wherein said first transistor is the only transistor of said first inverter, and said second transistor is the only transistor of said second inverter, the method comprising: coupling said first and second access lines to a second supply voltage while said access lines are coupled to said first and second storage nodes respectively, the data value being determined by the relative resistance
  • the method further comprises, a first time period after coupling said first and second storage nodes to said first supply voltage, the step of isolating said first and second storage nodes from said first supply voltage.
  • coupling said first and second storage nodes to said second supply voltage comprises activating a third transistor coupled between said first storage node and said first access line, and activating a fourth transistor coupled between said second storage node and said second access line.
  • Figure 1 illustrates a volatile SRAM cell
  • Figure 2 illustrates a memory cell with volatile and non-volatile data storage according to an embodiment of the present invention
  • Figure 3 illustrates programming circuitry for programming the non-volatile portion of the memory cell of Figure 2;
  • Figures 4A and 4B schematically represent examples of the programming of a specific resistance switching memory device
  • Figure 5 is a timing diagram illustrating an example of the signals used for programming the non-volatile portion of the memory cell of Figure 3;
  • Figure 6 illustrates an example of control circuitry for copying data stored by non-volatile data storage elements to volatile data storage elements of the memory cell;
  • FIGS 7A and 7B are timing diagrams showing examples of signals in the circuitry of Figure 6;
  • Figures 7C and 7D are graphs illustrating the transition between stable states of the cell of Figure 6 according to one example
  • Figure 8 illustrates a memory cell with volatile and non-volatile data storage according to a further embodiment of the present invention
  • Figure 9 illustrates a memory array according to an embodiment of the present invention.
  • FIG. 10A illustrates a field programmable gate array (FPGA) according to an embodiment of the present invention.
  • Figure 10B illustrates a configurable logic block of the FPGA of Figure 10A in more detail according to an embodiment of the present invention.
  • Figure 2 illustrates a memory cell 200 that stores, in addition to one bit of volatile data, one bit of non-volatile data.
  • the volatile data is stored in electronic form by a latch.
  • the non-volatile data however is stored by the physical state of a pair of resistance switching elements, as will now be described.
  • the memory cell 200 is similar to the SRAM cell 100 of Figure 1 described above, and the common portions will not be described again in detail. However, rather than comprising six transistors, the memory cell 200 comprises just four transistors. Indeed, the PMOS transistors 103 and 105 forming half of each inverter are removed, and thus there is no connection to the supply voltage Vpp in memory cell 200. Furthermore, the memory cell 200 additionally comprises resistance switching elements 202 and 204, of which element 202 is coupled between the drain of transistor 110 and bit line BL, and element 204 is coupled between the drain of transistor 112 and the bit line BLB.
  • the resistance switching elements 202 and 204 are any resistive elements switchable between two resistance values. Such elements maintain the programmed resistive state even after a supply voltage is removed.
  • the resistance switching elements 202, 204 are programmed to have opposite values, and the relative values of the elements indicate one binary data value.
  • the resistance switching elements 202, 204 are based on magnetic tunnelling junctions (MTJs) , such as field-induced magnetic switching (FIMS) elements or thermally assisted switching (TAS) elements, STT (spin-torque-transfer) elements, or those of Toggle MRAM.
  • FIMS-MRAM magnetic random access memory
  • FIMS-MRAM magnetic random access memory
  • S.Tehrani Proceedings of IEEE, 91 (5) : 3707-714, May 2003.
  • TAS-MRAM are for example discussed in more detail in the publication titled "Thermally
  • the resistance switching elements 202, 204 could be other types of resistance switching memory devices, including those used in programmable metallization cells (PCM) , such as oxide resistive RAM (OxRRAM) , conductive bridging RAM
  • PCM programmable metallization cells
  • OxRRAM oxide resistive RAM
  • CBRAM phase change RAM
  • PCRAM phase change RAM
  • each of the resistance switching elements 202, 204 for example has just two resistive states corresponding to the high and low resistances R max and R m i n ' although the exact values of R m j_ n and R max may vary depending on conditions such as temperature, process variations etc.
  • the non-volatile data value represented by the resistive elements 202, 204 depends on which of the resistive elements is at the resistance R max an d R min' i- n other words on the relative resistances .
  • the resistance elements 202, 204 are for example selected such that R max is always significantly greater than R m j_ n , for example at least 20 percent greater.
  • the ratio between the resistance R max and the resistance R m j_ n is for example between 1.7 and 5 for an MRAM, or more generally between 1.2 and 10000.
  • R m j_ n is in the region of 2.5 k ohms
  • R max is in the region of 5 k ohms, although many other values are possible .
  • transistors 103 and 103 are connected in the SRAM cell 100 of Figure 1, transistors 103 and 102.
  • the 105 are coupled to the supply rail Vpp and perform the role of maintaining the high state of Q or Q at node 106 or 108 when the cell is in standby between write and read operations .
  • the high state of Q or Q is maintained by leakage current passing through the PMOS transistor 110 or 112, from the corresponding bit line BL or BLB.
  • the bit lines BL and BLB are charged to the supply voltage Vpp at least periodically during the standby state, to generate the leakage current .
  • the threshold voltages of the PMOS transistors 110, 112 are lower than those of MOS transistors 102, 104, such that when in the non-conducting state, the current leakage through transistors 110 and 112 is greater than through transistor 102 or 104, thereby keeping the corresponding node 106 or 108 at a voltage high enough to be seen as a high logic level .
  • the leakage current I Q ffp flowing through PMOS transistor 110 or 112 when a high voltage is applied to its gate node is greater that the leakage current loffN flowing through the corresponding NMOS transistor 102 or 104 when a low voltage is applied to its gate node.
  • the particular threshold voltages will depend on the technology used.
  • the threshold voltages of PMOS transistors 110, 112 are chosen to be in the range 0.3 to 0.5 V, while the threshold voltages of NMOS transistors 102, 104 are in the range 0.4 to 0.6 V.
  • the ratio loffp/ ⁇ Offn i- s selected for example to be greater than 25, and preferably greater than 100.
  • writing a bit of data to nodes 106, 108 involves applying, while transistors 110 and 112 are turned on, a high or low voltage to bit line BL depending on the data to be stored, and the opposite voltage to bit line BLB.
  • Reading the data from nodes 106 and 108 involves pre-charging the bit lines BL and BLB, for example to the supply voltage pp.
  • transistors 110 and 112 are turned on and it is determined which bit line voltage drops first, with the aid of a sense amplifier (not illustrated) , which amplifies the voltage difference between the bit lines.
  • a sense amplifier not illustrated
  • the value of R max is chosen not to be greater than around 5 k ohms, although this value will depend on the particular technology used, and in particular the on resistance of the transistors.
  • the resistance switching elements 202, 204 may be programmed to store non-volatile data, and the memory cell may be controlled to transfer this data, from physical storage determined by the resistive states of elements 202, 204, to electronic storage determined by the voltage states of the storage nodes 106, 108. Once transferred, this data may be read from the SRAM cell in a standard fashion. Programming of the resistance switching elements 202 and 204 according to one example will now be described with reference to Figures 3, 4A, 4B and 5.
  • Figure 3 illustrates the memory cell 200 along with write control circuitry 302 arranged to program the resistance switching elements 202 and 204 based on one bit of non-volatile data % j y received on an input line 304.
  • the circuitry 302 based on the non-volatile data % j y the circuitry 302 generates a write current IwRITE' which is provided on a conductive track 306 that passes by the resistance switching elements 202 and 204.
  • the current IwRITE flowing through the conductive track 306 generates a magnetic field, which passes through the resistance switching elements 202, 204, and programs their resistive states .
  • the resistance switching elements 202, 204 Prior to supplying the write current to program each of the resistance switching elements 202, 204, the resistance switching elements are heated by passing a current through them, which aids the transition from one resistive state to another.
  • heat control circuitry 312 is for example provided, which applies a voltage to each of the bit lines BL and BLB, this voltage for example being equal to or greater than the supply voltage pp.
  • NMOS transistors 308 and 310 are coupled between the drains of transistors 110 and 112 respectively and the ground voltage, transistors 308, 310 being activated by a control signal "HEAT" at their gate terminals. Then, by activating the transistors 308, 310 and/or transistors 110, 112, a current will flow from the bit lines BL and BLB through the corresponding resistance switching elements 202, 204 to the ground voltage, which will heat these elements.
  • An advantage of providing the NMOS transistors 308, 310 is that a relatively high heat current can be generated more easily, and/or the dimensions of transistors 102, 104, 110 and 112 may be reduced. Furthermore, when only these transistors are used to heat the elements 202, 204, the state stored by the volatile storage nodes 106, 108 will not be lost during this heating process.
  • FIGS 4A and 4B show the resistance switching elements 202, 204 in more detail in the example that they are TAS elements.
  • Each of the resistance switching elements 202, 204 comprises a pinned ferromagnetic plate 402 and a free ferromagnetic plate 404, plates 402 and 404 sandwiching a tunnel oxide layer 406.
  • the conductive track 306 passes close to the free plate 404 of ferromagnetic material, such that it is affected by the magnetic field generated by the current 1 ⁇ 2RITE flowing through track 306.
  • the pinned plate 402 for example has a magnetic orientation in a first direction, while the magnetic orientation of plate 404 may be programmed, by the polarity of the current 1 ⁇ 2RITE' to be in the same or opposite direction to that of plate 402. However, programming only occurs in elements that have already been heated, as described in more detail below.
  • Figure 4A illustrates the case in which the magnetic orientations are in opposite directions in the plates 402, 404, resulting in a maximum resistance %iax °f the resistance switching element 202, for example in the range 2 k to 5 k Ohms.
  • Figure 4B illustrates the case in which the magnetic orientations are in a same direction in the plates 402 and 404, resulting in a minimum resistance %iin °f the resistance switching element 204, for example in the range of 100 to 3k Ohms .
  • the conductive track 306 is arranged such that the current 1 ⁇ 2RITE passes by each resistance switching element 202, 204 in opposite directions, one of which corresponds to the magnetic orientation of the pinned plate 402, and the other being the opposite orientation.
  • a same current 1 ⁇ 2RITE can be used to program both the resistive states of the resistance switching element 202 and 204 at the same time, one of which is equal to R ma x' an d the other to R m j_ n -
  • Figure 5 is a timing diagram illustrating an example of the signal HEAT that controls transistors 308, 310, and the signal IWRI TE during the programming of the resistance switching elements 202, 204.
  • the signal HEAT goes high at a rising edge 502, thereby activating the transistors 308 and 310 to conduct a current IHEAT through the resistance switching elements 202 and 204.
  • the signal WL may alternatively or additionally be brought low at this time, to activate transistors 110, 112 and thus generate a heat current via transistors 102, 104.
  • the signal 1 ⁇ 2RITE i- s asserted, as shown by the rising edge 504 of this signal.
  • the current becomes positive, which for example programs resistor 202 to be at a high resistance value R ma x' an d resistor 204 to be at low resistance R m j_ n -
  • the signal HEAT is brought low again by falling edge 506, (and/or the signal WL is brought high) such that the heating current 3 ⁇ 4EAT i- s stopped, and the resistance switching elements 202, 204 cool in their current resistive state. Then the signal 1 ⁇ 2RITE i- s brought low by a falling edge 508, to end the programming process.
  • the time during which the signals HEAT and/or WL are active between edges 502 and 506 is around 20 ns .
  • a write operation can be achieved in little more than 35 ns .
  • the heating and cooling-off times will vary based on factors such as the materials used, their volumes, etc., and also the heat currents that are applied, and thus the above values are given only as approximate examples .
  • FIG. 6 illustrates the memory cell 200 along with transfer control circuitry 602, for controlling the transfer of data stored in the non-volatile portion of the memory cell to the volatile data storage portion.
  • the circuitry 602 comprises output lines 604 and 606 coupled to bit lines BL and BLB respectively, and an output line 608 coupled to the word line WL.
  • the transfer phase comprises applying by the control circuitry 602 a supply voltage to each of the bit lines BL and BLB while transistors 110 and 112 are conducting. This generates a current through each of the resistance switching elements 202, 204, such that the voltages at nodes 106, 108 will depend on the relative resistances of the elements 202, 204.
  • Figure 7A shows timing diagrams illustrating the voltages on the bit lines BL and BLB, as well as on the word line WL, and the corresponding voltages Q and Q at the storage nodes 106 and 108.
  • the circuitry 602 applies a high voltage to each of the bit lines BL, BLB, for example at the supply voltage Vpp.
  • the bit lines BL and BLB are likely to be close to or at the supply voltage Vpp during a standby or read phase prior to the transfer phase, but during such phases they are generally only periodically charged to the supply voltage, and for this reason the voltages of BL and BLB prior to and after the transfer phase have been indicated by dashed lines in Figure 7A.
  • the supply voltage is constantly applied to the bit lines BL, BLB, as indicated by solid lines in Figure 7A, such that currents may be drawn from the bit lines.
  • FIG. 7A assumes that the SRAM cell is initially in a state in which Q is low and Q is high. Thus initially, transistor 104 will be non-conducting, and transistor 102 conducting. However, it is also assumed that resistance switching element 202 has a resistance %iax' anc ⁇ thus the current flowing through it will be limited. This current causes the voltage Q to rise slightly when WL is brought low, which in turn causes a partial activation of transistor 104, causing a current to flow through element 204, which has a low resistance R-min- This will also reduce the voltage Q slightly, but the higher current through transistor 104 will cause the voltage Q to be higher than the voltage Q.
  • the PMOS transistors 102, 104 are chosen to have equal dimensions and thus very similar off resistances, such that the voltage drop across each transistor 102, 104 will be proportional to the current level flowing through it.
  • the equilibrium position will be that the voltage Q at node 106 is closer to ground, and the voltage Q at node 108 will be closer to pp.
  • the word line voltage WL goes high, isolating the storage nodes 106, 108 from bit lines BL and BLB, the states of Q and Q will settle to the closest stable state.
  • the storage nodes 106, 108 will settle to a state in which Q is low and Q is high, which corresponds to the state stored by the elements 202 and 204.
  • Figure 7B illustrates the case in which Q and Q are again initially equal to 0 V and Vpp respectively, but in which element 202 is at R m j_ n , anc ⁇ element 204 at R ma x- ⁇ ⁇ this case, transistor 102 will initially be conducting, and transistor 104 non-conducting, and the voltage Q at node 106 will rise due to the current flowing through the resistance switching element 202. However, when the current through transistor 104 starts to rise, it will be a low current due to the high resistance of element 204, and thus the voltage Q falls to a relatively low value, while the voltage Q will rise to a relatively high value. Then, when the word line voltage WL is brought high again, isolating the storage nodes 106, 108 from the respective bit lines, the states of storage nodes 106, 108 will be such that voltage Q is high and voltage Q is low.
  • the duration that the supply voltage is applied to the bit lines BL and BLB is for example in the region of 1 ns, and thus the data transfer from the non-volatile storage to the volatile storage can be performed in approximately only 1 ns, a time comparable to the read and write times of the SRAM portion of the memory cell 200.
  • Figures 7C and 7D are graphs illustrating the transitions between different states of Q and Q .
  • Figure 7C illustrates the case of a transition to a low Q, high Q state, labelled 702 in Figure 7C. If starting from this state, as Q starts to rise, the curve 704 will be followed, in which initially Q falls slowly until an elbow 706 is reached and transistor 104 starts to turn on. Then Q falls more quickly as Q rises, until a point 708 is reached at which the voltage Q is at a value Vmin, resulting from the relatively large voltage drop across the resistance value R max of element 202 and the on resistance of transistor 110. From this point, the closest stable point is back to the low Q, high Q state 702, and thus when the word line signal WL goes high, the voltages Q and Q return to this state.
  • a curve 712 will be followed, in which Q will initially fall very slowly as Q rises, until an elbow 714 is reached when transistor 102 starts to turn on. Q then falls more quickly, and passes a point of metastability 716, at which point voltages Q and Q are equal. A point 718 is then reached, when voltage Q is at Vmax, resulting from the relatively small voltage drop across the resistance R m j_ n °f element 204 and the on resistance of transistor 112. In this example, the metastability point 716 has been crossed, and thus the closest stable state is the low Q, high Q state 702. Thus, when the signal WL is brought high, Q will quickly go to the logic 0 state, before Q rises to the logic 1 state.
  • the new states of these voltage will be determined by the programmed resistance values of the elements 202 and 204.
  • the elements 202 and 204 result in an intermediate state 708, 718, 720 or 722, in which the values of Q and Q are closest to the stable state corresponding to the programmed states of elements 202, 204.
  • Figure 8 illustrates a memory cell 800, which is similar to cell 200 of Figure 2, but in which the NMOS transistors 102, 104 are replaced by PMOS transistors 802 and 804 coupled between respective nodes 806, 808 and a supply voltage pp, and the PMOS transistors 110, 112 are replaced by NMOS transistors 810, 812 coupled between the respective bit lines BL and BLB and the respective nodes 806, 808.
  • the resistance switching elements 202, 204 are coupled between the drains of transistors 810 and 812 respectively, and the bit lines BL and BLB respectively.
  • the threshold voltages of transistors 810 and 812 are lower than those of transistors 802 and 804, such that a leakage current will keep the state of the corresponding node 806 or 808 at a voltage value low enough to be seen as a logic low state during the standby phase between write operations.
  • the resistance switching elements 202, 204 are coupled respectively between the transistors 802, 804 and the supply voltage pp.
  • the bit lines BL and BLB are for example at least periodically brought to a low voltage during the standby phase to ensure such a leakage current.
  • the circuit 800 operates in a similar fashion to the circuit 200, except that transistors 810, 812 are activated by a high voltage level on the word line WL, and a low supply voltage, for example at 0 V, will be applied by circuitry 602 of Figure 6 to the bit lines BL, BLB during the transfer phase from the non-volatile storage elements 202, 204 to the volatile storage nodes 806, 808, and by circuitry 312 of Figure 3 to heat the resistance switching elements 202, 204.
  • Figure 9 illustrates a memory array 900 of the memory cells 200 and/or 800.
  • the memory cells 200, 800 are arranged in columns and rows, each being coupled to bit lines BL and BLB common to each of the columns.
  • the bit lines are coupled to control circuitry 902, which for example receives volatile input data DyiN' anc ⁇ volatile output data DvoUT' which could be the externally inputted volatile data, or volatile data that is generated from a transfer of the non-volatile data stored by the resistance switching elements.
  • the circuitry 902 for example also controls the voltages on the bit lines BL and BLB during the transfer phase, and if appropriate during the writing of non-volatile data.
  • Each of the cells 200, 800 is also coupled to a corresponding word line WL common to each row of cells, and a conductive track 306 forms a loop passing by each cell and conducting the current 1 ⁇ 2RITE f° r writing to the resistance switching elements of each of the memory cells.
  • Each of the lines WL and 306 is controlled by control circuitry 904, which receives input non-volatile data 3 ⁇ 4vin' anc ⁇ provides the current 1 ⁇ 2RITE °f the corresponding polarity.
  • the writing of the non-volatile data is for example performed row by row, in two phases.
  • a first phase only the resistance switching elements of cells for which a first logic value, such as logic "0", is to be programmed are heated.
  • the corresponding write current is applied to the conductive track 306
  • the resistive states of only the elements that have been heated will be programmed.
  • the resistance switching elements of the other cells, for which the second logic value, for example a logic "1" is to be programmed are heated.
  • the corresponding write current is applied to the conductive track 306, again only the resistive states of the elements that have been heated will be programmed.
  • the memory array 900 may comprise any number of rows of cells and any number of columns of cells, depending on the desired storage capacity.
  • a common track 306 could be used for each column, which has the advantage that a row of memory cells can all be programmed in a single programming cycle. Furthermore, given that a current generator provides the current on each track 306, the number current generators would then be reduced to the number of columns rather than the number of rows of the memory.
  • FIG. 10A illustrates an FPGA (field programmable gate array) 1000 in which the memory cells 200 or 800 described herein may be implemented.
  • the FPGA comprises an array of configurable logic blocks (CLB) 1002 selectively interconnected by columns of lines 1004, which in turn are selectively interconnected with rows of lines 1006.
  • CLB configurable logic blocks
  • switch blocks 1008 are provided at each intersection between column lines 1004 and row lines 1006, allowing the connections between the each of the column lines 1004 with each of the row lines
  • the switching blocks 1008 for example comprise one or more of the memory cells 200 or 800, allowing the connections between the lines to be programmed in a non ⁇ volatile fashion.
  • Figure 10B illustrates one of the CLB 1002 in more detail according to one example in which it comprises a look-up table formed of a multiplexer 1010 having 8 data inputs, each of which is coupled to a memory cell 200 or 800 that outputs a data value from its volatile storage, i.e. one of the storage nodes 106, 108 or 806, 808.
  • the memory cell is not coupled to bit lines of a memory array, such bit lines being coupled to multiple memory cells. Instead, they are more generally coupled to access lines, which could be bit lines, or lines coupled to just one memory cell. One of these access lines for example provides the output data value of the cell.
  • the multiplexer 1010 also comprises a 3-bit control input 1012, controlling which of the 8 input lines is selected, and an output line 1014, outputting the data of the selected input line.
  • An advantage of the embodiments of the memory cell described herein is that it is capable of storing not only one bit of volatile data, but additionally one bit of non-volatile data. Furthermore, the programmed non-volatile data can be quickly loaded to the volatile portion of the memory cell in a simple fashion, by application of a voltage to the access lines of the memory cell. This advantageously means that a state programmed in a non-volatile fashion may be quickly loaded (in less than 1 ns) , for example upon activation of the memory on power-up or after a sleep period. In the case of an FPGA, this allows a circuit design to be quickly initialised, without the need of loading external data into the device to program memory latches and switches.
  • the inverters forming the memory cell are each implemented by a single transistor coupled to the same supply voltage.
  • the memory cell is connected to only one power rail: ground in
  • the volatile data stored by the memory is maintained by current leakage passing through the access transistors of the memory cell, and this leads to very little static current consumption during a standby state in which the volatile data is to be maintained. Furthermore, this volatile data can be independent of the programmed state of the resistive switching elements.
  • the power to the bit lines can be removed altogether, such that even the leakage current becomes negligible.
  • the power consumption of the memory is thus extremely low during such a standby state.
  • a further advantage of the use of a single transistor for forming each inverter of the memory cell is that the difference between the resistances R m in an d Rmax °f the resistance switching elements 202, 204 can be relatively low and/or the speed of the transfer of the programmed non-volatile data to the volatile portion of the memory cell can be relative quick.
  • the time for the voltage Q at node 106 to go from the high state at point 710 to a relatively low voltage a point 718 is relatively short, given that the voltage at node 106 will be discharged via transistor 102, and the only current charging node 106 passes through the resistance R ma x' an d is therefore limited.
  • each inverter formed by transistor 102 could comprise a second transistor coupling node 106 to Vpp and controlled by the voltage Q , there would be an additional current charging node 106 from Vpp, thus slowing the speed at which the voltage Q can fall.
  • the use of a single transistor for forming each inverter allows the difference between the resistances R m j_ n an d 3 ⁇ 4ax to be reduced without impacting the transfer speed, or the speed of transfer to be increased for the same values of R m i n an d Rmax-
  • a greater tolerance for the resistance values of R m j_ n and R max provides the additional advantage of permitting a broader range of materials to be used for forming the resistance switching elements 202, 204.
  • the cell is capable of fast (in around 1 ns) write and read operations for the volatile storage portions, which may occur in a normal fashion irrespective of the programmed states of the non-volatile resistive elements.
  • the write time for the non ⁇ volatile portion is also relatively fast (in around 35 ns in the case of an MRAM) .
  • a further advantage of the memory cells described herein is that the circuit is compact, comprising only four transistors and two programmable resistors for the storage of one bit of non-volatile data and one bit of volatile data. Furthermore, the non-volatile data may be read without the need of additional transistors in each memory cell.
  • the resistance switching elements 202, 204 of Figures 2 and 8 are for example formed in a metal layer above a silicon layer in which the transistors 102, 104 or 802, 804 are formed.
  • the positioning of these resistance switching elements 202, 204 connected directly to the bit lines is thus advantageous as a single via may be used from the silicon layer to one terminal of each resistance switching element, and the other terminal of each element can be connected directly to the corresponding bit line, rather than returning on another via to the silicon layer.
  • ground voltage described herein may be at 0 V, or more generally at any supply voltage 55, that could be different from 0 V.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

L'invention concerne un dispositif de mémoire comportant au moins une cellule de mémoire comportant : un premier transistor (102) couplé entre un premier nœud (106) de stockage et une première tension d'alimentation (GND, VDD ) ; un deuxième transistor (104) couplé entre un deuxième nœud (108) de stockage et ladite première tension d'alimentation, une borne de commande dudit premier transistor étant couplée audit deuxième nœud de stockage et une borne de commande dudit deuxième transistor étant couplée audit premier nœud de stockage ; un premier élément (202) à commutation de résistance couplé entre ledit premier nœud de stockage et une première ligne d'accès (BL) ; et un deuxième élément (204) à commutation de résistance couplé entre ledit deuxième nœud de stockage et une deuxième ligne d'accès (BLB).
PCT/EP2012/050768 2011-01-19 2012-01-19 Cellule de mémoire volatile et non volatile combinée WO2012098182A1 (fr)

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EP3537413A1 (fr) * 2018-03-09 2019-09-11 Karlsruher Institut für Technologie Architecture puf basée sur une mémoire de faible puissance fiable

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Publication number Priority date Publication date Assignee Title
US20100080042A1 (en) * 2007-03-12 2010-04-01 International Business Machines Corporation Integrating nonvolatile memory capability within sram devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100080042A1 (en) * 2007-03-12 2010-04-01 International Business Machines Corporation Integrating nonvolatile memory capability within sram devices

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
S.TEHRANI: "Magnetoresistive random access memory using magnetic tunnel junctions", PROCEEDINGS OF IEEE, vol. 91, no. 5, May 2003 (2003-05-01), pages 3707 - 714, XP011065156
WEISHENG ZHAO ET AL: "TAS-MRAM based Non-volatile FPGA logic circuit", FIELD-PROGRAMMABLE TECHNOLOGY, 2007. ICFPT 2007. INTERNATIONAL CONFERE NCE ON, IEEE, PI, 1 December 2007 (2007-12-01), pages 153 - 160, XP031208385, ISBN: 978-1-4244-1471-0 *

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