WO2012097373A1 - Oxide-nitride-oxide stack having multiple oxynitride layers - Google Patents
Oxide-nitride-oxide stack having multiple oxynitride layers Download PDFInfo
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- WO2012097373A1 WO2012097373A1 PCT/US2012/021583 US2012021583W WO2012097373A1 WO 2012097373 A1 WO2012097373 A1 WO 2012097373A1 US 2012021583 W US2012021583 W US 2012021583W WO 2012097373 A1 WO2012097373 A1 WO 2012097373A1
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
Definitions
- This invention relates to semiconductor processing and, more particularly to an oxide-nitride-oxide stack having an improved oxide-nitride or oxynitride layer and methods of forming the same.
- Non-volatile semiconductor memories such as a split gate flash memory, typically use a stacked floating gate type field effect transistors, in which electrons are induced into a floating gate of a memory cell to be programmed by biasing a control gate and grounding a body region of a substrate on which the memory cell is formed.
- An oxide-nitride-oxide (ONO) stack is used as either a charge storing layer, as in silicon-oxide-nitride-oxide-silicon (SONOS) transistor, or as an isolation layer between the floating gate and control gate, as in a split gate flash memory.
- SONOS silicon-oxide-nitride-oxide-silicon
- FIG. 1 is a partial cross-sectional view of an intermediate structure for a semiconductor device 100 4 such as a memory device, having a SONOS gate stack or structure 102 including a conventional ONO stack 104 formed over a surface 106 of a silicon substrate 108 according to a conventional method.
- the device 100 typically further includes one or more diffusion regions 110, such as source and drain regions, aligned to the gate stack and separated by a channel region 112.
- the SONOS structure 102 includes a poly- silicon (poly) gate layer 114 formed upon and in contact with the ONO stack 104. The poly gate layer 114 is separated or electrically isolated from the substrate 108 by the ONO stack 104.
- the ONO stack 104 generally includes a lower oxide layer 116, a nitride or oxynitride layer 118 which serves as a charge storing or memory layer for the device 100, and a top, high-temperature oxide (HTO) layer 120 overlying the nitride or oxynitride layer.
- HTO high-temperature oxide
- One problem with conventional SONOS structures 102 and methods of forming the same is the poor data retention of the nitride or oxynitride layer 118 that limits the device 100 lifetime and/or its use in several applications due to leakage current through the layer.
- the stochiometry of the oxynitride layer 118 is neither uniform nor optimized across the thickness of the layer.
- the oxynitride layer 118 is conventionally formed or deposited in a single step using a single process gas mixture and fixed or constant processing conditions in an attempt to provide a homogeneous layer having a high nitrogen and high oxygen concentration across the thickness of the relatively thick layer.
- nitrogen, oxygen and silicon concentrations which can vary throughout the conventional oxynitride layer 118.
- the top effect is caused by the order in which process gases are shut off following deposition.
- the silicon containing process gas such as silane
- the silicon containing process gas is typically shut off first resulting in a top portion of the oxynitride layer 118 that is high in oxygen and/or nitride and low in silicon.
- the bottom effect is caused by the order in which process gases are introduced to initiate deposition.
- the deposition of the oxynitride layer 118 typically follows an annealing step, resulting in a peak or relatively high concentration of ammonia (NH 3 ) at the beginning of the deposition process and producing in a bottom portion of the oxynitride layer that is low in oxygen and silicon and high in nitrogen.
- the bottom effect is also due to surface nucleation phenomena in which that oxygen and silicon that is available in the initial process gas mixture preferentially reacts with silicon at the surface of the substrate and does not contribute to the formation of the oxynitride layer. Consequently, the charge storage characteristics, and in particular programming and erase speed and data retention of a memory device 100 made with the ONO stack 104, are adversely effected.
- a semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided.
- the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer.
- the method includes: (i) forming a tunnel oxide layer on a silicon containing layer of a substrate; (ii) forming a multi-layer charge storing layer by depositing on the tunnel oxide layer an oxygen-rich first oxynitride layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free; and depositing on the first oxynitride layer an oxygen-lean second oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; (iii) forming a blocking oxide layer on the second oxynitride layer; and (iv) forming a silicon containing gate layer on the blocking oxide layer.
- FIG. 1 (prior art) is a block diagram illustrating a cross-sectional side view of an intermediate structure for a memory device for which a method having an oxide- nitride-oxide (ONO) stack formed according to conventional method;
- FIG. 2 is a block diagram illustrating a cross-sectional side view of a portion of a semiconductor device having a silicon-oxide-oxynitride-oxide-silicon structure including a multi-layer charge storing layer according to an embodiment of the present disclosure;
- FIG. 3 is flow chart of a method for forming an oxide-oxynitride-oxide structure including a multi-layer charge storing layer according to an embodiment of the present disclosure
- FIG. 4 is a graph showing an improvement in data retention for a memory device using a memory layer formed according to the present disclosure as compared to a memory device using a conventional memory layer;
- FIG. 5 is flow chart of a method for forming an oxide-oxynitride-oxide structure including a multi-layer charge storing layer according to another embodiment of the present disclosure
- FIG. 6 is an energy band diagram of a programmed conventional memory device having an ONO structure
- FIGs. 7A and 7B are energy band diagrams of a memory device including a multi-layer charge storing layer according to an embodiment of the present disclosure prior to and following programming.
- the present invention is directed generally to a device comprising a silicon-oxide-oxynitride-oxide-silicon gate structure including a multi-layer charge storing layer and methods for making the same.
- the gate structure and method are particularly useful for forming a memory layer in a memory device, such as a memory transistor.
- the method involves forming a multi-layer charge storing layer including multiple oxynitride layers, such as silicon oxynitride (S1 2 N 2 O) layers, having differing concentrations of Oxygen, Nitrogen and/or Silicon.
- oxynitride layers are formed at higher temperatures than nitride or oxynitride layers in conventional ONO structures, and each of the layers are formed using differing process gases mixtures and/or at differing flow rates.
- the oxynitride layers include at least a top oxynitride layer and a bottom oxynitride layer.
- the stochiometric compositions of the layers is tailored or selected such that the lower or bottom oxynitride has a high oxygen and silicon content, and the top oxynitride layer has high silicon and a high nitrogen concentration with a low oxygen concentration to produce an oxygen-lean, silicon-rich nitride or oxynitride.
- the silicon-rich and oxygen-rich bottom oxynitride layer reduces stored charge loss without compromising device speed or an initial (beginning of life) difference between program and erase voltages.
- the silicon-rich, oxygen-lean top oxynitride layer increases a difference between programming and erase voltages of memory devices, thereby improving device speed, increasing data retention, and extending the operating life of the device.
- the silicon-rich, oxygen-lean top oxynitride layer can further include a concentration of carbon selected to increase the number of traps therein.
- the ratio of thicknesses between the top oxynitride layer and the bottom oxynitride layer can be selected to facilitate forming of the oxynitride layers over a tunneling or first oxide layer of a silicon-oxide-oxynitride-oxide-silicon gate structure following the forming of the first oxide layer using a dry or wet oxidation.
- a silicon-oxide-oxynitride-oxide-silicon structure and methods for fabricating the same according to various embodiments of the present disclosure will now be described in greater detail with reference to FIGs. 2 through 4.
- FIG. 2 is a block diagram illustrating a cross-sectional side view of a portion of a semiconductor memory device 200 having a silicon-oxide-oxynitride-oxide- silicon gate structure including a multi-layer charge storing layer according to one embodiment.
- the memory device 200 includes a silicon-oxide- oxynitride-oxide-silicon gate structure or gate stack 202 including a multi-layer charge storing layer 204 formed over a surface 206 of silicon layer on a substrate or a silicon substrate 208.
- the device 200 further includes one or more diffusion regions 210, such as source and drain regions or structures, aligned to the gate stack 202 and separated by a channel region 212.
- the silicon-oxide-oxynitride-oxide-silicon gate structure includes a silicon containing gate layer, such as a poly- silicon or poly gate layer 214 formed upon and in contact with the multi-layer charge storing layer 204, and a portion of the silicon layer or substrate 208.
- the poly gate layer 214 is separated or electrically isolated from the substrate 208 by the multi-layer charge storing layer 204.
- the silicon-oxide-oxynitride-oxide-silicon structure includes a thin, lower oxide layer or tunneling oxide layer 216 that separates or electrically isolates the gate stack 202 from the channel region 212, a top or blocking oxide layer 218, and the multi-layer charge storing layer 204.
- the multi-layer charge storing layer 204 includes at least two oxynitride layers, including a top oxynitride layer 220A and a bottom oxynitride layer 220B.
- the substrate 208 may include any known silicon-based semiconductor material including silicon, silicon-germanium, silicon-on-insulator, or silicon-on-sapphire substrate.
- the substrate 208 may include a silicon layer formed on a non- silicon-based semiconductor material, such as gallium-arsenide, germanium, gallium- nitride, or aluminum-phosphide.
- the substrate 208 is a doped or undoped silicon substrate.
- the lower oxide layer or tunneling oxide layer 216 of the silicon-oxide- oxynitride-oxide-silicon structure generally includes a relatively thin layer of silicon dioxide (Si0 2 ) of from about 15 angstrom (A) to about 22 A, and in some embodiments about 18 A.
- the tunneling oxide layer 216 can be formed or deposited by any suitable means including, for example, being thermally grown or deposited using chemical vapor deposition (CVD). Generally, the tunnel oxide layer is formed or grown using a thermal oxidation in oxygen ambient.
- the process involves a dry oxidation method in which the substrate 208 is placed in a in a deposition or processing chamber, heated to a temperature from about 700°C to about 850°C, and exposed to oxygen for a predetermined period of time selected based on a desired thickness of the finished tunneling oxide layer 216.
- the tunnel oxide layer is grown in an ISSG (In-Situ Steam Generation) chamber with a radical oxidation using a reaction between oxygen (0 2 ) and hydrogen (H 2 ) on the substrate at temperatures of at least 1000°C. Exemplary process times are from about 10 to about 100 minutes.
- the oxidation can be performed at atmospheric or at low pressure.
- the multi-layer charge storing layer generally includes at least two oxynitride layers having differing compositions of silicon, oxygen and nitrogen, and can have an overall thickness of from about 70 A to about 150 A, and in certain embodiments about 100 A.
- the oxynitride layers are formed or deposited in a low pressure CVD process using a silicon source, such as silane (SiH4), chlorosilane (SiH 3 Cl), dichlorosilane or DCS (SiH 2 Cl 2 ), tetrachloro silane (SiCl 4 ) or Bis- TertiaryButylAmino Silane (BTBAS), a nitrogen source, such as nitrogen (N2), ammonia (NH 3 ), nitrogen trioxide (N0 3 ) or nitrous oxide (N 2 0), and an oxygen-containing gas, such as oxygen (0 2 ) or N 2 0.
- a silicon source such as silane (SiH4), chlorosilane (SiH 3 Cl), dichlorosilane or DCS (SiH 2 Cl 2 ), tetrachloro silane (SiCl 4 ) or Bis- TertiaryButylAmino Silane (BTBAS)
- a nitrogen source such as
- gases in which hydrogen has been replaced by deuterium can be used, including, for example, the substitution of deuterated- ammonia (ND 3 ) for NH 3 .
- ND 3 deuterated- ammonia
- the substitution of deuterium for hydrogen advantageously passivates Si dangling bonds at the silicon-oxide interface, thereby increasing an NBTI (Negative Bias Temperature Instability) lifetime of the devices.
- NBTI Negative Bias Temperature Instability
- the lower or bottom oxynitride layer 220B can be deposited over the tunneling oxide layer 216 by placing the substrate 208 in a deposition chamber and introducing a process gas including N 2 0, NH 3 and DCS, while maintaining the chamber at a pressure of from about 5 millitorr (mT) to about 500 mT, and maintaining the substrate at a temperature of from about 700°C to about 850°C and in certain embodiments at least about 760°C, for a period of from about 2.5 minutes to about 20 minutes.
- mT millitorr
- the process gas can include a first gas mixture of N 2 0 and NH 3 mixed in a ratio of from about 8: 1 to about 1:8 and a second gas mixture of DCS and NH 3 mixed in a ratio of from about 1:7 to about 7: 1, and can be introduced at a flow rate of from about 5 to about 200 standard cubic centimeters per minute (seem). It has been found that an oxynitride layer produced or deposited under these condition yields a silicon-rich, oxygen-rich, bottom oxynitride layer 220B, that decrease the charge loss rate after programming and after erase, which is manifested in a small voltage shift in the retention mode.
- the top oxynitride layer 220A can be deposited over the bottom oxynitride layer 220B in a CVD process using a process gas including N 2 0, NH 3 and DCS, at a chamber pressure of from about 5 mT to about 500 mT, and at a substrate temperature of from about 700°C to about 850°C and in certain embodiments at least about 760°C, for a period of from about 2.5 minutes to about 20 minutes.
- a process gas including N 2 0, NH 3 and DCS at a chamber pressure of from about 5 mT to about 500 mT
- a substrate temperature of from about 700°C to about 850°C and in certain embodiments at least about 760°C, for a period of from about 2.5 minutes to about 20 minutes.
- the process gas can include a first gas mixture of N20 and NH3 mixed in a ratio of from about 8: 1 to about 1:8 and a second gas mixture of DCS and NH3 mixed in a ratio of from about 1:7 to about 7: 1, and can be introduced at a flow rate of from about 5 to about 20 seem.
- an oxynitride layer produced or deposited under these condition yields a silicon-rich, nitrogen-rich, and oxygen-lean top oxynitride layer 220A, which improves the speed and increases of the initial difference between program and erase voltage without compromising a charge loss rate of memory devices made using an embodiment of the silicon-oxide-oxynitride-oxide-silicon structure, thereby extending the operating life of the device.
- the silicon-rich, nitrogen-rich, and oxygen-lean top oxynitride layer 220A can be deposited over the bottom oxynitride layer 220B in a CVD process using a process gas including BTBAS and ammonia (NH 3 ) mixed at a ratio of from about 7: 1 to about 1:7 to further include a concentration of carbon selected to increase the number of traps therein.
- the selected concentration of carbon in the second oxynitride layer can include a carbon concentration of from about 5% to about 15%.
- the top oxynitride layer 220A is deposited sequentially in the same tool used to form the bottom oxynitride layer 220B, substantially without breaking vacuum on the deposition chamber. In certain embodiments, the top oxynitride layer 220A is deposited substantially without altering the temperature to which the substrate 208 was heated during deposition of the bottom oxynitride layer 220B.
- the top oxynitride layer 220A is deposited sequentially and immediately following the deposition of the bottom oxynitride layer 220B by decreasing the flow rate of the N 2 O/NH 3 gas mixture relative to the DCS/NH 3 gas mixture to provide the desired ratio of the gas mixtures to yield the silicon-rich, nitrogen-rich, and oxygen- lean top oxynitride layer 220A.
- another oxide or oxide layer (not shown in these figures) is formed after the formation of the gate stack 202 in a different area on the substrate 208 or in the device using a steam oxidation.
- the top oxynitride layer 220A and top or blocking oxide layer 218 of the silicon-oxide- oxynitride-oxide-silicon structure are beneficially steam annealed during the steam oxidation process.
- steam annealing improves the quality of the top or blocking oxide layer 218 reducing the number of traps formed near a top surface of the blocking oxide layer and near a top surface of the underlying top oxynitride layer 220A, thereby reducing or substantially eliminating an electric field that could otherwise form across the blocking oxide layer, which could result in back streaming of charge carriers therethrough and adversely affecting data or charge retention in the charge storing layer.
- a suitable thickness for the bottom oxynitride layer 220B has been found to be from about 10 A to about 80 A, and a ratio of thicknesses between the bottom layer and the top oxynitride layer has been found to be from about 1:6 to about 6: 1, and in certain embodiments at least about 1:4.
- the top or blocking oxide layer 218 of the silicon-oxide-oxynitride-oxide- silicon structure includes a relatively thick layer of Si0 2 of from about 30 A to about 70
- the top or blocking oxide layer 218 can be formed or deposited by any suitable means including, for example, being thermally grown or deposited using CVD.
- the top or blocking oxide layer 218 is a high-temperature-oxide (HTO) deposited using CVD process.
- the deposition process involves exposing the substrate 208 to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as 0 2 or N 2 0 in a deposition chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650°C to about 850°C.
- a silicon source such as silane, chlorosilane, or dichlorosilane
- an oxygen-containing gas such as 0 2 or N 2 0
- the top or blocking oxide layer 218 is deposited sequentially in the same tool used to form the oxynitride layers 220A, 220B. In certain embodiments, the oxynitride layers 220A, 220B, and the top or blocking oxide layer 218 are formed or deposited in the same tool used to grow the tunneling oxide layer 216. Suitable tools include, for example, an ONO AVP, commercially available from AVIZA technology of Scotts Valley, California.
- the method begins with forming a first oxide layer, such as a tunneling oxide layer 216, of the silicon-oxide-oxynitride-oxide-silicon gate stack 202 over a silicon containing layer on a surface of a substrate 208 (300).
- a first oxide layer such as a tunneling oxide layer 216
- this first or bottom oxynitride layer 220B can be formed or deposited by a CVD process using a process gas including ⁇ 2 0/ ⁇ 3 and DCS/NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer.
- the second or top oxynitride layer 220A of the multi-layer charge storing layer 204 is then formed on a surface of the first or bottom oxynitride layer 220B (304).
- the second or top oxynitride layer 220A has a stochiometric composition of oxygen, nitrogen and/or silicon different from that of the first or bottom oxynitride layer 220B.
- the second or top oxynitride layer 220A can be formed or deposited by a CVD process using a process gas including DCS/NH 3 and N 2 0/NH 3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top oxynitride layer.
- a top or blocking oxide layer 218 of the silicon-oxide-oxynitride-oxide-silicon structure is formed on a surface of the second layer of the multi-layer charge storing layer (306).
- this top or blocking oxide layer 218 can be formed or deposited by any suitable means, but in some embodiments is deposited in a CVD process.
- the top or blocking oxide layer 218 is a high temperature oxide deposited in a HTO CVD process.
- the top or blocking oxide layer 218 can be thermally grown, however it will be appreciated that in this embodiment the thickness of the top oxynitride 220A may be adjusted or increased as some of the top oxynitride will be effectively consumed or oxidized during the process of thermally growing the top or blocking oxide layer 218.
- the method may further include forming or depositing a silicon containing layer on a surface of the top or blocking oxide layer 218 to form a silicon- oxide-oxynitride-oxide-silicon stack or structure (308).
- the silicon containing layer can be, for example, a polysilicon layer deposited by a CVD process to form a control or poly gate layer 214 of the transistor or device 200.
- FIG. 4 illustrates the change in threshold voltage of devices in an electronically erasable programmable read-only memory (EEPROM) during programming (VTP) during erase (VTE) over device life for an EEPROM made using a conventional ONO structure and a silicon-oxide-oxynitride-oxide-silicon structure having a multi-layer oxynitride layer.
- EEPROM electronically erasable programmable read-only memory
- VTP electronically erasable programmable read-only memory
- VTE erase
- the graph or line 402 illustrates the change over time of a VTP for an EEPROM made using a conventional ONO structure having a single oxynitride layer without refreshing the memory after the initial writing - program or erase. Actual data points on line 402 are shown by unfilled circles, the remainder of the line showing an extrapolation of VTP to a specified end-of-life (EOL) for the EEPROM.
- Graph or line 404 illustrates the change over time of a VTE for the EEPROM made using a conventional ONO structure. Actual data points on line 404 are shown by filled circles, and the remainder of the line shows an extrapolation of VTE to EOL for the EEPROM.
- the specified difference between the VTE and VTP for an EEPROM at EOL is at least 0.5 V to be able to identify or sense the difference between the program and erase state.
- an EEPROM made using a conventional ONO structure has a difference between VTE and VTP of about 0.35V at a specified EOL of 20 years.
- an EEPROM made using a conventional ONO structure and operated under the conditions described above will fail to meet the specified operating life by at least about 17 years.
- the method begins with forming a tunneling oxide layer 216 on a substrate (500).
- an oxygen-rich, first or bottom oxynitride layer 220B of a multi-layer charge storing layer 204 is formed on a surface of the tunneling oxide layer 216 (502).
- this oxygen-rich, first or bottom oxynitride layer 220B can be formed or deposited by a CVD process using a process gas comprising a dichlorosilane (SiH 2 Cl 2 )/ammonia (NH 3 ) mixture at a ratio in the range of about 5: 1 to 15: 1; and a nitrous oxide (N 2 0)/NH 3 mixture at a ratio in the range of about 2: 1 to 4: 1 and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer which is substantially trap free.
- a process gas comprising a dichlorosilane (SiH 2 Cl 2 )/ammonia (NH 3 ) mixture at a ratio in the range of about 5: 1 to 15: 1; and a nitrous oxide (N 2 0)/NH 3 mixture at a ratio in the range of about 2: 1 to 4: 1 and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer which is substantially
- the stoichiometric composition of the first or bottom oxynitride layer 220B comprises a high concentration of oxygen selected to increase retention performance of the multi-layer charge storing layer by acting as a barrier between charge trapped in the second or top oxynitride layer 220A and the substrate 208.
- the selected concentration of oxygen in the first or bottom oxynitride layer 220B can include an oxygen concentration of from about 15% to about 40%, and, in certain embodiments about 35%.
- An oxygen-lean, second or top oxynitride layer 220A is then formed on a surface of the first or bottom oxynitride layer 220B (504).
- the second or top oxynitride layer 220A has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the first layer.
- the second or top oxynitride layer 220A can be formed or deposited by a CVD process using a process gas using a process gas comprising a N 2 O/NH 3 mixture at a ratio in the range of about 1:6 to 1:8 and a SiH 2 Cl 2 /NH 3 mixture at a ratio in the range of about 1.5: 1 to 3: 1 to provide a trap dense oxynitride layer having an oxygen concentration of about 5% or less.
- the second or top oxynitride layer 220A comprises a charge trap density at least 1000 times greater than the first or bottom oxynitride layer 220B.
- a top or blocking oxide layer 218 is formed over the second or top oxynitride layer 220A of the multi-layer charge storing layer 204 (506).
- this top or blocking oxide layer 218 can be formed or deposited by any suitable means.
- the second or blocking oxide layer 218 is formed a manner that results in thinning of the second or top oxynitride layer 220A to a predetermined thickness through oxidization of a portion of the second oxynitride layer.
- the increased retention performance of the multi-layer charge storing layer 204 increases an end-of-life (EOL) for the semiconductor device at a specified difference between program voltage (VTP) and erase voltage (VTE) to at least about 20 years.
- EOL end-of-life
- the multi-layer charge storing layer of the present disclosure has bandgap energy engineered to generate an electrical field opposing that built-up due to charge storage in the charge storing layer in a programmed state, thereby increasing data retention, without impacting programming voltages and/or device speed.
- FIG. 6 An energy band diagram of a programmed conventional device including a channel in silicon substrate 602, a tunneling oxide layer 604, a homogeneous nitride or oxynitride charge storing layer 606, oxide blocking layer 608 and a polysilicon control gate 610 is illustrated in FIG. 6.
- a programmed conventional device including a channel in silicon substrate 602, a tunneling oxide layer 604, a homogeneous nitride or oxynitride charge storing layer 606, oxide blocking layer 608 and a polysilicon control gate 610 is illustrated in FIG. 6.
- FIG. 6 it is noted that large number of trapped charges located near the center of the charge storing layer 606 results in a build-up of a large electric field away from the tunneling oxide layer 604 towards the trapped charges, and which can cause or result in loss of stored charges
- FIG. 7A An unprogrammed memory device including a multi-layer charge storing layer 706 is shown in FIG. 7A.
- the device includes a channel in silicon substrate 702, a tunneling oxide layer 704, an oxygen-lean oxynitride layer 706A, an oxygen-rich bottom oxynitride layer 706B, an oxide blocking layer 708 and a polysilicon control gate 710.
- the trap sites in the oxygen-lean top oxynitride layer 706A produces an electric field that will oppose the electric field produced by the trapped charges in the programmed device.
- the resultant bandgap diagram of a device including a multi-layer charge storing layer 706 in a programmed state is shown in FIG. 7A.
- the multi-layer charge storing layer can include any number, n, of oxynitride layers, any or all of which may have differing stochiometric compositions of oxygen, nitrogen and/or silicon.
- multi-layer charge storing layers having up to five oxynitride layers each with differing stochiometric compositions have been produced and tested.
- utilizing as few layers as possible also results in higher yields as it is simpler to control the stoichiometric composition and dimensions of the fewer layers.
- FIGs. 8A-8E are schematic diagrams of exemplary memory cell architectures for which the multi-layer charge storing layer of the present disclosure is particularly useful.
- the advantages of the structures and methods of forming the same according to an embodiment of the present disclosure over previous or conventional approaches include: (i) the ability to enhance data retention in memory devices using the structure by dividing the oxynitride layer into a plurality of films or layers and tailoring the oxygen, nitrogen and silicon profile across each layer; (ii) the ability to enhance speed of a memory device without compromising data retention; (iii) the ability to meet or exceed data retention and speed specifications for memory devices using a silicon-oxide- oxynitride-oxide-silicon structure of an embodiment of the present disclosure at a temperature of at least about 125°C; and (iv) provide heavy duty program erase cycles of 100,000 cycles or more.
- references in the description to "one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the hot de-latch system or method.
- the appearances of the phrase “one embodiment” in various places in the specification do not necessarily all refer to the same embodiment.
- the term “to couple” as used herein may include both to directly electrically connect two or more components or elements and to indirectly connect through one or more intervening components.
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