WO2012083783A1 - Double-diffusion metal-oxide semiconductor devices - Google Patents
Double-diffusion metal-oxide semiconductor devices Download PDFInfo
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- WO2012083783A1 WO2012083783A1 PCT/CN2011/083106 CN2011083106W WO2012083783A1 WO 2012083783 A1 WO2012083783 A1 WO 2012083783A1 CN 2011083106 W CN2011083106 W CN 2011083106W WO 2012083783 A1 WO2012083783 A1 WO 2012083783A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 12
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 12
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- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000004806 packaging method and process Methods 0.000 claims abstract description 17
- 230000001788 irregular Effects 0.000 claims description 2
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Abstract
A double-diffusion metal-oxide semiconductor (DMOS) device (100) is disclosed. The DMOS device (100) includes a substrate, a source region on the substrate, a gate region on the substrate, and a drain region on the substrate. The DMOS device (100) also includes a source metal layer (101) positioned on the source region and a gate metal layer (102) positioned on the gate region. The source metal layer (101) has a first pattern, the gate metal layer (102) has a second pattern, and the first pattern is different from the second pattern such that the source metal layer (101) can be distinguished from the gate metal layer (102) by packaging equipment based on the different first pattern and second pattern.
Description
FIELD OF THE INVENTION
The present invention generally relates to the field
of semiconductor manufacturing and, more particularly, to the metal-oxide
semiconductor technologies.
BACKGROUND
A double-diffusion metal-oxide-semiconductor (DMOS)
device has a structure similar to that of a CMOS device, which includes a
source electrode, a gate electrode, and a drain electrode. The DMOS devices are
often divided into VDMOS (vertical double-diffusion MOS) devices and LDMOS
(lateral double-diffusion MOS) devices. The DMOS devices are often designed for
applications with large currents and high voltages, and a DMOS device usually
has an excellent thermal stability, frequency stability, high gain, high
durability, low noise, low feedback capacitance, constant input impedance, and
simple bias circuit.
A conventional method for fabricating a DMOS device
often includes a packaging process. Because the source metal layer of the DMOS
device is often positioned close to the gate metal layer of the DMOS device and
these two metal layers appear identical, a problem can occur in the packaging
process as it is difficult to distinguish these two metal layers. To address
this problem, the conventional method may define a notch between the source
metal layer and the gate metal layer or may increase the distance between the
source metal layer and the gate metal layer, such that the packaging equipment
can distinguish the source metal layer from the gate metal layer during the
packaging process.
However, such approach may have certain disadvantages.
For example, if the distance between the source metal layer and the gate metal
layer is not large enough, the packaging equipment may be unable to distinguish
the source metal layer from the gate metal layer. If the distance is increased
or the notch is used, the area of the DMOS device may also become large, which
may cause additional cost and poor electricity distribution.
The disclosed methods and systems are directed to
solve one or more problems set forth above and other problems.
BRIEF SUMMARY OF THE DISCLOSURE
One aspect of the present disclosure includes a
double-diffusion metal-oxide semiconductor (DMOS) device. The DMOS device
includes a substrate, a source region on the substrate, a gate region on the
substrate, and a drain region on the substrate. The DMOS device also includes a
source metal layer positioned on the source region and a gate metal layer
positioned on the gate region. The source metal layer has a first pattern, the
gate metal layer has a second pattern, and the first pattern is different from
the second pattern such that the source metal layer can be distinguished from
the gate metal layer by packaging equipment based on the different first
pattern and second pattern.
Another aspect of the present disclosure includes a
double-diffusion metal-oxide semiconductor (DMOS) device. The DMOS device a
substrate, a source region on the substrate, a gate region on the substrate,
and a drain region on the substrate. The DMOS device also includes a source
metal layer positioned on the source region and a gate metal layer positioned
on the gate region. The source metal layer has a first color, the gate metal
layer has a second color, and the first color is different from the second
color such that the source metal layer can be distinguished from the gate metal
layer by packaging equipment based on the different first color and second
color.
Other aspects of the present disclosure can be
understood by those skilled in the art in light of the description, the claims,
and the drawings of the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows a conventional double-diffusion
metal-oxide-semiconductor (DMOS) device ; and
Figure 2 illustrates an exemplary DMOS device
consistent with the disclosed embodiments.
DETAILED DESCRIPTION
Reference will now be made in detail to exemplary
embodiments of the invention, which are illustrated in the accompanying
drawings. Wherever possible, the same reference numbers will be used throughout
the drawings to refer to the same or like parts.
Figure 1 shows a conventional double-diffusion
metal-oxide-semiconductor (DMOS) device. As shown in Figure 1, the conventional
DMOS device includes a source metal layer 01 and a gate metal layer 02. Because
the source metal layer 01 and the gate metal layer 02 appear similarly, it may
be difficult to distinguish the source metal layer 01 and the gate metal layer
02 during a packaging process. Thus, in the DMOS device shown in Figure 1,
notches (not shown) may be defined between the source metal layer 01 and the
gate metal layer 02 or the distance between the source metal layer 01 and the
gate metal layer 02 may be increased so that it may become less difficult to
distinguish the source metal layer 01 and the gate metal layer 02 during the
packaging process .
Figure 2 illustrates an exemplary DMOS device 100
consistent with the disclosed embodiments. The DMOS device 100 may include a
substrate (not shown) and may also include a source region, a gate region, and
a drain region (not shown) on the substrate. Further, as shown in Figure 2,
DMOS device 100 includes a source metal layer 101 positioned on the source
region and a gate metal layer 102 positioned on the gate region . Other
structures may also be included.
To form the source metal layer 101 and the gate metal
layer 102, one or a plurality of metal layers are formed on the source region
and the gate region. The metal layer may be made of a conductor metal, such as
tungsten, titanium, aluminum, copper, and aluminum-copper alloy, etc. The metal
layer may include a plurality of metal films, such as titanium film,
aluminum-copper alloy film, or titanium nitride serving as anti-reflection
layer. Other arrangements may also be used.
After forming the metal layer(s), a photoresist layer
may be coated on the metal layer, and a source pattern and a gate pattern may
be formed in the photoresist layer using photolithography, such as performing
exposure and development processes on the photoresist layer. The source pattern
and the gate pattern (i.e., the photoresist pattern) may be designed to
implement multiple functionalities. For example, at first, the source pattern
may be designed to define an area and shape of the source metal layer 101 as
positioned on the source region, and the gate pattern may be designed to define
an area and shape of the gate metal layer 102 as positioned on the gate region.
In this respect, after forming the source pattern and the gate pattern, the
metal layer located outside the source pattern and the gate pattern is removed
by plasma etching or other etching method using the source pattern and the gate
pattern as a mask to form the source metal layer 101 and the gate metal layer
102, respectively .
Further, the source pattern may be designed to define
a surface pattern of the source metal layer 101, and the gate pattern may be
designed to define a surface pattern of the gate metal layer 102. In certain
embodiments, the source pattern is different from the gate pattern such that
the surface pattern of the source metal layer 101 and the surface pattern of
the gate metal layer 102 are substantially different so that the source metal
layer 101 and the gate metal layer 102 can be distinguished from each other by
packaging equipment . That is, because the surface pattern of the gate metal
layer 101 is the same as the gate pattern in the photoresist layer through the
etching process, the surface pattern of the source metal layer 102 is the same
as the source pattern in the photoresist layer, and the source pattern is
different from the gate pattern in the photoresist layer, the surface pattern
of the source metal layer 101 is different from the surface pattern of the gate
metal layer 102 .
The surface pattern (or simply the pattern) of the
source metal layer 101 or the gate metal layer 102, as used herein, may refer
to a shape, size, texture, structure, and/or geometrical pattern, etc., of the
source metal layer 101 and the gate metal layer 102. Other characteristics may
also be included.
Thus, to distinguish the source metal layer 101 from
the gate metal layer 102, the pattern of the source metal layer 101 is made
different from that of the gate metal layer 102. In other words, the pattern of
the source metal layer 101 and the pattern of the gate metal layer 102 are
different such that the source metal layer 101 and the gate metal layer 102 can
be distinguished by packaging equipment based on the different patterns. Any
appropriate patterns may be used for the source metal layer 101 and the gate
metal layer 102. For example, the pattern of the source metal layer 101 or the
gate metal layer 102 can be consisted of a plurality of circles, a plurality of
ovals, and/or a plurality of rectangles. The pattern of the source metal layer
101 or the gate metal layer 102 can also be consisted of a plurality of regular
polygons or a plurality of irregular polygons. Further, the pattern of the
source metal layer 101 or the gate metal layer 102 can be consisted of a
plurality of lines and/or dots, and the lines may be arc, straight, and/or
curve lines.
The pattern of the source metal layer 101 or the gate
metal layer 102 may be consisted of identical patterns or lines, or may be
consisted of different patterns or lines. For example, the pattern of the
source metal layer 101 may be consisted of a plurality of circles, while the
pattern of the gate metal layer 102 may be consisted of a plurality of cubes
and triangles. Also, the pattern of the source metal layer 101 may be consisted
of a plurality of rectangles, while the pattern of the gate metal layer 102 may
be consisted of a plurality of ovals. Other patterns or lines may also be used
so long as the patterns of the source metal layer 101 and the gate metal layer
102 can be distinguished by the packaging equipment.
Further, in a DMOS device consisted by a plurality of
DMOS cells, a dielectric layer may be positioned between the metal layer and
the source region, the gate region, and the drain region. The dielectric layer
may include a plurality of through holes for contacting the source region, the
gate region, and the drain region by the metal layers. In addition, a gate
oxide layer may be positioned between the gate region and the gate metal layer
102. Based on the electric requirements of the DMOS device, the thickness of
the gate oxide layer may be greater than that of conventional semiconductor
device. Furthermore, a drain metal layer (not shown) may also be formed on the
drain region.
Additionally or alternatively, in DMOS device 100, the
source metal layer 101 may have a color different from the color of the gate
metal layer 102 , such that during the subsequent package processes, the
packaging equipment can distinguish the source metal layer 101 from the gate
metal layer 102 based on the different color of the source metal layer 101 and
the gate metal layer 102. In certain embodiments, the source metal layer 101
and the gate metal layer 102 can be distinguished by the packaging equipment
based on both the different patterns and the different colors of the source
metal layer 101 and the gate metal layer 102 . Other features may also be
used.
The DMOS device 100 may be a vertical double-diffusion
MOS (VDMOS) device or a lateral double-diffusion MOS (LDMOS) device. Based on
the particular type of device (VDMOS or LDMOS), different patterns may be used
for the source metal layer 101 and the gate metal layer 102 of the DMOS device
100.
When the DMOS device 100 is an LDMOS device, in the
planar-structured LDMOS device, the source electrode, the gate electrode, and
the drain electrode are led out from an upper surface of the DMOS device 100 so
as to integrate the DMOS device with other devices. The source region is
self-aligned and the gate metal layer 102 is departed from the drain region to
reduce the input and feedback capacitance and to alleviate the short-channel
effect. The LDMOS device 100 forms the channel by co-diffusion of the source
region and a trap area surrounding the source region. Further, the LDMOS device
100 has a threshold voltage close to that of an ordinary MOS transistor, and
the LDMOS device 100 may be used in high-voltage power circuits.
In addition, in the LDMOS device 100, a drift region
(not shown) may be positioned between the source region and the drain region.
The drift region may have a low concentration of the impurity such that, when a
high voltage is applied to the LDMOS device 100, the drift region is in a high
impedance state. Thus, the LDMOS device 100 can sustain the high voltage from
the drain end.
On the other hand, when the DMOS device 100 is a VDMOS
device, the VDMOS device 100 may have an epitaxial layer (not shown) formed on
a back side of the silicon substrate (not shown) of the VDMOS device 100. The
current flowing along the channel may change to a vertical direction and flow
towards the substrate. Accordingly, the drain electrode of the VDMOS device 100
is led out from the bottom side of the silicon substrate, and the source
electrode and the drain electrode are positioned on a front side of the silicon
substrate to improve the integrity. Compared with a bipolar transistor, the
VDMOS device 100 may have a high switching speed, low switching loss, high
input resistance, low driving power, and negative temperature coefficient, and
is less likely to have a second breakdown. Thus, the VDMOS device 100 may be a
desired power device for switching or linear applications.
Further, the DMOS device 100 may be an N-channel
double-diffusion MOS (N-channel DMOS) device or a P- channel double-diffusion
MOS (P-channel DMOS) device according to the types of carriers in the channel
of the device. Based on the particular type of device (the N-channel DMOS
device and the P-channel DMOS device), different patterns may be used for the
source metal layer 101 and the gate metal layer 102 of the DMOS device 100.
When the DMOS device 100 is an N-channel DMOS device,
the substrate of the N-channel DMOS device 100 is an N- type
material. To form the source region and the drain region of the N-channel DMOS
device 100, a P-type diffusion may be performed on a special region of the
substrate to form a P-type region using a corresponding mask, and an N+
diffusion may be performed using the same mask. The lateral length of the
P-type region is then the length of the channel. Further, if the lateral
diffusion depth is the same as the vertical diffusion depth, the length of the
channel can be controlled within 1μm. Since the N- layer can sustain
a high base voltage and have a low feedback capacitance, an improved
characteristic of the DMOS device 100 can be achieved.
When the DMOS device 100 is a P-channel DMOS device,
the P-channel DMOS device may have a similar structure to the N-channel DMOS
device described above, and the difference lies in the opposite doping carrier
type.
Therefore, by using the disclosed methods and devices,
the pattern of the source metal layer of the DMOS device is made different from
the pattern of the gate metal layer of the DMOS device. Thus, during packaging
processes, the packaging equipment can distinguish the source metal layer from
the gate metal layer according to their different patterns. In such a manner,
it may be unnecessary to increase the distance between the source metal layer
and the gate metal layer. Thus, the area of the DMOS device may be reduced to
achieve lower cost and improved performance. In addition, the current processes
of fabricating the DMOS device do not have to be changed to add any special
process to identify the source metal layer and the gate metal layer.
Whether the DMOS device is an LDMOS device or a VDMOS
device, the pattern of the source metal layer of the L DMOS device or the VDMOS
device is made different from that of the gate metal layer of the L DMOS device
or the VDMOS device. The packaging equipment thus can distinguish the source
metal layer from the gate metal layer according to their different patterns
during packaging processes without employing any special process to identify
the source metal layer and the gate metal layer.
Further, whether the DMOS device is an N-channel DMOS
device or a P-channel DMOS device, the pattern of the source metal layer of the
N-channel DMOS device or the P-channel DMOS device is made different from that
of the gate metal layer of the N-channel DMOS device or the P-channel DMOS
device. Thus, packaging equipment can distinguish the source metal layer from
the gate metal layer according to their different patterns during packaging
processes without employing any special process to identify the source metal
layer and the gate metal layer.
It is understood that the disclosed embodiments may
be applied to any appropriate semiconductor device manufacturing processes.
Various alternations, modifications, or equivalents to the technical solutions
of the disclosed embodiments can be obvious to those skilled in the art.
Claims (11)
- A double-diffusion metal-oxide semiconductor (DMOS) device, comprising:a substrate;a source region on the substrate;a gate region on the substrate;a drain region on the substrate;a source metal layer positioned on the source region; anda gate metal layer positioned on the gate region,wherein:the source metal layer has a first pattern;the gate metal layer has a second pattern; andthe first pattern is different from the second pattern such that the source metal layer can be distinguished from the gate metal layer by packaging equipment based on the different first pattern and second pattern.
- The DMOS device according to claim 1, wherein:the source metal layer has a first color;the gate metal layer has a second color; andthe first color is different from the second color such that the source metal layer can be distinguished from the gate metal layer by the packaging equipment based on the different first color and second color.
- The DMOS device according to claim 1, wherein:the first pattern and the second patter are different and from a plurality of circles, a plurality of ovals, and a plurality of rectangles.
- The DMOS device according to claim 1, wherein:the first pattern and the second patter are a plurality of regular polygons and a plurality of irregular polygons.
- The DMOS device according to claim 1, wherein:the first pattern and the second patter are a plurality of lines and a plurality of dots.
- The DMOS device according to claim 1, wherein:the DMOS device is a vertical double-diffusion metal-oxide semiconductor (VDMOS) device.
- The DMOS device according to claim 1, wherein:the DMOS device is a lateral double-diffusion metal-oxide semiconductor (LDMOS) device.
- The DMOS device according to claim 1, wherein:the DMOS device is an N-channel double-diffusion metal-oxide semiconductor (NDMOS) device.
- The DMOS device according to claim 1, wherein:the DMOS device is a P-channel double-diffusion metal-oxide semiconductor (PDMOS) device.
- A double-diffusion metal-oxide semiconductor (DMOS) device, comprising:a substrate;a source region on the substrate;a gate region on the substrate;a drain region on the substrate;a source metal layer positioned on the source region; anda gate metal layer positioned on the gate region,wherein:the source metal layer has a first color;the gate metal layer has a second color; andthe first color is different from the second color such that the source metal layer can be distinguished from the gate metal layer by packaging equipment based on the different first color and second color.
- The DMOS device according to claim 10, wherein:the source metal layer has a first pattern;the gate metal layer has a second pattern; andthe first pattern is different from the second pattern such that the source metal layer can be distinguished from the gate metal layer by packaging equipment based on the different first pattern and second pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013545020A JP5918257B2 (en) | 2010-12-22 | 2011-11-29 | Double diffusion metal oxide semiconductor device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010601804.9A CN102569387B (en) | 2010-12-22 | 2010-12-22 | Double diffusion metal-oxide-semiconductor (DMOS) device |
| CN201010601804.9 | 2010-12-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2012083783A1 true WO2012083783A1 (en) | 2012-06-28 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CN2011/083106 WO2012083783A1 (en) | 2010-12-22 | 2011-11-29 | Double-diffusion metal-oxide semiconductor devices |
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|---|---|
| JP (1) | JP5918257B2 (en) |
| CN (1) | CN102569387B (en) |
| WO (1) | WO2012083783A1 (en) |
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| JPS61114565A (en) * | 1984-11-09 | 1986-06-02 | Hitachi Ltd | Semiconductor device |
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- 2011-11-29 WO PCT/CN2011/083106 patent/WO2012083783A1/en active Application Filing
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Also Published As
| Publication number | Publication date |
|---|---|
| JP5918257B2 (en) | 2016-05-18 |
| JP2014505360A (en) | 2014-02-27 |
| CN102569387A (en) | 2012-07-11 |
| CN102569387B (en) | 2014-08-27 |
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