WO2012083783A1 - Double-diffusion metal-oxide semiconductor devices - Google Patents

Double-diffusion metal-oxide semiconductor devices Download PDF

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Publication number
WO2012083783A1
WO2012083783A1 PCT/CN2011/083106 CN2011083106W WO2012083783A1 WO 2012083783 A1 WO2012083783 A1 WO 2012083783A1 CN 2011083106 W CN2011083106 W CN 2011083106W WO 2012083783 A1 WO2012083783 A1 WO 2012083783A1
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Prior art keywords
metal layer
pattern
source
gate
dmos
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Ceased
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PCT/CN2011/083106
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French (fr)
Inventor
Jian Cao
Guangyan ZHAO
Dongyue GAO
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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Priority to JP2013545020A priority Critical patent/JP5918257B2/en
Publication of WO2012083783A1 publication Critical patent/WO2012083783A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts

Definitions

  • the present invention generally relates to the field of semiconductor manufacturing and, more particularly, to the metal-oxide semiconductor technologies.
  • a double-diffusion metal-oxide-semiconductor (DMOS) device has a structure similar to that of a CMOS device, which includes a source electrode, a gate electrode, and a drain electrode.
  • the DMOS devices are often divided into VDMOS (vertical double-diffusion MOS) devices and LDMOS (lateral double-diffusion MOS) devices.
  • VDMOS vertical double-diffusion MOS
  • LDMOS lateral double-diffusion MOS
  • the DMOS devices are often designed for applications with large currents and high voltages, and a DMOS device usually has an excellent thermal stability, frequency stability, high gain, high durability, low noise, low feedback capacitance, constant input impedance, and simple bias circuit.
  • a conventional method for fabricating a DMOS device often includes a packaging process. Because the source metal layer of the DMOS device is often positioned close to the gate metal layer of the DMOS device and these two metal layers appear identical, a problem can occur in the packaging process as it is difficult to distinguish these two metal layers. To address this problem, the conventional method may define a notch between the source metal layer and the gate metal layer or may increase the distance between the source metal layer and the gate metal layer, such that the packaging equipment can distinguish the source metal layer from the gate metal layer during the packaging process.
  • the packaging equipment may be unable to distinguish the source metal layer from the gate metal layer. If the distance is increased or the notch is used, the area of the DMOS device may also become large, which may cause additional cost and poor electricity distribution.
  • the disclosed methods and systems are directed to solve one or more problems set forth above and other problems.
  • the DMOS device includes a substrate, a source region on the substrate, a gate region on the substrate, and a drain region on the substrate.
  • the DMOS device also includes a source metal layer positioned on the source region and a gate metal layer positioned on the gate region.
  • the source metal layer has a first pattern
  • the gate metal layer has a second pattern
  • the first pattern is different from the second pattern such that the source metal layer can be distinguished from the gate metal layer by packaging equipment based on the different first pattern and second pattern.
  • the DMOS device a substrate, a source region on the substrate, a gate region on the substrate, and a drain region on the substrate.
  • the DMOS device also includes a source metal layer positioned on the source region and a gate metal layer positioned on the gate region.
  • the source metal layer has a first color
  • the gate metal layer has a second color
  • the first color is different from the second color such that the source metal layer can be distinguished from the gate metal layer by packaging equipment based on the different first color and second color.
  • Figure 1 shows a conventional double-diffusion metal-oxide-semiconductor (DMOS) device ;
  • Figure 2 illustrates an exemplary DMOS device consistent with the disclosed embodiments.
  • Figure 1 shows a conventional double-diffusion metal-oxide-semiconductor (DMOS) device.
  • the conventional DMOS device includes a source metal layer 01 and a gate metal layer 02. Because the source metal layer 01 and the gate metal layer 02 appear similarly, it may be difficult to distinguish the source metal layer 01 and the gate metal layer 02 during a packaging process.
  • notches may be defined between the source metal layer 01 and the gate metal layer 02 or the distance between the source metal layer 01 and the gate metal layer 02 may be increased so that it may become less difficult to distinguish the source metal layer 01 and the gate metal layer 02 during the packaging process .
  • FIG. 2 illustrates an exemplary DMOS device 100 consistent with the disclosed embodiments.
  • the DMOS device 100 may include a substrate (not shown) and may also include a source region, a gate region, and a drain region (not shown) on the substrate. Further, as shown in Figure 2, DMOS device 100 includes a source metal layer 101 positioned on the source region and a gate metal layer 102 positioned on the gate region . Other structures may also be included.
  • the metal layer 101 and the gate metal layer 102 one or a plurality of metal layers are formed on the source region and the gate region.
  • the metal layer may be made of a conductor metal, such as tungsten, titanium, aluminum, copper, and aluminum-copper alloy, etc.
  • the metal layer may include a plurality of metal films, such as titanium film, aluminum-copper alloy film, or titanium nitride serving as anti-reflection layer. Other arrangements may also be used.
  • a photoresist layer may be coated on the metal layer, and a source pattern and a gate pattern may be formed in the photoresist layer using photolithography, such as performing exposure and development processes on the photoresist layer.
  • the source pattern and the gate pattern (i.e., the photoresist pattern) may be designed to implement multiple functionalities. For example, at first, the source pattern may be designed to define an area and shape of the source metal layer 101 as positioned on the source region, and the gate pattern may be designed to define an area and shape of the gate metal layer 102 as positioned on the gate region.
  • the metal layer located outside the source pattern and the gate pattern is removed by plasma etching or other etching method using the source pattern and the gate pattern as a mask to form the source metal layer 101 and the gate metal layer 102, respectively .
  • the source pattern may be designed to define a surface pattern of the source metal layer 101
  • the gate pattern may be designed to define a surface pattern of the gate metal layer 102.
  • the source pattern is different from the gate pattern such that the surface pattern of the source metal layer 101 and the surface pattern of the gate metal layer 102 are substantially different so that the source metal layer 101 and the gate metal layer 102 can be distinguished from each other by packaging equipment .
  • the surface pattern of the gate metal layer 101 is the same as the gate pattern in the photoresist layer through the etching process
  • the surface pattern of the source metal layer 102 is the same as the source pattern in the photoresist layer, and the source pattern is different from the gate pattern in the photoresist layer
  • the surface pattern of the source metal layer 101 is different from the surface pattern of the gate metal layer 102 .
  • the surface pattern (or simply the pattern) of the source metal layer 101 or the gate metal layer 102 may refer to a shape, size, texture, structure, and/or geometrical pattern, etc., of the source metal layer 101 and the gate metal layer 102. Other characteristics may also be included.
  • the pattern of the source metal layer 101 is made different from that of the gate metal layer 102.
  • the pattern of the source metal layer 101 and the pattern of the gate metal layer 102 are different such that the source metal layer 101 and the gate metal layer 102 can be distinguished by packaging equipment based on the different patterns.
  • Any appropriate patterns may be used for the source metal layer 101 and the gate metal layer 102.
  • the pattern of the source metal layer 101 or the gate metal layer 102 can be consisted of a plurality of circles, a plurality of ovals, and/or a plurality of rectangles.
  • the pattern of the source metal layer 101 or the gate metal layer 102 can also be consisted of a plurality of regular polygons or a plurality of irregular polygons. Further, the pattern of the source metal layer 101 or the gate metal layer 102 can be consisted of a plurality of lines and/or dots, and the lines may be arc, straight, and/or curve lines.
  • the pattern of the source metal layer 101 or the gate metal layer 102 may be consisted of identical patterns or lines, or may be consisted of different patterns or lines.
  • the pattern of the source metal layer 101 may be consisted of a plurality of circles, while the pattern of the gate metal layer 102 may be consisted of a plurality of cubes and triangles.
  • the pattern of the source metal layer 101 may be consisted of a plurality of rectangles, while the pattern of the gate metal layer 102 may be consisted of a plurality of ovals.
  • Other patterns or lines may also be used so long as the patterns of the source metal layer 101 and the gate metal layer 102 can be distinguished by the packaging equipment.
  • a dielectric layer may be positioned between the metal layer and the source region, the gate region, and the drain region.
  • the dielectric layer may include a plurality of through holes for contacting the source region, the gate region, and the drain region by the metal layers.
  • a gate oxide layer may be positioned between the gate region and the gate metal layer 102. Based on the electric requirements of the DMOS device, the thickness of the gate oxide layer may be greater than that of conventional semiconductor device.
  • a drain metal layer (not shown) may also be formed on the drain region.
  • the source metal layer 101 may have a color different from the color of the gate metal layer 102 , such that during the subsequent package processes, the packaging equipment can distinguish the source metal layer 101 from the gate metal layer 102 based on the different color of the source metal layer 101 and the gate metal layer 102.
  • the source metal layer 101 and the gate metal layer 102 can be distinguished by the packaging equipment based on both the different patterns and the different colors of the source metal layer 101 and the gate metal layer 102 . Other features may also be used.
  • the DMOS device 100 may be a vertical double-diffusion MOS (VDMOS) device or a lateral double-diffusion MOS (LDMOS) device. Based on the particular type of device (VDMOS or LDMOS), different patterns may be used for the source metal layer 101 and the gate metal layer 102 of the DMOS device 100.
  • VDMOS vertical double-diffusion MOS
  • LDMOS lateral double-diffusion MOS
  • the DMOS device 100 is an LDMOS device
  • the source electrode, the gate electrode, and the drain electrode are led out from an upper surface of the DMOS device 100 so as to integrate the DMOS device with other devices.
  • the source region is self-aligned and the gate metal layer 102 is departed from the drain region to reduce the input and feedback capacitance and to alleviate the short-channel effect.
  • the LDMOS device 100 forms the channel by co-diffusion of the source region and a trap area surrounding the source region. Further, the LDMOS device 100 has a threshold voltage close to that of an ordinary MOS transistor, and the LDMOS device 100 may be used in high-voltage power circuits.
  • a drift region (not shown) may be positioned between the source region and the drain region.
  • the drift region may have a low concentration of the impurity such that, when a high voltage is applied to the LDMOS device 100, the drift region is in a high impedance state.
  • the LDMOS device 100 can sustain the high voltage from the drain end.
  • the VDMOS device 100 when the DMOS device 100 is a VDMOS device, the VDMOS device 100 may have an epitaxial layer (not shown) formed on a back side of the silicon substrate (not shown) of the VDMOS device 100. The current flowing along the channel may change to a vertical direction and flow towards the substrate. Accordingly, the drain electrode of the VDMOS device 100 is led out from the bottom side of the silicon substrate, and the source electrode and the drain electrode are positioned on a front side of the silicon substrate to improve the integrity. Compared with a bipolar transistor, the VDMOS device 100 may have a high switching speed, low switching loss, high input resistance, low driving power, and negative temperature coefficient, and is less likely to have a second breakdown. Thus, the VDMOS device 100 may be a desired power device for switching or linear applications.
  • the DMOS device 100 may be an N-channel double-diffusion MOS (N-channel DMOS) device or a P- channel double-diffusion MOS (P-channel DMOS) device according to the types of carriers in the channel of the device. Based on the particular type of device (the N-channel DMOS device and the P-channel DMOS device), different patterns may be used for the source metal layer 101 and the gate metal layer 102 of the DMOS device 100.
  • N-channel DMOS N-channel double-diffusion MOS
  • P-channel DMOS P-channel double-diffusion MOS
  • the substrate of the N-channel DMOS device 100 is an N - type material.
  • a P-type diffusion may be performed on a special region of the substrate to form a P-type region using a corresponding mask, and an N+ diffusion may be performed using the same mask.
  • the lateral length of the P-type region is then the length of the channel. Further, if the lateral diffusion depth is the same as the vertical diffusion depth, the length of the channel can be controlled within 1 ⁇ m. Since the N - layer can sustain a high base voltage and have a low feedback capacitance, an improved characteristic of the DMOS device 100 can be achieved.
  • the P-channel DMOS device may have a similar structure to the N-channel DMOS device described above, and the difference lies in the opposite doping carrier type.
  • the pattern of the source metal layer of the DMOS device is made different from the pattern of the gate metal layer of the DMOS device.
  • the packaging equipment can distinguish the source metal layer from the gate metal layer according to their different patterns. In such a manner, it may be unnecessary to increase the distance between the source metal layer and the gate metal layer. Thus, the area of the DMOS device may be reduced to achieve lower cost and improved performance.
  • the current processes of fabricating the DMOS device do not have to be changed to add any special process to identify the source metal layer and the gate metal layer.
  • the pattern of the source metal layer of the L DMOS device or the VDMOS device is made different from that of the gate metal layer of the L DMOS device or the VDMOS device.
  • the packaging equipment thus can distinguish the source metal layer from the gate metal layer according to their different patterns during packaging processes without employing any special process to identify the source metal layer and the gate metal layer.
  • the pattern of the source metal layer of the N-channel DMOS device or the P-channel DMOS device is made different from that of the gate metal layer of the N-channel DMOS device or the P-channel DMOS device.
  • packaging equipment can distinguish the source metal layer from the gate metal layer according to their different patterns during packaging processes without employing any special process to identify the source metal layer and the gate metal layer.

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Abstract

A double-diffusion metal-oxide semiconductor (DMOS) device (100) is disclosed. The DMOS device (100) includes a substrate, a source region on the substrate, a gate region on the substrate, and a drain region on the substrate. The DMOS device (100) also includes a source metal layer (101) positioned on the source region and a gate metal layer (102) positioned on the gate region. The source metal layer (101) has a first pattern, the gate metal layer (102) has a second pattern, and the first pattern is different from the second pattern such that the source metal layer (101) can be distinguished from the gate metal layer (102) by packaging equipment based on the different first pattern and second pattern.

Description

DOUBLE-DIFFUSION METAL-OXIDE SEMICONDUCTOR DEVICES
FIELD OF THE INVENTION
The present invention generally relates to the field of semiconductor manufacturing and, more particularly, to the metal-oxide semiconductor technologies.
BACKGROUND
A double-diffusion metal-oxide-semiconductor (DMOS) device has a structure similar to that of a CMOS device, which includes a source electrode, a gate electrode, and a drain electrode. The DMOS devices are often divided into VDMOS (vertical double-diffusion MOS) devices and LDMOS (lateral double-diffusion MOS) devices. The DMOS devices are often designed for applications with large currents and high voltages, and a DMOS device usually has an excellent thermal stability, frequency stability, high gain, high durability, low noise, low feedback capacitance, constant input impedance, and simple bias circuit.
A conventional method for fabricating a DMOS device often includes a packaging process. Because the source metal layer of the DMOS device is often positioned close to the gate metal layer of the DMOS device and these two metal layers appear identical, a problem can occur in the packaging process as it is difficult to distinguish these two metal layers. To address this problem, the conventional method may define a notch between the source metal layer and the gate metal layer or may increase the distance between the source metal layer and the gate metal layer, such that the packaging equipment can distinguish the source metal layer from the gate metal layer during the packaging process.
However, such approach may have certain disadvantages. For example, if the distance between the source metal layer and the gate metal layer is not large enough, the packaging equipment may be unable to distinguish the source metal layer from the gate metal layer. If the distance is increased or the notch is used, the area of the DMOS device may also become large, which may cause additional cost and poor electricity distribution.
The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.
BRIEF SUMMARY OF THE DISCLOSURE
One aspect of the present disclosure includes a double-diffusion metal-oxide semiconductor (DMOS) device. The DMOS device includes a substrate, a source region on the substrate, a gate region on the substrate, and a drain region on the substrate. The DMOS device also includes a source metal layer positioned on the source region and a gate metal layer positioned on the gate region. The source metal layer has a first pattern, the gate metal layer has a second pattern, and the first pattern is different from the second pattern such that the source metal layer can be distinguished from the gate metal layer by packaging equipment based on the different first pattern and second pattern.
Another aspect of the present disclosure includes a double-diffusion metal-oxide semiconductor (DMOS) device. The DMOS device a substrate, a source region on the substrate, a gate region on the substrate, and a drain region on the substrate. The DMOS device also includes a source metal layer positioned on the source region and a gate metal layer positioned on the gate region. The source metal layer has a first color, the gate metal layer has a second color, and the first color is different from the second color such that the source metal layer can be distinguished from the gate metal layer by packaging equipment based on the different first color and second color.
Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows a conventional double-diffusion metal-oxide-semiconductor (DMOS) device ; and
Figure 2 illustrates an exemplary DMOS device consistent with the disclosed embodiments.
DETAILED DESCRIPTION
Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
Figure 1 shows a conventional double-diffusion metal-oxide-semiconductor (DMOS) device. As shown in Figure 1, the conventional DMOS device includes a source metal layer 01 and a gate metal layer 02. Because the source metal layer 01 and the gate metal layer 02 appear similarly, it may be difficult to distinguish the source metal layer 01 and the gate metal layer 02 during a packaging process. Thus, in the DMOS device shown in Figure 1, notches (not shown) may be defined between the source metal layer 01 and the gate metal layer 02 or the distance between the source metal layer 01 and the gate metal layer 02 may be increased so that it may become less difficult to distinguish the source metal layer 01 and the gate metal layer 02 during the packaging process .
Figure 2 illustrates an exemplary DMOS device 100 consistent with the disclosed embodiments. The DMOS device 100 may include a substrate (not shown) and may also include a source region, a gate region, and a drain region (not shown) on the substrate. Further, as shown in Figure 2, DMOS device 100 includes a source metal layer 101 positioned on the source region and a gate metal layer 102 positioned on the gate region . Other structures may also be included.
To form the source metal layer 101 and the gate metal layer 102, one or a plurality of metal layers are formed on the source region and the gate region. The metal layer may be made of a conductor metal, such as tungsten, titanium, aluminum, copper, and aluminum-copper alloy, etc. The metal layer may include a plurality of metal films, such as titanium film, aluminum-copper alloy film, or titanium nitride serving as anti-reflection layer. Other arrangements may also be used.
After forming the metal layer(s), a photoresist layer may be coated on the metal layer, and a source pattern and a gate pattern may be formed in the photoresist layer using photolithography, such as performing exposure and development processes on the photoresist layer. The source pattern and the gate pattern (i.e., the photoresist pattern) may be designed to implement multiple functionalities. For example, at first, the source pattern may be designed to define an area and shape of the source metal layer 101 as positioned on the source region, and the gate pattern may be designed to define an area and shape of the gate metal layer 102 as positioned on the gate region. In this respect, after forming the source pattern and the gate pattern, the metal layer located outside the source pattern and the gate pattern is removed by plasma etching or other etching method using the source pattern and the gate pattern as a mask to form the source metal layer 101 and the gate metal layer 102, respectively .
Further, the source pattern may be designed to define a surface pattern of the source metal layer 101, and the gate pattern may be designed to define a surface pattern of the gate metal layer 102. In certain embodiments, the source pattern is different from the gate pattern such that the surface pattern of the source metal layer 101 and the surface pattern of the gate metal layer 102 are substantially different so that the source metal layer 101 and the gate metal layer 102 can be distinguished from each other by packaging equipment . That is, because the surface pattern of the gate metal layer 101 is the same as the gate pattern in the photoresist layer through the etching process, the surface pattern of the source metal layer 102 is the same as the source pattern in the photoresist layer, and the source pattern is different from the gate pattern in the photoresist layer, the surface pattern of the source metal layer 101 is different from the surface pattern of the gate metal layer 102 .
The surface pattern (or simply the pattern) of the source metal layer 101 or the gate metal layer 102, as used herein, may refer to a shape, size, texture, structure, and/or geometrical pattern, etc., of the source metal layer 101 and the gate metal layer 102. Other characteristics may also be included.
Thus, to distinguish the source metal layer 101 from the gate metal layer 102, the pattern of the source metal layer 101 is made different from that of the gate metal layer 102. In other words, the pattern of the source metal layer 101 and the pattern of the gate metal layer 102 are different such that the source metal layer 101 and the gate metal layer 102 can be distinguished by packaging equipment based on the different patterns. Any appropriate patterns may be used for the source metal layer 101 and the gate metal layer 102. For example, the pattern of the source metal layer 101 or the gate metal layer 102 can be consisted of a plurality of circles, a plurality of ovals, and/or a plurality of rectangles. The pattern of the source metal layer 101 or the gate metal layer 102 can also be consisted of a plurality of regular polygons or a plurality of irregular polygons. Further, the pattern of the source metal layer 101 or the gate metal layer 102 can be consisted of a plurality of lines and/or dots, and the lines may be arc, straight, and/or curve lines.
The pattern of the source metal layer 101 or the gate metal layer 102 may be consisted of identical patterns or lines, or may be consisted of different patterns or lines. For example, the pattern of the source metal layer 101 may be consisted of a plurality of circles, while the pattern of the gate metal layer 102 may be consisted of a plurality of cubes and triangles. Also, the pattern of the source metal layer 101 may be consisted of a plurality of rectangles, while the pattern of the gate metal layer 102 may be consisted of a plurality of ovals. Other patterns or lines may also be used so long as the patterns of the source metal layer 101 and the gate metal layer 102 can be distinguished by the packaging equipment.
Further, in a DMOS device consisted by a plurality of DMOS cells, a dielectric layer may be positioned between the metal layer and the source region, the gate region, and the drain region. The dielectric layer may include a plurality of through holes for contacting the source region, the gate region, and the drain region by the metal layers. In addition, a gate oxide layer may be positioned between the gate region and the gate metal layer 102. Based on the electric requirements of the DMOS device, the thickness of the gate oxide layer may be greater than that of conventional semiconductor device. Furthermore, a drain metal layer (not shown) may also be formed on the drain region.
Additionally or alternatively, in DMOS device 100, the source metal layer 101 may have a color different from the color of the gate metal layer 102 , such that during the subsequent package processes, the packaging equipment can distinguish the source metal layer 101 from the gate metal layer 102 based on the different color of the source metal layer 101 and the gate metal layer 102. In certain embodiments, the source metal layer 101 and the gate metal layer 102 can be distinguished by the packaging equipment based on both the different patterns and the different colors of the source metal layer 101 and the gate metal layer 102 . Other features may also be used.
The DMOS device 100 may be a vertical double-diffusion MOS (VDMOS) device or a lateral double-diffusion MOS (LDMOS) device. Based on the particular type of device (VDMOS or LDMOS), different patterns may be used for the source metal layer 101 and the gate metal layer 102 of the DMOS device 100.
When the DMOS device 100 is an LDMOS device, in the planar-structured LDMOS device, the source electrode, the gate electrode, and the drain electrode are led out from an upper surface of the DMOS device 100 so as to integrate the DMOS device with other devices. The source region is self-aligned and the gate metal layer 102 is departed from the drain region to reduce the input and feedback capacitance and to alleviate the short-channel effect. The LDMOS device 100 forms the channel by co-diffusion of the source region and a trap area surrounding the source region. Further, the LDMOS device 100 has a threshold voltage close to that of an ordinary MOS transistor, and the LDMOS device 100 may be used in high-voltage power circuits.
In addition, in the LDMOS device 100, a drift region (not shown) may be positioned between the source region and the drain region. The drift region may have a low concentration of the impurity such that, when a high voltage is applied to the LDMOS device 100, the drift region is in a high impedance state. Thus, the LDMOS device 100 can sustain the high voltage from the drain end.
On the other hand, when the DMOS device 100 is a VDMOS device, the VDMOS device 100 may have an epitaxial layer (not shown) formed on a back side of the silicon substrate (not shown) of the VDMOS device 100. The current flowing along the channel may change to a vertical direction and flow towards the substrate. Accordingly, the drain electrode of the VDMOS device 100 is led out from the bottom side of the silicon substrate, and the source electrode and the drain electrode are positioned on a front side of the silicon substrate to improve the integrity. Compared with a bipolar transistor, the VDMOS device 100 may have a high switching speed, low switching loss, high input resistance, low driving power, and negative temperature coefficient, and is less likely to have a second breakdown. Thus, the VDMOS device 100 may be a desired power device for switching or linear applications.
Further, the DMOS device 100 may be an N-channel double-diffusion MOS (N-channel DMOS) device or a P- channel double-diffusion MOS (P-channel DMOS) device according to the types of carriers in the channel of the device. Based on the particular type of device (the N-channel DMOS device and the P-channel DMOS device), different patterns may be used for the source metal layer 101 and the gate metal layer 102 of the DMOS device 100.
When the DMOS device 100 is an N-channel DMOS device, the substrate of the N-channel DMOS device 100 is an N- type material. To form the source region and the drain region of the N-channel DMOS device 100, a P-type diffusion may be performed on a special region of the substrate to form a P-type region using a corresponding mask, and an N+ diffusion may be performed using the same mask. The lateral length of the P-type region is then the length of the channel. Further, if the lateral diffusion depth is the same as the vertical diffusion depth, the length of the channel can be controlled within 1μm. Since the N- layer can sustain a high base voltage and have a low feedback capacitance, an improved characteristic of the DMOS device 100 can be achieved.
When the DMOS device 100 is a P-channel DMOS device, the P-channel DMOS device may have a similar structure to the N-channel DMOS device described above, and the difference lies in the opposite doping carrier type.
Therefore, by using the disclosed methods and devices, the pattern of the source metal layer of the DMOS device is made different from the pattern of the gate metal layer of the DMOS device. Thus, during packaging processes, the packaging equipment can distinguish the source metal layer from the gate metal layer according to their different patterns. In such a manner, it may be unnecessary to increase the distance between the source metal layer and the gate metal layer. Thus, the area of the DMOS device may be reduced to achieve lower cost and improved performance. In addition, the current processes of fabricating the DMOS device do not have to be changed to add any special process to identify the source metal layer and the gate metal layer.
Whether the DMOS device is an LDMOS device or a VDMOS device, the pattern of the source metal layer of the L DMOS device or the VDMOS device is made different from that of the gate metal layer of the L DMOS device or the VDMOS device. The packaging equipment thus can distinguish the source metal layer from the gate metal layer according to their different patterns during packaging processes without employing any special process to identify the source metal layer and the gate metal layer.
Further, whether the DMOS device is an N-channel DMOS device or a P-channel DMOS device, the pattern of the source metal layer of the N-channel DMOS device or the P-channel DMOS device is made different from that of the gate metal layer of the N-channel DMOS device or the P-channel DMOS device. Thus, packaging equipment can distinguish the source metal layer from the gate metal layer according to their different patterns during packaging processes without employing any special process to identify the source metal layer and the gate metal layer.
It is understood that the disclosed embodiments may be applied to any appropriate semiconductor device manufacturing processes. Various alternations, modifications, or equivalents to the technical solutions of the disclosed embodiments can be obvious to those skilled in the art.

Claims (11)

  1. A double-diffusion metal-oxide semiconductor (DMOS) device, comprising:
    a substrate;
    a source region on the substrate;
    a gate region on the substrate;
    a drain region on the substrate;
    a source metal layer positioned on the source region; and
    a gate metal layer positioned on the gate region,
    wherein:
    the source metal layer has a first pattern;
    the gate metal layer has a second pattern; and
    the first pattern is different from the second pattern such that the source metal layer can be distinguished from the gate metal layer by packaging equipment based on the different first pattern and second pattern.
  2. The DMOS device according to claim 1, wherein:
    the source metal layer has a first color;
    the gate metal layer has a second color; and
    the first color is different from the second color such that the source metal layer can be distinguished from the gate metal layer by the packaging equipment based on the different first color and second color.
  3. The DMOS device according to claim 1, wherein:
    the first pattern and the second patter are different and from a plurality of circles, a plurality of ovals, and a plurality of rectangles.
  4. The DMOS device according to claim 1, wherein:
    the first pattern and the second patter are a plurality of regular polygons and a plurality of irregular polygons.
  5. The DMOS device according to claim 1, wherein:
    the first pattern and the second patter are a plurality of lines and a plurality of dots.
  6. The DMOS device according to claim 1, wherein:
    the DMOS device is a vertical double-diffusion metal-oxide semiconductor (VDMOS) device.
  7. The DMOS device according to claim 1, wherein:
    the DMOS device is a lateral double-diffusion metal-oxide semiconductor (LDMOS) device.
  8. The DMOS device according to claim 1, wherein:
    the DMOS device is an N-channel double-diffusion metal-oxide semiconductor (NDMOS) device.
  9. The DMOS device according to claim 1, wherein:
    the DMOS device is a P-channel double-diffusion metal-oxide semiconductor (PDMOS) device.
  10. A double-diffusion metal-oxide semiconductor (DMOS) device, comprising:
    a substrate;
    a source region on the substrate;
    a gate region on the substrate;
    a drain region on the substrate;
    a source metal layer positioned on the source region; and
    a gate metal layer positioned on the gate region,
    wherein:
    the source metal layer has a first color;
    the gate metal layer has a second color; and
    the first color is different from the second color such that the source metal layer can be distinguished from the gate metal layer by packaging equipment based on the different first color and second color.
  11. The DMOS device according to claim 10, wherein:
    the source metal layer has a first pattern;
    the gate metal layer has a second pattern; and
    the first pattern is different from the second pattern such that the source metal layer can be distinguished from the gate metal layer by packaging equipment based on the different first pattern and second pattern.
PCT/CN2011/083106 2010-12-22 2011-11-29 Double-diffusion metal-oxide semiconductor devices Ceased WO2012083783A1 (en)

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CN102569387A (en) 2012-07-11
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CN102569387B (en) 2014-08-27

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