WO2012071910A1

WO2012071910A1 - Method and device for achieving time synchronization

Info

Publication number: WO2012071910A1
Application number: PCT/CN2011/078863
Authority: WO
Inventors: 宋雪雁
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-12-02
Filing date: 2011-08-24
Publication date: 2012-06-07
Also published as: CN102013969A; CN102013969B

Abstract

Disclosed are a method and device for achieving time synchronization. The method includes: configuring a clock private address for the clock chip of a slave clock device; the clock chip regarding the clock private address as the address of the slave clock port of the slave clock device and performing message interaction with a master clock device using the address of the slave clock port when performing time synchronization. In the present invention, by way of configuring a clock private address on the clock chip and packaging the PTP message using the clock private address, frequent update of the port information on the clock chip caused by the switching of clock sources can be avoided, making the operation of the clock chip more stable and prolonging the service life of the clock chip.

Description

Method and device for realizing time synchronization

Technical field

The present invention relates to the field of communications technologies, and in particular, to a method and apparatus for implementing time synchronization.

Background technique

In Time Division-Synchronous Code Division Multiple Access (TD-SCDMA) mobile networks, not only clock synchronization but also frequency synchronization is required between base stations, and strict time synchronization and frequency and phase synchronization are required. . The most widely used time synchronization technology in the industry is IEEE1588 (Accurate Clock Synchronization Protocol). The basic function of IEEE1588 is to keep other clocks in the distributed network synchronized with the most accurate clock. It defines a Precision Time Protocol (PTP) for standard Ethernet and other multicast technologies. Sub-microsecond time synchronization of sensors in sensors, actuators, and other terminal devices in a distributed bus system.

The function of the protocol includes two aspects:

(1) Selecting the state of the port through the Best Master Clock Algorithm (BMC) to determine the topology of the entire network. First, determine the GM (Grandmaster) device in the network according to the PTP priority setting on the device. Then, determine the port role of the device in the network through the port state selection algorithm. The port election on the device is The slave device is the slave clock. The clock corresponding to the upstream master port directly connected to the slave is the master clock.

(2) Through the transmission and reception of PTP messages, the calculation of time offset check, etc., completes the time synchronization of the whole network, and guarantees the verification error.

The PTP message type used for the time offset check calculation mainly includes two types: event message and general message. The event message includes: Sync (synchronous message), Delay_Req (delay request message), Pdelay_Req (point-to-point delay request message) and Pdelay_Resp (point-to-point delay response message). Common message messages include: Announce (announce message), Follow-Up (艮艮 4艮), Delay Resp (delay response 4艮), Pdelay-Resp- Follow-Up (point The point delay response follows the message), Management (Management Message) and Signaling (Signal Message). The above event message message is mainly used to send and exchange common and edge clock information that needs to be synchronized, and uses a "delay request response mechanism". The general message is mainly used to measure the link delay between clock ports, using the "peer delay mechanism". Announce is used to enable synchronous layering. Management is used between the management node and the clock to query and upgrade the PTP data settings for clock maintenance. It can also be used to customize the PTP system and initialization and error management. Signaling is used to perform other purposes of interaction between clocks, such as negotiating unicast message rates.

The PTP packet encapsulation format supports IEEE802.13, IPV4, and IPV6. The encapsulation format of the IEEE802.13 protocol is Layer 2 packet encapsulation and is transmitted in Layer 2 multicast mode. In this kind of encapsulation, there is no requirement for the VLAN (Virtual Local Area Network) configuration of the device. When the message sent by the device is in Ethernet (Ethernet) format, no tag information is added. The IPV4 packet encapsulation format is encapsulated in Layer 3 packets, including Layer 3 unicast and Layer 3 multicast. The port of the device is required to be added to the Layer 3 PTP-enabled VLAN. If the Layer 3 unicast format is required, the Layer 3 routing between devices is required. If the Layer 3 multicast format is used, the device in the network is required. Multicast in the same VLAN.

At present, the time synchronization function can be realized by frequency recovery. When time synchronization is implemented, the clock source is required to recover the frequency of the clock source by means of the clock chip, and then the protocol message and the FPGA (field programmable gate array) loaded report are sent by the CPU. Time stamp to complete the time correction of the slave clock. Currently, for the implementation of Layer 3 unicast packets, the configuration of the PTP-enabled port (PTP port) needs to be written to the clock chip. The configuration of the port includes the source and destination IP address information of the ^^ message. The IP address information is used to encapsulate the packet.

Because the PTN (Packet Transport Network) device has a lot of port resources, there may be multiple PTP ports on one device according to the needs of the networking. When there are multiple devices in the network, and the clock source of the slave clock is protected. During the switching, when the clock source is switched, it is necessary to update the corresponding information stored in the clock chip by using the information of the changed clock source port, which may easily lead to unstable operation of the clock chip or due to repeated operation of the chip. The chip is necrotic or does not function properly. Summary of the invention

The technical problem to be solved by the present invention is to provide a method and device for realizing time synchronization, which solves Due to the repeated operation of the clock chip, the clock chip is unstable, easily necrotic or cannot operate normally.

In order to solve the above technical problem, a method for implementing time synchronization according to the present invention includes: configuring a clock dedicated address for a clock chip from a clock device; and performing time synchronization, using the address of the slave clock port with the master clock device. Intertextual interaction.

Optionally, the method further includes:

When the clock dedicated address is configured for the clock chip of the slave clock device, the master clock port on the master clock device is also configured with a destination address, and the master clock port is configured with a communication address, and the destination address is a clock-specific address.

Optionally, the method further includes:

After configuring the clock-specific address for the clock chip from the clock device, a communication route between the clock-specific address and the communication address of the master clock port is also established between the master clock device and the slave clock device.

Optionally, the step of establishing a communication route between the clock-specific address and the communication address of the master clock port includes:

Enable routing on the primary clock device to add the communication address configured for the primary clock port to the routing domain;

Routing is enabled on the slave clock device, a communication address is configured for the slave port of the slave clock device, and a clock private address and a communication address configured for the slave port of the slave clock device are added to the routing domain.

Optionally, the step of using the address of the slave clock port to perform packet interaction with the master clock device includes:

The master clock device constructs a first packet, and the destination address of the first packet is an address of the slave clock port, and the source address of the first packet is a communication address of the master clock port, and the first packet is sent according to the communication route. Slave clock device

After receiving the first packet from the clock chip of the clock device, constructing a second packet, where the source address of the second packet is the address of the slave clock port, and the destination address of the second packet is the communication site of the master clock port. The address, according to the communication route, sends the second message to the master clock device.

Optionally, the communication address configured for the primary clock port and the communication address configured for the slave clock device are the virtual local area network interface addresses of the virtual local area network added on the port.

Optionally, the master clock device is a grandfather clock device.

A device for implementing time synchronization, comprising: a configuration module and a clock chip, wherein: the configuration module is configured to: configure a clock dedicated address for the clock chip;

The clock chip is set to: use the clock private address as the address of the slave clock port on the slave clock device. When time synchronization is performed, the address of the slave clock port is used to communicate with the master clock device.

Optionally, the configuration module is further configured to: configure a message address of the primary clock port on the primary clock device, and configure a communication address for the primary clock port, where the destination address of the packet is a clock-specific address.

Optionally, the device further includes a routing processing module, where:

The configuration module is further configured to: add a clock private address, a communication address of the communication port of the slave clock device, and a communication address of the master clock port to the routing processing module;

The routing processing module is configured to: establish a communication route between the clock-specific address and the communication address of the primary clock port.

Optionally, the clock chip is configured to perform message exchange with the primary clock device by using the address of the slave clock port as follows:

Receiving a first packet sent by the master clock device, and constructing a second packet, where the source address of the second packet is an address of the slave clock port, and the destination address of the second packet is a communication address of the master clock port, The second packet is sent to the routing processing module;

The routing processing module is further configured to: send the second packet to the primary clock device according to the communication route;

The destination address of the first text is the address of the slave clock port, and the source address of the first text is the communication address of the master clock port.

Optionally, the master clock device is a grandfather clock device.

In summary, by setting a clock-specific address on the clock chip, the clock is dedicated. The address encapsulates the PTP packet to avoid frequent update of the port information on the clock chip caused by the switching of the clock source, which makes the clock chip work more stable and can prolong the service life of the clock chip. BRIEF abstract

1 is a networking model diagram of a method for implementing time synchronization according to an embodiment of the present invention;

2 is an architectural diagram of an apparatus for implementing time synchronization according to an embodiment of the present invention;

FIG. 3 is a flowchart of a configuration flow in a method for implementing time synchronization according to an embodiment of the present invention; FIG. 4 is a flowchart of text interaction in a method for implementing time synchronization according to an embodiment of the present invention.

Preferred embodiment of the invention

The networking model involved in this embodiment is shown in Figure 1. The active primary clock device and the standby primary clock device exist in the networking. The active and standby devices may be the same source or different sources. Perform clock synchronization. In order to avoid the restart or crash of the primary master clock device, or because the link between the slave clock (SLAVE) device and the master master clock device is broken, the slave clock device can synchronize with the time of the standby master clock device. Ensure a stable switch of the time source. In the present embodiment, the soil 1 "clock set - ready" is considered to be the i parent clock device.

In this embodiment, by configuring a clock dedicated address for the clock chip of the slave clock device, when the message is encapsulated, the clock private address is used as the address of the slave clock port to avoid the address change of the slave clock port caused by the master clock device switching. When the clock chip configuration is modified, the repeated operation of the clock chip is performed.

Referring to Figure 1, the slave clock device has two communication ports P1 and P2. When the master clock device is used for time synchronization of the slave clock device, P1 is the slave clock port, and when the slave master clock device is used, the slave clock is used. When the device synchronizes time, P2 is the slave clock port. In the prior art, when the primary and backup master clock devices are switched, the configuration of the slave clock port for packet exchange is changed, and the clock chip needs to be updated from the clock port configuration, and the clock chip is repeatedly operated, resulting in a clock. The chip works unstable. In this embodiment, the configured clock private address is used as the address of the slave clock port. Frequent operation of the clock chip due to switching of the primary and backup master clock devices is avoided. To implement the method in this embodiment, the following configuration process is required, including:

(1) The primary clock port on the primary clock device is configured with the destination address and communication address required for PTP packet encapsulation;

As shown in Figure 1, the destination address of the PTP packet is specified on the primary clock port P11 of the master clock device. The destination address of the packet is the clock-specific address of the slave clock device. At the same time, the VLAN for PTP routing communication needs to be added to the P11 port, and the VLAN interface address is Ipl.

The clock-specific address Zipl can also be configured for the master clock device. The clock-specific address of the master clock device is used to time synchronize the time-switched slave clock device when the master clock device and the slave clock device have a role change.

(2) Configure the clock-specific address required for PTP packet encapsulation from the clock device. As shown in Figure 1, configure the clock-specific address Zip2 for the clock chip on the slave clock device. At the same time, you need to configure the P1 and P2 ports. The VLAN used for PTP routing communication is configured with the IP address of the P2 port as Ip2, and the VLAN interface address of the PI port is Ip3. Ip2 and Ip3 are required to be on the same network segment. The IP addresses configured for P1 and P2 are used to form a Layer 3 unicast communication route.

In the process of implementing the time synchronization in the embodiment, the master clock device and the slave clock device need to communicate with the PTP protocol packet. The clock nodes in the networking use the E2E delay mechanism to describe the communication process of the packet. Includes:

Step 1: The primary master clock device sends a Sync message to the SLAVE device, and the Sync message is encapsulated in a format of three layers of unicast packets. The destination address of the layer 3 unicast message is the clock dedicated address Zip2 configured on the SLAVE device. The address is Ip 1;

Step 2: After receiving the Sync message sent by the active primary clock device, the SLAVE device sends a Delay_request message to the active primary clock device, and the Delay-request message is encapsulated in a format of the Layer 3 unicast message. The destination address of the Layer 3 unicast packet is Ipl and the source address is Zip2.

Step 3: After receiving the Delay_request message, the active primary clock device replies to the Delay- response message to the SLAVE device, and the Delay-response message is encapsulated in the format of the Layer 3 unicast message. The destination address of the Layer 3 unicast message is Zip2, and the source address is Ipl.

The routing processing steps performed by the broadcast communication include:

Step 1: Enable ospf (that is, open shortest path first) routing on the primary clock device, and add the Zipl network segment and the network segment Ipl to the ospf routing domain.

Step 2: Enable ospf routing on the SLAVE device, and add the network segment Zip2 and the network segments Ip2 and Ip3 to the ospf routing domain, thereby establishing a communication route between the clock dedicated address and the port communication address on the primary clock device and the SLAVE device, Communicate through the communication route;

The ospf route here can also be implemented by using an isis (Intermediate System-Intermediate System) route or a static route. After the routing configuration is complete on the clock device, the subnet routing table and host routing table are generated on the device. When the primary clock device and the SLAVE device send packets, the outbound routing table and the host routing table generated on the clock device are used to find the outbound interface. The outgoing interface of the primary master clock device is the P11 port. The outgoing interface of the route discovered by the SLAVE device is the P1 port.

In this embodiment, a PTP packet is encapsulated by configuring a clock dedicated address on a clock chip to avoid repeated operations on the clock chip caused by frequent switching of the master clock device, and a device for implementing the method is also proposed. As shown in FIG. 2, the method includes: a configuration module, a clock chip processing module, and a routing processing module, where:

The configuration module is configured to: configure a clock private address on the SLAVE device and a clock private address on the primary clock device, configure a PTP text encapsulation address and a communication address on the primary clock device, and add PTP routing communication VLAN, configuring the VLAN interface address, adding the PTP routing communication VLAN to the SLAVE device, and configuring the VLAN interface address. Add the network segment Zipl and the network segment Ipl to the ospf routing domain on the routing processing module on the primary clock device. Adding the network segment Zip2 and the network segments Ip2 and Ip3 to the ospf routing domain on the routing processing module on the SLAVE device, thereby establishing a communication route between the clock dedicated address and the port communication address on the primary clock device and the SLAVE device, to pass The communication route communicates. The clock chip is set to: use the clock private address as the address of the slave clock port on the slave clock device, and use the clock private address to exchange packets with the master clock device, and receive the message sent by the master clock device (first report) After the message, the returned message (the second message) is constructed, and the source address of the second packet is the address of the slave clock port, and the destination address is the communication address of the master clock port, and the second packet is sent to the route. Processing module

The routing processing module is configured to: enable routings such as ospf and Isls, and establish a communication route between the clock-specific address and the communication address of the primary clock port, and implement the function of searching for the outgoing port of the PTP protocol packet to the PTP packet. The text is sent.

As shown in Figure 3, the configuration module mainly completes the configuration of the PTP interface and protocol, the configuration of the clock-specific address, and the configuration of the communication route, including:

Step 301: Perform PTP interface and PTP protocol-related configuration, add a PTP interface, and perform PTP protocol configuration on the interface.

Step 302, performing clock IP address configuration of the clock chip;

Step 303, adding force to the PTP interface. VLAN, and configure the VLAN interface address;

Step 304: Configure a destination address and a communication address of the primary clock port on the primary clock device, and the destination address of the packet is a clock dedicated address of the SLAVE device.

Step 305: Perform routing configuration to ensure that the routing between the VLAN interface address and the clock private address of the primary clock device and the SLAVE slave clock device is open.

After the configuration of the configuration module is complete, the BMC algorithm performs the PTP port status selection and the 1588 time synchronization function. The time synchronization implementation process is as shown in Figure 4, including:

Step 401: The PTP port of the clock device sends an announce message, and calculates a state of the PTP port by using a BMC algorithm.

Step 402, the clock device determines the PTP packet transmission on the port according to the judgment of the state of the PTP port. If the PTP port status is master (main), go to step 403; otherwise, go to step 406; Step 403: The master port sends a Sync message, and the Sync message uses a format of a Layer 3 unicast message. The destination address of the Layer 3 unicast message is encapsulated into a clock-specific address configured on the SLAVE device, and the source address is encapsulated as a PTP interface. IP address of the VLAN;

Step 404: The master port receives the Delay-req packet sent by the slave port.

In step 405, the master port replies to the slave port to the slave port, and ends. Step 406: The non-master port receives the Sync message from the master port, and determines whether the port status is a slave. If yes, go to step 408, if not Go to step 407;

Step 407: If the port is not a slave port, the port is in a passive state, and the passive port only receives the PTP protocol packet but does not send any PTP packet, and ends;

Step 408: The slave port sends a Delay-request message, and the Delay-request message uses a format of a Layer 3 unicast message. The destination address of the Layer 3 unicast message is the source IP address of the Sync message, and the source address is slave. The clock-specific address configured by the clock device where the port is located;

Step 409: After receiving the Delay-response packet from the master, the slave port extracts the timestamp of the packet, completes the check of the slave port, and completes time synchronization with the master.

Obviously, those skilled in the art should understand that the above modules and steps can be implemented by using a general-purpose computing device, which can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. They may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device, or they may be fabricated into individual integrated circuit modules, or multiple modules thereof or The steps are made into a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.

The above is only the embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. All modifications, equivalents, improvements, etc., made within the spirit and scope of the invention are intended to be included within the scope of the invention.

Industrial applicability

The above embodiment adopts a clock dedicated address on the clock chip, and uses the clock The PTP packet is encapsulated by the address to avoid frequent update of the port information on the clock chip caused by the switching of the clock source, which makes the clock chip work more stable and can prolong the service life of the clock chip.

Claims

Claim

1. A method for implementing time synchronization, comprising:

Configuring a clock-specific address for the clock chip from the clock device;

The address of the slave clock port is used to exchange messages with the master clock device during time synchronization.

2. The method of claim 1 further comprising:

When the clock-specific address is configured from the clock chip of the clock device, the master clock port on the master clock device is configured with a text address, and the master clock port is configured with a communication address. The address is the clock dedicated address.

3. The method of claim 2, further comprising:

After the clock-specific address is configured from the clock chip of the clock device, a communication route between the clock-specific address and the communication address of the master clock port is also established on the master clock device and the slave clock device.

4. The method of claim 3, wherein the step of establishing a communication route between the clock-specific address and the communication address of the master clock port comprises:

Enabling routing on the primary clock device to add a communication address configured for the primary clock port to the routing domain;

Routing is enabled on the slave clock device, a communication address is configured for the communication port of the slave clock device, and the clock private address and the communication address configured for the communication port of the slave clock device are added to the routing domain.

The method of claim 3, wherein the step of interacting with the master clock port by using the address of the slave clock port comprises:

The master clock device constructs a first packet, the destination address of the first packet is an address of the slave clock port, and the source address of the first packet is a communication address of the master clock port, Sending the first packet to the slave clock device according to the communication route; After receiving the first packet from the clock chip of the clock device, constructing a second packet, where a source address of the second text is an address of the slave clock port, and a destination address of the second packet Sending, by the communication address of the primary clock port, the second packet to the primary clock device according to the communication route.

6. The method of claim 4, wherein

The communication address configured for the primary clock port and the communication address configured for the communication port of the slave clock device are virtual local area network interface addresses of a virtual local area network added on the port.

7. The method of claims 1-6, wherein the master clock device is a grandfather clock device.

8. The device for implementing time synchronization, comprising: a configuration module and a clock chip, wherein: the configuration module is configured to: configure a clock-specific address for the clock chip; and address the port, when performing time synchronization, use the The address of the slave clock port interacts with the master clock device.

9. Apparatus according to claim 8 wherein:

The configuration module is further configured to: configure an address of a message for the master clock port on the master clock device, and configure a communication address for the master clock port, where the destination address is the clock-specific address.

10. The apparatus of claim 9, further comprising a routing processing module, wherein: the configuration module is further configured to:: the clock dedicated address, a communication address of a communication port of the slave clock device, and the The communication address of the master clock port is added to the route processing module; the route processing module is configured to: establish a communication route between the clock-specific address and the communication address of the master clock port.

11. The apparatus according to claim 9, wherein the clock chip is configured to perform message exchange with the master clock device by using an address of the slave clock port as follows:

Receiving a first packet sent by the master clock device, and constructing a second packet, where a source address of the second packet is an address of the slave clock port, and a destination address of the second packet is the master clock Port a communication address, the second packet is sent to the routing processing module;

The destination address of the first packet is an address of the slave clock port, and the source address of the first packet is a communication address of the master clock port.

12. Apparatus according to claims 8-11, wherein said master clock device is a grandfather clock device.