WO2012060262A1 - Sinter bonding agent, method for producing same, and bonding method using same - Google Patents

Sinter bonding agent, method for producing same, and bonding method using same Download PDF

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Publication number
WO2012060262A1
WO2012060262A1 PCT/JP2011/074688 JP2011074688W WO2012060262A1 WO 2012060262 A1 WO2012060262 A1 WO 2012060262A1 JP 2011074688 W JP2011074688 W JP 2011074688W WO 2012060262 A1 WO2012060262 A1 WO 2012060262A1
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WO
WIPO (PCT)
Prior art keywords
bonding agent
copper
sintered
joining
cupric oxide
Prior art date
Application number
PCT/JP2011/074688
Other languages
French (fr)
Japanese (ja)
Inventor
雄亮 保田
俊章 守田
芳男 小林
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株式会社日立製作所
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Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Publication of WO2012060262A1 publication Critical patent/WO2012060262A1/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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Definitions

  • the present invention relates to a sintered bonding agent used for bonding electronic members and forming circuit wiring, and in particular, a highly heat-conductive sintered bonding agent mainly composed of copper oxide nanoparticles, a manufacturing method thereof, and the same
  • the present invention relates to a joining method.
  • semiconductor elements, circuit boards and the like are collectively referred to as electronic members.
  • Metal nanoparticles are attracting attention as new functional materials because their surface area is larger than the volume of the particles and their chemical activity is high and the sintering temperature is greatly reduced. Yes.
  • a paste containing metal nanoparticles is expected as a material used for joining electronic members in electronic equipment and forming circuit wiring.
  • metal nanoparticles having high thermal conductivity, electrical conductivity, and heat resistance (oxidation resistance) are preferred for use in such applications. Therefore, noble metal nanoparticles such as gold and silver are often used, and among them, relatively inexpensive silver is often used.
  • silver has a weak point that it tends to cause ion migration and easily cause a short circuit.
  • copper For suppressing ion migration, it is effective to use copper nanoparticles.
  • Copper has a thermal conductivity comparable to that of silver (silver: 430 W / m ⁇ K, copper: 400 W / m ⁇ K) and is far more advantageous than silver in terms of cost.
  • Non-Patent Document 1 reports a method of producing copper nanoparticles having a particle size of 100 nm or less using CTAB (Cetyl® Trimethyl® Ammonium® Bromide) as a dispersant. However, it is necessary to wash the copper nanoparticles to remove excess CTAB before the sintering heat treatment.
  • CTAB Cosmetic Acid® Trimethyl® Ammonium® Bromide
  • Patent Document 4 discloses a method of reducing and sintering cupric oxide nanoparticles in hydrogen. According to Patent Document 4, cupric oxide is reduced from around 200 ° C. in hydrogen, so that low temperature sintering is possible. In addition, since cupric oxide is stable at room temperature, there is no need to add viscosity modifiers or oxidation-resistant additives, and it is easier to handle than metallic copper nanoparticles and can be stored for a long time. Yes.
  • Patent Document 1 and Patent Document 2 seem to be excellent in terms of oxidation resistance, but in a narrow space such as a joint application between electronic members, Residues are likely to remain at the joints, and there is a concern that joint strength and thermal conductivity may be reduced.
  • the method described in Non-Patent Document 2 is liable to cause residual resin during sintering heat treatment, which may impair sinterability.
  • the additive coating method described in Patent Document 3 is to adsorb the antioxidant on the surface of the produced copper fine powder using a ball mill or the like.
  • this method it is difficult to uniformly coat nanoparticles having a particle size of 100 nm or less, and it is difficult to suppress oxidation of the nanoparticles.
  • An object of the present invention is to provide a sintered bonding agent mainly comprising copper oxide nanoparticles that can be produced, a method for producing the same, and a bonding method using the same.
  • a sintered bonding agent using cupric oxide nanoparticles wherein the cupric oxide nanoparticles having a particle size of 2 nm to 50 nm are 1 Sintered bonding agent characterized in that the primary particles are aggregated to form secondary particles having a particle size of 3 to 1000 nm, and the secondary particles are dispersed in a solution.
  • the primary particles are aggregated to form secondary particles having a particle size of 3 to 1000 nm, and the secondary particles are dispersed in a solution.
  • the present invention can add the following improvements and changes to the sintered bonding agent according to the above-described invention.
  • the solution is water or a mixed solution of water and an alcohol solvent.
  • the content of the cupric oxide nanoparticles is 90% by mass or more.
  • the primary particles are composed of single crystallites.
  • the primary particles are composed of a plurality of crystallites.
  • V The method for producing the sintered bonding agent, wherein after the step of dissolving the copper compound in the solution to produce copper ions, an alkaline solution is added to the solution while flowing an inert gas to oxidize the solution. Producing cupric colloid.
  • the copper compound is at least one of copper nitrate hydrate, copper oxide, and carboxylic acid copper salt.
  • a method for joining electronic members comprising a step of applying a sintering heat treatment at 100 to 500 ° C. in a reducing atmosphere after the step of applying the above-mentioned sintered bonding agent to the joining portion.
  • the reducing atmosphere is a hydrogen, formic acid, or ethanol atmosphere.
  • the electronic member In the joining method between the electronic members, the electronic member is a cooling fin and a metal support plate of a cooling unit, and the sintering is performed while pressurizing the cooling fin and the metal support plate in a joining direction. Apply heat treatment.
  • the electronic member In the bonding method between the electronic members, the electronic member is a chip and a wiring board of a semiconductor device, and the sintering heat treatment is performed while pressing in the direction in which the chip and the wiring board are bonded.
  • a sintered bonding agent mainly composed of copper oxide nanoparticles that can suppress ion migration while achieving both stable dispersibility and bonding properties a sintered bonding agent mainly composed of copper oxide nanoparticles that can suppress ion migration while achieving both stable dispersibility and bonding properties.
  • FIG. 1A and 1B are schematic views showing an insulating semiconductor device to which the present invention is applied, in which FIG. 1A is a plan view and FIG. It is the isometric view schematic diagram which showed the principal part of FIG. It is the cross-sectional schematic diagram which expanded and showed the semiconductor element mounting part of FIG. It is a cross-sectional schematic diagram of a capacitor built in a component built-in type multilayer wiring board. It is a cross-sectional schematic diagram of an LSI chip incorporated in a component built-in type multilayer wiring board.
  • the inventors of the present invention conducted a verification experiment of the prior art first. According to the investigations and examinations by the present inventors, a paste prepared by mixing cupric oxide powder (commercial product) with an average particle size of ⁇ m and water using an organic dispersant (commercial product) is used. As a result of the joining experiment, it was found that the residue of the organic dispersant hindered the sintering of the powder and the joining was not successful. In addition, when a paste was prepared by mixing cupric oxide nanoparticles (commercially available) having an average particle size of 50 mm or less and water without using a dispersant, and a bonding experiment between electronic members was conducted, nanoparticles were obtained. It was found that the dispersibility of the film was poor, and spots were formed at the joint. Details of each will be described later.
  • FIG. 1 is a flowchart showing an example of a method for synthesizing cupric oxide nanoparticles according to the present invention.
  • a solvent for synthesizing cupric oxide nanoparticles prepared is distilled water that has been subjected to inert gas bubbling for 30 minutes or more with stirring.
  • the reason for performing inert gas bubbling is to remove dissolved oxygen in the solvent and prevent impurities other than cupric oxide from being generated during synthesis.
  • the inert gas may be anything as long as it suppresses copper ions in the solution from reacting with other than cupric oxide, and examples thereof include nitrogen gas, argon gas, and helium gas.
  • the inert gas bubbling is preferably continued until the synthesis of cupric oxide is completed. Further, the flow rate of bubbling is not particularly limited, but for example, a range of 1 to 1000 mL / min or less is preferable.
  • the copper compound powder as a raw material is dissolved to produce copper ions.
  • the copper compound as a raw material is preferably a compound that can reduce the residue resulting from the anion at the time of dissolution, for example, copper nitrate trihydrate, copper chloride, copper hydroxide, copper carboxylate, etc. are preferred as copper acetate Used.
  • copper nitrate trihydrate is particularly preferable because it produces a small amount of impurities during the synthesis of cupric oxide and does not hinder secondary particle formation (aggregate formation).
  • the concentration of the copper compound solution is preferably such that the copper concentration is 0.001 to 1 mol / L, particularly preferably 0.010 mol / L.
  • a concentration of less than 0.001 mol / L is not preferable because it is too dilute and the yield of cupric oxide decreases.
  • a concentration of more than 1 mol / L is not preferable because formation of aggregates (secondary particles) is inhibited.
  • the reason for setting the solvent temperature to 5 ° C or higher and 90 ° C or lower is as follows. Since this synthesis method uses a solvent mainly composed of water, when the solvent temperature (reaction temperature) exceeds 90 ° C., nanoparticles (primary particles) and aggregates (secondary particles) having a stable size and shape are obtained. It is not preferable because it cannot be obtained. Moreover, when the solvent temperature (reaction temperature) is less than 5 ° C., the desired cupric oxide is hardly produced, and the yield is unfavorable.
  • a colloid of cupric oxide nanoparticles is generated by adding an alkaline solution.
  • the alkaline solution to be added is not particularly limited.
  • potassium hydroxide (KOH), barium hydroxide (Ba (OH) 2 ), sodium carbonate (Na 2 CO 3 ), calcium hydroxide (Ca (OH) 2 ), Sodium hydroxide (NaOH) and the like are preferably used.
  • NaOH and KOH are particularly preferred. This is because NaOH and KOH have a low content of impurities and hardly generate by-products and impurities during synthesis.
  • the alkali ion content of the copper ion content [Cu 2+] [OH -] molar ratio ([OH -] / [Cu 2+]) be made to be 1.5 or more and less than 2.1 Is preferred.
  • this synthesis method uses a solvent mainly composed of water
  • the reaction rate and the primary particle size can be controlled by mixing a polar organic solvent.
  • polar organic solvents include alcohols (eg, ethanol, methanol, isopropyl alcohol, 2-ethylhexyl alcohol, ethylene glycol, triethylene glycol, ethylene glycol monobutyl ether), aldehydes (eg, acetaldehyde), polyols (For example, glycol etc.) can be suitably used.
  • the mixing ratio of water and polar organic solvent can be arbitrary.
  • nonpolar organic solvents for example, ketones such as acetone, tetrahydrofuran, N, N-dimethylformamide, toluene, hexane, cyclohexane, xylene, benzene, etc.
  • ketones such as acetone, tetrahydrofuran, N, N-dimethylformamide, toluene, hexane, cyclohexane, xylene, benzene, etc.
  • ketones such as acetone, tetrahydrofuran, N, N-dimethylformamide, toluene, hexane, cyclohexane, xylene, benzene, etc.
  • the synthesis time is preferably performed in the range of 1 minute to 336 hours (14 days). When the time is less than 1 minute, the synthesis reaction is not completed, and the yield decreases. On the other hand, since the synthesis reaction is completed within 336 hours at the latest, a longer time is wasted.
  • the nanoparticles synthesized above may be used directly as a sintered binder, but unreacted products, by-products, anions, etc. may remain in the synthesis. It is preferably performed 1 to 10 times. Thereby, unreacted substances, by-products, anions and the like at the time of synthesis can be removed.
  • the cleaning liquid the above-described water or polar organic solvent can be preferably used.
  • the cupric oxide nanoparticles obtained by centrifugal washing and then disperse them in an appropriate liquid (dispersion medium) to prepare a paste-like sintered bonding agent.
  • the cupric oxide content in the sintered bonding agent is preferably 90% by mass or more from the viewpoint of improving the bonding strength.
  • the dispersion medium water or the above-mentioned polar organic solvent (for example, alcohols, aldehydes, polyols) can be preferably used. Further, in addition to the polar machine solvent, the aforementioned nonpolar organic solvent may be added.
  • a dispersant may be added.
  • the dispersant is preferably one that has little influence during sintering joining (one with little residue).
  • the dispersant is preferably one that has little influence during sintering joining (one with little residue).
  • the dispersant may be mixed to such an extent that the dispersibility of the nanoparticles is improved, and 30 parts by mass or less of the dispersant is preferable with respect to 100 parts by mass of cupric oxide. If it is added more than that, a residue is likely to remain in the bonding layer, which causes a decrease in bonding strength.
  • the primary particle size of the cupric oxide nanoparticles is preferably 2 to 50 nm, more preferably 8 to 18 nm.
  • the primary particle diameter is less than 2 nm, the chemical activity of the surface becomes too high, and it becomes difficult to control the secondary particles (aggregates).
  • primary particles having a particle size of more than 50 nm are difficult to produce by the above-described synthesis method, and the chemical activity of the surface becomes too low to control secondary particles (aggregates).
  • the primary particle diameter is 8 to 18 nm, more uniform secondary particles (aggregates) can be formed, and as a result, a strong bond can be obtained.
  • the shape of the primary particles need not be a true sphere, but may be an elliptical sphere or a polyhedron.
  • the primary particle may be composed of a single crystallite or a plurality of crystallites.
  • the sintered bonding agent according to the present invention is characterized in that the primary particles described above aggregate to form secondary particles (aggregates), and the aggregates are uniformly dispersed.
  • Aggregates are defined as aggregates in which primary particles are fused or in contact with each other.
  • the aggregate size is preferably 3 to 1000 nm.
  • the aspect ratio of the major axis length to the minor axis length of the aggregate is preferably 1 or more and 3 or less.
  • the aspect ratio of the aggregate is larger than 3, the denseness at the time of bonding deteriorates and the bonding strength is reduced.
  • agglomerating primary particles composed of nanoparticles as described above it is possible to improve the denseness of the bonding layer as compared with a bonding agent in which single nanoparticles (primary particles) as in the prior art are dispersed. Thus, a stronger bonding strength can be obtained.
  • the aggregate size is more preferably from 50 nm to 800 nm.
  • the aggregate size is more preferably 10 to 100 nm.
  • primary particles composed of single crystallites that is, particles having a large crystallite diameter
  • primary particles composed of a plurality of crystallites that is, particles having a small crystallite diameter
  • Observation of primary particles and secondary particles can be performed using an electron microscope (for example, a transmission electron microscope).
  • the crystallite diameter can be calculated from the peak obtained by the X-ray diffraction method using the Scherrer equation.
  • the measured crystallite diameter is not less than the major axis diameter of the observed primary particles, it can be determined that the primary particles are composed of single crystallites.
  • the measured crystallite diameter is less than the observed major axis diameter of the primary particles, it can be determined that the primary particles are composed of a plurality of single crystallites.
  • the sintering heat treatment for the sintered binder according to the present invention it is preferable to perform the heat treatment at a temperature of 100 to 500 ° C. in a reducing atmosphere.
  • the reducing atmosphere is not particularly limited, but for example, a hydrogen atmosphere, a formic acid atmosphere, an ethanol atmosphere, or the like is preferable.
  • Cu (NO 3 ) 2 .3H 2 O powder was used as a raw material copper compound, water was used as a solvent, and NaOH was used as a precipitant for cupric oxide nanoparticles.
  • Cu (NO 3 ) 2 ⁇ 3H 2 O powder so that the copper ion concentration becomes 0.01 mol / L to 985 mL of distilled water with nitrogen bubbling for 30 minutes in a beaker with a volume of 1000 mL. It was dissolved uniformly in a water bath at 80 ° C. Then, cupric oxide nanoparticle colloid was synthesize
  • cupric oxide particles were centrifuged (centrifugal washing machine: Tommy Seiko Co., Ltd., Suprema 21) and washing operations three times each. Thereafter, the cupric oxide particles were taken out and dried to obtain 0.085 g of cupric oxide particles (samples 1 to 7).
  • Samples 1 to 4 (particles synthesized at 20 to 50 ° C.) have a crystallite diameter larger than the major axis diameter of the primary particles, and the primary particles are made from a single crystallite. It turns out that it is composed.
  • Samples 5 to 7 (particles synthesized at 60 to 80 ° C.) had a crystallite diameter shorter than the major axis diameter of the primary particles, and the primary particles were composed of a plurality of crystallites. .
  • Comparative Sample 1 almost precipitated in 5 minutes after standing. Further, Comparative Sample 2 had good dispersibility, and no precipitation was observed even after 1 day after standing, but this was considered to be an effect of adding a dispersant.
  • the prepared cupric oxide particles (Samples 1 to 7) maintained a good dispersion state even after one day after standing, although no dispersant was added. This indicates that the dispersibility is improved by the cupric oxide particles of the present invention being an aggregate of nanoparticles. That is, it was confirmed that the particles obtained in the present invention were excellent in dispersibility in a dispersion medium without using a dispersant as in the prior art.
  • Each sintered bonding agent was prepared by adding each of Samples 1 to 7 and Comparative Samples 1 and 2 described above into water so that the content was 90% by mass and well stirred.
  • a copper test piece used for the measurement a lower test piece having a diameter of 10 mm and a thickness of 5 mm and an upper test piece having a diameter of 5 mm and a thickness of 2 mm were used.
  • the upper test piece was placed on the dried sintered bond, and the temperature was increased to 400 ° C in hydrogen. A sintering heat treatment was performed for a minute. At this time, a load with a surface pressure of 1.2 MPa was simultaneously applied. Using a shear tester (made by Seishin Shoji Co., Ltd., Bond Tester SS-100KP, maximum load 100 kg), shear stress was applied to the bonded specimens (shear rate 30 mm / min), and maximum load at break Was measured. The bonding strength was determined by dividing the maximum load by the bonding area. Furthermore, it normalized with the joint strength of the comparative sample 1, and calculated the normalization joint strength of each sintering joining agent.
  • FIG. 5 is a graph showing the relationship between the number of washings and the normalized bonding strength, and the relationship between the number of washings and the content of cupric oxide nanoparticles in the dry powder.
  • the normalized bonding strength was improved by increasing the number of times of centrifugal cleaning, and the content of cupric oxide nanoparticles in the dry powder increased.
  • the normalized bonding strength exceeded “1”. This was thought to be because impurities during the synthesis of copper oxide nanoparticles were removed by centrifugal washing.
  • the content of cupric oxide nanoparticles in the dry powder may be 90% by mass or more. It was confirmed that it was preferable.
  • FIG. 6 is a schematic cross-sectional view showing an example of a wiring board on which a semiconductor power module is mounted and a pin fin cooling unit.
  • the wiring substrate 14 includes a circuit wiring 11 connected to the semiconductor chip, an insulating substrate 12 for electrically insulating the semiconductor chip and the circuit wiring 11 inside the module, A metallization layer 13 for soldering the pin fin cooling unit 111 to the metal support plate 101 is laminated.
  • the pin fin cooling unit 111 has a structure in which a large number of pin fins 201 are bonded to the metal support plate 101 via the bonding layer 100. The heat generated in the semiconductor power module is transferred in the thickness direction of the wiring board 14, and the final heat dissipation is performed via the pin fins 201 attached to the metal support plate 101.
  • the metal support plate 101 and the pin fin 201 of the pin fin cooling unit 111 are usually made of copper. Conventionally, the joining of the metal support plate 101 and the pin fins 201 has been performed at a temperature of 800 ° C. or higher using a silver brazing material. Therefore, the metal support plate 101 and the pin fins 201 are softened, and there is a problem that the mechanical strength is reduced and the metal support plate 101 and the pin fins 201 are easily deformed.
  • the metal support plate 101 and the pin fin 201 were joined using a sintered joining agent in which the sample 1 of Example 1 was dispersed in water.
  • the sintering heat treatment was performed at a temperature of 400 ° C. in hydrogen while applying a pressure of 1.2 ⁇ M. Joining at a temperature lower than the softening temperature of copper was possible, and the problem of copper softening could be solved.
  • FIGS. 7A and 7B are schematic views showing an insulating semiconductor device to which the present invention is applied, in which FIG. 7A is a plan view and FIG. 7B is a cross-sectional view taken along line AA of FIG.
  • FIG. 8 is a schematic perspective view showing the main part of FIG.
  • FIG. 9 is an enlarged schematic cross-sectional view showing the semiconductor element mounting portion of FIG.
  • FIGS. 7A and 7B are schematic views showing an insulating semiconductor device to which the present invention is applied, in which FIG. 7A is a plan view and FIG. 7B is a cross-sectional view taken along line AA of FIG.
  • FIG. 8 is a schematic perspective view showing the main part of FIG.
  • FIG. 9 is an enlarged schematic cross-sectional view showing the semiconductor element mounting portion of FIG.
  • a wiring board composed of the ceramic insulating substrate 303 and the wiring layer 302 is joined to the support member 310 via the solder layer 309.
  • the wiring layer 302 is obtained by applying nickel plating to a copper wiring.
  • the collector electrode 307 of the semiconductor element 301 and the wiring layer 302 on the ceramic insulating substrate 303 are joined via a joining layer 305 (pure copper layer after joining) formed by the sintered joining agent according to the present invention.
  • the copper oxide particle-using bonding material 305 (pure copper layered after bonding) produced in Example 1 at 20 ° C. has the emitter electrode 306 of the semiconductor element 301 and the connection terminal 401 in a sintered bonding according to the present invention. Bonding is performed via a bonding layer 305 (pure copper layering after bonding) formed by an agent.
  • connection terminal 401 and the wiring layer 304 on the ceramic insulating substrate 303 are joined via a joining layer 305 (pure copper layer after joining) formed by the sintered joining agent according to the present invention.
  • the bonding layer 305 has a thickness of 80 ⁇ m.
  • Nickel plating is applied to the surfaces of the collector electrode 307 and the emitter electrode 306.
  • the connection terminal 401 is made of Cu or a Cu alloy. 7 denote the case 311, the external terminal 312, the bonding wire 313, and the sealing material 314, respectively.
  • the bonding layer 305 is formed by, for example, applying a sintered bonding agent containing 90% by mass of the cupric oxide nanoparticle aggregate and 10% by mass of water according to the present invention to the bonding surface of the member to be bonded. After drying at 80 ° C. for 1 hour, sintering heat treatment at 350 ° C. for 1 minute in hydrogen while applying a pressure of 1.0 kg MPa is possible. In joining, ultrasonic vibration may be applied. Further, the bonding layer 305 may be formed individually or simultaneously.
  • FIG. 10A is a schematic cross-sectional view of a capacitor incorporated in a component-embedded multilayer wiring board.
  • a metallized layer 802 is formed as an electrode, and a copper plating layer 801 is formed on the outer layer of the metallized layer 802.
  • FIG. 10B is a schematic cross-sectional view of an LSI chip embedded in a component-embedded multilayer wiring board.
  • bumps 805 are provided on the electrodes
  • a copper plating layer 806 is formed on the outer layer of the bumps 805.
  • 10C is a schematic cross-sectional view of a core layer portion of a component-embedded multilayer wiring board.
  • Conduction in the thickness direction of the core 807 is performed by the surface wiring 809 of the through hole 808.
  • Conduction in the thickness direction of the prepreg 810 is performed by a bump-like 812 having a copper plating layer 811 on the surface. Further, a copper plating layer 811 may be provided on the surface wiring 809.
  • FIG. 11 is a schematic cross-sectional view showing an example of a component built-in multilayer wiring board to which the present invention is applied.
  • FIG. 12 is a schematic cross-sectional view showing another example of a component built-in multilayer wiring board to which the present invention is applied.
  • FIG. 13 is a schematic cross-sectional view showing still another example of a component built-in multilayer wiring board to which the present invention is applied.
  • each of the capacitors 803, the LSI chip 804, the through wiring 812, and the surface wiring 809 is bonded to the copper plating layers 801, 806, 811 by applying the sintered bonding agent according to the present invention, and then dried in a formic acid atmosphere. This is done through a sintered copper layer 813 formed by the sintering heat treatment. It should be noted that the sintered copper layer 814 other than the respective joint portions is in close contact with the prepreg 810. Also, in the component built-in type multilayer wiring board to which the present invention is applied, an electronic component (for example, a capacitor 803) is connected in the vertical direction as shown in FIG. 12, or is connected in the horizontal direction as shown in FIG.
  • the projected area of the multilayer wiring board can be minimized or the thickness can be minimized, and the degree of freedom in design is high. Furthermore, since the sintered copper layer 813 formed using the sintered bonding agent according to the present invention is thin, it is possible to perform bonding while suppressing delay of the electric signal.
  • FIG. 14 is a schematic cross-sectional view showing an example of a laminated chip to which the present invention is applied.
  • a through electrode 903 is formed in the semiconductor element 901 with an insulating layer 902 interposed therebetween.
  • a copper metallized layer 904 is provided on one surface of the through electrode 903, and the sintered bonding agent according to the present invention is applied and dried on this surface, and then sintered by heat treatment at 300 ° C. in hydrogen.
  • a plurality of semiconductor elements are stacked via a bonding layer 905 made of copper.
  • the semiconductor element 906 has a Cu metallized layer 907 formed on both sides of the through electrode with such a configuration, and the bonding layer 905 using the sintered bonding agent according to the present invention formed on the Cu metallized layer 907 is formed.
  • the joining with the interposer 908 may be brazing or pressure bonding.
  • the present invention may be applied to the bonding between the bump 910 provided on the interposer 908 and the circuit board, or a conventional bonding method may be applied.

Abstract

The purpose of the present invention is to provide: a sinter bonding agent which is mainly composed of copper oxide nanoparticles and capable of suppressing ion migration, while having a good balance between stable dispersibility and adequate bondability in the sinter bonding agent that uses nanoparticles; a method for producing the sinter bonding agent; and a bonding method using the sinter bonding agent. This sinter bonding agent uses copper (II) oxide nanoparticles and is characterized in that: the copper (II) oxide nanoparticles each having a particle diameter of 2-50 nm (inclusive) are used as primary particles; the primary particles aggregate to form secondary particles each having a particle diameter of 3-1,000 nm (inclusive); and the secondary particles are dispersed in a solution.

Description

焼結接合剤、その製造方法およびそれを用いた接合方法Sintered bonding agent, manufacturing method thereof and bonding method using the same
 本発明は、電子部材同士の接合や回路配線の形成に用いられる焼結接合剤に関し、特に酸化銅ナノ粒子を主材とする高伝熱性の焼結接合剤、その製造方法およびそれを用いた接合方法に関するものである。なお、本発明においては、半導体素子や回路基板等を総称して電子部材と称す。 The present invention relates to a sintered bonding agent used for bonding electronic members and forming circuit wiring, and in particular, a highly heat-conductive sintered bonding agent mainly composed of copper oxide nanoparticles, a manufacturing method thereof, and the same The present invention relates to a joining method. In the present invention, semiconductor elements, circuit boards and the like are collectively referred to as electronic members.
 金属ナノ粒子(例えば、粒径100 nm以下)は粒子の体積に比して表面積が大きいために化学的活性が高く焼結温度が大幅に低下することから、新しい機能性材料として注目を浴びている。例えば、金属ナノ粒子を含有したペーストは、電子機器中の電子部材同士の接合や回路配線の形成に用いられる材料として期待されている。そのような用途に用いるためには、一般的に、高い熱伝導率・導電性・耐熱性(耐酸化性)を有する金属ナノ粒子が好ましい。そのため、金や銀などの貴金属ナノ粒子が用いられることが多く、中でも比較的安価な銀がしばしば用いられている。 Metal nanoparticles (for example, particle size of 100 nm or less) are attracting attention as new functional materials because their surface area is larger than the volume of the particles and their chemical activity is high and the sintering temperature is greatly reduced. Yes. For example, a paste containing metal nanoparticles is expected as a material used for joining electronic members in electronic equipment and forming circuit wiring. In general, metal nanoparticles having high thermal conductivity, electrical conductivity, and heat resistance (oxidation resistance) are preferred for use in such applications. Therefore, noble metal nanoparticles such as gold and silver are often used, and among them, relatively inexpensive silver is often used.
 しかしながら、銀は、イオンマイグレーションが発生しやすく短絡の要因になりやすいという弱点がある。イオンマイグレーションの抑制に関しては、銅ナノ粒子を用いることが有効である。また、銅は銀と同程度の熱伝導率を有し(銀:430 W/m・K、銅:400 W/m・K)、かつコスト面では銀よりもはるかに有利である。 However, silver has a weak point that it tends to cause ion migration and easily cause a short circuit. For suppressing ion migration, it is effective to use copper nanoparticles. Copper has a thermal conductivity comparable to that of silver (silver: 430 W / m · K, copper: 400 W / m · K) and is far more advantageous than silver in terms of cost.
 銅ナノ粒子の製造方法としては、例えば、非特許文献1にCTAB(Cetyl Trimethyl Ammonium Bromide)を分散剤として用いて粒径が100 nm以下の銅ナノ粒子を製造する方法が報告されている。ただし、焼結熱処理前に過剰なCTABを除去するため銅ナノ粒子を洗浄する必要がある。 As a method for producing copper nanoparticles, for example, Non-Patent Document 1 reports a method of producing copper nanoparticles having a particle size of 100 nm or less using CTAB (Cetyl® Trimethyl® Ammonium® Bromide) as a dispersant. However, it is necessary to wash the copper nanoparticles to remove excess CTAB before the sintering heat treatment.
 しかしながら、銅ナノ粒子を洗浄すると、金属銅が酸化して酸化第一銅に変化してしまうという問題がある。金属銅が酸化第一銅に一旦酸化してしまうと、大気中での焼結が困難になる上に、水素などの還元雰囲気中でも400℃以上の加熱が必要となることから、低温焼結自体が困難になる。 However, there is a problem that when copper nanoparticles are washed, metallic copper is oxidized and converted to cuprous oxide. Once metallic copper is oxidized to cuprous oxide, it becomes difficult to sinter in the atmosphere, and heating at 400 ° C or higher is required even in a reducing atmosphere such as hydrogen. Becomes difficult.
 これに対し銅ナノ粒子の酸化を防ぐ技術として、銅ナノ粒子の作製時にシリコーンオイルによってナノ粒子の周囲を被覆する方法や(例えば、特許文献1、特許文献2参照)、銅の微細粉末を作製した後に添加剤を加えて銅の酸化を抑制する方法や(例えば、特許文献3参照)、銅ナノ粒子の分散性や粘度を調節するとともに酸化を抑制するために樹脂と混合する方法(例えば、非特許文献2参照)などが開示されている。 On the other hand, as a technique for preventing the oxidation of copper nanoparticles, a method of coating the periphery of the nanoparticles with silicone oil at the time of preparing the copper nanoparticles (see, for example, Patent Document 1 and Patent Document 2), or a fine copper powder is produced. After that, a method of adding an additive to suppress copper oxidation (for example, see Patent Document 3), a method of adjusting the dispersibility and viscosity of copper nanoparticles and mixing with a resin to suppress oxidation (for example, Non-Patent Document 2) is disclosed.
 一方、特許文献4には、酸化第二銅のナノ粒子を用い水素中で還元して焼結させる方法が開示されている。特許文献4によると、酸化第二銅は水素中で200℃付近から還元することから、低温焼結が可能であるとされている。また、酸化第二銅は室温で安定であることから、粘度調整剤や耐酸化添加剤などを加える必要がなく、金属銅のナノ粒子よりも取り扱いが容易で長期保存が可能であるとされている。 On the other hand, Patent Document 4 discloses a method of reducing and sintering cupric oxide nanoparticles in hydrogen. According to Patent Document 4, cupric oxide is reduced from around 200 ° C. in hydrogen, so that low temperature sintering is possible. In addition, since cupric oxide is stable at room temperature, there is no need to add viscosity modifiers or oxidation-resistant additives, and it is easier to handle than metallic copper nanoparticles and can be stored for a long time. Yes.
特開2005-60779号公報Japanese Patent Laid-Open No. 2005-60777 特開2005-60778号公報Japanese Patent Laid-Open No. 2005-60778 特開2007-258123号公報JP 2007-258123 A 特開2008-244242号公報JP 2008-244242 A
 特許文献1や特許文献2に記載の銅ナノ粒子は、耐酸化性という点において優れていると思われるが、電子部材同士の接合用途のような狭小空間においては、焼結熱処理時にシリコーンオイルの残渣が接合箇所に残りやすく、接合強度や熱伝導性を低下させることが危惧される。また、非特許文献2に記載の方法も、焼結熱処理時に樹脂の残渣が残りやすく、焼結性を阻害することが危惧される。 The copper nanoparticles described in Patent Document 1 and Patent Document 2 seem to be excellent in terms of oxidation resistance, but in a narrow space such as a joint application between electronic members, Residues are likely to remain at the joints, and there is a concern that joint strength and thermal conductivity may be reduced. In addition, the method described in Non-Patent Document 2 is liable to cause residual resin during sintering heat treatment, which may impair sinterability.
 さらに、特許文献3に記載されている添加剤被覆の方法は、作製した銅微粉末の表面にボールミル等を用いて酸化防止剤を吸着させるものである。しかしながら、該方法では粒径が100 nm以下のナノ粒子に対する均一なコーティングが難しく、ナノ粒子の酸化を抑制することが困難であることが危惧される。 Furthermore, the additive coating method described in Patent Document 3 is to adsorb the antioxidant on the surface of the produced copper fine powder using a ball mill or the like. However, with this method, it is difficult to uniformly coat nanoparticles having a particle size of 100 nm or less, and it is difficult to suppress oxidation of the nanoparticles.
 一方、特許文献4に記載の酸化第二銅ナノ粒子を用いた接合は、粒子の安定性の観点で大変興味深い技術であるが、接合剤用のペーストを作製するためには溶媒中に均一分散させる必要があり、低分子系、高分子系あるいはオリゴマー系の分散剤が用いられている。しかしながら、この場合も焼結熱処理時に有機分散剤の残渣がナノ粒子の焼結を阻害し、接合強度の低下を招くことが危惧される。 On the other hand, bonding using cupric oxide nanoparticles described in Patent Document 4 is a very interesting technique from the viewpoint of particle stability, but in order to produce a paste for bonding agent, it is uniformly dispersed in a solvent. Low molecular, high molecular or oligomeric dispersants are used. However, in this case as well, there is a concern that the residue of the organic dispersant inhibits the sintering of the nanoparticles during the sintering heat treatment and causes a decrease in bonding strength.
 本発明は、上記事情を鑑みてなされたものであり、従来技術の問題点を解決し、ナノ粒子を用いた焼結接合剤において安定した分散性と接合性とを両立するとともにイオンマイグレーションを抑制することができる酸化銅ナノ粒子を主材とする焼結接合剤、その製造方法およびそれを用いた接合方法を提供することを目的とする。 The present invention has been made in view of the above circumstances, solves the problems of the prior art, and achieves both stable dispersibility and bondability in a sintered bonding agent using nanoparticles and suppresses ion migration. An object of the present invention is to provide a sintered bonding agent mainly comprising copper oxide nanoparticles that can be produced, a method for producing the same, and a bonding method using the same.
 本発明の1つの態様は、上記目的を達成するため、酸化第二銅ナノ粒子を用いた焼結接合剤であって、粒径2 nm以上50 nm以下の前記酸化第二銅ナノ粒子を1次粒子として用い、前記1次粒子が凝集して粒径3 nm以上1000 nm以下の2次粒子を構成し、前記2次粒子が溶液中に分散していることを特徴とする焼結接合剤を提供する。 In one aspect of the present invention, in order to achieve the above object, a sintered bonding agent using cupric oxide nanoparticles, wherein the cupric oxide nanoparticles having a particle size of 2 nm to 50 nm are 1 Sintered bonding agent characterized in that the primary particles are aggregated to form secondary particles having a particle size of 3 to 1000 nm, and the secondary particles are dispersed in a solution. I will provide a.
 また、本発明は、上記の発明に係る焼結接合剤において、以下のような改良や変更を加えることができる。
(i)前記溶液が、水、または水とアルコール系溶剤との混合溶液である。
(ii)前記酸化第二銅ナノ粒子の含有量が90質量%以上である。
(iii)前記1次粒子が単結晶子から構成されている。
(iv)前記1次粒子が複数の結晶子から構成されている。
(v)上記焼結接合剤の製造方法であって、前記溶液中に銅化合物を溶解させて銅イオンを生成させる工程の後に、前記溶液中に不活性ガスを流しながらアルカリ性溶液を加えて酸化第二銅コロイドを生成する工程を有する。
(vi)上記焼結接合剤の製造方法において、前記銅化合物が、硝酸銅水和物、銅酸化物、カルボン酸銅塩のうちの少なくとも一種である。
(vii)電子部材同士の接合方法であって、上記の焼結接合剤を接合箇所に塗布する工程の後に、還元雰囲気中100~500℃の焼結熱処理を施す工程を有する。
(viii)上記電子部材同士の接合方法おいて、前記還元雰囲気が、水素、ギ酸、またはエタノール雰囲気である。
(ix)上記電子部材同士の接合方法おいて、前記電子部材が、冷却ユニットの冷却フィンと金属支持板であり、前記冷却フィンと前記金属支持板とを接合する方向に加圧しながら前記焼結熱処理を施す。
(x)上記電子部材同士の接合方法おいて、前記電子部材が、半導体装置のチップと配線基板であり、前記チップと前記配線基板とを接合する方向に加圧しながら前記焼結熱処理を施す。
Moreover, the present invention can add the following improvements and changes to the sintered bonding agent according to the above-described invention.
(I) The solution is water or a mixed solution of water and an alcohol solvent.
(Ii) The content of the cupric oxide nanoparticles is 90% by mass or more.
(Iii) The primary particles are composed of single crystallites.
(Iv) The primary particles are composed of a plurality of crystallites.
(V) The method for producing the sintered bonding agent, wherein after the step of dissolving the copper compound in the solution to produce copper ions, an alkaline solution is added to the solution while flowing an inert gas to oxidize the solution. Producing cupric colloid.
(Vi) In the method for producing a sintered bonding agent, the copper compound is at least one of copper nitrate hydrate, copper oxide, and carboxylic acid copper salt.
(Vii) A method for joining electronic members, comprising a step of applying a sintering heat treatment at 100 to 500 ° C. in a reducing atmosphere after the step of applying the above-mentioned sintered bonding agent to the joining portion.
(Viii) In the method for joining electronic members, the reducing atmosphere is a hydrogen, formic acid, or ethanol atmosphere.
(Ix) In the joining method between the electronic members, the electronic member is a cooling fin and a metal support plate of a cooling unit, and the sintering is performed while pressurizing the cooling fin and the metal support plate in a joining direction. Apply heat treatment.
(X) In the bonding method between the electronic members, the electronic member is a chip and a wiring board of a semiconductor device, and the sintering heat treatment is performed while pressing in the direction in which the chip and the wiring board are bonded.
 本発明によれば、ナノ粒子を用いた焼結接合剤において安定した分散性と接合性とを両立するとともにイオンマイグレーションを抑制することができる酸化銅ナノ粒子を主材とする焼結接合剤、その製造方法およびそれを用いた接合方法を提供することができる。 According to the present invention, in a sintered bonding agent using nanoparticles, a sintered bonding agent mainly composed of copper oxide nanoparticles that can suppress ion migration while achieving both stable dispersibility and bonding properties, The manufacturing method and the joining method using the same can be provided.
本発明に係る酸化第二銅ナノ粒子の合成方法の1例を示すフローチャートである。It is a flowchart which shows one example of the synthesis | combining method of the cupric oxide nanoparticle which concerns on this invention. 1次粒子の長軸径と結晶子径との関係を示すグラフである。It is a graph which shows the relationship between the major axis diameter of a primary particle, and a crystallite diameter. 凝集体サイズと規格化接合強度との関係を示すグラフである。It is a graph which shows the relationship between an aggregate size and normalized bonding strength. 凝集体アスペクト比と規格化接合強度との関係を示すグラフである。It is a graph which shows the relationship between an aggregate aspect ratio and normalized bonding strength. 洗浄回数と規格化接合強度との関係、および洗浄回数と乾燥粉末中の酸化銅第二銅ナノ粒子の含有率との関係を示すグラフである。It is a graph which shows the relationship between the frequency | count of washing | cleaning and normalized bonding strength, and the relationship between the frequency | count of washing | cleaning and the content rate of the cupric oxide cupric nanoparticle in dry powder. 半導体パワーモジュールを搭載する配線基板とピンフィン冷却ユニットの1例を示す断面模式図である。It is a cross-sectional schematic diagram which shows an example of the wiring board which mounts a semiconductor power module, and a pin fin cooling unit. 本発明を適用した絶縁型半導体装置を示した模式図であり、(a)は平面図、(b)は(a)のA-A断面図である。1A and 1B are schematic views showing an insulating semiconductor device to which the present invention is applied, in which FIG. 1A is a plan view and FIG. 図7の要部を示した斜視模式図である。It is the isometric view schematic diagram which showed the principal part of FIG. 図7の半導体素子搭載部分を拡大して示した断面模式図である。It is the cross-sectional schematic diagram which expanded and showed the semiconductor element mounting part of FIG. 部品内蔵型の多層配線基板の内蔵されるコンデンサの断面模式図である。It is a cross-sectional schematic diagram of a capacitor built in a component built-in type multilayer wiring board. 部品内蔵型の多層配線基板の内蔵されるLSIチップの断面模式図である。It is a cross-sectional schematic diagram of an LSI chip incorporated in a component built-in type multilayer wiring board. 部品内蔵型の多層配線基板のコア層部分の断面模式図である。It is a cross-sectional schematic diagram of a core layer portion of a component built-in type multilayer wiring board. 本発明を適用した部品内蔵型多層配線基板の1例を示す断面模式図である。It is a cross-sectional schematic diagram which shows an example of the component built-in type multilayer wiring board to which this invention is applied. 本発明を適用した部品内蔵型多層配線基板の他の1例を示す断面模式図である。It is a cross-sectional schematic diagram which shows another example of the component-embedded multilayer wiring board to which the present invention is applied. 本発明を適用した部品内蔵型多層配線基板の更に他の1例を示す断面模式図である。It is a cross-sectional schematic diagram which shows another example of the multilayer wiring board with a built-in component to which the present invention is applied. 本発明を適用した積層チップの1例を示す断面模式図である。It is a cross-sectional schematic diagram which shows an example of the laminated chip to which this invention is applied.
 本発明者等は、はじめに、従来技術の検証実験を行った。本発明者等の調査・検討によると、平均粒径がμmオーダーの酸化第二銅粉末(市販品)に有機分散剤(市販品)を用いて水と混合したペーストを作製し、電子部材同士の接合実験を行ったところ、有機分散剤の残渣が該粉末の焼結を阻害して接合が上手くいかないことが判った。また、分散剤を用いずに平均粒径が50 nm以下の酸化第二銅ナノ粒子(市販品)と水とを混合したペーストを作製し、電子部材同士の接合実験を行ったところ、ナノ粒子の分散性が悪いために接合部分に斑ができてしまうことが判った。それぞれ詳細は後述する。 The inventors of the present invention conducted a verification experiment of the prior art first. According to the investigations and examinations by the present inventors, a paste prepared by mixing cupric oxide powder (commercial product) with an average particle size of μm and water using an organic dispersant (commercial product) is used. As a result of the joining experiment, it was found that the residue of the organic dispersant hindered the sintering of the powder and the joining was not successful. In addition, when a paste was prepared by mixing cupric oxide nanoparticles (commercially available) having an average particle size of 50 mm or less and water without using a dispersant, and a bonding experiment between electronic members was conducted, nanoparticles were obtained. It was found that the dispersibility of the film was poor, and spots were formed at the joint. Details of each will be described later.
 以下、本発明の実施形態について、図面を参照しながら焼結接合剤の製造手順に沿って説明する。ただし、本発明はここで取り上げた実施形態に限定されることはなく、要旨を変更しない範囲で適宜組み合わせや改良が可能である。 Hereinafter, an embodiment of the present invention will be described along a manufacturing procedure of a sintered bonding agent with reference to the drawings. However, the present invention is not limited to the embodiments taken up here, and can be appropriately combined and improved without departing from the scope of the invention.
 (焼結接合剤の製造方法)
 図1は、本発明に係る酸化第二銅ナノ粒子の合成方法の1例を示すフローチャートである。はじめに、酸化第二銅ナノ粒子合成のための溶媒として、撹拌しながら不活性ガスバブリングを30分間以上行った蒸留水を準備する。不活性ガスバブリングを行う理由は、溶媒中の溶存酸素を取り除き、合成時において酸化第二銅以外の不純物が生成するのを防ぐためである。
(Method for producing sintered bonding agent)
FIG. 1 is a flowchart showing an example of a method for synthesizing cupric oxide nanoparticles according to the present invention. First, as a solvent for synthesizing cupric oxide nanoparticles, prepared is distilled water that has been subjected to inert gas bubbling for 30 minutes or more with stirring. The reason for performing inert gas bubbling is to remove dissolved oxygen in the solvent and prevent impurities other than cupric oxide from being generated during synthesis.
 不活性ガスとしては、溶液中の銅イオンが酸化第二銅以外へ反応することを抑制するものであれば何でもよく、例えば、窒素ガス、アルゴンガス、ヘリウムガスなどが挙げられる。なお、不活性ガスバブリングは、酸化第二銅の合成完了まで継続されることが望ましい。また、バブリングの流量に特段の限定はないが、例えば、1 mL/min以上1000 mL/min以下の範囲が好適である。 The inert gas may be anything as long as it suppresses copper ions in the solution from reacting with other than cupric oxide, and examples thereof include nitrogen gas, argon gas, and helium gas. The inert gas bubbling is preferably continued until the synthesis of cupric oxide is completed. Further, the flow rate of bubbling is not particularly limited, but for example, a range of 1 to 1000 mL / min or less is preferable.
 次に、5℃以上90℃以下に温度制御した該溶媒を攪拌しながら、原料となる銅化合物の粉末を溶解させて銅イオンを生成させる。原料となる銅化合物としては、溶解時のアニオンに起因する残留物を少なくできる化合物が好ましく、例えば、硝酸銅三水和物、塩化銅、水酸化銅、カルボン酸銅塩として酢酸銅などが好ましく用いられる。中でも硝酸銅三水和物は、酸化第二銅合成時の不純物生成量が少なく、かつ2次粒子形成(凝集体の形成)を阻害しないことから特に好ましい。 Next, while stirring the solvent whose temperature is controlled at 5 ° C. or more and 90 ° C. or less, the copper compound powder as a raw material is dissolved to produce copper ions. The copper compound as a raw material is preferably a compound that can reduce the residue resulting from the anion at the time of dissolution, for example, copper nitrate trihydrate, copper chloride, copper hydroxide, copper carboxylate, etc. are preferred as copper acetate Used. Among these, copper nitrate trihydrate is particularly preferable because it produces a small amount of impurities during the synthesis of cupric oxide and does not hinder secondary particle formation (aggregate formation).
 銅化合物溶液の濃度としては、銅濃度が0.001~1 mol/Lとなるようにすることが好ましく、0.010 mol/Lが特に好ましい。0.001 mol/L未満の濃度では、希薄過ぎるため酸化第二銅の収率が低下することから好ましくない。また、1 mol/L超の濃度では、凝集体(2次粒子)の形成が阻害されることから好ましくない。 The concentration of the copper compound solution is preferably such that the copper concentration is 0.001 to 1 mol / L, particularly preferably 0.010 mol / L. A concentration of less than 0.001 mol / L is not preferable because it is too dilute and the yield of cupric oxide decreases. A concentration of more than 1 mol / L is not preferable because formation of aggregates (secondary particles) is inhibited.
 溶媒温度を5℃以上90℃以下とした理由は次のとおりである。本合成方法は水を主体とする溶媒を用いることから、溶媒温度(反応温度)が90℃超となると、サイズや形状が安定したナノ粒子(1次粒子)および凝集体(2次粒子)を得ることが出来なくなることから好ましくない。また、溶媒温度(反応温度)が5℃未満では目的とする酸化第二銅が生成されにくく、収率が低下することから好ましくない。 The reason for setting the solvent temperature to 5 ° C or higher and 90 ° C or lower is as follows. Since this synthesis method uses a solvent mainly composed of water, when the solvent temperature (reaction temperature) exceeds 90 ° C., nanoparticles (primary particles) and aggregates (secondary particles) having a stable size and shape are obtained. It is not preferable because it cannot be obtained. Moreover, when the solvent temperature (reaction temperature) is less than 5 ° C., the desired cupric oxide is hardly produced, and the yield is unfavorable.
 次に、アルカリ性溶液を加えることで酸化第二銅ナノ粒子のコロイドを生成する。添加するアルカリ性溶液に特段の限定はないが、例えば、水酸化カリウム(KOH)、水酸化バリウム(Ba(OH)2)、炭酸ナトリウム(Na2CO3)、水酸化カルシウム(Ca(OH)2)、水酸化ナトリウム(NaOH)などが好適に用いられる。中でもNaOHとKOHが特に好ましい。NaOHやKOHは、不純物の含有量が少なく合成時に副生成物や不純物を生成しにくいからである。 Next, a colloid of cupric oxide nanoparticles is generated by adding an alkaline solution. The alkaline solution to be added is not particularly limited. For example, potassium hydroxide (KOH), barium hydroxide (Ba (OH) 2 ), sodium carbonate (Na 2 CO 3 ), calcium hydroxide (Ca (OH) 2 ), Sodium hydroxide (NaOH) and the like are preferably used. Of these, NaOH and KOH are particularly preferred. This is because NaOH and KOH have a low content of impurities and hardly generate by-products and impurities during synthesis.
 添加するアルカリ性溶液の量は、銅イオン量[Cu2+]に対するアルカリイオン量[OH-]のモル比([OH-]/[Cu2+])が1.5以上2.1未満となるようにすることが好ましい。「[OH-]/[Cu2+]」が2.1以上になると生成される酸化第二銅2次粒子の形状が劣化し、電子部材同士を接合した時の接合強度の低下を招く。また、「[OH-]/[Cu2+]」が1.5より小さくとなると酸化第二銅自体が生成されにくくなる。詳細は後述する。 The amount of the alkaline solution to be added, the alkali ion content of the copper ion content [Cu 2+] [OH -] molar ratio ([OH -] / [Cu 2+]) be made to be 1.5 or more and less than 2.1 Is preferred. When “[OH ] / [Cu 2+ ]” is 2.1 or more, the shape of the produced cupric oxide secondary particles deteriorates, and the bonding strength is lowered when the electronic members are bonded together. Further, when “[OH ] / [Cu 2+ ]” is less than 1.5, cupric oxide itself is hardly generated. Details will be described later.
 前述したように、本合成方法は水を主体とする溶媒を用いるが、極性有機溶媒を混合させることで反応速度および1次粒子径の制御が可能である。極性有機溶媒としては、アルコール類(例えば、エタノール、メタノール、イソプロピルアルコール、2-エチルヘキシルアルコール、エチレングリコール、トリエチレングリコール、エチレングリコールモノブチルエーテル等)や、アルデヒド類(例えば、アセトアルデヒド等)や、ポリオール類(例えば、グリコール等)を好適に利用できる。水と極性有機溶媒の混合比は任意とすることができる。また、極性機溶媒に加えて、非極性有機溶媒(例えば、アセトン等のケトン類、テトラヒドロフラン、N,N-ジメチルホルムアミド、トルエン、ヘキサン、シクロヘキサン、キシレン、ベンゼン等)を添加してもよい。 As described above, although this synthesis method uses a solvent mainly composed of water, the reaction rate and the primary particle size can be controlled by mixing a polar organic solvent. Examples of polar organic solvents include alcohols (eg, ethanol, methanol, isopropyl alcohol, 2-ethylhexyl alcohol, ethylene glycol, triethylene glycol, ethylene glycol monobutyl ether), aldehydes (eg, acetaldehyde), polyols (For example, glycol etc.) can be suitably used. The mixing ratio of water and polar organic solvent can be arbitrary. In addition to polar machine solvents, nonpolar organic solvents (for example, ketones such as acetone, tetrahydrofuran, N, N-dimethylformamide, toluene, hexane, cyclohexane, xylene, benzene, etc.) may be added.
 なお、合成時間として特段の限定はないが、1分~336時間(14日間)の範囲で行うことが好ましい。1分以下になると合成反応が終了していないため収率が低下する。一方、合成反応は遅くとも336時間の間に完了するため、それよりも長い時間は無駄になる。 Although there is no particular limitation on the synthesis time, it is preferably performed in the range of 1 minute to 336 hours (14 days). When the time is less than 1 minute, the synthesis reaction is not completed, and the yield decreases. On the other hand, since the synthesis reaction is completed within 336 hours at the latest, a longer time is wasted.
 上記で合成したナノ粒子は、焼結接合剤としてそのまま用いてもよいが、合成時の未反応物や副生成物、アニオンなどが残留している可能性があるため、合成後には遠心洗浄を1~10回行うことが好ましい。これにより、合成時の未反応物や副生成物、アニオンなどを取り除くことができる。洗浄液としては、上述した水や極性有機溶剤を好ましく用いることができる。 The nanoparticles synthesized above may be used directly as a sintered binder, but unreacted products, by-products, anions, etc. may remain in the synthesis. It is preferably performed 1 to 10 times. Thereby, unreacted substances, by-products, anions and the like at the time of synthesis can be removed. As the cleaning liquid, the above-described water or polar organic solvent can be preferably used.
 遠心洗浄して得られた酸化第二銅ナノ粒子を乾燥させた後に、適当な液体(分散媒)に分散させてペースト状の焼結接合剤を調合することが好ましい。このとき、焼結接合剤中の酸化第二銅含有量は、接合強度向上の観点から90質量%以上とすることが好ましい。分散媒としては、水や前述した極性有機溶媒(例えば、アルコール類、アルデヒド類、ポリオール類)を好ましく用いることができる。また、極性機溶媒に加えて、前述した非極性有機溶媒を添加してもよい。 It is preferable to dry the cupric oxide nanoparticles obtained by centrifugal washing and then disperse them in an appropriate liquid (dispersion medium) to prepare a paste-like sintered bonding agent. At this time, the cupric oxide content in the sintered bonding agent is preferably 90% by mass or more from the viewpoint of improving the bonding strength. As the dispersion medium, water or the above-mentioned polar organic solvent (for example, alcohols, aldehydes, polyols) can be preferably used. Further, in addition to the polar machine solvent, the aforementioned nonpolar organic solvent may be added.
 焼結接合剤中の酸化第二銅ナノ粒子の分散性を向上させるため、分散剤を添加してもよい。このとき、分散剤としては焼結接合時に影響が少ないもの(残渣の少ないもの)が好ましい。例えば、ドデシル硫酸ナトリウム、セチルトリメチルアンモニウムクロライド(CTAC)、クエン酸、エチレンジアミン四酢酸、ビス(2-エチルへキシル)スルホン酸ナトリウム(AOT)、セチルトリメチルアンモニウムブロミド(CTAB)、ポリビニルピロリドン、ポリアクリル酸、ポリビニルアルコール、ポリエチレングリコール等が挙げられる。 In order to improve the dispersibility of the cupric oxide nanoparticles in the sintered bonding agent, a dispersant may be added. At this time, the dispersant is preferably one that has little influence during sintering joining (one with little residue). For example, sodium dodecyl sulfate, cetyltrimethylammonium chloride (CTAC), citric acid, ethylenediaminetetraacetic acid, sodium bis (2-ethylhexyl) sulfonate (AOT), cetyltrimethylammonium bromide (CTAB), polyvinylpyrrolidone, polyacrylic acid , Polyvinyl alcohol, polyethylene glycol and the like.
 分散剤はナノ粒子の分散性を向上させる程度に混ぜればよく、酸化第二銅100質量部に対して分散剤30質量部以下が好適である。それよりも多く添加すると、接合層中に残渣が残りやすく接合強度を低下させる要因となる。 The dispersant may be mixed to such an extent that the dispersibility of the nanoparticles is improved, and 30 parts by mass or less of the dispersant is preferable with respect to 100 parts by mass of cupric oxide. If it is added more than that, a residue is likely to remain in the bonding layer, which causes a decrease in bonding strength.
 (焼結接合剤の性状)
 酸化第二銅ナノ粒子の1次粒子径は2~50 nmが好ましく、8~18 nmがより好ましい。1次粒子径が2 nm未満になると、表面の化学活性度が高くなり過ぎて2次粒子(凝集体)の制御が困難になる。また、粒子径が50 nm超の1次粒子は、上述の合成法での作製が困難であるとともに、表面の化学活性度が低くなり過ぎて2次粒子(凝集体)の制御が困難になる。1次粒子径が8~18 nmの場合、より均一な2次粒子(凝集体)を形成することが可能になり、その結果、強固な接合を得ることができる。
(Properties of sintered bonding agent)
The primary particle size of the cupric oxide nanoparticles is preferably 2 to 50 nm, more preferably 8 to 18 nm. When the primary particle diameter is less than 2 nm, the chemical activity of the surface becomes too high, and it becomes difficult to control the secondary particles (aggregates). In addition, primary particles having a particle size of more than 50 nm are difficult to produce by the above-described synthesis method, and the chemical activity of the surface becomes too low to control secondary particles (aggregates). . When the primary particle diameter is 8 to 18 nm, more uniform secondary particles (aggregates) can be formed, and as a result, a strong bond can be obtained.
 なお、1次粒子の形状としては、真球体状である必要はなく楕円球体状や多面体状であってもよい。また、粒子形状が楕円球体状や多面体状である場合の粒子径は、粒子の長軸径と短軸径とから楕円球体の体積を求め、これと等しい体積を有する球体の径(換算径)とする(長軸の長さ×短軸の長さの2乗=換算径の3乗)。また、1次粒子は、単結晶子から構成される場合と複数の結晶子から構成される場合とがある。 The shape of the primary particles need not be a true sphere, but may be an elliptical sphere or a polyhedron. In addition, when the particle shape is an ellipsoidal shape or a polyhedral shape, the volume of the ellipsoidal sphere is obtained from the major axis diameter and minor axis diameter of the particle, and the diameter of the sphere having the same volume (converted diameter) (The length of the long axis x the square of the length of the short axis = the cube of the converted diameter). Further, the primary particle may be composed of a single crystallite or a plurality of crystallites.
 本発明に係る焼結接合剤は、上述の1次粒子が凝集して2次粒子(凝集体)を形成し、該凝集体が均一分散していることに最大の特徴がある。なお、凝集体とは、1次粒子同士が相互に融合もしくは接触した集合体と定義する。凝集体の長軸長さと短軸長さとの相加平均を凝集体サイズと定義すると、凝集体サイズとしては、3 nm以上1000 nm以下が好ましい。凝集体サイズが1000 nm超になると、分散性が低下し焼結接合剤としての安定性が劣化する。また、凝集体の長軸長と短軸長とのアスペクト比は、1以上3以下であることが好ましい。凝集体のアスペクト比が3より大きくなると、接合時の緻密性が悪くなり接合強度の低下を招く。上記のようにナノ粒子からなる1次粒子を凝集させることで、従来技術のようなナノ粒子単体(1次粒子)を分散させた接合剤よりも、接合層の緻密性を向上させることが可能となり、より強固な接合強度を得ることができる。 The sintered bonding agent according to the present invention is characterized in that the primary particles described above aggregate to form secondary particles (aggregates), and the aggregates are uniformly dispersed. Aggregates are defined as aggregates in which primary particles are fused or in contact with each other. When the arithmetic average of the major axis length and the minor axis length of the aggregate is defined as the aggregate size, the aggregate size is preferably 3 to 1000 nm. When the aggregate size exceeds 1000 nm, the dispersibility decreases and the stability as a sintered bonding agent deteriorates. The aspect ratio of the major axis length to the minor axis length of the aggregate is preferably 1 or more and 3 or less. When the aspect ratio of the aggregate is larger than 3, the denseness at the time of bonding deteriorates and the bonding strength is reduced. By agglomerating primary particles composed of nanoparticles as described above, it is possible to improve the denseness of the bonding layer as compared with a bonding agent in which single nanoparticles (primary particles) as in the prior art are dispersed. Thus, a stronger bonding strength can be obtained.
 1次粒子が単結晶子から構成される場合には、凝集体サイズは50 nm以上800 nm以下がより好ましい。一方、1次粒子が複数の結晶子から構成される場合には、凝集体サイズは10 nm以上100 nm以下がより好ましい。このように、より好ましい凝集体サイズが異なるメカニズムは未だ解明されていないが、酸化銅が金属銅に還元されて焼結する過程が関連しているものと考えられる。焼結接合過程において、酸化銅粒子は、一旦多結晶化を経てから金属銅に還元され、その後焼結する。そのため、単結晶子から構成される1次粒子(すなわち、結晶子径が大きい粒子)は、複数の結晶子に再配列しながら還元されるため、より多くのエネルギーを要すると考えられる。一方、複数の結晶子から構成される1次粒子(すなわち、結晶子径が小さい粒子)は、比較的少ないエネルギーで還元が進行すると考えられる。 When the primary particles are composed of single crystallites, the aggregate size is more preferably from 50 nm to 800 nm. On the other hand, when the primary particles are composed of a plurality of crystallites, the aggregate size is more preferably 10 to 100 nm. Thus, although the mechanism by which a more preferable aggregate size differs is not yet elucidated, it is thought that the process in which copper oxide is reduced to metallic copper and sintered is related. In the sintering joining process, the copper oxide particles are once polycrystallized, then reduced to metallic copper, and then sintered. For this reason, primary particles composed of single crystallites (that is, particles having a large crystallite diameter) are reduced while rearranging to a plurality of crystallites, and thus it is considered that more energy is required. On the other hand, primary particles composed of a plurality of crystallites (that is, particles having a small crystallite diameter) are considered to proceed with reduction with relatively little energy.
 1次粒子や2次粒子の観察は、電子顕微鏡(例えば、透過型電子顕微鏡)を用いて行うことができる。また、結晶子径の測定は、X線回折法により得られるピークからシェラー式を用いて算出することができる。測定された結晶子径が、観察された1次粒子の長軸径以上であった場合、その1次粒子は単結晶子から構成されていると判定することができる。一方、測定された結晶子径が、観察された1次粒子の長軸径未満であった場合、その1次粒子は複数の単結晶子から構成されていると判定することができる。 Observation of primary particles and secondary particles can be performed using an electron microscope (for example, a transmission electron microscope). The crystallite diameter can be calculated from the peak obtained by the X-ray diffraction method using the Scherrer equation. When the measured crystallite diameter is not less than the major axis diameter of the observed primary particles, it can be determined that the primary particles are composed of single crystallites. On the other hand, when the measured crystallite diameter is less than the observed major axis diameter of the primary particles, it can be determined that the primary particles are composed of a plurality of single crystallites.
 (焼結熱処理)
 本発明に係る焼結接合剤に対する焼結熱処理としては、還元雰囲気中100~500℃の温度で熱処理を施すことが好ましい。また、還元雰囲気としては特段に限定されるものではないが、例えば、水素雰囲気やギ酸雰囲気、エタノール雰囲気などが好適である。
(Sintering heat treatment)
As the sintering heat treatment for the sintered binder according to the present invention, it is preferable to perform the heat treatment at a temperature of 100 to 500 ° C. in a reducing atmosphere. Further, the reducing atmosphere is not particularly limited, but for example, a hydrogen atmosphere, a formic acid atmosphere, an ethanol atmosphere, or the like is preferable.
 以下、本発明を実施例により具体的に説明するが、本発明はこれらの記載に限定されるものではない。 Hereinafter, the present invention will be specifically described by way of examples, but the present invention is not limited to these descriptions.
 (酸化銅ナノ粒子の作製)
 原料銅化合物としてCu(NO3)2・3H2O粉末を用い、溶媒として水を用い、酸化第二銅ナノ粒子の析出剤としてNaOHを用いた。容積1000 mLのビーカーにて30分間の窒素バブリングを行った蒸留水985 mLに対し、銅イオン濃度が0.01 mol/LとなるようにCu(NO3)2・3H2O粉末を加え、20~80℃のウォーターバス中で均一に溶解させた。その後、1.0 mol/mLのNaOH水溶液(15 mL)を滴下することで、酸化第二銅ナノ粒子コロイドを合成した。
(Preparation of copper oxide nanoparticles)
Cu (NO 3 ) 2 .3H 2 O powder was used as a raw material copper compound, water was used as a solvent, and NaOH was used as a precipitant for cupric oxide nanoparticles. Add Cu (NO 3 ) 2 · 3H 2 O powder so that the copper ion concentration becomes 0.01 mol / L to 985 mL of distilled water with nitrogen bubbling for 30 minutes in a beaker with a volume of 1000 mL. It was dissolved uniformly in a water bath at 80 ° C. Then, cupric oxide nanoparticle colloid was synthesize | combined by dripping 1.0 mol / mL NaOH aqueous solution (15 mL).
 室温で24時間攪拌した後、合成した酸化第二銅粒子の遠心分離(遠心洗浄機:株式会社トミー精工、Suprema21)と洗浄作業とを3回ずつ行った。その後、酸化第二銅粒子を取り出して乾燥し、0.085 gの酸化第二銅粒子(試料1~7)を得た。 After stirring at room temperature for 24 hours, the synthesized cupric oxide particles were centrifuged (centrifugal washing machine: Tommy Seiko Co., Ltd., Suprema 21) and washing operations three times each. Thereafter, the cupric oxide particles were taken out and dried to obtain 0.085 g of cupric oxide particles (samples 1 to 7).
 (酸化銅ナノ粒子の性状調査)
 作製した酸化第二銅粒子(試料1~7)に対し、透過型電子顕微鏡(日本電子株式会社製、JEM-2000FX II)を用いて1次粒子サイズと凝集体サイズとを観察・測定した。また、X線回折装置(株式会社リガク製、RU200B)を用いて1次粒子を構成する結晶子径を測定した(スキャン速度=2 deg/min)。結晶子径は、XRD回折パターンにおける酸化第二銅の(002)面と(-111)面とのピークからシェラー式を用いて算出した。試料1~7における1次粒子と凝集体の性状を表1にまとめ、1次粒子の長軸径と結晶子径との関係を図2に示した。
(Investigation of properties of copper oxide nanoparticles)
With respect to the prepared cupric oxide particles (samples 1 to 7), the primary particle size and the aggregate size were observed and measured using a transmission electron microscope (JEM-2000FX II, manufactured by JEOL Ltd.). Moreover, the crystallite diameter which comprises a primary particle was measured using the X-ray-diffraction apparatus (Rigaku Corporation make, RU200B) (scanning speed = 2deg / min). The crystallite diameter was calculated using the Scherrer equation from the peaks of the (002) plane and the (-111) plane of cupric oxide in the XRD diffraction pattern. The properties of the primary particles and aggregates in Samples 1 to 7 are summarized in Table 1, and the relationship between the major axis diameter of the primary particles and the crystallite diameter is shown in FIG.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001

 表1および図2に示したように、試料1~4(20~50℃で合成した粒子)は、結晶子径が1次粒子の長軸径以上であり、1次粒子が単結晶子から構成されていることが判った。
一方、試料5~7(60~80℃で合成した粒子)は、結晶子径が1次粒子の長軸径よりも短く、1次粒子が複数の結晶子から構成されていることが判った。

As shown in Table 1 and FIG. 2, Samples 1 to 4 (particles synthesized at 20 to 50 ° C.) have a crystallite diameter larger than the major axis diameter of the primary particles, and the primary particles are made from a single crystallite. It turns out that it is composed.
On the other hand, Samples 5 to 7 (particles synthesized at 60 to 80 ° C.) had a crystallite diameter shorter than the major axis diameter of the primary particles, and the primary particles were composed of a plurality of crystallites. .
 (酸化銅ナノ粒子の分散性調査)
 作製した酸化第二銅粒子(試料1~7)の分散性を調査した。比較のため、市販の酸化第二銅ナノ粒子(シグマ アルドリッチ ジャパン株式会社製、製品番号544868-25G、粒径50 nm以下)を比較試料1として用いた。また、粒径がμmオーダーの市販の酸化第二銅粒子(和光純薬工業株式会社製、製品番号036-14792)に対し、特許文献4に記載された手法に従って分散剤(ディスパービック)を添加したものを比較試料2として用いた。試験方法は、分散媒として水を用い、分散媒中に粒子を投入してよく撹拌した後、静置して分散の様子を目視で観察した。結果を表2に示す。
(Dispersibility investigation of copper oxide nanoparticles)
The dispersibility of the prepared cupric oxide particles (samples 1 to 7) was investigated. For comparison, commercially available cupric oxide nanoparticles (manufactured by Sigma Aldrich Japan, product number 544868-25G, particle size of 50 nm or less) were used as comparative sample 1. Also, a dispersant (dispervic) is added to commercially available cupric oxide particles having a particle size of μm order (product number 036-14792 manufactured by Wako Pure Chemical Industries, Ltd.) according to the technique described in Patent Document 4. This was used as Comparative Sample 2. In the test method, water was used as a dispersion medium, and the particles were put into the dispersion medium and stirred well, and then allowed to stand to visually observe the state of dispersion. The results are shown in Table 2.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002

 表2に示したように、比較試料1は、静置後5分でほぼ沈殿した。また、比較試料2は、分散性がよく静置後1日を経ても沈殿が見られなかったが、これは分散剤を添加したことによる効果と考えられた。一方、作製した酸化第二銅粒子(試料1~7)は、分散剤を添加していないにもかかわらず、静置後1日を経ても良好な分散状態を維持した。これは本発明の酸化第二銅粒子がナノ粒子の凝集体であることによって、分散性が向上したことを示している。すなわち、本発明で得られた粒子は、従来技術のように分散剤を用いなくても分散媒中における分散性が優れた粒子であることが確認された。

As shown in Table 2, Comparative Sample 1 almost precipitated in 5 minutes after standing. Further, Comparative Sample 2 had good dispersibility, and no precipitation was observed even after 1 day after standing, but this was considered to be an effect of adding a dispersant. On the other hand, the prepared cupric oxide particles (Samples 1 to 7) maintained a good dispersion state even after one day after standing, although no dispersant was added. This indicates that the dispersibility is improved by the cupric oxide particles of the present invention being an aggregate of nanoparticles. That is, it was confirmed that the particles obtained in the present invention were excellent in dispersibility in a dispersion medium without using a dispersant as in the prior art.
 (焼結接合剤の接合強度試験)
 電子部材同士の接合を模擬して接合強度試験を実施した。試験方法は次のとおりである。各焼結接合剤は、前述した試料1~7および比較試料1~2のそれぞれを含有率が90質量%になるように水中に投入し、よく撹拌した状態で用意した。測定用に用いた銅試験片としては、直径10 mm・厚さ5 mmの下側試験片と、直径5 mm・厚さ2 mmの上側試験片とを用いた。
(Joint strength test of sintered bonding agent)
A joining strength test was conducted by simulating joining between electronic members. The test method is as follows. Each sintered bonding agent was prepared by adding each of Samples 1 to 7 and Comparative Samples 1 and 2 described above into water so that the content was 90% by mass and well stirred. As a copper test piece used for the measurement, a lower test piece having a diameter of 10 mm and a thickness of 5 mm and an upper test piece having a diameter of 5 mm and a thickness of 2 mm were used.
 下側試験片上に用意した焼結接合剤を塗布し、80℃で1時間減圧乾燥させた後、乾燥した焼結接合剤の上に上側試験片を設置し、水素中400℃の温度で5分間の焼結熱処理を行った。このとき、面圧1.2 MPaの荷重を同時に加えた。剪断試験機(西進商事株式会社製、ボンドテスターSS-100KP、最大荷重100 kg)を用いて、接合させた試験片に剪断応力を負荷し(剪断速度30 mm/min)、破断時の最大荷重を測定した。最大荷重を接合面積で除して接合強度を求めた。さらに、比較試料1の接合強度で規格化して各焼結接合剤の規格化接合強度を算出した。 After applying the prepared sintered binder on the lower test piece and drying under reduced pressure at 80 ° C for 1 hour, the upper test piece was placed on the dried sintered bond, and the temperature was increased to 400 ° C in hydrogen. A sintering heat treatment was performed for a minute. At this time, a load with a surface pressure of 1.2 MPa was simultaneously applied. Using a shear tester (made by Seishin Shoji Co., Ltd., Bond Tester SS-100KP, maximum load 100 kg), shear stress was applied to the bonded specimens (shear rate 30 mm / min), and maximum load at break Was measured. The bonding strength was determined by dividing the maximum load by the bonding area. Furthermore, it normalized with the joint strength of the comparative sample 1, and calculated the normalization joint strength of each sintering joining agent.
 試料1~7における規格化接合強度の結果を表1に併記し、凝集体サイズと規格化接合強度との関係を図3に示す。図3に示したように、本発明の焼結接合剤は、酸化第二銅ナノ粒子の凝集体が大きくなると接合強度が高くなることが判った。焼結接合剤としてナノ粒子の凝集体を分散させることによって、接合層における緻密性が向上しやすく接合強度が向上したものと考えられる。また、試料1,2,5においては、良好な分散性に加えて、比較試料1よりも高い接合強度が得られることが確認された。 The results of the normalized bonding strength for samples 1 to 7 are also shown in Table 1, and the relationship between the aggregate size and the normalized bonding strength is shown in FIG. As shown in FIG. 3, it was found that the bonding strength of the sintered bonding agent of the present invention increases as the aggregate of cupric oxide nanoparticles increases. It is considered that by dispersing nanoparticle aggregates as a sintered bonding agent, the denseness in the bonding layer is easily improved and the bonding strength is improved. In addition, in Samples 1, 2, and 5, it was confirmed that a bonding strength higher than that of Comparative Sample 1 was obtained in addition to good dispersibility.
 (凝集体アスペクト比と接合強度との関係)
 酸化第二銅ナノ粒子の合成時における銅イオン量[Cu2+]に対するアルカリイオン量[OH-]のモル比([OH-]/[Cu2+])を変化させて得られる凝集体のアスペクト比を変化させ、接合強度との関係を調査した。酸化第二銅ナノ粒子の合成・性状調査は実施例1と同様に行い、接合強度試験は実施例3と同様の方法で行った。合成温度は20℃とした。作製した試料8~15の性状を表3にまとめ、凝集体アスペクト比と規格化接合強度との関係を図4に示す。
(Relationship between aggregate aspect ratio and bonding strength)
The molar ratio of - alkali ion content of the copper ion content [Cu 2+] in the synthesis of cupric oxide nanoparticles [OH] ([OH -] / [Cu 2+]) to change the by aggregates obtained The relationship with the bonding strength was investigated by changing the aspect ratio. The synthesis and properties of cupric oxide nanoparticles were examined in the same manner as in Example 1, and the bonding strength test was conducted in the same manner as in Example 3. The synthesis temperature was 20 ° C. The properties of the produced samples 8 to 15 are summarized in Table 3, and the relationship between the aggregate aspect ratio and the normalized bonding strength is shown in FIG.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003

 表3および図4に示したように、凝集体アスペクト比が「1.5~3.0」の範囲においては「1」よりも高い規格化接合強度が得られたが、凝集体アスペクト比が「3.0」以上になると規格化接合強度の低下が見られた。これは、凝集体アスペクト比が大きくなると接合層の緻密性が低下しやすくなるためと考えられた。上記の結果から、酸化第二銅ナノ粒子の凝集体アスペクト比は3.0より低い方が良好な接合が得られることが判った。

As shown in Table 3 and FIG. 4, a standardized bonding strength higher than “1” was obtained when the aggregate aspect ratio was in the range of “1.5 to 3.0”, but the aggregate aspect ratio was “3.0” or more. As a result, a decrease in normalized bonding strength was observed. This is thought to be because the denseness of the bonding layer tends to decrease as the aggregate aspect ratio increases. From the above results, it was found that better bonding is obtained when the aggregate aspect ratio of cupric oxide nanoparticles is lower than 3.0.
 (酸化銅ナノ粒子合成時の洗浄回数と接合強度との関係)
 酸化銅ナノ粒子合成時における遠心分離後の洗浄回数と接合強度との関係を調査した。酸化銅ナノ粒子の合成は実施例1と同様に行い(合成温度20℃)、接合強度試験は実施例3と同様の方法で行った。
(Relationship between cleaning frequency and bonding strength during copper oxide nanoparticle synthesis)
The relationship between the number of washings after centrifugation during the synthesis of copper oxide nanoparticles and the bonding strength was investigated. The synthesis of the copper oxide nanoparticles was performed in the same manner as in Example 1 (synthesis temperature 20 ° C.), and the bonding strength test was performed in the same manner as in Example 3.
 図5は、洗浄回数と規格化接合強度との関係、および洗浄回数と乾燥粉末中の酸化銅第二銅ナノ粒子の含有率との関係を示すグラフである。図5に示したように、遠心洗浄回数を増やすことで規格化接合強度が向上するとともに、乾燥粉末中の酸化第二銅ナノ粒子の含有率が増加した。特に、酸化第二銅ナノ粒子の含有率が90質量%以上になると規格化接合強度が「1」を超えた。これは、遠心洗浄によって酸化銅ナノ粒子合成時の不純物が取り除かれたためと考えられた。上記の結果から、接合強度を向上させるためには、酸化銅ナノ粒子合成時に遠心洗浄を行うことが好ましく、乾燥粉末中の酸化第二銅ナノ粒子の含有率を90質量%以上とすることが好ましいことが確認された。 FIG. 5 is a graph showing the relationship between the number of washings and the normalized bonding strength, and the relationship between the number of washings and the content of cupric oxide nanoparticles in the dry powder. As shown in FIG. 5, the normalized bonding strength was improved by increasing the number of times of centrifugal cleaning, and the content of cupric oxide nanoparticles in the dry powder increased. In particular, when the content of cupric oxide nanoparticles was 90% by mass or more, the normalized bonding strength exceeded “1”. This was thought to be because impurities during the synthesis of copper oxide nanoparticles were removed by centrifugal washing. From the above results, in order to improve the bonding strength, it is preferable to perform centrifugal cleaning at the time of copper oxide nanoparticle synthesis, and the content of cupric oxide nanoparticles in the dry powder may be 90% by mass or more. It was confirmed that it was preferable.
 (冷却ユニットへの適用)
 半導体パワーモジュールのピンフィン冷却ユニットのピン接続に本発明を適用する例を示す。半導体パワーモジュールは、近年、発熱量が増加傾向にあるため、動作時に発生する熱を該モジュールの外へ効率良く放散させる技術がますます重要になっている。
(Application to cooling unit)
The example which applies this invention to the pin connection of the pin fin cooling unit of a semiconductor power module is shown. In recent years, semiconductor power modules have a tendency to increase the amount of heat generated, and therefore, technology for efficiently dissipating heat generated during operation to the outside of the module has become increasingly important.
 図6は、半導体パワーモジュールを搭載する配線基板とピンフィン冷却ユニットの1例を示す断面模式図である。図6に示すように、配線基板14は、半導体チップと接続される回路配線11と、モジュール内部で半導体チップと回路配線11とを電気的に絶縁するための絶縁基板12と、絶縁基板12とピンフィン冷却ユニット111とを金属支持板101にはんだ付けするためのメタライズ層13とが積層された構造をしている。また、ピンフィン冷却ユニット111は、金属支持板101に多数のピンフィン201が接合層100を介して接合された構造をしている。半導体パワーモジュールで発生した熱は配線基板14の厚さ方向に伝熱され、最終的な放熱は金属支持板101に取り付けられたピンフィン201を介してなされる。 FIG. 6 is a schematic cross-sectional view showing an example of a wiring board on which a semiconductor power module is mounted and a pin fin cooling unit. As shown in FIG. 6, the wiring substrate 14 includes a circuit wiring 11 connected to the semiconductor chip, an insulating substrate 12 for electrically insulating the semiconductor chip and the circuit wiring 11 inside the module, A metallization layer 13 for soldering the pin fin cooling unit 111 to the metal support plate 101 is laminated. The pin fin cooling unit 111 has a structure in which a large number of pin fins 201 are bonded to the metal support plate 101 via the bonding layer 100. The heat generated in the semiconductor power module is transferred in the thickness direction of the wiring board 14, and the final heat dissipation is performed via the pin fins 201 attached to the metal support plate 101.
 ピンフィン冷却ユニット111の金属支持板101やピンフィン201は、通常、銅で構成されている。従来、金属支持板101とピンフィン201との接合は、銀ろう材を用いて800℃以上の温度で行われていた。そのため、金属支持板101やピンフィン201が軟化してしまい、機械的強度が低下して変形し易いという問題があった。 The metal support plate 101 and the pin fin 201 of the pin fin cooling unit 111 are usually made of copper. Conventionally, the joining of the metal support plate 101 and the pin fins 201 has been performed at a temperature of 800 ° C. or higher using a silver brazing material. Therefore, the metal support plate 101 and the pin fins 201 are softened, and there is a problem that the mechanical strength is reduced and the metal support plate 101 and the pin fins 201 are easily deformed.
 そこで、実施例1の試料1を水に分散させた焼結接合剤を用いて、金属支持板101とピンフィン201との接合を行った。焼結熱処理は、1.2 MPaの加圧をしながら水素中400℃の温度で行った。銅の軟化温度よりも低い温度での接合が可能となり、銅が軟化してしまう問題を解決することができた。 Therefore, the metal support plate 101 and the pin fin 201 were joined using a sintered joining agent in which the sample 1 of Example 1 was dispersed in water. The sintering heat treatment was performed at a temperature of 400 ° C. in hydrogen while applying a pressure of 1.2 μM. Joining at a temperature lower than the softening temperature of copper was possible, and the problem of copper softening could be solved.
 (半導体装置への適用)
 図7は、本発明を適用した絶縁型半導体装置を示した模式図であり、(a)は平面図、(b)は(a)のA-A断面図である。図8は、図7の要部を示した斜視模式図である。図9は、図7の半導体素子搭載部分を拡大して示した断面模式図である。以下、図7~9を参照しながら絶縁型半導体装置への適用について説明する。
(Application to semiconductor devices)
7A and 7B are schematic views showing an insulating semiconductor device to which the present invention is applied, in which FIG. 7A is a plan view and FIG. 7B is a cross-sectional view taken along line AA of FIG. FIG. 8 is a schematic perspective view showing the main part of FIG. FIG. 9 is an enlarged schematic cross-sectional view showing the semiconductor element mounting portion of FIG. Hereinafter, application to an insulating semiconductor device will be described with reference to FIGS.
 セラミックス絶縁基板303と配線層302とからなる配線基板は、はんだ層309を介して支持部材310に接合されている。配線層302は銅配線にニッケルめっきが施されたものである。半導体素子301のコレクタ電極307とセラミックス絶縁基板303上の配線層302とが、本発明に係る焼結接合剤によって形成された接合層305(接合後は純銅層化)を介して接合されている。また、実施例1の20℃で作製した酸化銅粒子使用接合材305(接合後は純銅層化)は、半導体素子301のエミッタ電極306と接続用端子401とが、本発明に係る焼結接合剤によって形成された接合層305(接合後は純銅層化)を介して接合されている。 A wiring board composed of the ceramic insulating substrate 303 and the wiring layer 302 is joined to the support member 310 via the solder layer 309. The wiring layer 302 is obtained by applying nickel plating to a copper wiring. The collector electrode 307 of the semiconductor element 301 and the wiring layer 302 on the ceramic insulating substrate 303 are joined via a joining layer 305 (pure copper layer after joining) formed by the sintered joining agent according to the present invention. . In addition, the copper oxide particle-using bonding material 305 (pure copper layered after bonding) produced in Example 1 at 20 ° C. has the emitter electrode 306 of the semiconductor element 301 and the connection terminal 401 in a sintered bonding according to the present invention. Bonding is performed via a bonding layer 305 (pure copper layering after bonding) formed by an agent.
 さらに、接続用端子401とセラミックス絶縁基板303上の配線層304とが、本発明に係る焼結接合剤によって形成された接合層305(接合後は純銅層化)を介して接合されている。接合層305は厚さ80μmである。コレクタ電極307表面とエミッタ電極306表面には、ニッケルメッキが施されている。また、接続用端子401はCuまたはCu合金で構成されている。なお、図7における他の符号は、それぞれ、ケース311、外部端子312、ボンディングワイヤ313、封止材314を示している。 Furthermore, the connection terminal 401 and the wiring layer 304 on the ceramic insulating substrate 303 are joined via a joining layer 305 (pure copper layer after joining) formed by the sintered joining agent according to the present invention. The bonding layer 305 has a thickness of 80 μm. Nickel plating is applied to the surfaces of the collector electrode 307 and the emitter electrode 306. The connection terminal 401 is made of Cu or a Cu alloy. 7 denote the case 311, the external terminal 312, the bonding wire 313, and the sealing material 314, respectively.
 接合層305の形成は、例えば、本発明に係る酸化銅第二銅ナノ粒子の凝集体を90質量%含みかつ水を10質量%含んだ焼結接合剤を接合する部材の接合面に塗布し、80℃で1時間乾燥した後、1.0 MPaの圧力を加えながら水素中350℃で1分間の焼結熱処理を施すことにより可能である。接合にあたって、超音波振動を加えてもよい。また、接合層305の形成は、それぞれ個別に行ってもよいし、同時に行ってもよい。 The bonding layer 305 is formed by, for example, applying a sintered bonding agent containing 90% by mass of the cupric oxide nanoparticle aggregate and 10% by mass of water according to the present invention to the bonding surface of the member to be bonded. After drying at 80 ° C. for 1 hour, sintering heat treatment at 350 ° C. for 1 minute in hydrogen while applying a pressure of 1.0 kg MPa is possible. In joining, ultrasonic vibration may be applied. Further, the bonding layer 305 may be formed individually or simultaneously.
 (多層配線基板への適用)
 本実施例では、部品内蔵型の多層配線基板への適用について説明する。図10Aは、部品内蔵型の多層配線基板の内蔵されるコンデンサの断面模式図である。コンデンサ803は、電極としてメタライズ層802が形成され、メタライズ層802の外層に銅めっき層801が形成されている。図10Bは、部品内蔵型の多層配線基板の内蔵されるLSIチップの断面模式図である。LSIチップ804は、電極上にバンプ805が設けられており、バンプ805の外層に銅めっき層806が形成されている。図10Cは、部品内蔵型の多層配線基板のコア層部分の断面模式図である。コア807の厚さ方向の導通は、スルーホール808の表面配線809によりなされる。プリプレグ810の厚さ方向の導通は、表面に銅めっき層811を有するバンプ状の812によりなされる。また、表面配線809上に銅めっき層811が設けられていてもよい。
(Application to multilayer wiring board)
In this embodiment, application to a component-embedded multilayer wiring board will be described. FIG. 10A is a schematic cross-sectional view of a capacitor incorporated in a component-embedded multilayer wiring board. In the capacitor 803, a metallized layer 802 is formed as an electrode, and a copper plating layer 801 is formed on the outer layer of the metallized layer 802. FIG. 10B is a schematic cross-sectional view of an LSI chip embedded in a component-embedded multilayer wiring board. In the LSI chip 804, bumps 805 are provided on the electrodes, and a copper plating layer 806 is formed on the outer layer of the bumps 805. FIG. 10C is a schematic cross-sectional view of a core layer portion of a component-embedded multilayer wiring board. Conduction in the thickness direction of the core 807 is performed by the surface wiring 809 of the through hole 808. Conduction in the thickness direction of the prepreg 810 is performed by a bump-like 812 having a copper plating layer 811 on the surface. Further, a copper plating layer 811 may be provided on the surface wiring 809.
 図11は、本発明を適用した部品内蔵型多層配線基板の1例を示す断面模式図である。図12は、本発明を適用した部品内蔵型多層配線基板の他の1例を示す断面模式図である。図13は、本発明を適用した部品内蔵型多層配線基板の更に他の1例を示す断面模式図である。 FIG. 11 is a schematic cross-sectional view showing an example of a component built-in multilayer wiring board to which the present invention is applied. FIG. 12 is a schematic cross-sectional view showing another example of a component built-in multilayer wiring board to which the present invention is applied. FIG. 13 is a schematic cross-sectional view showing still another example of a component built-in multilayer wiring board to which the present invention is applied.
 コンデンサ803、LSIチップ804、貫通配線812、表面配線809間のそれぞれの接合は、本発明に係る焼結接合剤を銅めっき層801,806,811上に塗布・乾燥した後、ギ酸雰囲気中での焼結熱処理により形成される焼結銅層813を介してなされる。なお、それぞれの接合箇所以外の焼結銅層814はプリプレグ810と密着している。また、本発明を適用した部品内蔵型多層配線基板は、図12に示すように電子部品(例えばコンデンサ803)を垂直方向に接続したり、図13に示すように水平方向に接続したりすることで、積層配線基板の投影面積を最小にしたり厚さを最小にしたりすることができ、設計の自由度が高い。さらに、本発明に係る焼結接合剤を用いて形成した焼結銅層813は、厚さが薄いことから電気信号の遅延を抑制した接合が可能である。 Each of the capacitors 803, the LSI chip 804, the through wiring 812, and the surface wiring 809 is bonded to the copper plating layers 801, 806, 811 by applying the sintered bonding agent according to the present invention, and then dried in a formic acid atmosphere. This is done through a sintered copper layer 813 formed by the sintering heat treatment. It should be noted that the sintered copper layer 814 other than the respective joint portions is in close contact with the prepreg 810. Also, in the component built-in type multilayer wiring board to which the present invention is applied, an electronic component (for example, a capacitor 803) is connected in the vertical direction as shown in FIG. 12, or is connected in the horizontal direction as shown in FIG. Thus, the projected area of the multilayer wiring board can be minimized or the thickness can be minimized, and the degree of freedom in design is high. Furthermore, since the sintered copper layer 813 formed using the sintered bonding agent according to the present invention is thin, it is possible to perform bonding while suppressing delay of the electric signal.
 (積層チップへの適用)
 本実施例では、積層チップへの適用について説明する。図14は、本発明を適用した積層チップの1例を示す断面模式図である。半導体素子901には、絶縁層902を介して貫通電極903が形成されている。貫通電極903の一方の面には銅メタライズ層904が設けられており、これに本発明に係る焼結接合剤を塗布・乾燥した後、水素中300℃の焼結熱処理により形成された焼結銅からなる接合層905を介して、複数の半導体素子が積層されている。
(Application to multilayer chip)
In this embodiment, application to a multilayer chip will be described. FIG. 14 is a schematic cross-sectional view showing an example of a laminated chip to which the present invention is applied. A through electrode 903 is formed in the semiconductor element 901 with an insulating layer 902 interposed therebetween. A copper metallized layer 904 is provided on one surface of the through electrode 903, and the sintered bonding agent according to the present invention is applied and dried on this surface, and then sintered by heat treatment at 300 ° C. in hydrogen. A plurality of semiconductor elements are stacked via a bonding layer 905 made of copper.
 貫通電極の素材が銅ではない場合(例えば、アルミニウムの場合)、貫通電極上にニッケルめっき層を形成し、その上に銅めっき層を形成することで本発明に係る焼結接合剤を用いた接合が可能である。半導体素子906は、そのような構成によって貫通電極の両面にCuメタライズ層907が形成されており、該Cuメタライズ層907上に形成された本発明に係る焼結接合剤を用いた接合層905を介して、インターポーザ908の電極909と接合されている。なお、インターポーザ908との接合は、ろう付けや圧着であっても構わない。また、インターポーザ908に設けられたバンプ910と回路基板との接合に関しても、本発明を適用してもよいし、従前の接合方法を適用してもよい。 When the material of the through electrode is not copper (for example, in the case of aluminum), a nickel plating layer is formed on the through electrode, and the copper plating layer is formed thereon, thereby using the sintered bonding agent according to the present invention. Joining is possible. The semiconductor element 906 has a Cu metallized layer 907 formed on both sides of the through electrode with such a configuration, and the bonding layer 905 using the sintered bonding agent according to the present invention formed on the Cu metallized layer 907 is formed. Via the electrode 909 of the interposer 908. The joining with the interposer 908 may be brazing or pressure bonding. Further, the present invention may be applied to the bonding between the bump 910 provided on the interposer 908 and the circuit board, or a conventional bonding method may be applied.
 11…回路配線、12…絶縁基板、13…メタライズ層、14…配線基板、100…接合層、101…金属支持板、111…ピンフィン冷却ユニット、201…ピンフィン、301…半導体素子、302,304…配線層、303…セラミックス絶縁基板、305…接合層、306…エミッタ電極、307… コレクタ電極、309…はんだ層、310…支持部材、311…ケース、312…外部端子、313…ボンディングワイヤ、314…封止材、401…接続用端子、801,806,811…銅めっき層、802…メタライズ層、803…コンデンサ、804…LSIチップ、805…バンプ、807…コア、808…スルーホール、809…表面配線、810…プリプレグ、812…貫通電極、813,814…焼結銅層、901,906…半導体素子、902…絶縁層、903…貫通電極、904,907…銅メタライズ層、905…接合層、908…インターポーザ、909…電極、910…バンプ。 11 ... Circuit wiring, 12 ... Insulating substrate, 13 ... Metallized layer, 14 ... Wiring substrate, 100 ... Bonding layer, 101 ... Metal support plate, 111 ... Pin fin cooling unit, 201 ... Pin fin, 301 ... Semiconductor element, 302, 304 ... Wiring layer, 303 ... ceramic insulating substrate, 305 ... bonding layer, 306 ... emitter electrode, 307 ... collector electrode, 309 ... solder layer, 310 ... support member, 311 ... case, 312 ... external terminal, 313 ... bonding wire, 314 ... Sealing material, 401 ... Connection terminal, 801, 806, 811 ... Copper plating layer, 802 ... Metallized layer, 803 ... Capacitor, 804 ... LSI chip, 805 ... Bump, 807 ... Core, 808 ... Through hole, 809 ... Surface 810 ... prepreg, 812 ... through electrode, 813,814 ... sintered copper layer, 901,906 ... semiconductor element, 902 ... insulating layer, 903 ... through electrode, 904,907 ... copper metallized layer, 905 ... joining layer, 908 ... interposer, 909 ... electrode, 910 ... bump.

Claims (11)

  1.  酸化第二銅ナノ粒子を用いた焼結接合剤であって、
    粒径2 nm以上50 nm以下の前記酸化第二銅ナノ粒子を1次粒子として用い、
    前記1次粒子が凝集して粒径3 nm以上1000 nm以下の2次粒子を構成し、
    前記2次粒子が溶液中に分散していることを特徴とする焼結接合剤。
    A sintered bonding agent using cupric oxide nanoparticles,
    Using the cupric oxide nanoparticles having a particle diameter of 2 nm to 50 nm as primary particles,
    The primary particles aggregate to form secondary particles having a particle size of 3 nm to 1000 nm,
    A sintered bonding agent, wherein the secondary particles are dispersed in a solution.
  2.  請求項1に記載の焼結接合剤において、
    前記溶液が、水、または水とアルコール系溶剤との混合溶液であることを特徴とする焼結接合剤。
    In the sintered bonding agent according to claim 1,
    The sintered bonding agent, wherein the solution is water or a mixed solution of water and an alcohol solvent.
  3.  請求項1または請求項2に記載の焼結接合剤において、
    前記酸化第二銅ナノ粒子の含有量が90質量%以上であることを特徴とする焼結接合剤。
    In the sintered bonding agent according to claim 1 or 2,
    A sintered bonding agent, wherein the content of the cupric oxide nanoparticles is 90% by mass or more.
  4.  請求項1乃至請求項3のいずれかに記載の焼結接合剤において、
    前記1次粒子が単結晶子から構成されていることを特徴とする焼結接合剤。
    In the sintered bonding agent according to any one of claims 1 to 3,
    A sintered bonding agent, wherein the primary particles are composed of single crystallites.
  5.  請求項1乃至請求項3のいずれかに記載の焼結接合剤において、
    前記1次粒子が複数の結晶子から構成されていることを特徴とする焼結接合剤。
    In the sintered bonding agent according to any one of claims 1 to 3,
    A sintered bonding agent, wherein the primary particles are composed of a plurality of crystallites.
  6.  請求項1に記載の焼結接合剤の製造方法であって、
    前記溶液中に銅化合物を溶解させて銅イオンを生成させる工程の後に、
    前記溶液中に不活性ガスを流しながらアルカリ性溶液を加えて酸化第二銅コロイドを生成する工程を有することを特徴とする焼結接合剤の製造方法。
    It is a manufacturing method of the sintered joining agent according to claim 1,
    After the step of dissolving the copper compound in the solution to generate copper ions,
    A method for producing a sintered binder, comprising a step of adding an alkaline solution while flowing an inert gas into the solution to produce a cupric oxide colloid.
  7.  請求項6に記載の焼結接合剤の製造方法において、
    前記銅化合物が、硝酸銅水和物、銅酸化物、カルボン酸銅塩のうちの少なくとも一種であることを特徴とする焼結接合剤の製造方法。
    In the manufacturing method of the sintered joining agent of Claim 6,
    The copper compound is at least one of copper nitrate hydrate, copper oxide, and carboxylic acid copper salt.
  8.  電子部材同士の接合方法であって、
    請求項1乃至請求項5のいずれかに記載の焼結接合剤を接合箇所に塗布する工程の後に、還元雰囲気中100~500℃の焼結熱処理を施す工程を有することを特徴とする電子部材同士の接合方法。
    A method for joining electronic members,
    6. An electronic member comprising a step of applying a sintering heat treatment at 100 to 500 ° C. in a reducing atmosphere after the step of applying the sintered bonding agent according to any one of claims 1 to 5 to a bonding portion. Bonding method between each other.
  9.  請求項8に記載の電子部材同士の接合方法おいて、
    前記還元雰囲気が、水素、ギ酸、またはエタノール雰囲気であることを特徴とする電子部材同士の接合方法。
    In the joining method of the electronic members of Claim 8,
    The method for bonding electronic members, wherein the reducing atmosphere is a hydrogen, formic acid, or ethanol atmosphere.
  10.  請求項8または請求項9に記載の電子部材同士の接合方法おいて、
    前記電子部材が、冷却ユニットの冷却フィンと金属支持板であり、
    前記冷却フィンと前記金属支持板とを接合する方向に加圧しながら前記焼結熱処理を施すことを特徴とする電子部材同士の接合方法。
    In the joining method of the electronic members of Claim 8 or Claim 9,
    The electronic member is a cooling fin and a metal support plate of a cooling unit,
    A method for joining electronic members, wherein the sintering heat treatment is performed while pressurizing the cooling fin and the metal support plate in a joining direction.
  11.  請求項8または請求項9に記載の電子部材同士の接合方法おいて、
    前記電子部材が、半導体装置のチップと配線基板であり、
    前記チップと前記配線基板とを接合する方向に加圧しながら前記焼結熱処理を施すことを特徴とする電子部材同士の接合方法。
    In the joining method of the electronic members of Claim 8 or Claim 9,
    The electronic member is a chip of a semiconductor device and a wiring board,
    A method for joining electronic members, wherein the sintering heat treatment is performed while pressurizing the chip and the wiring board in a joining direction.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014029930A1 (en) * 2012-08-21 2014-02-27 Commissariat A L'energie Atomique Et Aux Energies Alternatives Flip-chip hybridisation of two microelectronic components using a uv anneal
WO2016136409A1 (en) * 2015-02-27 2016-09-01 富士フイルム株式会社 Composition for forming conductive film and method for producing conductive film
EP3409402A4 (en) * 2016-01-27 2019-09-04 Mitsubishi Materials Corporation Manufacturing method of copper member bonded body

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5772539B2 (en) * 2011-11-21 2015-09-02 日立化成株式会社 Method for producing copper oxide paste and metallic copper layer
JP2014043382A (en) * 2012-08-27 2014-03-13 Toyota Central R&D Labs Inc Semiconductor device and method of manufacturing the same
WO2015029152A1 (en) * 2013-08-28 2015-03-05 株式会社日立製作所 Semiconductor device
EP3104400B1 (en) 2014-02-04 2022-08-31 Murata Manufacturing Co., Ltd. Manufacturing method of electronic component module
WO2016031409A1 (en) * 2014-08-29 2016-03-03 富士フイルム株式会社 Composition and method for forming conductive film
JP6488152B2 (en) * 2015-02-27 2019-03-20 富士フイルム株式会社 Method for producing cupric oxide fine particles and cupric oxide fine particles
JP2018098219A (en) * 2015-03-18 2018-06-21 株式会社日立製作所 Semiconductor device and manufacturing method of the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02276111A (en) * 1988-06-09 1990-11-13 Toshiba Corp Compound superconductor and its manufacture
JPH0465010A (en) * 1990-07-04 1992-03-02 Sumitomo Metal Ind Ltd Copper conductive paste
JPH06262375A (en) * 1992-06-05 1994-09-20 Matsushita Electric Ind Co Ltd Diffused junction method for copper or copper alloy at low temperature, and manufacture of conductive paste and manufacture wiring board using the same
JPH0817241A (en) * 1994-06-30 1996-01-19 Mitsuboshi Belting Ltd Copper conductive paste and manufacture of copper conductive film
JPH10283840A (en) * 1997-03-31 1998-10-23 Mitsuboshi Belting Ltd Copper conductor paste for aluminum nitride board, and aluminum nitride board
JP2002222613A (en) * 2000-09-14 2002-08-09 Dowa Mining Co Ltd Copper powder for conductive paste, copper powder particles and the conductive paste

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5144154B2 (en) * 2006-07-28 2013-02-13 古河電気工業株式会社 Fine particle production method and fine particle dispersion production method
JP5006081B2 (en) * 2007-03-28 2012-08-22 株式会社日立製作所 Semiconductor device, manufacturing method thereof, composite metal body and manufacturing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02276111A (en) * 1988-06-09 1990-11-13 Toshiba Corp Compound superconductor and its manufacture
JPH0465010A (en) * 1990-07-04 1992-03-02 Sumitomo Metal Ind Ltd Copper conductive paste
JPH06262375A (en) * 1992-06-05 1994-09-20 Matsushita Electric Ind Co Ltd Diffused junction method for copper or copper alloy at low temperature, and manufacture of conductive paste and manufacture wiring board using the same
JPH0817241A (en) * 1994-06-30 1996-01-19 Mitsuboshi Belting Ltd Copper conductive paste and manufacture of copper conductive film
JPH10283840A (en) * 1997-03-31 1998-10-23 Mitsuboshi Belting Ltd Copper conductor paste for aluminum nitride board, and aluminum nitride board
JP2002222613A (en) * 2000-09-14 2002-08-09 Dowa Mining Co Ltd Copper powder for conductive paste, copper powder particles and the conductive paste

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014029930A1 (en) * 2012-08-21 2014-02-27 Commissariat A L'energie Atomique Et Aux Energies Alternatives Flip-chip hybridisation of two microelectronic components using a uv anneal
FR2994768A1 (en) * 2012-08-21 2014-02-28 Commissariat Energie Atomique HYBRIDIZATION FACE AGAINST FACE OF TWO MICROELECTRONIC COMPONENTS USING A UV RECEIVER
US9318453B2 (en) 2012-08-21 2016-04-19 Commissariat A L'energie Atomique Et Aux Energies Alternatives Flip-chip hybridisation of two microelectronic components using a UV anneal
WO2016136409A1 (en) * 2015-02-27 2016-09-01 富士フイルム株式会社 Composition for forming conductive film and method for producing conductive film
JPWO2016136409A1 (en) * 2015-02-27 2017-09-28 富士フイルム株式会社 Conductive film forming composition and conductive film manufacturing method
EP3409402A4 (en) * 2016-01-27 2019-09-04 Mitsubishi Materials Corporation Manufacturing method of copper member bonded body

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