WO2012056994A1

WO2012056994A1 - Timing signal generating device, timing signal generating method, liquid crystal display device, and television receiver

Info

Publication number: WO2012056994A1
Application number: PCT/JP2011/074194
Authority: WO
Inventors: 亮山川
Original assignee: シャープ株式会社
Priority date: 2010-10-27
Filing date: 2011-10-20
Publication date: 2012-05-03

Abstract

A timing signal generating device (10) of the present invention is provided with a CS_ENABLE circuit (6) wherein, when a period between a time when the level of an SSP signal became high and the subsequent time when the level of the SSP signal became high is expressed as a first horizontal period (Ha), a shift period of a second horizontal period (Hb) with respect to the first horizontal period (Ha) is detected as a CLK count number, said second horizontal period being obtained on the basis of a clock frequency and a frame frequency, and corresponding to the detected period, control signals that control fetching of CS signals to a pixel array are generated.

Description

Timing signal generating device, timing signal generating method, liquid crystal display device, and television receiver

The present invention relates to a timing signal generator provided in a liquid crystal display device.

2. Description of the Related Art Conventionally, there is a matrix type display device in which pixels are arranged in a matrix as an example of a device provided with a drive circuit that drives display pixels in which electronic elements are arranged in an array. As a typical example of such a matrix display device, for example, an active matrix liquid crystal display device is well known.

Fig. 10 is a diagram schematically showing an example of a schematic configuration of a conventional active matrix type liquid crystal display device. As shown in the figure, the liquid crystal display device 500 includes a liquid crystal display panel 501, a source driver 502, a gate driver 503, and a liquid crystal display control circuit 504.

The liquid crystal display panel 501 is a liquid crystal display panel in which pixel electrodes for display and TFT transistors for applying a voltage to the pixel electrodes are arranged in a matrix on a substrate.

The source driver 502 is disposed on the upper side of the liquid crystal display panel 501, and the gate driver 503 is disposed on the left side of the liquid crystal display panel 501 so as to display a desired image on the liquid crystal display panel 501. It has become. Specifically, the display data latched by the source driver 502 in units of one line in the horizontal direction is D / A converted and converted into grayscale voltages on the pixel electrodes of the liquid crystal display panel 501 from the top to the bottom in units of one line in the horizontal direction. By sequentially writing, a voltage for each pixel is applied between the pixel electrode and the common electrode, and the transmittance of the liquid crystal between the electrodes is controlled according to the applied voltage value to display a desired image on the liquid crystal display panel 501. Let

The liquid crystal display control circuit 504 generates various timing signals for image display, controls the source driver 502 and the gate driver 503, and drives the liquid crystal display panel 501, and generates the various timing signals. The timing signal generator 300 is provided.

FIG. 11 is a circuit block diagram schematically showing the configuration of the timing signal generator 300. As shown in FIG. As shown in the figure, the timing signal generator 300 includes a counter initialization circuit 31, a horizontal direction counter 32, a vertical direction counter 33, and a signal generation circuit group 34.

The counter initialization circuit 31 receives a horizontal reference signal (hereinafter “HSYNC signal”), a vertical reference signal (hereinafter “VSYNC signal”), and a clock signal (hereinafter “CLK signal”). A control signal is output to each of the direction counters 33.

The horizontal counter 32 receives the CLK signal, counts the number of clocks, and supplies it to a horizontal decoder (not shown) of the signal generation circuit group 34. The horizontal counter 32 is configured to reset the count when a control signal synchronized with the HSYNC signal is supplied from the counter initialization circuit 31.

The vertical direction counter 33 receives the CLK signal and the HSYNC signal, counts the number of HSYNC signal pulses in synchronization with the CLK signal, and supplies it to a vertical decoder (not shown) of the signal generation circuit group 34. The vertical counter 33 is configured to reset the count when the control signal synchronized with the VSYNC signal is supplied from the counter initialization circuit 31. That is, the control signal output from the counter initialization circuit 31 functions as a count reset signal.

The signal generation circuit group 34 includes a plurality of signal generation circuits for generating various timing signals for driving the liquid crystal display device. Specifically, an SSP circuit 34a that generates a shift start signal (hereinafter “SSP signal”) of the source driver 502, a GSP circuit 34b that generates a bus line selection start signal (hereinafter “GSP signal”) of the gate driver 503, and a gate A GCK circuit 34c that generates a shift clock signal for bus line selection signal (hereinafter referred to as "GCK signal") of the driver 503, and a polarity selection signal (hereinafter referred to as "FRP signal") used as a base signal for polarity inversion of the COM signal and video signal. An FRP circuit 34d for generating, an LR circuit 34e for generating a scanning direction switching signal (hereinafter referred to as “LR signal”) of the source driver 502, and a PWC for generating a bus line selection signal width control signal (hereinafter referred to as “PWC signal”) for the gate driver 503. The circuit 34f generates a precharge control signal (hereinafter referred to as “PCTL signal”). PCTL circuit 34g, and a UD circuit 34h for generating a scanning direction switching signal of the gate driver 503 (hereinafter "UD signal").

International Patent Publication “WO 2006/035843 Publication (International Publication Date: April 6, 2006)”

By the way, the source start pulse SSP generated from the SSP circuit 34a of the signal generation circuit group 34 is a signal for signaling the head column of the horizontal line, and when it becomes High, it starts to be taken into the source driver 502. Therefore, next, the period T until becoming High, that is, the High-High period becomes one horizontal period Ha.

On the other hand, one horizontal period Hb of the signal output from the timing controller (actually output signal) is Hb = Fclk / (Fframe * Vtotal) using the clock frequency (Fclk), the frame frequency (Fframe), Htotal, and Vtotal. ).

Here, in order to improve the viewing angle characteristics in the liquid crystal display device, a storage capacitor signal (hereinafter referred to as “CS signal”) is input to the liquid crystal panel 501 at a predetermined timing.

The timing of outputting the CS signal to the liquid crystal panel 501 is defined based on the above SSP.

Therefore, when the horizontal period Hb is significantly different from one horizontal period Ha corresponding to the High-High period of the SSP due to variations in the clock frequency (Fclk) and the frame frequency (Fframe), Display quality is significantly deteriorated due to a CS stripe defect caused by a difference between the period Hb and the output timing of the CS signal. This CS streak failure means a state in which black and white streaks enter the entire display as shown in FIG. 12, for example.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a timing signal generation device capable of preventing the occurrence of CS stripe defects.

In order to solve the above-described problem, the timing signal generation device of the present invention provides a display signal to a drive circuit for driving a pixel array composed of electronic elements arranged in an array in which at least a reference signal is input. Is a timing signal generation device that outputs a timing signal for obtaining a timing for taking in a storage capacitor signal into the pixel array and a timing for taking a storage capacitor signal into the pixel array, and performs a counting operation based on the reference signal. 1 counter means, a signal generation circuit for generating the timing signal in accordance with the count output of the first counter means, and a period until the timing signal becomes high level and becomes the next high level, the first horizontal period Whether Ha is the clock frequency or frame frequency of the signal output from the timing signal generator When the obtained horizontal period is a second horizontal period Hb, a period detecting unit that detects a shift period of the second horizontal period Hb from the first horizontal period Ha, and a period detected by the period detecting unit. Accordingly, a control signal generation circuit that generates a control signal for controlling the capture of the storage capacitor signal into the pixel array is provided.

In order to solve the above-described problem, the timing signal generation method of the present invention provides a display signal to a drive circuit for driving a pixel array composed of electronic elements arranged in an array and receiving at least a reference signal. Is a timing signal generation method for generating a timing signal for obtaining a timing for taking in the driving circuit and a timing for taking a storage capacitor signal into the pixel array, and performing a counting operation based on the reference signal. And a timing signal generating step for generating the timing signal in accordance with the count output of the first counting step, and further, a period until the timing signal becomes high level and becomes the next high level. , The first horizontal period Ha, and the clock of the signal output from the timing signal generator When the horizontal period obtained from the wave number and the frame frequency is the second horizontal period Hb, a period detecting step for detecting a shift period of the second horizontal period Hb with respect to the first horizontal period Ha, and the period detecting step And a control signal generator for generating a control signal for controlling the capture of the storage capacitor signal into the pixel array in accordance with the detected period.

Usually, in order to improve viewing angle characteristics in a liquid crystal display device, a storage capacitor signal is output to a pixel array (for example, a liquid crystal panel) at a predetermined timing.

Here, the horizontal period obtained from the first horizontal period Ha defined as a period from when the timing signal becomes high level to the next high level, and the clock frequency and frame frequency of the signal output from the timing signal generator. If the second horizontal period Hb defined as follows coincides with the second horizontal period Hb or is an error within a predetermined period, CS unevenness does not occur and display does not cause a problem.

However, when the difference between the first horizontal period Ha and the second horizontal period Hb is greater than a predetermined period, the timing at which the CS signal is input to the liquid crystal panel is shifted, CS streaks occur, and display defects are caused. Become.

The timing signal generation device according to the present invention has a timing for capturing a display signal in a driving circuit for driving a pixel array composed of electronic elements arranged in an array in which at least a reference signal is input. And a timing signal generating device that outputs a timing signal for obtaining a storage capacitor signal into the pixel array, wherein the first counter means performs a counting operation based on the reference signal, and the first counter. According to the count output of the means, a signal generation circuit for generating the timing signal, and a period from when the timing signal becomes high level to the next high level is defined as a first horizontal period Ha, from the timing signal generator. From the timing of the output signal, the water obtained from the clock frequency and frame frequency When the period is the second horizontal period Hb, to the pixel array according to the period detecting means for detecting a shift period of the horizontal period Hb with respect to the horizontal period Ha and the period detected by the period detecting means. And a control signal generation circuit that generates a control signal for controlling the capture of the storage capacitor signal. Thereby, there is an effect that it is possible to provide a timing signal generation device capable of preventing the occurrence of CS line defects.

1 is a schematic configuration block diagram of a timing signal generation device according to a first embodiment of the present invention. (A) is a figure which shows the example of a 1st horizontal period Ha, (b) is a figure which shows the example of a 2nd horizontal period Hb. 2 is a horizontal timing chart in the timing signal generation device shown in FIG. 1. 2 is a timing chart in the vertical direction in the timing signal generation device shown in FIG. 1. FIG. 2 is a schematic configuration block diagram of an active matrix liquid crystal display device including the timing signal generation device shown in FIG. 1. It is a schematic block diagram of the timing signal generation device according to the second embodiment of the present invention. 7 is a timing chart in the horizontal direction in the timing signal generation device shown in FIG. 6. 7 is a timing chart in the vertical direction in the timing signal generation device shown in FIG. 6. It is a disassembled perspective view which shows the outline of the television receiver provided with the active matrix type liquid crystal display device shown in FIG. It is a schematic block diagram of a liquid crystal display device provided with a conventional timing signal generation device. It is a schematic block diagram of a timing signal generator provided in the liquid crystal display device shown in FIG. It is a figure which shows the example of a display of CS stripe defect.

[Embodiment 1]
An embodiment of the present invention will be described as follows.

(General description of active matrix liquid crystal display device)
FIG. 5 is a diagram schematically illustrating an example of a schematic configuration of the active matrix liquid crystal display device according to the present embodiment. As shown in the figure, a liquid crystal display device (liquid crystal module) 100 includes a timing signal generation device (timing generator; hereinafter referred to as “TG”) 10, a power supply circuit 11, a liquid crystal display control circuit (hereinafter referred to as “LCDC”) 12, A video circuit 13, a driver circuit 14, and a pixel array 15 are provided.

The pixel array 15 is a liquid crystal display panel in which display pixel electrodes and TFT transistors for applying a voltage to the pixel electrodes are arranged in a matrix on a substrate, and functions as an image display element.

Here, a description will be given assuming a liquid crystal display panel as the pixel array 15. Therefore, in the pixel array 15, a plurality of gate lines and source lines are arranged orthogonally, and pixel electrodes are provided at the intersections via switching elements (for example, TFTs). Furthermore, in order to improve the viewing angle characteristics, a storage capacitor wiring (hereinafter referred to as “CS wiring”) arranged in parallel to the gate lines constituting the pixel array 15 is formed, and a CS signal is transmitted as necessary. This CS wiring is taken in.

The CS signal is supplied from the LCDC 12 to the CS wiring of the pixel array 15. Hereinafter, for convenience, “the CS signal is supplied to the CS wiring of the pixel array 15” will be simply described as “the CS signal is supplied to the pixel array 15”. Further, the supply control of the CS signal in the LCDC 12 is performed based on a control signal from the TG 10. Details of this control will be described later.

The driver circuit 14 includes a source driver (horizontal drive circuit) 14a and a gate driver (vertical drive circuit) 14b.

The source driver 14a is disposed, for example, on the upper side of the pixel array 15, and the gate driver 14b is disposed on the left side of the pixel array 15, so that the pixel array 15 displays a desired video. More specifically, the display data latched in units of one line in the horizontal direction in the source driver 14a is D / A converted and applied as gradation voltages to the pixel electrodes of the pixel array 15 from the upper side to the lower side in units of one horizontal line. By sequentially writing, a voltage for each pixel is applied between the pixel electrode and the common electrode, and the transmittance of the liquid crystal between the electrodes is controlled according to the applied voltage value so that a desired image is displayed on the pixel array 15. .

The power supply circuit 11 is a circuit for supplying power to the video circuit 13, the driver circuit 14, and the pixel array 15.

The LCDC 12 outputs a reference signal (horizontal reference signal (hereinafter “HSYNC signal”), vertical reference signal (hereinafter “VSYNC signal”)) and a clock signal (hereinafter “CLK signal”) to the TG 10, and digital video. The signal is output to the video circuit 13.

The TG 10 generates various timing signals in accordance with the reference signal and supplies them to the video circuit 13 or the driver circuit 14. The timing signal includes, for example, a shift start signal (hereinafter “SSP signal”) of the source driver 14a, a scanning direction switching signal (hereinafter “LR signal”) of the source driver 14a, and a shift clock for a bus line selection signal of the gate driver 14b. Signal (hereinafter “GCK signal”), bus driver bus line selection signal width control signal (hereinafter “PWC signal”), precharge control signal (hereinafter “PCTL signal”), polarity selection signal (hereinafter “FRP signal”), Examples include a bus line selection start signal (hereinafter “GSP signal”) of the gate driver 14b, a scanning direction switching signal (hereinafter “UD signal”) of the gate driver 14b, and the like. Note that the FRP signal here is used as a base signal for the polarity inversion of the COM signal and the video signal.

The video circuit 13 supplies an analog video signal for driving a liquid crystal to the driver circuit 14. The driver circuit 14 drives the pixel array 15 based on various signals from the TG 10 and the video circuit 13. In other words, the gate driver 14b operates according to the GSP and sequentially selects each row of the liquid crystal pixels, and the source driver 14a operates according to the SSP and sequentially selects the video signal distributed to each column of the liquid crystal pixels. The liquid crystal pixels in the row are written, and the image is displayed on the pixel array 15.

The LCDC 12 controls supply of the CS signal to the pixel array 15 based on the control signal from the TG 10. By supplying the CS signal to the pixel array 15, the viewing angle characteristics in the pixel array 15 are improved.

That is, the CS signal is input to a CS wiring (not shown) arranged in parallel with the gate line (not shown) in the pixel array 15.

Here, in the pixel portion of the pixel array 15, the applied voltage of the pixel is changed by a potential change caused by a potential difference between the source voltage applied to the liquid crystal from the source electrode and the voltage in the CS wiring to which the CS signal is input. It is determined. As a result, in the pixel array 15, two types of pixels are formed by the CS signal, a bright pixel that is brightened by applying a larger voltage and a dark pixel that is darkened by canceling the source voltage. Thereby, the viewing angle characteristics can be improved without changing the total front luminance in the pixel array 15.

Thus, the viewing angle characteristic can be improved by supplying the CS signal to the pixel array 15. Hereinafter, the function of improving the viewing angle characteristic by the CS signal is referred to as a CS function.

(Description of timing signal generator)
Next, TG10 which is a characteristic part of the present invention will be described.

The TG 10 receives at least a horizontal reference signal, a vertical reference signal, and a clock signal, and generates and outputs timing signals to a horizontal driving circuit and a vertical driving circuit for driving display pixels arranged in a matrix. It functions as a signal generation device. In this specification, a liquid crystal display element is described as an example of a display pixel. However, the present invention is not limited to this, and the present invention can be widely applied to matrix display pixels. The horizontal reference signal and the vertical reference signal may be configured to be supplied from, for example, an external computer.

FIG. 1 is a circuit block diagram schematically showing the configuration of the TG 10.

The TG 10 includes a counter initialization circuit 1, a horizontal direction counter 2, a vertical direction counter 3, and a signal generation circuit group 4 as shown in FIG.

The counter initialization circuit 1 receives the HSYNC signal, the VSYNC signal, and the CLK signal, and outputs control signals to the horizontal direction counter 2 and the vertical direction counter 3, respectively.

The horizontal counter 2 receives the CLK signal, counts the number of clocks, and supplies it to a horizontal decoder (not shown) of the signal generation circuit group 4. The horizontal counter 2 is configured to reset the clock count when a control signal is supplied from the counter initialization circuit 1. That is, the control signal supplied from the counter initialization circuit 1 to the horizontal counter 2 is synchronized with the HSYNC signal and functions as a count reset signal. Therefore, it can be said that the horizontal counter 2 functions as horizontal counter means for counting the number of clocks according to the HSYNC signal.

The vertical counter 3 receives the CLK signal, counts the number of clocks, and supplies it to a vertical decoder (not shown) of the signal generation circuit group 4. The vertical counter 3 is configured to reset the clock count when a control signal is supplied from the counter initialization circuit 1. That is, the control signal supplied from the counter initialization circuit 1 to the vertical counter 3 is synchronized with the VSYNC signal and functions as a count reset signal. Therefore, it can be said that the vertical counter 3 functions as a vertical counter means for counting the number of clocks according to the VSYNC signal.

The signal generation circuit group 4 is a signal generation circuit group that generates a plurality of timing signals according to the count outputs of the horizontal direction counter 2 and the vertical direction counter 3, and generates various control signals for driving the liquid crystal display device 100. A plurality of signal generating circuits for performing the above are provided. Here, the SSP circuit 4a that generates the SSP signal, the GSP circuit 4b that generates the GSP signal, the GCK circuit 4c that generates the GCK signal, the COM signal, and the FRP that generates the FRP signal used as a base signal for polarity inversion of the video signal, etc. The circuit 4d includes an LR circuit 4e that generates an LR signal, a PWC circuit 4f that generates a PWC signal, a PCTL circuit 4g that generates a PCTL signal, and a UD circuit 4h that generates a UD signal. Note that the types of signal generation circuits included in the signal generation circuit group 4 are not limited to those described above, and signal generation circuits that can be used in a conventionally known matrix display device can be suitably combined.

In the present invention, the length of two types of horizontal periods is detected, and the CS function is controlled (stopped, delayed) according to the detection result. Specifically, two types of horizontal periods, for example, a first horizontal period Ha shown in FIG. 2A and a second horizontal period Hb shown in FIG. 2B are used.

(Description of horizontal period)
The first horizontal period Ha is a period from when the timing signal becomes high level (High) until the next high level (High), as shown in FIG.

The second horizontal period Hb is a period obtained from an output value (for example, a clock frequency or a frame frequency) of a signal (video signal or the like) output from the TG 10, as shown in FIG.

A specific method for obtaining the second horizontal period Hb will be described.

As the output value of the signal output from the TG 10, the second horizontal period Hb = Fclk / (Fframe * Vtotal) is obtained using the clock frequency (Fclk), the frame frequency (Fframe), Htotal, and Vtotal.

Here, when the first horizontal period Ha is set to 668CLK, if the second horizontal period Hb is also determined to be the same 668CLK, there is no problem in display. However, if the obtained CLK value in the second horizontal period Hb is remarkably far from the first horizontal period Ha, a display problem (CS streak defect) occurs.

The significant difference is, for example, 1960 clk or less as the target Htotal of the number of CLKs in the second horizontal period Hb = 2116clk when Hframe = 120.64 Hz and Fclk = 320 MHz and the frequency of the input signal is 60 Hz. , 2326 clk or more. That is, when this difference is exceeded, CS streak failure occurs.

Therefore, the above-mentioned significant difference indicates the value of Htotal when the allowable range of deterioration in display quality due to the occurrence of CS stripe defects is exceeded.

Here, in order to realize the function control of the CS function, the TG 10 is further provided with a GCK counter (second counter means) 5, a CS_ENABLE circuit 6, and an LUT 7, as shown in FIG.

The GCK counter 5 receives the SSP signal from the SSP circuit 4a and the GCK signal from the GCK circuit. That is, the GCK counter 5 starts counting the number of clocks of the GCK signal output from the GCK circuit 4c immediately after the SSP signal output from the SSP circuit 4a becomes High, and then continues until the SSP signal becomes High. The count of GCK output from the GCK circuit 4c is continued. The count result is output to the subsequent CS_ENABLE circuit 6.

The GCK counter 5 also functions as a period detecting unit that detects a shift period of the second horizontal period Hb with respect to the first horizontal period Ha.

The CS_ENABLE circuit 6 obtains the difference between the count number obtained from the count result and the CLK number in the first horizontal period Ha defined in advance, and controls the capture of the CS signal according to the magnitude of the difference. A capture control signal (control signal) is output to the LCDC 12 (FIG. 5). If the difference is significantly larger than a preset difference, whether a capture stop signal (stop signal) for turning off the CS function of the next frame is output to the LCDC 12 (FIG. 5) as a control signal. Alternatively, a delay instruction signal (delay signal) for delaying the CS signal change timing is output to the LCDC 12 (FIG. 5) as a control signal in accordance with the counted CLK number. The CLK counter is performed by the horizontal counter 2 in the figure.

The LUT 7 is a lookup table that defines the relationship between the GCK count number / CS delay timing. In this LUT 7, for each pixel array 15 and driver circuit 14, the relationship between the GCK count number / CS delay timing, that is, the delay period for delaying the capture of the CS signal into the pixel array 15 is set to the horizontal period Ha of the horizontal period Hb. A relationship in which the number of clocks indicating the shift period is associated with the delay period is defined. Specifically, the parameters of the LUT 7 are adjusted for each parameter and IC.

The CS_ENABLE circuit 6 determines a delay instruction signal indicating the delay timing with reference to the LUT 7.

As described above, the TG 10 receives a display signal from the driver circuit 14 that is a drive circuit for driving the pixel array 15 as an electronic element arranged in an array and receives at least a reference signal. This is a timing signal generation device (timing signal generation circuit) that outputs a timing signal (SSP signal) for obtaining the timing for taking in the circuit 14 and the timing for taking in the storage capacitor signal (CS signal) into the pixel array 15. .

Further, as described above, the TG 10 determines the timing according to the count output of the horizontal counter 2 as the first counter means that performs the counting operation based on the reference signal and the horizontal counter 2 as the first counter means. A signal generation circuit group 4 which is a signal generation circuit for generating a signal, a GCK counter 5 as a period detection unit for detecting a shift period of the second horizontal period Hb with respect to the first horizontal period Ha, and the GCK which is the period detection unit By including a CS_ENABLE circuit 6 as a control signal generation circuit that generates a control signal for controlling the capture of the storage capacitor signal (CS signal) into the pixel array 15 according to the period detected by the counter 5. The following effects are obtained.

That is, the CS signal source driver is generated by generating a control signal for controlling the capturing of the CS signal into the source driver 14a according to a period indicating a difference between the first horizontal period Ha and the second horizontal period Hb. Since the capture to 14a is controlled, it is possible to reduce the occurrence of CS stripes due to the shift in the input timing of the CS signal to the pixel array 15.

That is, it is possible to realize a timing signal generation device that can prevent the occurrence of CS stripe defects.

(Explanation about timing chart of timing signal generator)
Here, timing charts in the TG 10 having the above-described configuration are shown in FIGS.

3 is a timing chart in the horizontal direction, and FIG. 4 is a timing chart in the vertical direction.

First, the horizontal timing chart will be described.

In the horizontal timing chart shown in FIG. 3, the HSYNC signal, SSP signal, LR signal, GCK signal, PWC signal, PCTL signal, FRP signal, and the operation period of the horizontal counter 2 are shown.

As shown in the figure, the SSP signal is configured such that a change point occurs immediately after the HSYNC signal becomes “Low” and becomes “High” again. Also, the LR signal, GCK signal, PWC signal, PCTL signal, and FRP signal change point just before the next HSYNC signal becomes “Low” after the HSYNC signal becomes “Low” and becomes “High” again. Is configured to occur.

Here, in a period from when the HSYNC signal becomes “Low” and becomes “High” again until the next HSYNC signal becomes “Low” and becomes “High” again, that is, in one horizontal scanning period T91 of the video signal, There is a horizontal effective display period T92 (horizontal effective display area) in which a video signal including video information is output, and a horizontal blanking period.

In general, the horizontal effective display period T92 is from the output of the change point of the SSP signal to the end of the horizontal scanning, and the horizontal blanking is performed between an arbitrary horizontal effective display period T92 and the next horizontal effective display period T92. It becomes a period. Various timing signals such as the LR signal, the GCK signal, the PWC signal, the PCTL signal, and the FRP signal are configured such that a change point occurs in the horizontal blanking period.

Here, the horizontal direction counter 2 needs to count the number of clocks to a position (mainly a change point) required by the signal output from the signal generation circuit group 4. For this reason, the horizontal counter 2 does not change until the next HSYNC signal becomes “Low” and becomes “High” after the HSYNC signal becomes “Low” and becomes “High” again, that is, during one horizontal scanning period T91. It is necessary to count continuously. That is, the horizontal direction counter 2 continues to count without stopping during one horizontal scanning period T91.

Next, a vertical timing chart will be described.

The vertical timing chart shown in FIG. 4 includes VSYNC signal, HSYNC signal, SSP signal, GCK signal, PWC signal, GSP signal, PCTL signal, UD signal, vertical effective display period T95 (vertical effective display area) and vertical block. The ranking period T96 and the operation period of the vertical direction counter 3 are shown.

In this timing chart, in the period from when the VSYNC signal becomes “Low” and becomes “High” again until the next VSYNC signal becomes “Low” and becomes “High” again, that is, one vertical scanning period T94, A vertical blanking period T96 exists between the effective display period T95 (vertical effective display area) and the period after the last horizontal video signal is output until the first horizontal video signal of the next vertical scanning period T94 is input. .

In the vertical blanking period T96, it is common to stop various signals such as the SSP signal in order to reduce power consumption. Therefore, as shown in FIG. 6B, the SSP signal, the GCK signal, and the PWC signal The PCTL signal is configured such that a change point occurs within the vertical effective display period T95. The GSP signal is configured such that a change point is generated immediately after the VSYNC signal becomes “Low” and becomes “High” again. The UD signal is configured such that a change point occurs immediately after the VSYNC signal becomes “Low” and becomes “High” again, and immediately before the next VSYNC signal becomes “Low” and becomes “High” again.

Here, since it is necessary for the vertical counter 3 to determine the start position of the vertical blanking period T96, it is necessary to count at least within the vertical effective display period T95, and usually the vertical blanking period T96 is also counted. It is configured. Therefore, in the same way as the horizontal counter 2, the vertical counter 3 also becomes “Low” and becomes “High” again until the next VSYNC signal becomes “Low” and becomes “High” again. That is, it is set to continuously count during one vertical scanning period T94. That is, the vertical direction counter 3 continues to count without stopping during one vertical scanning period T94.

As described above, the timing signal generation method by the TG 10 having the above-described configuration includes the first count process for performing the counting operation using the reference signal as a reference, and the timing signal for generating the timing signal according to the count output of the first count process. Generating step, and
The period from when the timing signal becomes high level to the next high level is defined as a first horizontal period Ha, and the horizontal period obtained from the clock frequency and the frame frequency of the signal output from the timing signal generation circuit, When the second horizontal period Hb is set, the pixel array is detected according to a period detecting step for detecting a shift period of the second horizontal period Hb with respect to the first horizontal period Ha, and a period detected by the period detecting step. And a control signal generation step for generating a control signal for controlling the taking-in of the storage capacitor signal into the.

The above method also has the effect of preventing the occurrence of CS stripe defects.

[Embodiment 2]
Another embodiment of the present invention will be described as follows. Note that members having the same functions as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

(Description of timing signal generator)
FIG. 6 is a circuit block diagram schematically showing the configuration of the timing signal generator (TG) 20 according to the present embodiment.

The TG 20 has substantially the same configuration as the TG 10 described in the first embodiment. The TG 20 differs from the TG 10 in that it includes a stop circuit 8 for stopping the horizontal counter 2 and a stop circuit 9 for stopping the vertical counter 3.

In the TG 10 of the first embodiment, the horizontal direction counter 2 continues to count without stopping during one horizontal scanning period T91, and the vertical direction counter 3 counts without stopping during one vertical scanning period T94. However, like the TG 20 of the present embodiment, by providing the horizontal counter stop circuit (count stop means) 8 and the vertical counter stop circuit (count stop means) 9, it is necessary to perform the counting operation in each counter. If it can be stopped accordingly, the power consumption can be reduced.

The horizontal counter stop circuit 8 starts counting the number of clocks after the horizontal counter 2 inputs the HSYNC signal, then stops counting at a predetermined time, and stops counting until the next HSYNC signal is input. It functions as a horizontal counter stop means for controlling to continue. Specifically, the horizontal counter stop circuit 8 is configured to stop the count of the horizontal direction counter 2 at a predetermined timing for stopping the count of the horizontal direction counter 2 based on the count output from the horizontal direction counter 2. Has been. The predetermined time (predetermined timing) at which the horizontal counter stop circuit 8 stops the counting of the horizontal counter 2 will be described later.

The vertical counter stop circuit 9 starts counting the number of clocks after the vertical counter 3 inputs the VSYNC signal, then stops counting at a predetermined time, and stops counting until the next vertical reference signal VSYNC is input. It functions as a vertical counter stop means for controlling to continue. Specifically, the vertical counter stop circuit 9 is configured to stop the count of the vertical counter 3 at a predetermined timing for stopping the count of the vertical counter 3 based on the count output from the vertical counter 3. Has been. The predetermined time (predetermined timing) when the vertical counter stop circuit 9 stops the counting of the vertical counter 3 will be described later.

In the present embodiment, the horizontal counter stop circuit 8 and the vertical counter stop circuit 9 are provided outside the horizontal direction counter 2 and the vertical direction counter 3. However, the present invention is not limited to this configuration. 2 and the vertical direction counter 3 can be integrated in the horizontal counter stop circuit 8 and the vertical counter stop circuit 9, respectively.

(Explanation about timing chart of timing signal generator)
7 and 8 are diagrams showing timing charts in the TG 20 described above. FIG. 7 is a timing chart in the horizontal direction, and FIG. 8 is a timing chart in the vertical direction.

First, the horizontal timing chart will be described.

In the horizontal timing chart shown in FIG. 7, the HSYNC signal, SSP signal, LR signal, GCK signal, PWC signal, PCTL signal, FRP signal, and the operation period of the horizontal counter 2 are shown. As shown in the figure, the LR signal, the GCK signal, the PWC signal, the PCTL signal, and the FRP signal are configured such that a change point is generated immediately after the HSYNC signal becomes “Low”. The SSP signal is configured such that a change point is generated after the HSYNC signal becomes “Low” and the change point of the LR signal, the GCK signal, the PWC signal, the PCTL signal, and the FRP signal is generated. .

Here, the period from the input of an arbitrary HSYNC signal to the input of the next new HSYNC signal is one horizontal scanning period T1 of the video signal. In one horizontal scanning period T1 of the video signal in the present embodiment, that is, a period from when the HSYNC signal becomes “Low” until the next HSYNC signal becomes “Low”, the video signal including the video information is displayed. There is an output horizontal effective display period T2 (horizontal effective display area) and a horizontal blanking period T3. The LR signal, the GCK signal, the PWC signal, the PCTL signal, and the FRP signal are configured to generate a change point within the horizontal blanking period T3, and after the change point is generated in the SSP signal, Since the effective display period T2 begins, a period indicated by an arrow above the waveform of the SSP signal in the figure becomes the horizontal effective display period T2.

The horizontal counter 2 needs to count the number of clocks up to a position (mainly a position where a change point is generated) required by a signal output from the signal generation circuit group 4. In the case of the present embodiment, the horizontal counter 2 needs to count at least the number of clocks during the period from when the HSYNC signal becomes “Low” until a change point occurs in the SSP signal. That is, in this embodiment, the horizontal counter 2 needs to count at least the horizontal blanking period T3.

In the period when the horizontal counter 2 does not need to count, the power consumption can be reduced by stopping the counting of the horizontal counter 2. That is, a new HSYNC signal is input after a change point occurs in all timing signals generated in the signal generation circuit group 4 within one horizontal scanning period T1 of the video signal by the horizontal counter stop circuit 8. Power consumption can be reduced by controlling the horizontal counter 2 to stop counting until the time until

More specifically, as shown in the present embodiment, after an arbitrary HSYNC signal is input, the TG 10 starts a horizontal blanking period T3 of the video signal, and then shifts to a horizontal effective display period T2, and the next HSYNC When the horizontal effective display period T2 is set to continue until a signal is input, the horizontal counter stop circuit 8 counts at least during the horizontal blanking period T3, and then the next The count may be controlled to stop at a predetermined time until the HSYNC signal is input. That is, when the function of the horizontal counter stop circuit 8 is generalized, an arbitrary horizontal reference signal is input, and there are changing points in all timing signals generated by the signal generation circuit within one horizontal scanning period T1 of the video signal. Any control is possible as long as it has a period during which the counting of the horizontal direction counter means is stopped from when it occurs to when a new horizontal reference signal is input.

The horizontal counter 2 needs to count at least the above period, but needless to say, it may count more than that period. However, since the power consumption increases as the counting time of the horizontal counter 2 increases, the counting period of the horizontal counter 2 should be as short as possible, and is configured to count only the horizontal blanking period T3. It is preferable. In other words, it is preferable that the horizontal counter stop circuit 8 controls the horizontal counter 2 to count only during the horizontal blanking period T3 and then stop counting.

In other words, the signal generation circuit group 4 generates change points in all timing signals generated within one horizontal scanning period T1 of the video signal within the period in which the horizontal counter 2 is counting. It can be said that it is a thing.

Further, the signal generation circuit group 4 can be considered based on an SSP signal in which a signal change point is generated in the vicinity of the switching timing between the horizontal blanking period T3 and the horizontal effective display period T2. In this case, the signal generation circuit group 4 includes an SSP circuit 4a that generates at least an SSP signal, and the SSP signal is inputted within an horizontal scanning period T1 of a video signal after an arbitrary horizontal reference signal is inputted. Of all the timing signals generated in the signal generation circuit group, the change point is generated at the latest timing. The horizontal counter stop circuit 8 receives an arbitrary HSYNC signal, and the signal generation circuit Control to stop the counting of the horizontal counter 2 at a predetermined time from when a change point occurs in the SSP signal generated by the SSP circuit 4a of group 4 to when a new HSYNC signal is input. It can be expressed as something to do.

Although one horizontal scanning period T1 has been described as an example of a period from when the HSYNC signal becomes “Low” until the next HSYNC signal becomes “Low”, the present invention is not limited to this. The one horizontal scanning period T1 may be a period from when the HSYNC signal becomes “Low” and becomes “High” again until the next HSYNC signal becomes “Low” and becomes “High” again. Further, the HSYNC signal may be a signal having the same duty ratio obtained by inverting “High” and “Low” of the HSYNC signal shown in FIG.

Next, a vertical timing chart will be described.

The vertical timing chart shown in FIG. 8 shows the VSYNC signal, HSYNC signal, SSP signal, GCK signal, PWC signal, GSP signal, PCTL signal, UD signal, vertical effective display period T5 (vertical effective display area) and vertical block. The ranking period T6 and the operation period of the vertical direction counter 3 are shown.

In this timing chart, the vertical effective display period T5 (vertical effective display area) in the period from when the VSYNC signal becomes “Low” until the next VSYNC signal becomes “Low”, that is, one vertical scanning period T4. And a vertical blanking period T6.

As shown in FIG. 8, the SSP signal and the PCTL signal are configured such that a change point occurs in the vertical effective display period T5. Further, the GCK signal and the PWC signal are generated at the change point mainly in the vertical effective display period T5, but the change point is slightly generated also in the vertical blanking period T6. The GSP signal is configured such that, after the VSYNC signal becomes “Low”, a vertical blanking period T6 starts, and a change point is generated at the time of switching between the vertical blanking period T6 and the vertical effective display period T5. Yes. The UD signal is also configured such that after the VSYNC signal becomes “Low”, a vertical blanking period T6 starts, and a change point occurs at the time of switching between the vertical blanking period T6 and the vertical effective display period T5. However, the change point is generated earlier than the change point generation timing in the GSP signal. Note that in the vertical blanking period T6, it is common to stop various signals such as the SSP signal in order to reduce power consumption.

In other words, the TG 20 in this embodiment starts the vertical blanking period T6 of the video signal after an arbitrary VSYNC signal is input, then shifts to the vertical effective display period T5, and continues until the next VSYNC signal is input. The effective display period T5 is set to continue.

Here, since it is necessary to determine the timing at which the vertical blanking period T6 and the vertical effective display period T5 are switched, that is, the start position of the vertical effective display period T5, the vertical counter 3 counts at least the vertical blanking period T6. Need to do. After the start position of the vertical effective display period T5 is determined by the vertical counter 3, the power consumption can be reduced by stopping the vertical counter 3.

Therefore, the vertical counter stop circuit 9 performs control so that the vertical counter 3 performs counting at least during the vertical blanking period T6 and then stops counting at a predetermined time until the next VSYNC signal is input. . Furthermore, it is preferable that the vertical counter stop circuit 9 controls the vertical counter 3 to count only during the vertical blanking period T6 and then stop counting. This is because power consumption can be further reduced in this case.

When the function of the vertical counter stop circuit 9 is generalized, an arbitrary vertical reference signal is input, and all timing signals generated by the signal generation circuit within one vertical scanning period T4 of the video signal. It can be said that any control is possible so long as it has a period during which the counting of the vertical direction counter means is stopped during the period from when the change point occurs to when a new vertical reference signal is input.

Further, the signal generation circuit group 4 can be considered based on a GSP signal in which a signal change point is generated near the switching timing between the vertical blanking period T6 and the vertical effective display period T5. In this case, the signal generation circuit group 4 includes at least a circuit 4b that generates a shift start signal (GSP) of the gate drive circuit, and the vertical counter stop circuit 9 receives an arbitrary VSYNC signal, and the signal generation circuit group It is expressed that the control of the vertical counter 3 is stopped during a period from when a change point is generated in the GSP signal generated at 4 until a new VSYNC signal is input. it can.

Although one vertical scanning period T4 is a period from when the YSYNC signal becomes “Low” until the next YSYNC signal becomes “Low”, the present invention is not limited to this. The one vertical scanning period T4 may be a period from when the YSYNC signal becomes “Low” and becomes “High” again until the next Y signal becomes “Low” and becomes “High” again. The YSYNC signal may be a signal having the same duty ratio obtained by inverting “High” and “Low” of the YSYNC signal shown in FIG.

As described above, the TG 20 according to the present embodiment operates the horizontal counter 2 and the vertical counter 3 for a predetermined period, and then stops the counter stop means (horizontal counter stop circuit 8, vertical counter stop). Circuit 9). For this reason, the operation period of the horizontal direction counter 2 and the vertical direction counter 3 can be shortened, and power consumption can be reduced correspondingly.

In the present embodiment, the TG 20 including both the horizontal counter stop circuit 8 and the vertical counter stop circuit 9 has been described. However, in order to achieve the object of the present invention, which is to reduce power consumption, the horizontal counter stop circuit 8 and It suffices if at least one of the vertical counter stop circuits 9 is provided.

(Effect of timing signal generator)
In general, if the lengths of the first horizontal period Ha and the second horizontal period Hb described above match, there is no problem in display, but the lengths of the periods do not match due to variations in the second horizontal period Hb. There is a case. In such a case, there is no problem in the display if the amount of shift of the period is to some extent, but if the amount of shift of the period exceeds a certain value, a problem occurs in the display. That is, when the difference between the first horizontal period Ha and the second horizontal period Hb is larger than a predetermined period, the timing at which the CS signal is input to the liquid crystal panel is shifted, CS streaks occur, resulting in display defects. . The problem that occurs at this time is the CS streak defect described so far, and the display is as shown in FIG.

On the other hand, according to TG10 and TG20 of the above configuration, when the amount of shift between the first horizontal period Ha and the second horizontal period Hb exceeds a certain value (preset value), Since it is possible to prevent the CS signal from being taken into the pixel array 15, CS line defects caused by the CS signal do not occur.

Further, when the amount of shift between the first horizontal period Ha and the second horizontal period Hb exceeds a certain value (a preset value), the timing at which the CS signal is taken into the pixel array 15 is shifted. Therefore, it is possible to reduce the influence of CS streak failure caused by the CS signal.

Here, the shift amount of the period as a criterion is different for each device, and is set as the lowest value at which CS streak failure occurs for each device.

In the present invention, the horizontal direction counter and the vertical direction counter may be synchronous counters or asynchronous counters. In this embodiment, a binary counter is used. However, the present invention is not limited to this, and a similar result can be obtained with a BCD counter, but a binary counter is more preferable.

[Embodiment 3]
The following will describe still another embodiment of the present invention.

As shown in FIG. 9, the television receiver according to the present embodiment includes a liquid crystal display device 100 that displays a television broadcast received by a tuner unit (not shown) that receives the television broadcast. .

Specifically, as shown in FIG. 9, the television receiver has a configuration in which the liquid crystal display device 100 is sandwiched between a first housing 101 and a second housing 102.

The first casing 101 has an opening 101a through which an image displayed on the liquid crystal display device 100 is transmitted.

The second casing 102 covers the back side of the liquid crystal display device 100. The second housing 102 is provided with an operation circuit 103 for operating the liquid crystal display device 100, and a support member 104 is attached below. ing.

Here, the liquid crystal display device 100 includes a liquid crystal module including the timing signal generation device described in the first and second embodiments.

As a result, there is an effect that it is possible to display an image with high display quality that does not cause a CS line defect due to a shift in CS signal capture timing or is reduced.

In this specification, “array form” is used in a concept including both one arranged in a row and one arranged in a matrix.

As described above, in the present invention, Fclk increases when the temperature of the timing controller is low, and as a result, the value of the second horizontal period Hb increases or the Fframe of the input signal varies, etc. The CS function is turned off when the value of the period Hb varies, that is, when the second horizontal period Hb, which is one horizontal period, varies due to variations in Fclk and Fframe of the output signals from the TG10 and TG20. Alternatively, the fail-safe function of the timing controller that prevents the occurrence of CS stripe defects is realized by delaying the CS change timing in accordance with the fluctuating number of CLKs.

As a result, the liquid crystal display device 100 including the pixel array 15 having the CS function can suppress the deterioration of display quality due to the occurrence of the CS stripe defect.

That is, as in the above configuration, the storage capacitor signal (CS signal) to the pixel array 15 is detected in accordance with the period detected by the GCK counter 5 and indicating the difference between the first horizontal period Ha and the second horizontal period Hb. ) Is generated to control the capture of the CS signal into the pixel array 15, so that the occurrence of CS unevenness due to the shift in the input timing of the CS signal to the pixel array 15 is generated. Can be reduced.

The control signal may be a stop signal for stopping the capture of the CS signal into the pixel array 15 or may be a delay signal for delaying the capture of the CS signal into the pixel array 15. Specifically, it can be realized by the following configuration.

That is, when the period detected by the period detection unit is larger than a preset period, the control signal generation circuit outputs a stop signal for stopping the capture of the storage capacitor signal into the pixel array 15 as a control signal. It is the structure to do.

Further, the control signal generation circuit outputs a delay signal for delaying the capture of the storage capacitor signal to the pixel array 15 for a predetermined period when the period detected by the period detection unit is larger than a preset period. As the output.

The specific configuration of the above-described storage capacitor signal take-in control is as follows.

That is, the control signal generation circuit further includes second counter means for counting the number of clocks of the signal output from the timing signal generation device immediately after the timing signal becomes high level, and the second counter means The difference between the number of clocks counted by the above and the number of clocks in the first horizontal period Ha is a period of deviation of the second horizontal period Hb from the first horizontal period Ha detected by the period detecting means, When the period is longer than a preset period, a stop signal for stopping the capture of the storage capacitor signal into the pixel array is output as a control signal.

The control signal generation circuit further includes second counter means for counting the number of clocks of the signal output from the timing signal generator immediately after the timing signal becomes high level, and the second counter means. The difference between the number of clocks counted by the above and the number of clocks in the first horizontal period Ha is a period of deviation of the second horizontal period Hb from the first horizontal period Ha detected by the period detecting means, When the period is longer than a preset period, a delay signal that delays the capture of the storage capacitor signal into the pixel array for a predetermined period is output as a control signal.

In addition, it is preferable to obtain the delay period for taking in the storage capacitor signal from the lookup table shown below.

That is, the control signal generation circuit associates the delay period for delaying the capture of the storage capacitor signal into the pixel array with the shift period of the second horizontal period Hb relative to the first horizontal period Ha and the delay period. Preferably determined from a lookup table.

In addition, after an arbitrary reference signal is input, a count stop means that can stop the counting operation of the first counter means is provided until the next reference signal is input. preferable.

In this case, the counting of the counter means can be operated during a period requiring the counting operation and then stopped. For this reason, since the operation stop period of the counter means is generated, the power consumption can be reduced.

In order to solve the above problems, the liquid crystal display device of the present invention is provided with at least a liquid crystal display panel composed of electronic elements arranged in an array, a drive circuit for driving the liquid crystal display panel, and a reference signal. A liquid crystal provided with a timing signal generation circuit for outputting a timing signal for obtaining a timing for taking a display signal into the drive circuit and a timing for taking a storage capacitor signal into the liquid crystal display panel. In the display device, the timing signal generation circuit is realized by the above-described timing signal generation device.

According to the liquid crystal display device having the above-described configuration, it is possible to display an image with high display quality without causing a streak defect (CS streak defect) due to the storage capacitor signal.

In order to solve the above-described problems, a television receiver of the present invention includes a tuner unit that receives a television broadcast and a display device that displays the television broadcast received by the tuner unit. The liquid crystal display device is used as the display device.

According to the television receiver having the above-described configuration, it is possible to display an image with high display quality without causing a streak defect (CS streak defect) due to the retention capacity signal.

The timing signal generation device of the present invention is applicable to any liquid crystal display having a function for controlling viewing angle characteristics using a storage capacitor signal, that is, a CS function, and thus includes such a liquid crystal display. In addition to an electronic device, for example, a television receiver, any electronic device in which a liquid crystal display can be mounted, such as a monitor for a personal computer and a portable terminal device, can be applied.

The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims, and technical means disclosed in different embodiments are appropriately combined. The obtained embodiments are also included in the technical scope of the present invention.

The present invention can be used for a liquid crystal display having a CS function and an electronic device including such a liquid crystal display.

1 Counter initialization circuit 2 Horizontal direction counter (first counter means)
3 vertical counter 4 signal generation circuit group

4a SSP circuit

4b GSP circuit 4c GCK circuit 4d FRP circuit 4e LR circuit 4f PWC circuit 4g PCTL circuit 4h UD circuit 5 GCK counter (second counter means, period detection means)
6 CS__ENABLE circuit (control signal generation circuit)
7 LUT (Look Up Table)
8 Horizontal counter stop circuit (count stop means)
9 Vertical counter stop circuit (count stop means)
10 TG (timing signal generation device, timing signal generation circuit)
11 Power supply circuit 12 LCDC
13 Video circuit 14 Driver circuit

14a Source driver

14b Gate driver 15 Pixel array 20 TG (timing signal generation device, timing signal generation circuit)
DESCRIPTION OF SYMBOLS 100 Liquid crystal display device 101 1st housing | casing 101a Opening part 102 2nd housing | casing 103 Operation circuit 104 Support member Ha 1st horizontal period Hb 2nd horizontal period T1 1 horizontal scanning period T2 Horizontal effective display period T3 Horizontal blanking period T4 1 vertical scanning period T5 vertical effective display period T6 vertical blanking period T91 1 horizontal scanning period T92 horizontal effective display period T94 1 vertical scanning period T95 vertical effective display period T96 vertical blanking period VSYNC vertical reference signal

Claims

For a drive circuit for driving a pixel array composed of electronic elements arranged in an array and receiving at least a reference signal, a timing for taking a display signal into the drive circuit and a storage capacitor signal are input to the pixel array. A timing signal generating device that outputs a timing signal for the timing to capture in
First counter means for performing a counting operation based on the reference signal;
A signal generation circuit for generating the timing signal in accordance with the count output of the first counter means;
A period from when the timing signal becomes high level to the next high level is defined as a first horizontal period Ha,
When the horizontal period obtained from the clock frequency and frame frequency of the signal output from the timing signal generator is the second horizontal period Hb,
Period detecting means for detecting a shift period of the second horizontal period Hb relative to the first horizontal period Ha;
A timing signal generation device comprising: a control signal generation circuit that generates a control signal for controlling the capture of the storage capacitor signal into the pixel array according to the period detected by the period detection means.
The control signal generation circuit includes:
2. The stop signal for stopping the capture of the storage capacitor signal into the pixel array is output as a control signal when the period detected by the period detection means is larger than a preset period. The timing signal generation device described.
The control signal generation circuit includes:
The delay signal for delaying the capture of the storage capacitor signal into the pixel array for a predetermined period is output as a control signal when the period detected by the period detection unit is larger than a preset period. The timing signal generator according to claim 1.
The control signal generation circuit includes:
Immediately after the timing signal becomes high level, the counter further comprises second counter means for counting the number of clocks of the signal output from the timing signal generator,
The difference between the number of clocks counted by the second counter means and the number of clocks of the first horizontal period Ha is detected by the period detecting means with respect to the first horizontal period Ha of the second horizontal period Hb. 3. The stop signal for stopping the capturing of the storage capacitor signal into the pixel array is output as a control signal when the period is larger than a preset period as the shift period. Timing signal generator.
The control signal generation circuit includes:
Immediately after the timing signal becomes high level, the counter further comprises second counter means for counting the number of clocks of the signal output from the timing signal generator,
The difference between the number of clocks counted by the second counter means and the number of clocks of the first horizontal period Ha is detected by the period detecting means with respect to the first horizontal period Ha of the second horizontal period Hb. 4. The delay signal for delaying the capture of the storage capacitor signal to the pixel array for a predetermined period is output as a control signal when the period is larger than a preset period as the shift period. The timing signal generation device described.
The control signal generation circuit includes:
The delay period for delaying the capture of the storage capacitor signal into the pixel array is determined from a lookup table in which the number of clocks indicating the shift period of the horizontal period Hb with respect to the horizontal period Ha is associated with the delay period. 6. The timing signal generation apparatus according to claim 5, wherein
A count stop means is further provided that can stop the counting operation of the first counter means after an arbitrary reference signal is inputted and before a next reference signal is inputted. The timing signal generation device according to any one of claims 1 to 6.
For a drive circuit for driving a pixel array composed of electronic elements arranged in an array and receiving at least a reference signal, a timing for taking a display signal into the drive circuit and a storage capacitor signal are input to the pixel array. A timing signal generation method by a timing signal generation circuit that generates a timing signal for timing to capture in
A first counting step for performing a counting operation based on the reference signal;
A timing signal generating step for generating the timing signal according to the count output of the first counting step, and
A period from when the timing signal becomes high level to the next high level is defined as a first horizontal period Ha,
When the horizontal period obtained from the clock frequency and the frame frequency of the signal output from the timing signal generation circuit is a second horizontal period Hb,
A period detection step of detecting a shift period of the second horizontal period Hb relative to the first horizontal period Ha;
A timing signal generation method, comprising: a control signal generation step of generating a control signal for controlling the capture of the storage capacitor signal into the pixel array according to the period detected by the period detection step.
A liquid crystal display panel comprising electronic elements arranged in an array;
A driving circuit for driving the liquid crystal display panel;
A timing signal that receives at least a reference signal and outputs a timing signal to the drive circuit to obtain a timing for taking a display signal into the drive circuit and a timing for taking a storage capacitor signal into the liquid crystal display panel In a liquid crystal display device including a generation circuit,
8. A liquid crystal display device, wherein the timing signal generation circuit is realized by the timing signal generation device according to claim 1.
In a television receiver including a tuner unit that receives a television broadcast and a display device that displays the television broadcast received by the tuner unit,
A television receiver comprising the liquid crystal display device according to claim 9 as the display device.