WO2012056600A1 - Oscillator - Google Patents

Oscillator Download PDF

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Publication number
WO2012056600A1
WO2012056600A1 PCT/JP2011/000424 JP2011000424W WO2012056600A1 WO 2012056600 A1 WO2012056600 A1 WO 2012056600A1 JP 2011000424 W JP2011000424 W JP 2011000424W WO 2012056600 A1 WO2012056600 A1 WO 2012056600A1
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Prior art keywords
wiring
negative resistance
parallel
oscillation units
transistors
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PCT/JP2011/000424
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French (fr)
Japanese (ja)
Inventor
小森　浩
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パナソニック株式会社
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Publication of WO2012056600A1 publication Critical patent/WO2012056600A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
    • H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B27/00—Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors

Definitions

  • the present invention relates to an oscillator mounted on a semiconductor integrated circuit, and particularly to an oscillator excellent in low current consumption performance.
  • an oscillator (differential oscillator) requires a large operating current in order to realize high stability of oscillation and reduction of phase noise.
  • FIG. 5 is a circuit diagram showing a schematic configuration of an oscillator having a conventional CMOS configuration.
  • the CMOS oscillator includes a negative resistance generator 41 that generates a negative resistance by connecting the gate terminals and drain terminals of a pair of PMOS transistors 411 and 412 so as to cross each other, and a pair of NMOS transistors.
  • the negative resistance generator 42 that generates a negative resistance by connecting the gate terminals and the drain terminals of the transistors 421 and 422 so as to cross each other, an inductor 431, and a capacitive element 432 are connected in parallel.
  • a resonance circuit (tank circuit) 43 is a resonance circuit (tank circuit) 43.
  • the Q value (Quality Factor) of the tank circuit 43 is practically a finite value, and an alternating current flows to cause the inductor 431 and Loss due to the resistance component of the capacitor 432 occurs. For this reason, in order for oscillation in the tank circuit 43 to be performed stably, a negative resistance sufficient to compensate for the loss due to the resistance component is required. In the oscillator shown in FIG. 5, two negative resistance generators 41 and 42 are intended to generate this negative resistance.
  • drain terminals of a pair of PMOS transistors 411 and 412 and drain terminals of a pair of NMOS transistors 421 and 422 corresponding thereto are respectively connected (having a so-called vertically stacked structure). Since each is connected in series between the power supply and GND, the same current flows as an operating current in the negative resistance generators 41 and 42. In such a configuration having two negative resistance generators 41 and 42, the negative resistance obtained from the same operating current can be made larger than when only one negative resistance generator is used. . In other words, since the negative resistance changes depending on the flowing current, the operating current for obtaining the necessary negative resistance can be reduced by using the two negative resistance generators 41 and 42. Can be said.
  • Patent Document 1 As another example of the conventional differential oscillator, in Patent Document 1, instead of the PMOS negative resistance generator 41, a differential pair circuit including a pair of NMOS transistors connected to each other by connecting their gate and drain. An oscillator in which is inserted is disclosed. Since this differential pair circuit is connected to its own gate and drain, negative resistance does not occur and it functions as a simple load.
  • the two negative resistance generators 41 and 42 have the effect of obtaining a stronger negative resistance than when only one of them is used, but the mutual conductance of the PMOS transistor is NMOS. As compared with the negative resistance of the negative resistance generator 42 alone, it has only a slight effect. For this reason, in order to obtain the negative resistance necessary for the oscillator to operate stably, the configuration of FIG. 5 combined with the negative resistance generator 41 using the PMOS transistor has only a small effect of reducing the operating current. .
  • an object of the present invention is to provide an oscillator that can operate stably by obtaining a necessary negative resistance with a small current.
  • an oscillator includes a first wiring and a second wiring, and a capacitive element and an inductor arranged in parallel with each other between the first wiring and the second wiring.
  • a negative resistance generator having a resonance circuit, and a plurality of transistors arranged so as to generate a negative resistance between the first wiring and the second wiring to cancel a loss generated in the resonance circuit;
  • a first bias terminal connected to the first wiring and the second wiring through the inductor; a second bias terminal connected to the first wiring and the second wiring through the plurality of transistors;
  • Each said first bias The terminals and the second bias terminal are connected in series with each other, and the plurality of transistors in the plurality of oscillation units are configured to have the same conductivity type.
  • the plurality of oscillating units are electrically coupled to each other so that the plurality of negative resistance generators are equivalently connected in parallel and the load resistance is increased. Furthermore, by electrically coupling the plurality of oscillation units, the plurality of resonance circuits are equivalently connected in parallel, and the capacitive elements and inductors of the plurality of resonance circuits are connected in parallel to each other.
  • the combined capacitance increases in proportion to the number of connected capacitive elements, and the combined value of resistance components indicating the loss of the capacitive elements and inductors is inversely proportional to the number of connected capacitive elements and inductors. Then decrease.
  • the Q values of the plurality of resonance circuits as a whole are proportional to the combined value of the capacitive element and the combined value of the resistance component indicating the loss, but the increase in the combined capacitance and the decrease in the combined value of the resistance component indicating the loss are mutually By canceling out, the Q value of the resonance circuit does not change as a result. For this reason, it is possible to obtain a sufficient negative resistance enough to cancel the resistance component generated in the plurality of resonance circuits without negatively operating the current, and a stable oscillation operation can be obtained.
  • the coupling portion includes a first capacitive element provided in a first coupling wiring that connects the first wirings of the plurality of oscillation units and a second coupling that connects the second wirings of the plurality of oscillation units.
  • the first wiring and the second wiring of the plurality of oscillation units are electrically connected to each other via the first capacitive element and the second capacitive element, respectively.
  • the impedance of the first capacitive element and the second capacitive element can be regarded as substantially zero. Therefore, the resonance circuits can be equivalently connected in parallel while preventing the direct current component of the current flowing through the first wiring and the second wiring from flowing directly between the resonance circuits. Therefore, the operating current can be reduced more effectively.
  • the coupling unit includes induction coils provided between the first wiring and the second wiring of the plurality of oscillation units, and the induction coils (coils) corresponding to the plurality of oscillation units are inducted by the induction coil. You may arrange
  • the coupling unit may be configured such that the inductors of the plurality of oscillation units are arranged in parallel so that electromagnetic induction occurs between the inductors.
  • the resonance circuits are equivalently connected in parallel without separately using a configuration in which the first wiring and the second wiring are electrically coupled to each other. Can be made.
  • the plurality of transistors may be N-type MOS transistors.
  • the present invention is configured as described above, and has the effect of being able to operate stably by obtaining the necessary negative resistance with a small current.
  • FIG. 1 is a circuit diagram showing a schematic configuration of the oscillator according to the first embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing a more detailed configuration of the oscillator shown in FIG.
  • FIG. 3 is a circuit diagram showing a schematic configuration of an oscillator according to the second embodiment of the present invention.
  • FIG. 4 is a circuit diagram showing a schematic configuration of the oscillator according to the third embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing a schematic configuration of an oscillator having a conventional CMOS configuration.
  • FIG. 1 is a circuit diagram showing a schematic configuration of the oscillator according to the first embodiment of the present invention.
  • an oscillator 1A in the present embodiment includes a plurality (two in the present embodiment) of oscillation units 10 and 20 (hereinafter also referred to as a first oscillation unit 10 and a second oscillation unit 20).
  • a coupling portion 30A that electrically couples the oscillation portions 10 and 20; These structures are formed on a semiconductor substrate.
  • the first oscillation unit 10 includes a resonance circuit (tank circuit) 13 having a capacitive element and an inductor (described later) disposed between the first wiring 11 and the second wiring 12 in parallel with each other, and a first wiring. 11 and the second wiring 12, a negative resistance generator 14 having a plurality of transistors (described later) disposed so as to generate a negative resistance that cancels the loss of the resonance circuit 13. Operates as a dynamic oscillator.
  • the second oscillation unit 20 includes a resonance circuit 23 and a negative resistance generator 24 between the first wiring 21 and the second wiring 22. In the negative resistance generators 14 and 24, the transistors that generate the negative resistance are all of the same conductivity type.
  • the oscillation units 10 and 20 include first bias terminals 15 and 25 connected to the first wirings 11 and 21 and the second wirings 12 and 22 via inductors of the resonance circuit 13, respectively, and a plurality of transistors. And second bias terminals 16 and 26 connected to the first wirings 11 and 21 and the second wirings 12 and 22.
  • the oscillation units 10 and 20 are connected in series with each other at the first bias terminal and the second bias terminal.
  • the first oscillating unit 10 and the second oscillating unit 20 include a second bias terminal 16 of the negative resistance generator 14 of the first oscillating unit 10 and a first bias terminal 25 of the second oscillating unit 20. Are connected in series with each other.
  • the first bias terminal 15 of the first oscillating unit 10 is connected to the positive voltage source VDD, and the second bias terminal 26 of the second oscillating unit 20 is connected to the ground GND.
  • the second bias terminal 26 of the second oscillation unit 20 may be connected to a voltage source having a voltage lower than the positive voltage source VDD instead of being connected to the ground GND.
  • the coupling unit 30A electrically couples the first wiring 11 of the first oscillating unit 10 and the first wiring 21 of the second oscillating unit 20 and also the second wiring 12 of the first oscillating unit 10 and the second oscillating unit.
  • the 20 second wirings 22 are electrically coupled.
  • the first wirings 11 and 21 and the second wirings 12 and 22 are electrically coupled to each other, whereby the plurality of negative resistance generators 14 and 24 are equivalently connected in parallel. Load resistance increases.
  • the first wirings 11 and 21 and the second wirings 12 and 22 are electrically coupled to each other, whereby the plurality of resonance circuits 13 and 23 are tightly coupled and equivalently connected in parallel.
  • the resonance circuits 13 and 23 oscillate at the same resonance frequency.
  • the overall Q value of the plurality of resonance circuits 13 and 23 does not change (details will be described later). For this reason, it is possible to obtain a sufficient negative resistance enough to cancel the resistance component generated in the plurality of resonance circuits 13 and 23 without increasing the operating current, and to obtain a stable oscillation operation.
  • FIG. 2 is a circuit diagram showing a more detailed configuration of the oscillator shown in FIG.
  • the resonant circuit 13 includes an inductor 133 and a capacitive element connected in parallel between the first terminal 131 connected to the first wiring 11 and the second terminal 132 connected to the second wiring 12. 134.
  • the first bias terminal 15 is connected to the first wiring 11 and the second wiring 12 via the inductor 133.
  • the resonance circuit 23 includes an inductor 233 and a capacitive element 234 connected in parallel with each other between the first terminal 231 and the second terminal 232.
  • the first bias terminal 25 is connected to the first wiring 21 and the second wiring 22 via the inductor 233.
  • FIG. 2 shows a configuration in which the first bias terminals 15 and 25 are connected to the central node of the inductors 133 and 233, but the present invention is not limited to this.
  • a plurality of inductors are connected in series.
  • the first bias terminal may be connected to any location where the inductors are connected.
  • the negative resistance generator 14 has one of main terminals (for example, a drain terminal) connected to a first terminal 141 connected to the first wiring 11 and a second terminal 142 connected to the second wiring 12, respectively.
  • a pair of transistors 143 and 144 are connected to each other (for example, source terminals).
  • each of the pair of transistors 143 and 144 is configured by an NMOS transistor (N-type MOSFET).
  • the control terminal (eg, gate terminal) of the transistor 143 is connected to one of the main terminals (eg, drain terminal) of the transistor 144, and the control terminal (eg, gate terminal) of the transistor 144 is connected to one of the main terminals of the transistor 143 (eg, drain). Terminal).
  • the negative resistance generator 24 includes a pair of transistors 243 and 244 in which one of the main terminals is connected to the first terminal 241 and the second terminal 242 and the other of the main terminals is connected to each other.
  • Each of the pair of transistors 243 and 244 is configured by an NMOS transistor.
  • the control terminal of the transistor 243 is connected to one of the main terminals of the transistor 244, and the control terminal of the transistor 244 is connected to one of the main terminals of the transistor 243.
  • the negative resistance generators 14 and 24 may have any configuration as long as negative resistance is generated by a plurality of transistors. For example, a plurality of pairs of transistors may be provided.
  • the second bias terminals 16 and 26 are connected to the other of the main terminals of the pair of transistors 143 and 144 and 243 and 244 (sides connected to each other) of the negative resistance generators 14 and 24.
  • the first oscillator 10 and the second oscillator 20 are connected in series by being connected to the first bias terminal 25 of one oscillator 20 and the second bias terminal 16 of the other first oscillator 10. Yes.
  • the first bias terminal 15 connected to the inductor 133 of the resonance circuit 13 is connected to the positive voltage source VDD, and the other of the main terminals of the pair of transistors 243 and 244 of the negative resistance generator 24.
  • the second bias terminal 26 connected to (the sides connected to each other) is connected to the ground GND.
  • the oscillating units 10 and 20 have a vertically stacked structure and are connected in series between the positive voltage source VDD and the ground GND, and thus operate with the same bias current.
  • the coupling unit 30A includes a first capacitive element 34 provided in the first coupling wiring 32 that connects the first wirings 11 and 21 of the oscillation units 10 and 20, and the second wirings 12 and 22 of the oscillation units 10 and 20. And a second capacitive element 33 provided in the second coupling wiring 31 for connecting the two.
  • the impedance of the first and second capacitive elements 33 and 34 with respect to the high-frequency signal generated in the resonance circuits 13 and 23 is small and can be regarded as substantially zero. Therefore, the resonance circuits 13 and 23 are equivalently connected in parallel to the high-frequency signal by the coupling unit 30A. Accordingly, the resonance circuits are equivalently connected in parallel while preventing the direct current component of the current flowing through the first wirings 11 and 21 and the second wirings 12 and 22 from flowing directly between the resonance circuits 13 and 23. be able to. Therefore, the operating current can be reduced more effectively.
  • the inductors 133 and 233 and the capacitive elements 134 and 234 of the resonance circuits 13 and 23 have the same inductance L and capacitance value C, respectively. Further, it is ideal that the inductors 133 and 233 and the capacitive elements 134 and 234 have no resistance component, but actually there are resistance components.
  • the resistance component indicating the loss due to these elements can be regarded as equivalent to a resistance element having a resistance value R connected in parallel with these elements.
  • the Q values of the resonance circuits 13 and 23 are represented by ⁇ CR which are respectively proportional to the combined capacitance of the capacitive elements 134 and 234 and the combined value of the resistance components indicating the loss.
  • ⁇ CR the combined capacitance value of the capacitive elements 134 and 234
  • the resistance value indicating the overall loss of the resonance circuits 13 and 23 can be regarded as an equivalent resistance element indicating the loss of each of the resonance circuits 13 and 23 being connected in parallel.
  • the Q values of the plurality of resonance circuits as a whole are such that the increase in the combined capacitance and the decrease in the combined value of the resistance component indicating the loss cancel each other, and as a result, the Q value of the resonance circuit does not change.
  • the plurality of resonance circuits 13 and 23 of the present embodiment can be regarded as one resonance circuit with respect to the Q value indicating the loss.
  • the negative resistance generators 14, 24 have transistors (MOS transistors) 143, 144, 243, 244 having the same conductivity type (N type), respectively, and are connected in parallel to the resonance circuits 13, 23, respectively. Since they are connected, the negative resistance in the entire two oscillation units 10 and 20 is doubled. Moreover, the two oscillating units 10 and 20 are connected in series with each other, and the bias current for operating them does not increase. Therefore, the negative resistance can be increased without increasing the Q value indicating the loss of the entire two oscillation units 10 and 20. Thereby, without increasing the operating current, it is possible to obtain a sufficient negative resistance enough to cancel the resistance component generated in the plurality of resonance circuits 13 and 23, and to obtain a stable oscillation operation.
  • MOS transistors MOS transistors
  • FIG. 3 is a circuit diagram showing a schematic configuration of an oscillator according to the second embodiment of the present invention.
  • the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
  • the difference of the oscillator 1B in the present embodiment from the first embodiment is that the coupling portion 30B is an induction coil provided between the first wirings 11 and 21 and the second wirings 12 and 22 of the plurality of oscillation units 10 and 20, respectively. 35, and the induction coils 35 and 36 are arranged in parallel so that electromagnetic induction occurs between the induction coils 35 and 36.
  • a high-frequency signal generated in the resonance circuits 13 and 23 due to electromagnetic induction by the induction coils 35 and 36 provided corresponding to each of the plurality of oscillation units 10 and 20 resonates through the induction coils 35 and 36. Transmission between the circuits 13 and 23 becomes possible. At this time, since the induction coils 35 and 36 are insulated, a direct current does not flow. Therefore, the resonance circuits 13 and 23 are equivalently connected in parallel while preventing the direct current component of the current flowing through the first wirings 11 and 21 and the second wirings 12 and 22 from flowing directly between the resonance circuits 13 and 23. Can be connected to. Therefore, the operating current can be reduced more effectively.
  • the first wirings 11 and 21 and the second wirings 12 and 22 of the plurality of oscillation units 10 and 20 are electrically coupled to each other as the first wirings 11 and 21.
  • the configuration is not limited to the configuration in which the second wirings 12 and 22 are connected to each other, and includes a configuration in which the first wirings 11 and 21 and the second wirings 12 and 22 are connected while being insulated.
  • FIG. 4 is a circuit diagram showing a schematic configuration of the oscillator according to the third embodiment of the present invention.
  • the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
  • the difference of the oscillator 1 ⁇ / b> C in the present embodiment from the first embodiment is that the coupling unit 30 ⁇ / b> C is arranged in parallel so that the inductors 133 and 233 of the plurality of oscillation units 10 and 20 generate electromagnetic induction between the inductors 133 and 233. Is configured.
  • FIG. 4 is a circuit diagram showing a schematic configuration of the oscillator according to the third embodiment of the present invention.
  • the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
  • the difference of the oscillator 1 ⁇ / b> C in the present embodiment from the first embodiment is that the coupling unit 30 ⁇ / b> C is arranged in parallel so that the induc
  • the coupling portion 30 ⁇ / b> C is shown by a broken line that connects the inductors 133 and 233.
  • the inductor 133 and the inductor 233 can be electromagnetically induced to each other. By being arranged in parallel, electrical coupling between the two is realized.
  • the induction coils 35 and 36 for electrically coupling the resonance circuits 13 and 23 are provided in addition to the inductors 133 and 233.
  • the inductor 133 and the induction coil 35 are connected in parallel. Since the inductor 233 and the induction coil 36 are connected in parallel, each can be equivalently composed of one inductor. That is, if the inductance of the inductor 133 is L1, and the inductance of the induction coil 35 is L2, the equivalent inductance value is L1 ⁇ L2 / (L1 + L2).
  • an inductor having such an inductance is used as the inductor 133 of the resonance circuit 13, and the inductors 133 and 233 of the plurality of resonance circuits 13 and 23 are inductively coupled (arranged so as to be capable of electromagnetic induction). is doing). Accordingly, the plurality of resonance circuits 13 and 23 are electrically coupled in the same manner as in the second embodiment without providing a separate coupling induction coil.
  • the first wirings 11 and 21 and the second wirings 12 and 22 are electrically coupled to each other by causing electromagnetic induction between the inductors 133 and 233 of the plurality of resonance circuits 13 and 23.
  • the resonance circuits 13 and 23 can be equivalently connected in parallel without using them. Thereby, the occupation area on the semiconductor substrate of the oscillator 1C can be reduced.
  • each resonance circuit and each negative resistance generator is not limited to the configuration illustrated in the above embodiment, and various configurations can be suitably applied.
  • an NMOS transistor is exemplified as a transistor constituting the negative resistance generator, but the present invention is not limited to this as long as a plurality of transistors used in the negative resistance generator have the same conductivity type.
  • an NPN transistor or a PNP transistor may be applied.
  • the capacitive element of the resonance circuit an element having a fixed capacitance is used as the capacitive element of the resonance circuit.
  • the present invention is not limited to this, and a variable capacitive element that can vary the capacitance according to the voltage may be used.
  • the oscillator can be configured as a voltage controlled oscillator (VCO) used in a phase locked loop (PLL) or the like.
  • the present invention is useful for operating the oscillator stably by obtaining a necessary negative resistance with a small current.

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  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

Provided is an oscillator capable of reliably operating by acquiring necessary negative resistance with less current. The present invention is provided with: a plurality of oscillation units (10 and 20) which are provided with resonant circuits (13 and 23) having capacitance elements (134 and 234) and inductors (133 and 233) which are disposed mutually in parallel, negative resistance generators (14 and 24) having a plurality of transistors disposed so that negative resistance which counteracts the loss from the resonant circuits (13 and 23) is generated, first bias terminals (15 and 25), and second bias terminals (16 and 26); and a coupling unit (30A) for electrically coupling the plurality of oscillation units (10 and 20) so that the resonant circuits (13 and 23) are each coupled to one another in parallel equivalently; wherein the plurality of oscillation units (10 and 20) are serially connected to one another in a first bias terminal (25) and a second bias terminal (16), respectively, thereof for each oscillation unit, and a plurality of transistors (143, 144, 243, and 244) in the plurality of oscillation units (10 and 20) are configured with mutually identical conductivity types.

Description

発振器Oscillator
　本発明は、半導体集積回路に搭載される発振器に関し、特に、低消費電流性能に優れた発振器に関する。 The present invention relates to an oscillator mounted on a semiconductor integrated circuit, and particularly to an oscillator excellent in low current consumption performance.
　近年、広く普及している移動体通信用無線機器において、低消費電流化への要求はますます高まってきている。送受信機能を実現する回路ブロックの中でも発振器（差動発振器）は、発振の高い安定性および位相雑音の低減を実現するため、大きな動作電流を必要とする。 In recent years, there has been an increasing demand for low current consumption in wireless devices for mobile communication that are widely used. Among circuit blocks that realize a transmission / reception function, an oscillator (differential oscillator) requires a large operating current in order to realize high stability of oscillation and reduction of phase noise.
　図５は従来のＣＭＯＳ構成を有する発振器の概略構成を示す回路図である。図５において、ＣＭＯＳ発振器は、一対のＰＭＯＳトランジスタ４１１，４１２のゲート端子とドレイン端子とが互いにクロスするように接続されることにより負性抵抗を生じさせる負性抵抗発生器４１と、一対のＮＭＯＳトランジスタ４２１，４２２のゲート端子とドレイン端子とが互いにクロスするように接続されることにより負性抵抗を生じさせる負性抵抗発生器４２と、インダクタ（inductor）４３１および容量素子４３２が並列接続された共振回路（タンク(tank)回路）４３とを備えている。 FIG. 5 is a circuit diagram showing a schematic configuration of an oscillator having a conventional CMOS configuration. In FIG. 5, the CMOS oscillator includes a negative resistance generator 41 that generates a negative resistance by connecting the gate terminals and drain terminals of a pair of PMOS transistors 411 and 412 so as to cross each other, and a pair of NMOS transistors. The negative resistance generator 42 that generates a negative resistance by connecting the gate terminals and the drain terminals of the transistors 421 and 422 so as to cross each other, an inductor 431, and a capacitive element 432 are connected in parallel. And a resonance circuit (tank circuit) 43.
　ここで、タンク回路４３を構成するインダクタ４３１および容量素子４３２は抵抗成分を有するため、タンク回路４３のＱ値（Ｑｕａｌｉｔｙ　Ｆａｃｔｏｒ）は現実的には有限値となり、交流電流が流れることでインダクタ４３１および容量素子４３２の抵抗成分による損失が発生する。このため、タンク回路４３における発振が安定に行われるためには、抵抗成分による損失を補うだけの負性抵抗が必要となる。図５に示す発振器では、２つの負性抵抗発生器４１，４２でこの負性抵抗を生じさせるように意図されている。負性抵抗発生器４１，４２は一対のＰＭＯＳトランジスタ４１１，４１２のドレイン端子とこれらに対応する一対のＮＭＯＳトランジスタ４２１，４２２のドレイン端子とがそれぞれ接続され（いわゆる縦積み構造を有しており）、それぞれが電源とＧＮＤとの間に直列に接続されているため、負性抵抗発生器４１，４２には同一の電流が動作電流として流れる。このような２つの負性抵抗発生器４１，４２を有する構成においては、負性抵抗発生器を１つだけ用いた場合に比べ、同じ動作電流から得られる負性抵抗をより大きくすることができる。逆に言えば、負性抵抗は流す電流に依存して変化することため、２つの負性抵抗発生器４１，４２を用いることにより、必要な負性抵抗を得るための動作電流を低減させることができるといえる。 Here, since the inductor 431 and the capacitive element 432 constituting the tank circuit 43 have resistance components, the Q value (Quality Factor) of the tank circuit 43 is practically a finite value, and an alternating current flows to cause the inductor 431 and Loss due to the resistance component of the capacitor 432 occurs. For this reason, in order for oscillation in the tank circuit 43 to be performed stably, a negative resistance sufficient to compensate for the loss due to the resistance component is required. In the oscillator shown in FIG. 5, two negative resistance generators 41 and 42 are intended to generate this negative resistance. In the negative resistance generators 41 and 42, drain terminals of a pair of PMOS transistors 411 and 412 and drain terminals of a pair of NMOS transistors 421 and 422 corresponding thereto are respectively connected (having a so-called vertically stacked structure). Since each is connected in series between the power supply and GND, the same current flows as an operating current in the negative resistance generators 41 and 42. In such a configuration having two negative resistance generators 41 and 42, the negative resistance obtained from the same operating current can be made larger than when only one negative resistance generator is used. . In other words, since the negative resistance changes depending on the flowing current, the operating current for obtaining the necessary negative resistance can be reduced by using the two negative resistance generators 41 and 42. Can be said.
　また、従来の差動発振器の別例として特許文献１では、ＰＭＯＳ負性抵抗発生器４１の代わりに、自身のゲートとドレインとを繋いでダイオード接続された一対のＮＭＯＳトランジスタからなる差動対回路が挿入された発振器が開示されている。この差動対回路は自身のゲートとドレインとが繋がれているため負性抵抗が生じず、単なる負荷として働いている。 As another example of the conventional differential oscillator, in Patent Document 1, instead of the PMOS negative resistance generator 41, a differential pair circuit including a pair of NMOS transistors connected to each other by connecting their gate and drain. An oscillator in which is inserted is disclosed. Since this differential pair circuit is connected to its own gate and drain, negative resistance does not occur and it functions as a simple load.
特開２００２－３５３７３６号公報JP 2002-353736 A
　図５に示したＣＭＯＳ発振器では二つの負性抵抗発生器４１，４２の働きで、一方のみを用いた場合に比べより強い負性抵抗が得られる効果があるものの、ＰＭＯＳトランジスタの相互コンダクタンスはＮＭＯＳのそれに比べ半分程度かそれ以下と小さいため、ＮＭＯＳトランジスタで構成された負性抵抗発生器４２単独の負性抵抗に比べ、わずかな効果しかなかった。このため、発振器が安定に動作するために必要な負性抵抗を得るためには、ＰＭＯＳトランジスタによる負性抵抗発生器４１を組み合わせた図５の構成においても動作電流の低減効果はわずかしかなかった。 In the CMOS oscillator shown in FIG. 5, the two negative resistance generators 41 and 42 have the effect of obtaining a stronger negative resistance than when only one of them is used, but the mutual conductance of the PMOS transistor is NMOS. As compared with the negative resistance of the negative resistance generator 42 alone, it has only a slight effect. For this reason, in order to obtain the negative resistance necessary for the oscillator to operate stably, the configuration of FIG. 5 combined with the negative resistance generator 41 using the PMOS transistor has only a small effect of reducing the operating current. .
　また、特許文献１に示した差動発振器においては、負荷として働く差動対回路が追加されるが、当該差動対回路においては負性抵抗が生じず、タンク回路に並列に抵抗性回路が付加されることとなるため、当該抵抗性回路で電力が消費されることとなり、動作電流が増大する問題がある。 In addition, in the differential oscillator shown in Patent Document 1, a differential pair circuit that acts as a load is added. However, in the differential pair circuit, a negative resistance is not generated, and a resistive circuit is provided in parallel with the tank circuit. Since this is added, power is consumed by the resistive circuit, and there is a problem that the operating current increases.
　そこで、本発明は上記の課題を解決するためになされたものであり、少ない電流で必要な負性抵抗が得られることにより、安定に動作することのできる発振器を提供することを目的とする。 Therefore, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide an oscillator that can operate stably by obtaining a necessary negative resistance with a small current.
　上記課題を解決するために、本発明に係る発振器は、第１配線および第２配線と、前記第１配線と前記第２配線との間に互いに並列に配設された容量素子およびインダクタを有する共振回路と、前記第１配線と前記第２配線との間に前記共振回路で生じた損失を打ち消す負性抵抗が生じるように配設された複数のトランジスタを有する負性抵抗発生器と、前記インダクタを介して第１配線及び第２配線に接続された第１バイアス（bias）端子と、前記複数のトランジスタを介して前記第１配線及び前記第２配線に接続された第２バイアス端子と、を備えた複数の発振部と、前記各共振回路が互いに等価的に並列に接続されるように、前記複数の発振部を電気的に結合する結合部と、を備え、前記複数の発振部は、それぞれの前記第１バイアス端子及び第２バイアス端子において互いに直列に接続され、前記複数の発振部における前記複数のトランジスタは、互いに同じ導電型で構成されている。 In order to solve the above problems, an oscillator according to the present invention includes a first wiring and a second wiring, and a capacitive element and an inductor arranged in parallel with each other between the first wiring and the second wiring. A negative resistance generator having a resonance circuit, and a plurality of transistors arranged so as to generate a negative resistance between the first wiring and the second wiring to cancel a loss generated in the resonance circuit; A first bias terminal connected to the first wiring and the second wiring through the inductor; a second bias terminal connected to the first wiring and the second wiring through the plurality of transistors; A plurality of oscillating units, and a coupling unit that electrically couples the plurality of oscillating units so that the respective resonance circuits are equivalently connected in parallel with each other. , Each said first bias The terminals and the second bias terminal are connected in series with each other, and the plurality of transistors in the plurality of oscillation units are configured to have the same conductivity type.
　上記構成によれば、複数の発振部が電気的に結合されることにより、複数の負性抵抗発生器が等価的に並列に接続され、負荷抵抗が増大する。さらに、複数の発振部が電気的に結合されることにより、複数の共振回路が等価的に並列に接続され、複数の共振回路の容量素子およびインダクタが互いに並列に接続される。容量素子が並列接続されると合成容量は接続される容量素子の数に比例して増大し、容量素子およびインダクタの損失を示す抵抗成分の合成値は接続される容量素子およびインダクタの数に反比例して減少する。複数の共振回路全体のＱ値は、容量素子の合成容量および損失を示す抵抗成分の合成値にそれぞれ比例するが、合成容量の増大分と損失を示す抵抗成分の合成値の減少分とが互いに打ち消しあうことにより、結果として共振回路のＱ値は変化しない。このため、動作電流を負やすことなく、複数の共振回路で生じる抵抗成分を打ち消すだけの十分な負性抵抗を得ることができ、安定な発振動作を得ることができる。 According to the above configuration, the plurality of oscillating units are electrically coupled to each other so that the plurality of negative resistance generators are equivalently connected in parallel and the load resistance is increased. Furthermore, by electrically coupling the plurality of oscillation units, the plurality of resonance circuits are equivalently connected in parallel, and the capacitive elements and inductors of the plurality of resonance circuits are connected in parallel to each other. When capacitive elements are connected in parallel, the combined capacitance increases in proportion to the number of connected capacitive elements, and the combined value of resistance components indicating the loss of the capacitive elements and inductors is inversely proportional to the number of connected capacitive elements and inductors. Then decrease. The Q values of the plurality of resonance circuits as a whole are proportional to the combined value of the capacitive element and the combined value of the resistance component indicating the loss, but the increase in the combined capacitance and the decrease in the combined value of the resistance component indicating the loss are mutually By canceling out, the Q value of the resonance circuit does not change as a result. For this reason, it is possible to obtain a sufficient negative resistance enough to cancel the resistance component generated in the plurality of resonance circuits without negatively operating the current, and a stable oscillation operation can be obtained.
　前記結合部は、前記複数の発振部の前記第１配線同士を接続する第１結合配線に設けられた第１容量素子と、前記複数の発振部の前記第２配線同士を接続する第２結合配線に設けられた第２容量素子とを有していてもよい。このような構成によれば、複数の発振部の第１配線および第２配線同士がそれぞれ第１容量素子および第２容量素子を介して電気的に接続されるため、共振回路で生じる高周波信号に対して第１容量素子および第２容量素子のインピーダンス（impedance）が略零とみなせる。したがって、第１配線および第２配線を流れる電流の直流成分が互いの共振回路間に直接流れ込むことを防止しつつ、共振回路同士を等価的に並列に接続させることができる。よって、より有効に動作電流を低減させることができる。 The coupling portion includes a first capacitive element provided in a first coupling wiring that connects the first wirings of the plurality of oscillation units and a second coupling that connects the second wirings of the plurality of oscillation units. You may have the 2nd capacitive element provided in wiring. According to such a configuration, the first wiring and the second wiring of the plurality of oscillation units are electrically connected to each other via the first capacitive element and the second capacitive element, respectively. On the other hand, the impedance of the first capacitive element and the second capacitive element can be regarded as substantially zero. Therefore, the resonance circuits can be equivalently connected in parallel while preventing the direct current component of the current flowing through the first wiring and the second wiring from flowing directly between the resonance circuits. Therefore, the operating current can be reduced more effectively.
　前記結合部は、前記複数の発振部の前記第１配線および前記第２配線間にそれぞれ設けられた誘導コイルを有し、前記複数の発振部に対応する前記誘導コイル(coil)同士が当該誘導コイル間で電磁誘導が生じるように並列配置されていてもよい。このような構成によれば、複数の発振部に対応する誘導コイルによる電磁誘導により共振回路で生じる高周波信号が共振回路間で伝達可能となる。したがって、第１配線および第２配線を流れる電流の直流成分が互いの共振回路間に直接流れ込むことを防止しつつ、共振回路同士を等価的に並列に接続されることができる。よって、より有効に動作電流を低減させることができる。 The coupling unit includes induction coils provided between the first wiring and the second wiring of the plurality of oscillation units, and the induction coils (coils) corresponding to the plurality of oscillation units are inducted by the induction coil. You may arrange | position in parallel so that electromagnetic induction may arise between coils. According to such a configuration, a high-frequency signal generated in the resonance circuit by electromagnetic induction by the induction coils corresponding to the plurality of oscillation units can be transmitted between the resonance circuits. Therefore, the resonance circuits can be equivalently connected in parallel while preventing the direct current component of the current flowing through the first wiring and the second wiring from flowing directly between the mutual resonance circuits. Therefore, the operating current can be reduced more effectively.
　前記結合部は、前記複数の発振部の前記インダクタ同士が当該インダクタ間で電磁誘導が生じるように並列配置されて構成されていてもよい。これにより、複数の共振回路のインダクタ間で電磁誘導を生じさせることにより、第１配線および第２配線同士を互いに電気的に結合する構成を別途用いることなく、共振回路同士を等価的に並列接続させることができる。 The coupling unit may be configured such that the inductors of the plurality of oscillation units are arranged in parallel so that electromagnetic induction occurs between the inductors. Thus, by causing electromagnetic induction between the inductors of the plurality of resonance circuits, the resonance circuits are equivalently connected in parallel without separately using a configuration in which the first wiring and the second wiring are electrically coupled to each other. Can be made.
　前記複数のトランジスタは、Ｎ型のＭＯＳトランジスタであってもよい。 The plurality of transistors may be N-type MOS transistors.
　本発明の上記目的、他の目的、特徴、及び利点は、添付図面参照の下、以下の好適な実施態様の詳細な説明から明らかにされる。 The above object, other objects, features, and advantages of the present invention will become apparent from the following detailed description of preferred embodiments with reference to the accompanying drawings.
　本発明は以上に説明したように構成され、少ない電流で必要な負性抵抗が得られることにより、安定に動作することができるという効果を奏する。 The present invention is configured as described above, and has the effect of being able to operate stably by obtaining the necessary negative resistance with a small current.
図１は本発明の第１実施形態に係る発振器の概略構成を示す回路図である。FIG. 1 is a circuit diagram showing a schematic configuration of the oscillator according to the first embodiment of the present invention. 図２は図１に示す発振器のより詳細な構成を示す回路図である。FIG. 2 is a circuit diagram showing a more detailed configuration of the oscillator shown in FIG. 図３は本発明の第２実施形態に係る発振器の概略構成を示す回路図である。FIG. 3 is a circuit diagram showing a schematic configuration of an oscillator according to the second embodiment of the present invention. 図４は本発明の第３実施形態に係る発振器の概略構成を示す回路図である。FIG. 4 is a circuit diagram showing a schematic configuration of the oscillator according to the third embodiment of the present invention. 図５は従来のＣＭＯＳ構成を有する発振器の概略構成を示す回路図である。FIG. 5 is a circuit diagram showing a schematic configuration of an oscillator having a conventional CMOS configuration.
　以下に、本発明に係る発振器の実施形態について、図面を参照しながら説明する。なお、以下では全ての図を通じて同一または相当する要素には同一の参照符号を付して、その重複する説明を省略する。 Hereinafter, embodiments of an oscillator according to the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference symbols throughout all the drawings, and redundant description thereof is omitted.
　＜第１実施形態＞
　まず、本発明の第１実施形態における発振器について説明する。図１は本発明の第１実施形態に係る発振器の概略構成を示す回路図である。図１に示すように、本実施形態における発振器１Ａは、複数（本実施形態においては２つ）の発振部１０，２０（以下、第１発振部１０および第２発振部２０とも称する）と、発振部１０，２０を電気的に結合する結合部３０Ａとを有している。これらの構成は、半導体基板上に形成される。 <First Embodiment>
First, the oscillator according to the first embodiment of the present invention will be described. FIG. 1 is a circuit diagram showing a schematic configuration of the oscillator according to the first embodiment of the present invention. As shown in FIG. 1, an oscillator 1A in the present embodiment includes a plurality (two in the present embodiment) of oscillation units 10 and 20 (hereinafter also referred to as a first oscillation unit 10 and a second oscillation unit 20). A coupling portion 30A that electrically couples the oscillation portions 10 and 20; These structures are formed on a semiconductor substrate.
　第１発振部１０は、第１配線１１と第２配線１２との間に互いに並列に配設された容量素子およびインダクタ（inductor：後述）を有する共振回路（タンク回路）１３と、第１配線１１と第２配線１２との間に共振回路１３の損失を打ち消す負性抵抗が生じるように配設された複数のトランジスタ（後述）を有する負性抵抗発生器１４とを有しており、差動発振器として動作する。同様に、第２発振部２０は、第１配線２１と第２配線２２との間に共振回路２３と、負性抵抗発生器２４とを有している。負性抵抗発生器１４，２４において負性抵抗を生じさせるトランジスタは何れも同じ導電型で構成されている。 The first oscillation unit 10 includes a resonance circuit (tank circuit) 13 having a capacitive element and an inductor (described later) disposed between the first wiring 11 and the second wiring 12 in parallel with each other, and a first wiring. 11 and the second wiring 12, a negative resistance generator 14 having a plurality of transistors (described later) disposed so as to generate a negative resistance that cancels the loss of the resonance circuit 13. Operates as a dynamic oscillator. Similarly, the second oscillation unit 20 includes a resonance circuit 23 and a negative resistance generator 24 between the first wiring 21 and the second wiring 22. In the negative resistance generators 14 and 24, the transistors that generate the negative resistance are all of the same conductivity type.
　また、発振部１０，２０は、それぞれ、共振回路１３のインダクタを介して第１配線１１，２１および第２配線１２，２２に接続された第１バイアス端子１５，２５と、複数のトランジスタを介して第１配線１１，２１および第２配線１２，２２に接続された第２バイアス端子１６，２６とを有している。そして、発振部１０，２０は、それぞれの第１バイアス端子および第２バイアス端子において互いに直列に接続されている。具体的には、第１発振部１０と第２発振部２０とは、第１発振部１０の負性抵抗発生器１４の第２バイアス端子１６と第２発振部２０の第1バイアス端子２５とが接続されることにより、互いに直列に接続されている。また、第１発振部１０の第1バイアス端子１５は正電圧源ＶＤＤに接続され、第２発振部２０の第２バイアス端子２６はグランドＧＮＤに接続されている。なお、第２発振部２０の第２バイアス端子２６は、グランドＧＮＤに接続される代わりに、正電圧源ＶＤＤより低い電圧を有する電圧源に接続されてもよい。 The oscillation units 10 and 20 include first bias terminals 15 and 25 connected to the first wirings 11 and 21 and the second wirings 12 and 22 via inductors of the resonance circuit 13, respectively, and a plurality of transistors. And second bias terminals 16 and 26 connected to the first wirings 11 and 21 and the second wirings 12 and 22. The oscillation units 10 and 20 are connected in series with each other at the first bias terminal and the second bias terminal. Specifically, the first oscillating unit 10 and the second oscillating unit 20 include a second bias terminal 16 of the negative resistance generator 14 of the first oscillating unit 10 and a first bias terminal 25 of the second oscillating unit 20. Are connected in series with each other. The first bias terminal 15 of the first oscillating unit 10 is connected to the positive voltage source VDD, and the second bias terminal 26 of the second oscillating unit 20 is connected to the ground GND. Note that the second bias terminal 26 of the second oscillation unit 20 may be connected to a voltage source having a voltage lower than the positive voltage source VDD instead of being connected to the ground GND.
　結合部３０Ａは、第１発振部１０の第１配線１１と第２発振部２０の第１配線２１とを電気的に結合するとともに、第１発振部１０の第２配線１２と第２発振部２０の第２配線２２とを電気的に結合するよう構成されている。 The coupling unit 30A electrically couples the first wiring 11 of the first oscillating unit 10 and the first wiring 21 of the second oscillating unit 20 and also the second wiring 12 of the first oscillating unit 10 and the second oscillating unit. The 20 second wirings 22 are electrically coupled.
　上記構成によれば、第１配線１１，２１および第２配線１２，２２同士が互いに電気的に結合されることにより、複数の負性抵抗発生器１４，２４が等価的に並列に接続され、負荷抵抗が増大する。また、第１配線１１，２１および第２配線１２，２２同士が互いに電気的に結合されることにより、複数の共振回路１３，２３同士が密に結合され、等価的に並列に接続される。これにより、複数の共振回路１３，２３の容量素子およびインダクタが互いに並列に接続されるため、共振回路１３，２３が同一の共振周波数で発振する。このとき、複数の共振回路１３，２３全体のＱ値は変化しない（詳しくは後述する）。このため、動作電流を増やすことなく、複数の共振回路１３，２３で生じる抵抗成分を打ち消すだけの十分な負性抵抗を得ることができ、安定な発振動作を得ることができる。 According to the above configuration, the first wirings 11 and 21 and the second wirings 12 and 22 are electrically coupled to each other, whereby the plurality of negative resistance generators 14 and 24 are equivalently connected in parallel. Load resistance increases. In addition, the first wirings 11 and 21 and the second wirings 12 and 22 are electrically coupled to each other, whereby the plurality of resonance circuits 13 and 23 are tightly coupled and equivalently connected in parallel. Thereby, since the capacitive elements and inductors of the plurality of resonance circuits 13 and 23 are connected in parallel to each other, the resonance circuits 13 and 23 oscillate at the same resonance frequency. At this time, the overall Q value of the plurality of resonance circuits 13 and 23 does not change (details will be described later). For this reason, it is possible to obtain a sufficient negative resistance enough to cancel the resistance component generated in the plurality of resonance circuits 13 and 23 without increasing the operating current, and to obtain a stable oscillation operation.
　以下、本実施形態のより具体的な構成について説明する。図２は図１に示す発振器のより詳細な構成を示す回路図である。本実施形態において、共振回路１３は、第１配線１１に接続される第１端子１３１と第２配線１２に接続される第２端子１３２との間に互いに並列に接続されたインダクタ１３３と容量素子１３４とを有している。第１バイアス端子１５は、インダクタ１３３を介して第１配線１１および第２配線１２に接続されている。同様に、共振回路２３は、第１端子２３１と第２端子２３２との間に互いに並列に接続されたインダクタ２３３と容量素子２３４とを有している。第１バイアス端子２５は、インダクタ２３３を介して第１配線２１および第２配線２２に接続されている。このように、互いに並列に接続されたインダクタ１３３，２３３と容量素子１３４，２３４とで構成され、第１バイアス端子１５，２５を介してインダクタ１３３，２３３に正電圧が印加されることにより、共振回路１３，２３は、並列共振する。なお、図２においては、第１バイアス端子１５，２５がインダクタ１３３，２３３の中央ノードに接続される構成が示されているが、本発明はこれに限られず、例えば複数のインダクタが直列接続された構成において、インダクタ同士が接続されているいずれかの箇所に第１バイアス端子が接続されることとしてもよい。 Hereinafter, a more specific configuration of the present embodiment will be described. FIG. 2 is a circuit diagram showing a more detailed configuration of the oscillator shown in FIG. In the present embodiment, the resonant circuit 13 includes an inductor 133 and a capacitive element connected in parallel between the first terminal 131 connected to the first wiring 11 and the second terminal 132 connected to the second wiring 12. 134. The first bias terminal 15 is connected to the first wiring 11 and the second wiring 12 via the inductor 133. Similarly, the resonance circuit 23 includes an inductor 233 and a capacitive element 234 connected in parallel with each other between the first terminal 231 and the second terminal 232. The first bias terminal 25 is connected to the first wiring 21 and the second wiring 22 via the inductor 233. In this way, the inductors 133 and 233 and the capacitive elements 134 and 234 connected in parallel to each other are configured, and a positive voltage is applied to the inductors 133 and 233 via the first bias terminals 15 and 25, thereby causing resonance. The circuits 13 and 23 resonate in parallel. FIG. 2 shows a configuration in which the first bias terminals 15 and 25 are connected to the central node of the inductors 133 and 233, but the present invention is not limited to this. For example, a plurality of inductors are connected in series. In this configuration, the first bias terminal may be connected to any location where the inductors are connected.
　負性抵抗発生器１４は、第１配線１１に接続される第１端子１４１および第２配線１２に接続される第２端子１４２にそれぞれ主端子の一方（例えばドレイン端子）が接続され、主端子の他方（例えばソース端子）同士が接続された一対のトランジスタ１４３，１４４を有している。本実施形態において、一対のトランジスタ１４３，１４４は何れもＮＭＯＳトランジスタ（Ｎ型のＭＯＳＦＥＴ）により構成されている。トランジスタ１４３の制御端子（例えばゲート端子）は、トランジスタ１４４の主端子の一方（例えばドレイン端子）に接続され、トランジスタ１４４の制御端子（例えばゲート端子）は、トランジスタ１４３の主端子の一方（例えばドレイン端子）に接続されている。同様に、負性抵抗発生器２４は、第１端子２４１および第２端子２４２にそれぞれ主端子の一方が接続され、主端子の他方同士が接続された一対のトランジスタ２４３，２４４を有している。一対のトランジスタ２４３，２４４は何れもＮＭＯＳトランジスタにより構成されている。トランジスタ２４３の制御端子は、トランジスタ２４４の主端子の一方に接続され、トランジスタ２４４の制御端子は、トランジスタ２４３の主端子の一方に接続されている。このように、一対のトランジスタ１４３，２４３および１４４，２４４の主端子の一方と制御端子とを互いにクロスさせるように接続することにより、負性抵抗発生器１４，２４は、負性抵抗を生じさせている。なお、負性抵抗発生器１４，２４の構成は、複数のトランジスタによって負性抵抗を生じさせる限りどのような構成を有しておいてもよい。例えば、一対のトランジスタが複数対設けられていてもよい。 The negative resistance generator 14 has one of main terminals (for example, a drain terminal) connected to a first terminal 141 connected to the first wiring 11 and a second terminal 142 connected to the second wiring 12, respectively. A pair of transistors 143 and 144 are connected to each other (for example, source terminals). In the present embodiment, each of the pair of transistors 143 and 144 is configured by an NMOS transistor (N-type MOSFET). The control terminal (eg, gate terminal) of the transistor 143 is connected to one of the main terminals (eg, drain terminal) of the transistor 144, and the control terminal (eg, gate terminal) of the transistor 144 is connected to one of the main terminals of the transistor 143 (eg, drain). Terminal). Similarly, the negative resistance generator 24 includes a pair of transistors 243 and 244 in which one of the main terminals is connected to the first terminal 241 and the second terminal 242 and the other of the main terminals is connected to each other. . Each of the pair of transistors 243 and 244 is configured by an NMOS transistor. The control terminal of the transistor 243 is connected to one of the main terminals of the transistor 244, and the control terminal of the transistor 244 is connected to one of the main terminals of the transistor 243. Thus, by connecting one of the main terminals of the pair of transistors 143, 243 and 144, 244 and the control terminal so as to cross each other, the negative resistance generators 14, 24 cause negative resistance. ing. The negative resistance generators 14 and 24 may have any configuration as long as negative resistance is generated by a plurality of transistors. For example, a plurality of pairs of transistors may be provided.
　また、負性抵抗発生器１４，２４の一対のトランジスタ１４３，１４４および２４３，２４４の主端子の他方（互いに接続されている側）には、第２バイアス端子１６，２６が接続されている。第１発振部１０と第２発振部２０とは、一方の発振部２０の第１バイアス端子２５と他方の第１発振部１０の第２バイアス端子１６と接続されることにより、直列接続されている。また、前述したように、共振回路１３のインダクタ１３３に接続された第１バイアス端子１５は、正電圧源ＶＤＤに接続され、負性抵抗発生器２４の一対のトランジスタ２４３，２４４の主端子の他方（互いに接続されている側）に接続された第２バイアス端子２６は、グランドＧＮＤに接続されている。このように、発振部１０，２０は、縦積み構造を有し、正電圧源ＶＤＤとグランドＧＮＤとの間に直列に接続されるため、同一のバイアス電流で動作する。 In addition, the second bias terminals 16 and 26 are connected to the other of the main terminals of the pair of transistors 143 and 144 and 243 and 244 (sides connected to each other) of the negative resistance generators 14 and 24. The first oscillator 10 and the second oscillator 20 are connected in series by being connected to the first bias terminal 25 of one oscillator 20 and the second bias terminal 16 of the other first oscillator 10. Yes. As described above, the first bias terminal 15 connected to the inductor 133 of the resonance circuit 13 is connected to the positive voltage source VDD, and the other of the main terminals of the pair of transistors 243 and 244 of the negative resistance generator 24. The second bias terminal 26 connected to (the sides connected to each other) is connected to the ground GND. As described above, the oscillating units 10 and 20 have a vertically stacked structure and are connected in series between the positive voltage source VDD and the ground GND, and thus operate with the same bias current.
　結合部３０Ａは、発振部１０，２０の第１配線１１，２１同士を接続する第１結合配線３２に設けられた第１容量素子３４と、発振部１０，２０の第２配線１２，２２同士を接続する第２結合配線３１に設けられた第２容量素子３３とを有している。 The coupling unit 30A includes a first capacitive element 34 provided in the first coupling wiring 32 that connects the first wirings 11 and 21 of the oscillation units 10 and 20, and the second wirings 12 and 22 of the oscillation units 10 and 20. And a second capacitive element 33 provided in the second coupling wiring 31 for connecting the two.
　共振回路１３，２３で発生した高周波信号に対して第１および第２容量素子３３，３４のインピーダンスは小さく略零とみなせる。従って、このような高周波信号に対して共振回路１３，２３は結合部３０Ａにより等価的に並列に接続されている。したがって、第１配線１１，２１および第２配線１２，２２を流れる電流の直流成分が互いの共振回路１３，２３間に直接流れ込むことを防止しつつ、共振回路同士を等価的に並列に接続させることができる。よって、より有効に動作電流を低減させることができる。 The impedance of the first and second capacitive elements 33 and 34 with respect to the high-frequency signal generated in the resonance circuits 13 and 23 is small and can be regarded as substantially zero. Therefore, the resonance circuits 13 and 23 are equivalently connected in parallel to the high-frequency signal by the coupling unit 30A. Accordingly, the resonance circuits are equivalently connected in parallel while preventing the direct current component of the current flowing through the first wirings 11 and 21 and the second wirings 12 and 22 from flowing directly between the resonance circuits 13 and 23. be able to. Therefore, the operating current can be reduced more effectively.
　ここで、等価的に並列に接続された共振回路１３，２３全体のＱ値について説明する。まず、共振回路１３，２３のインダクタ１３３，２３３および容量素子１３４，２３４は、それぞれ同様のインダクタンスＬおよび容量値Ｃを有している。また、インダクタ１３３，２３３および容量素子１３４，２３４は抵抗成分が存在しないことが理想であるが、実際には抵抗成分が存在する。これらの素子による損失を示す抵抗成分は、等価的にこれらの素子に並列に抵抗値Ｒの抵抗素子が接続されたものとみなせる。 Here, the overall Q value of the resonance circuits 13 and 23 connected in parallel will be described. First, the inductors 133 and 233 and the capacitive elements 134 and 234 of the resonance circuits 13 and 23 have the same inductance L and capacitance value C, respectively. Further, it is ideal that the inductors 133 and 233 and the capacitive elements 134 and 234 have no resistance component, but actually there are resistance components. The resistance component indicating the loss due to these elements can be regarded as equivalent to a resistance element having a resistance value R connected in parallel with these elements.
　このときの共振周波数をωとすると、共振回路１３，２３のＱ値は容量素子１３４，２３４の合成容量および損失を示す抵抗成分の合成値にそれぞれ比例するそれぞれωＣＲで表される。この２つの共振回路１３，２３を並列に接続した場合、容量素子１３４，２３４の合成容量値は、容量素子が並列接続されることにより２倍（２Ｃ）となる。また、共振回路１３，２３の全体の損失を示す抵抗値は、各共振回路１３，２３の損失を示す等価的な抵抗素子が並列接続されたものとみなせるため、１／２倍（Ｒ／２）となる。したがって、２つの共振回路１３，２３全体のＱ値はω（２Ｃ）（Ｒ／２）＝ωＣＲとなり、各共振回路１３，２３単体のＱ値と同じ値となる。すなわち、複数の共振回路全体のＱ値は、合成容量の増大分と損失を示す抵抗成分の合成値の減少分とが互いに打ち消しあうことにより、結果として共振回路のＱ値は変化しない。このように、本実施形態の複数の共振回路１３，２３は損失を示すＱ値に関してあたかも１つの共振回路とみなすことができる。 Suppose that the resonance frequency at this time is ω, the Q values of the resonance circuits 13 and 23 are represented by ωCR which are respectively proportional to the combined capacitance of the capacitive elements 134 and 234 and the combined value of the resistance components indicating the loss. When the two resonance circuits 13 and 23 are connected in parallel, the combined capacitance value of the capacitive elements 134 and 234 is doubled (2C) by connecting the capacitive elements in parallel. Further, the resistance value indicating the overall loss of the resonance circuits 13 and 23 can be regarded as an equivalent resistance element indicating the loss of each of the resonance circuits 13 and 23 being connected in parallel. ) Therefore, the Q value of the entire two resonance circuits 13 and 23 is ω (2C) (R / 2) = ωCR, which is the same value as the Q value of each of the resonance circuits 13 and 23 alone. In other words, the Q values of the plurality of resonance circuits as a whole are such that the increase in the combined capacitance and the decrease in the combined value of the resistance component indicating the loss cancel each other, and as a result, the Q value of the resonance circuit does not change. Thus, the plurality of resonance circuits 13 and 23 of the present embodiment can be regarded as one resonance circuit with respect to the Q value indicating the loss.
　これに対し、負性抵抗発生器１４，２４は、それぞれ同じ導電型（Ｎ型）を有するトランジスタ（ＭＯＳトランジスタ）１４３，１４４，２４３，２４４を有し、各共振回路１３，２３にそれぞれ並列に接続されているため、２つの発振部１０，２０全体における負性抵抗が２倍となる。しかも、２つの発振部１０，２０は互いに直列に接続されており、これらを動作させるバイアス電流は、増大しない。したがって、２つの発振部１０，２０全体の損失を示すＱ値を上げずに負性抵抗を上げることができる。これにより、動作電流を増やすことなく、複数の共振回路１３，２３で生じる抵抗成分を打ち消すだけの十分な負性抵抗を得ることができ、安定な発振動作を得ることができる。 On the other hand, the negative resistance generators 14, 24 have transistors (MOS transistors) 143, 144, 243, 244 having the same conductivity type (N type), respectively, and are connected in parallel to the resonance circuits 13, 23, respectively. Since they are connected, the negative resistance in the entire two oscillation units 10 and 20 is doubled. Moreover, the two oscillating units 10 and 20 are connected in series with each other, and the bias current for operating them does not increase. Therefore, the negative resistance can be increased without increasing the Q value indicating the loss of the entire two oscillation units 10 and 20. Thereby, without increasing the operating current, it is possible to obtain a sufficient negative resistance enough to cancel the resistance component generated in the plurality of resonance circuits 13 and 23, and to obtain a stable oscillation operation.
　＜第２実施形態＞
　次に、本発明の第２実施形態に係る発振器について説明する。図３は本発明の第２実施形態に係る発振器の概略構成を示す回路図である。本実施形態において第１実施形態と同様の構成については同じ符号を付し、説明を省略する。本実施形態における発振器１Ｂが第１実施形態と異なる点は、結合部３０Ｂが、複数の発振部１０，２０の第１配線１１，２１および第２配線１２，２２間にそれぞれ設けられた誘導コイル３５，３６を有し、誘導コイル３５，３６同士が当該誘導コイル３５，３６間で電磁誘導が生じるように並列配置されていることである。 Second Embodiment
Next, an oscillator according to a second embodiment of the invention will be described. FIG. 3 is a circuit diagram showing a schematic configuration of an oscillator according to the second embodiment of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The difference of the oscillator 1B in the present embodiment from the first embodiment is that the coupling portion 30B is an induction coil provided between the first wirings 11 and 21 and the second wirings 12 and 22 of the plurality of oscillation units 10 and 20, respectively. 35, and the induction coils 35 and 36 are arranged in parallel so that electromagnetic induction occurs between the induction coils 35 and 36.
　このような構成によれば、複数の発振部１０，２０のそれぞれに対応して設けられた誘導コイル３５，３６による電磁誘導により共振回路１３，２３で生じる高周波信号が誘導コイル３５，３６を通じて共振回路１３，２３間で伝達可能となる。このとき、誘導コイル３５，３６間は絶縁されているため、直流電流が流れることはない。したがって、第１配線１１，２１および第２配線１２，２２を流れる電流の直流成分が互いの共振回路１３，２３間に直接流れ込むことを防止しつつ、共振回路１３，２３同士を等価的に並列に接続されることができる。よって、より有効に動作電流を低減させることができる。 According to such a configuration, a high-frequency signal generated in the resonance circuits 13 and 23 due to electromagnetic induction by the induction coils 35 and 36 provided corresponding to each of the plurality of oscillation units 10 and 20 resonates through the induction coils 35 and 36. Transmission between the circuits 13 and 23 becomes possible. At this time, since the induction coils 35 and 36 are insulated, a direct current does not flow. Therefore, the resonance circuits 13 and 23 are equivalently connected in parallel while preventing the direct current component of the current flowing through the first wirings 11 and 21 and the second wirings 12 and 22 from flowing directly between the resonance circuits 13 and 23. Can be connected to. Therefore, the operating current can be reduced more effectively.
　なお、誘導コイル３５，３６のインダクタンスは、同じでもよいし、異なっていてもよい。誘導コイル３５に対する誘導コイル３６のインダクタンスの比をＮとすると、Ｎ＝１の場合は、第１実施形態と同様に同じ共振回路１３，２３同士を等価的に並列に接続した構成となるが、Ｎの値が１以外（０＜Ｎ＜１またはＮ＞１）となるようなインダクタンスの比にすることにより、一方の共振回路１３，２３の発振振幅を他方の共振回路２３，１３の発振振幅に対して大きくすることができ、設計の自由度を高めることができる。 Note that the inductances of the induction coils 35 and 36 may be the same or different. Assuming that the inductance ratio of the induction coil 36 to the induction coil 35 is N, when N = 1, the same resonance circuits 13 and 23 are equivalently connected in parallel as in the first embodiment. By making the inductance ratio such that the value of N is other than 1 (0 <N <1 or N> 1), the oscillation amplitude of one resonance circuit 13, 23 is changed to the oscillation amplitude of the other resonance circuit 23, 13. The degree of freedom of design can be increased.
　このように、本発明における結合部の構成において、複数の発振部１０，２０の第１配線１１，２１および第２配線１２，２２同士を互いに電気的に結合とは、第１配線１１，２１同士および第２配線１２，２２同士を接続する構成に限られず、第１配線１１，２１間および第２配線１２，２２間を絶縁（isolate）しつつ接続する構成も含まれる。 As described above, in the configuration of the coupling portion in the present invention, the first wirings 11 and 21 and the second wirings 12 and 22 of the plurality of oscillation units 10 and 20 are electrically coupled to each other as the first wirings 11 and 21. The configuration is not limited to the configuration in which the second wirings 12 and 22 are connected to each other, and includes a configuration in which the first wirings 11 and 21 and the second wirings 12 and 22 are connected while being insulated.
　＜第３実施形態＞
　次に、本発明の第３実施形態に係る発振器について説明する。図４は本発明の第３実施形態に係る発振器の概略構成を示す回路図である。本実施形態において第１実施形態と同様の構成については同じ符号を付し、説明を省略する。本実施形態における発振器１Ｃが第１実施形態と異なる点は、結合部３０Ｃが、複数の発振部１０，２０のインダクタ１３３，２３３同士が当該インダクタ１３３，２３３間で電磁誘導が生じるように並列配置されて構成されていることである。なお、図４においては理解容易のために、結合部３０Ｃがインダクタ１３３，２３３間を繋ぐような破線で示されているが、実際にはインダクタ１３３とインダクタ２３３とが互いに電磁誘導可能なように並列配置されていることにより両者間の電気的な結合が実現される。 <Third Embodiment>
Next, an oscillator according to a third embodiment of the invention will be described. FIG. 4 is a circuit diagram showing a schematic configuration of the oscillator according to the third embodiment of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The difference of the oscillator 1 </ b> C in the present embodiment from the first embodiment is that the coupling unit 30 </ b> C is arranged in parallel so that the inductors 133 and 233 of the plurality of oscillation units 10 and 20 generate electromagnetic induction between the inductors 133 and 233. Is configured. In FIG. 4, for easy understanding, the coupling portion 30 </ b> C is shown by a broken line that connects the inductors 133 and 233. However, in practice, the inductor 133 and the inductor 233 can be electromagnetically induced to each other. By being arranged in parallel, electrical coupling between the two is realized.
　前述した第２実施形態においては、インダクタ１３３，２３３とは別に共振回路１３，２３同士を電気的に結合するための誘導コイル３５，３６を設けているが、インダクタ１３３と誘導コイル３５とは並列に接続され、インダクタ２３３と誘導コイル３６とは並列に接続されているため、それぞれ等価的に１つのインダクタで構成することができる。すなわち、インダクタ１３３のインダクタンスをＬ１とし、誘導コイル３５のインダクタンスをＬ２とすれば、等価的なインダクタンスの値はＬ１・Ｌ２／（Ｌ１＋Ｌ２）となる。 In the second embodiment described above, the induction coils 35 and 36 for electrically coupling the resonance circuits 13 and 23 are provided in addition to the inductors 133 and 233. However, the inductor 133 and the induction coil 35 are connected in parallel. Since the inductor 233 and the induction coil 36 are connected in parallel, each can be equivalently composed of one inductor. That is, if the inductance of the inductor 133 is L1, and the inductance of the induction coil 35 is L2, the equivalent inductance value is L1 · L2 / (L1 + L2).
　したがって、本実施形態においては、このようなインダクタンスを有するインダクタを共振回路１３のインダクタ１３３として用い、複数の共振回路１３，２３のインダクタ１３３，２３３同士を誘導結合させている（電磁誘導可能に配置している）。これにより、別途結合用の誘導コイルを設けることなく第２実施形態と同様に複数の共振回路１３，２３が電気的に結合される。 Therefore, in the present embodiment, an inductor having such an inductance is used as the inductor 133 of the resonance circuit 13, and the inductors 133 and 233 of the plurality of resonance circuits 13 and 23 are inductively coupled (arranged so as to be capable of electromagnetic induction). is doing). Accordingly, the plurality of resonance circuits 13 and 23 are electrically coupled in the same manner as in the second embodiment without providing a separate coupling induction coil.
　このように、複数の共振回路１３，２３のインダクタ１３３，２３３間で電磁誘導を生じさせることにより、第１配線１１，２１および第２配線１２，２２同士を互いに電気的に結合する構成を別途用いることなく、共振回路１３，２３同士を等価的に並列接続させることができる。これにより、発振器１Ｃの半導体基板上の占有面積を小さくすることができる。 As described above, the first wirings 11 and 21 and the second wirings 12 and 22 are electrically coupled to each other by causing electromagnetic induction between the inductors 133 and 233 of the plurality of resonance circuits 13 and 23. The resonance circuits 13 and 23 can be equivalently connected in parallel without using them. Thereby, the occupation area on the semiconductor substrate of the oscillator 1C can be reduced.
　以上、本発明の実施の形態について説明したが、本発明は上記実施形態に限定されるものではなく、その趣旨を逸脱しない範囲内で種々の改良、変更、修正が可能である。例えば、複数の上記実施形態における各構成要素を任意に組み合わせることとしてもよい。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various improvements, changes, and modifications can be made without departing from the spirit of the present invention. For example, it is good also as combining each component in several said embodiment arbitrarily.
　上記実施形態においては、複数の発振部として２つの発振部を例示したが、本発明はこれに限られず、３つ以上の発振部を有する構成としてもよい。また、各共振回路および各負性抵抗発生器の構成は上記実施形態において例示した構成に限られず、種々の構成が好適に適用され得る。さらに、本実施形態においては負性抵抗発生器を構成するトランジスタとしてＮＭＯＳトランジスタを例示したが、本発明は負性抵抗発生器に用いられる複数のトランジスタが同じ導電型を有する限りこれに限られず、例えばＮＰＮトランジスタまたはＰＮＰトランジスタを適用してもよい。また、上記実施形態においては共振回路の容量素子として固定容量を有する素子を用いているが、本発明はこれに限られず電圧に応じて容量を可変することができる可変容量素子を用いてもよい。これにより発振器を位相同期回路（ＰＬＬ）等に用いられる電圧制御発振器（ＶＣＯ）として構成することも可能である。 In the above embodiment, two oscillating units are exemplified as the plurality of oscillating units. However, the present invention is not limited to this, and a configuration having three or more oscillating units may be employed. In addition, the configuration of each resonance circuit and each negative resistance generator is not limited to the configuration illustrated in the above embodiment, and various configurations can be suitably applied. Furthermore, in the present embodiment, an NMOS transistor is exemplified as a transistor constituting the negative resistance generator, but the present invention is not limited to this as long as a plurality of transistors used in the negative resistance generator have the same conductivity type. For example, an NPN transistor or a PNP transistor may be applied. In the above embodiment, an element having a fixed capacitance is used as the capacitive element of the resonance circuit. However, the present invention is not limited to this, and a variable capacitive element that can vary the capacitance according to the voltage may be used. . Thus, the oscillator can be configured as a voltage controlled oscillator (VCO) used in a phase locked loop (PLL) or the like.
　上記説明から、当業者にとっては、本発明の多くの改良や他の実施形態が明らかである。従って、上記説明は、例示としてのみ解釈されるべきであり、本発明を実行する最良の態様を当業者に教示する目的で提供されたものである。本発明の精神を逸脱することなく、その構造及び／又は機能の詳細を実質的に変更できる。 From the above description, many modifications and other embodiments of the present invention are apparent to persons skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure and / or function may be substantially changed without departing from the spirit of the invention.
　本発明は、発振器を、少ない電流で必要な負性抵抗が得られることにより、安定に動作させるために有用である。 The present invention is useful for operating the oscillator stably by obtaining a necessary negative resistance with a small current.
　１Ａ，１Ｂ，１Ｃ　発振器
　１０　第１発振部
　１１，２１　第１配線
　１２，２２　第２配線
　１３，２３　共振回路
　１４，２４　負性抵抗発生器
　１５，２５　第１バイアス端子
　１６，２６　第２バイアス端子
　２０　第２発振部
　３０Ａ，３０Ｂ，３０Ｃ　結合部
　３１　第１結合配線
　３２　第１容量素子
　３３　第２結合配線
　３４　第２容量素子
　３５，３６　誘導コイル
　１３１，１４１，２３１，２４１　第１端子
　１３２，１４２，２３２，２４２　第２端子
　１３３，２３３　インダクタ
　１３４，２３４　容量素子
　１４３，１４４，２４３，２４４　トランジスタ
 
  1A, 1B, 1C Oscillator 10 First oscillator 11, 21 First wire 12, 22 Second wire 13, 23 Resonant circuit 14, 24 Negative resistance generator 15, 25 First bias terminal 16, 26 Second bias terminal 20 2nd oscillation part 30A, 30B, 30C coupling | bond part 31 1st coupling wiring 32 1st capacitive element 33 2nd coupling wiring 34 2nd capacitive element 35,36 Inductive coil 131,141,231,241 1st terminal 132,142 , 232, 242 Second terminal 133, 233 Inductor 134, 234 Capacitor element 143, 144, 243, 244 Transistor

Claims (5)

  1. 　第１配線および第２配線と、前記第１配線と前記第２配線との間に互いに並列に配設された容量素子およびインダクタを有する共振回路と、前記第１配線と前記第２配線との間に前記共振回路の損失を打ち消す負性抵抗が生じるように配設された複数のトランジスタを有する負性抵抗発生器と、前記インダクタを介して第１配線および第２配線に接続された第１バイアス端子と、前記複数のトランジスタを介して前記第１配線および前記第２配線に接続された第２バイアス端子と、を備えた複数の発振部と、
    　前記各共振回路が互いに等価的に並列に接続されるように、前記複数の発振部を電気的に結合する結合部と、を備え、
    　前記複数の発振部は、それぞれの前記第１バイアス端子および第２バイアス端子において互いに直列に接続され、
    　前記複数の発振部における前記複数のトランジスタは、互いに同じ導電型で構成されている、発振器。     A resonance circuit having a first wiring and a second wiring, a capacitive element and an inductor disposed in parallel with each other between the first wiring and the second wiring, and the first wiring and the second wiring. A negative resistance generator having a plurality of transistors disposed so as to generate a negative resistance that cancels the loss of the resonant circuit between the first wiring and the first wiring connected to the first wiring and the second wiring through the inductor; A plurality of oscillation units comprising: a bias terminal; and a second bias terminal connected to the first wiring and the second wiring through the plurality of transistors;
    A coupling unit that electrically couples the plurality of oscillation units so that the resonance circuits are equivalently connected in parallel with each other, and
    The plurality of oscillation units are connected in series with each other at the first bias terminal and the second bias terminal,
    The plurality of transistors in the plurality of oscillation units are configured to have the same conductivity type.
  2. 　前記結合部は、前記複数の発振部の前記第１配線同士を接続する第１結合配線に設けられた第１容量素子と、前記複数の発振部の前記第２配線同士を接続する第２結合配線に設けられた第２容量素子とを有する、請求項１に記載の発振器。 The coupling portion includes a first capacitive element provided in a first coupling wiring that connects the first wirings of the plurality of oscillation units and a second coupling that connects the second wirings of the plurality of oscillation units. The oscillator according to claim 1, further comprising a second capacitor element provided in the wiring.
  3. 　前記結合部は、前記複数の発振部の前記第１配線および前記第２配線間にそれぞれ設けられた誘導コイルを有し、前記複数の発振部に対応する前記誘導コイル同士が当該誘導コイル間で電磁誘導が生じるように並列配置される、請求項１に記載の発振器。 The coupling unit includes induction coils respectively provided between the first wiring and the second wiring of the plurality of oscillation units, and the induction coils corresponding to the plurality of oscillation units are between the induction coils. The oscillator according to claim 1, which is arranged in parallel so that electromagnetic induction occurs.
  4. 　前記結合部は、前記複数の発振部の前記インダクタ同士が当該インダクタ間で電磁誘導が生じるように並列配置されて構成される、請求項１に記載の発振器。 2. The oscillator according to claim 1, wherein the coupling unit is configured such that the inductors of the plurality of oscillation units are arranged in parallel so that electromagnetic induction occurs between the inductors.
  5. 　前記複数のトランジスタは、Ｎ型のＭＯＳトランジスタである、請求項１に記載の発振器。 The oscillator according to claim 1, wherein the plurality of transistors are N-type MOS transistors.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014200065A (en) * 2013-03-12 2014-10-23 キヤノン株式会社 Oscillation element

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003078349A (en) * 2001-09-05 2003-03-14 Murata Mfg Co Ltd Balanced oscillator circuit and electronic device employing the same
US6639481B1 (en) * 2002-08-20 2003-10-28 Intel Corporation Transformer coupled quadrature tuned oscillator
JP2005513826A (en) * 2001-07-05 2005-05-12 テレフオンアクチーボラゲツト エル エム エリクソン（パブル） Oscillator
JP2005198084A (en) * 2004-01-08 2005-07-21 Matsushita Electric Ind Co Ltd Differential oscillation circuit
JP2007110701A (en) * 2005-10-11 2007-04-26 Samsung Electro Mech Co Ltd Body bias control type voltage controlled oscillator
JP2009177388A (en) * 2008-01-23 2009-08-06 Kawasaki Microelectronics Inc Lc oscillator

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005513826A (en) * 2001-07-05 2005-05-12 テレフオンアクチーボラゲツト エル エム エリクソン（パブル） Oscillator
JP2003078349A (en) * 2001-09-05 2003-03-14 Murata Mfg Co Ltd Balanced oscillator circuit and electronic device employing the same
US6639481B1 (en) * 2002-08-20 2003-10-28 Intel Corporation Transformer coupled quadrature tuned oscillator
JP2005198084A (en) * 2004-01-08 2005-07-21 Matsushita Electric Ind Co Ltd Differential oscillation circuit
JP2007110701A (en) * 2005-10-11 2007-04-26 Samsung Electro Mech Co Ltd Body bias control type voltage controlled oscillator
JP2009177388A (en) * 2008-01-23 2009-08-06 Kawasaki Microelectronics Inc Lc oscillator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014200065A (en) * 2013-03-12 2014-10-23 キヤノン株式会社 Oscillation element

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