JP4884405B2 - LC oscillator - Google Patents

Description

  The present invention relates to an LC oscillator (LC resonance circuit) including a negative resistance circuit that cancels the influence of parasitic resistance.

FIG. 10 is a conceptual diagram illustrating an example of the configuration of a conventional LC oscillator. The LC oscillator 50 shown in the figure is constituted by an inductor L _p , a capacitor C _p and a negative resistance circuit 52 connected in parallel between two terminals 20 and 22. The inductor L _p has a parasitic resistance. Therefore, the negative resistance circuit 52 is provided so as to cancel the influence of the parasitic resistance and to ensure that the LC oscillator 50 can oscillate at a predetermined frequency.

  In a conventional LC oscillator, an LC tank (a parallel circuit of an inductor and a capacitor) is configured by one inductor. In the LC oscillator of this configuration, the LC tank is directly subjected to various restrictions of the next-stage device, such as the load of the oscillation signal output from the two terminals being required to be equal (symmetry of output). . For this reason, the active element that constitutes the negative resistance circuit 52 that drives the LC tank is also subject to restrictions such as symmetry in its output signal.

  In the on-chip LC oscillator, there is a large loss (loss) due to parasitic resistance and mutual inductance with the silicon substrate in the inductor portion. For this reason, it is difficult to achieve a high Q value (amplitude increase coefficient), and it has always been a problem to reduce the phase noise (for example, jitter) of the oscillation signal. Here, the Q value is an index representing the state of vibration. A higher Q value means that the oscillation of the oscillation signal is more stable.

  In order to oscillate an LC oscillator having a low Q value, it is necessary to use an active element having a relatively large driving capability. However, there is a problem that the noise component generated in the active element is equal to or larger than the noise component due to the loss of the LC oscillator.

  By the way, in order to suppress the phase noise of the oscillation signal, there are two approaches, “make an on-chip inductor with a high Q factor” or “drive the LC tank with lower noise”, and have been actively discussed so far. I came.

  Regarding the former, the pattern ground shield (Pattern Ground Shield) technique dramatically improved the loss to the silicon substrate via the capacitor. However, even if the pattern ground shield technique is used, there is no way to prevent loss due to the induced current in the silicon substrate. Therefore, unless the manufacturing process itself is changed, it will be difficult to dramatically improve the loss in the future.

  On the other hand, various methods have been proposed for the latter. However, since the LC tank is directly connected to the active element that drives the LC tank, there are restrictions on the oscillation signal of the LC oscillator, such as the bias point, swing width (signal amplitude), symmetry, and so on. This is a major obstacle to reducing noise. As a result, it is inevitable that noise having the same strength as the noise component from the LC tank is also generated from the active element.

  As described above, in the on-chip LC oscillator, the loss of the LC tank itself is large, and unless the manufacturing process is improved, further improvement of the Q value cannot be expected. Also, the noise generated by the active element that drives the LC tank with a large loss is about the same as the noise from the LC tank. Under the situation where the LC tank and the active element are directly connected, the noise from the active element is further reduced. There was a problem that it was difficult to suppress.

  Here, there is no prior art document directly related to the present invention, but there is Patent Document 1 as a prior art document of an LC oscillator using a mutual inductance generated by a mutual induction action as in the present invention. .

  In Patent Document 1, a capacitor element and a switch element are connected in parallel between both terminals of a secondary side inductance element that is arranged so as to face an inductance element that constitutes an LC resonance circuit and is mutually inductively coupled. When the element is turned off, the capacitance element is connected between both terminals of the secondary side inductance element, and the equivalent inductance increases. When the switch element is turned on, between the terminals of the secondary side inductance element An LC resonant oscillation circuit is disclosed in which the equivalent inductance is reduced in a short-circuited state.

JP 2007-174552 A

An object of the present invention is to provide an LC oscillator capable of solving the problems of the prior art and improving the degree of freedom for controlling the restrictions even when restrictions such as symmetry of the oscillation signal are required. There is.
A further object of the present invention is to provide an LC oscillator capable of reducing the phase noise of the oscillation signal in addition to the above object.

In order to achieve the above object, the present invention relates to an LC tank including a first inductor and a capacitor connected in parallel, a primary LC oscillator including a first negative resistance circuit, and a mutual inductance. A second-side LC oscillator including a second inductor and a second negative resistance circuit coupled to the first inductor by a mutual inductive action that occurs, and only the primary-side LC oscillator is the first-side LC oscillator. An LC oscillator having two output terminals connected to both ends of one inductor for outputting an oscillation signal, wherein the secondary LC oscillator does not have an output terminal for outputting an oscillation signal. An oscillator is provided.

The negative resistance circuit of the primary side LC oscillator outputs a symmetric signal between the output terminals connected to both ends of the first inductor, and the negative resistance circuit of the secondary side LC oscillator Preferably outputs an asymmetric signal between terminals connected to both ends of the second inductor.

Here, the negative resistance circuit of the LC oscillator on the secondary side includes an inverter, a first capacitor connected between the input terminal of the inverter and the ground, and an output terminal of the inverter and the ground. A second capacitor connected to
It is preferable that the capacitance value of the second capacitor is larger than the capacitance value of the first capacitor.

  The negative resistance circuit on the secondary side has no restrictions such as a DC bias point, swing (signal amplitude), symmetry, and parasitic capacitance. As a result, according to the present invention, even when the negative resistance circuit on the primary side and the negative resistance circuit on the secondary side are combined, these restrictions are greatly improved, so that the negative resistance circuit with lower noise can be obtained. Can be realized. As a result, the phase noise of the oscillation signal can be greatly reduced as the entire LC oscillator.

  In addition, since the secondary side negative resistance circuit does not have the above-mentioned restrictions, the control of the DC bias point, swing, symmetry, parasitic capacitance, etc. is not limited to the reduction of the phase noise of the oscillation signal. In this LC oscillator, the degree of freedom can be improved to some extent. As a result, the degree of freedom of control of the DC bias point, swing, symmetry, parasitic capacitance, etc. can be improved for the entire LC oscillator.

  Further, according to the present invention, by designing the capacitance value of the capacitor on the output terminal side to be larger than the capacitance value of the capacitor on the input terminal side of the inverter constituting the secondary negative resistance circuit, The noise characteristics of the signal can be improved.

  Hereinafter, an LC oscillator according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a conceptual diagram of an embodiment showing the configuration of the LC oscillator of the present invention. The LC oscillator 10 shown in FIG. 1 includes a primary side LC oscillator 12 and a secondary side LC oscillator 14.

The primary-side LC oscillator 12 includes an inductor L _p , a capacitor C _p and a negative resistance circuit 16 connected in parallel between the two terminals 20 and 22. On the other hand, the secondary-side LC oscillator 14 includes an inductor L _m1 and a negative resistance circuit 18 connected to each other. The primary side and secondary side inductors L _p and L _m1 constitute a mutual inductor, and the two are coupled by a mutual induction action that generates a mutual inductance M.

  Here, in the negative resistance circuits 16 and 18, the current decreases as the output terminal voltage increases, and the current increases as the output terminal voltage decreases. In other words, the voltage increases as the current decreases. The voltage decreases as the current increases.

The LC tank including the inductor L _p and the capacitor C _p connected in parallel between the two terminals 20 and 22 always has a loss represented by parasitic resistance. Therefore, for the purpose of canceling the influence of the parasitic resistance and ensuring that the oscillation of the LC oscillator 10 is sustained, the negative resistance circuit 16 is provided in the primary LC oscillator 12 and the negative LC oscillator 14 is negative. A resistive circuit 18 is provided.

As shown in the conventional LC oscillator 50 shown in FIG. 10, the LC oscillator 10 moves a part of the negative resistance circuit originally provided only in the primary side LC oscillator 12 to the secondary side LC oscillator 14. Thus, the loss of the LC tank on the primary side is compensated. Therefore, the sum of the resistance value of the negative resistance circuit 16 on the primary side and the resistance value of the negative resistance circuit 18 on the secondary side is sufficiently large to cancel the resistance value of the parasitic resistance of the inductor L _p. In other words, it is designed to be equal to or greater than the resistance value of the parasitic resistance of the inductor L _p and have the opposite polarity.

  The negative resistance circuit 18 on the secondary side has no restrictions such as a DC bias point, swing, symmetry, and parasitic capacitance. As a result, even if the primary negative resistance circuit 16 and the secondary negative resistance circuit 18 are combined, these restrictions are greatly improved, so that a lower noise negative resistance circuit can be realized. As a result, the phase noise of the oscillation signal can be greatly reduced as the entire LC oscillator 10.

  Further, since the secondary side negative resistance circuit 18 does not have the above-described restriction, the control of the DC bias point, swing, symmetry, parasitic capacitance, etc. is not limited to the reduction of the phase noise of the oscillation signal. In the LC oscillator 14 on the side, the degree of freedom can be improved to some extent. As a result, the LC oscillator 10 as a whole can improve the degree of freedom in controlling the DC bias point, swing, symmetry, parasitic capacitance, and the like.

FIG. 2 is a circuit diagram showing the configuration of the negative resistance circuit on the primary side. The negative resistance circuit 16 shown in FIG. 1 includes two N-type MOS transistors (hereinafter referred to as NMOS) 24 and 26 and a constant current source 28. The drains of the NMOSs 24 and 26 are connected to the terminals 20 and 22, respectively, and the gates of the NMOSs 24 and 26 are connected to the terminals 22 and 20, respectively. The constant current source 28 is connected between the sources of the NMOSs 24 and 26 and the ground. In the figure, G _m represents the voltage / current gain (transconductance) of the NMOSs 24 and 26.

  In the negative resistance circuit 16, when the voltage at the terminal 20 decreases, and conversely, the voltage at the terminal 22 increases, the NMOS 24 transitions from the off state to the on state, and the NMOS 26 transitions from the on state to the off state. Therefore, the current flowing from the terminal 20 to the ground via the NMOS 24 and the constant current source 28 gradually increases, and the current flowing from the terminal 22 via the NMOS 26 and the constant current source 28 gradually decreases.

  On the other hand, when the voltage at the terminal 20 increases and the voltage at the terminal 22 decreases, the NMOS 24 transitions from the on state to the off state, and the NMOS 26 transitions from the off state to the on state. Therefore, the current flowing from the terminal 20 to the ground via the NMOS 24 and the constant current source 28 gradually decreases, and the current flowing from the terminal 22 via the NMOS 26 and the constant current source 28 gradually increases.

The primary-side negative resistance circuit 16 is required to have a symmetrical output signal. Therefore, the voltage / current gains G _m of the NMOSs 24 and 26 are designed to be equal, and a symmetrical signal is output between the terminals 20 and 22.

FIG. 3 is a circuit diagram showing the configuration of the negative resistance circuit on the secondary side. The negative resistance circuit 18 shown in the figure includes an inverter 30 connected between two terminals 32 and 34, a capacitor C ₁ connected between an input terminal of the inverter 30 and the ground, and an output of the inverter 30. The capacitor C ₂ is connected between the terminal and the ground. Here, the capacitance value of the capacitor C ₂ is set larger than the capacitance value of the capacitor C ₁ .

  The signal input to the negative resistance circuit 18 is, for example, a sine wave having a frequency of several GHz and a small amplitude. When such a high-frequency small signal (small amplitude signal) is input to the inverter 30, the inverter 30 has the same frequency as the input signal and the same frequency as the input signal, instead of the rectangular wave having the opposite polarity, A sine wave having substantially reverse polarity and an amplified amplitude is output.

The secondary negative resistance circuit 18 is not required to be symmetrical. For this reason, the capacitance value of the capacitor C ₂ is designed to be larger than the capacitance value of the capacitor C ₁ , and an asymmetric signal is output between the terminals 32 and 34. As in the above example, the noise characteristic of the oscillation signal can be improved by designing the capacitance value of the capacitor C ₂ to be larger than the capacitance value of the capacitor C ₁ .

  Next, noise characteristics of the LC oscillator 10 will be described.

FIG. 4 is a circuit diagram showing the configuration of the Spice model of the primary LC oscillator shown in FIG. The Spice model of the LC oscillator shown in FIG. 1 includes an inductor L _S and a capacitor C _p corresponding to the inductor L _p in FIG. 1, a resistor R _S , a capacitor C _ox2 , a resistor R _sub2 and a capacitor C _sub2, and a capacitor C. It is constituted by _ox1 , a resistor _Rsub1, and a capacitor _Csub1 .

The inductor L _S and the resistor R _S are connected in series between the two terminals 20 and 22. The capacitor C _ox2 is connected to the terminal 20, and the resistor R _sub2 and the capacitor C _sub2 are connected in parallel between the capacitor C _ox2 and the terminal 36. The capacitor C _ox1 is connected to the terminal 22, and the resistor R _sub1 and the capacitor C _sub1 are connected in parallel between the capacitor C _ox1 and the terminal 36.

Here, the resistor R _S represents the parasitic resistance of the inductor L _S. The terminal 36 is a terminal connected to the semiconductor substrate. Elements other than the inductor L _S , the capacitor C _p and the resistor R _S are provided between the terminals 20 and 22 to which the inductor L _S and the capacitor C _p constituting the LC tank are connected, and the terminal 36 connected to the semiconductor substrate. Represents existing parasitic resistance and capacitance. The negative resistance circuit 16 is not shown.

  Next, FIG. 5 is a circuit diagram showing the configuration of the Spice model of the LC oscillator shown in FIG. This figure is obtained by adding the secondary LC oscillator 18 shown in FIG. 3 to the Spice model of the primary LC oscillator 12 shown in FIG.

Here, inductance of inductor L _S = 10 nH, capacitance value of capacitor C _p = 1 pF, resistance value of resistor R _S = 10Ω, capacitance value of capacitor C _ox2 = 120 _fF , resistance value of resistor R _sub2 = 750Ω, capacitor C _sub2 Capacitance value = 50 _fF , capacitance value of capacitor C _ox1 = 120 _fF , resistance value of resistor R _sub1 = 500Ω, capacitance value of capacitor C _sub1 = 75 fF, oscillation frequency of oscillation signal = 10 ¹⁰ rad / s (1.6 GHz) To do.

Further, in the LC oscillator 14 on the secondary side, the inductance of the inductor L _m1 = 5 nH, the mutual inductance M = 5 nH generated by the mutual induction action of the inductor L _S and the inductor L _m1, and the voltage / current gain G _m of the inverter 30 = It is assumed that the capacitance value of the capacitor C ₁ on the input terminal side of the inverter 30 is 800 fF and the capacitance value of the capacitor C ₂ on the output terminal side is 2.5 pF.

FIG. 6 is a circuit diagram showing a configuration in which the secondary LC oscillator is replaced with an equivalent circuit in the Spice model of the LC oscillator shown in FIG. The equivalent circuit of the secondary-side LC oscillator 14 shown in the figure is configured by an inductor L _m1 , a resistor R _e1 and a capacitor C _e1, and a noise current source 38. The inductor L _m1 , the resistor R _e1 and capacitor C _e1 connected in series, and the noise current source 38 are connected in parallel.

In the secondary-side LC oscillator shown in FIG. 5, the voltage / current gain G _m = 0.05 of the inverter 30, the capacitance value of the capacitor C ₁ on the input terminal side of the inverter 30 = 800 fF, and the capacitor C ₂ on the output terminal side When the capacitance value is 2.5 pF, in the equivalent circuit of the secondary side LC oscillator 14 shown in FIG. 6, the resistance value of the resistor R _e1 = −250Ω, the capacitance value of the capacitor C _e1 = 600 fF, and the current of the noise current source 38 The value I _nX ² ￣ = 4 kTγ (0.05 / 56.1).

Here, k represents a Boltzmann coefficient, T represents an absolute temperature, and γ represents a noise coefficient of the MOS transistor. Noise occurs randomly. Therefore, the formula for calculating the current value I _nX ²の of the noise current source 38 represents the dispersion value of the current.

FIG. 7 is a circuit diagram showing a configuration in which the equivalent circuit of the secondary LC oscillator is replaced with the equivalent circuit of the primary LC oscillator in the Spice model of the LC oscillator shown in FIG. The equivalent circuit of the primary-side LC oscillator shown in the figure is constituted by an equivalent impedance Z _{neg, eq} and a noise voltage source 40. The equivalent impedance Z _{neg, eq} and the noise voltage source 40 are connected in series between the inductor L _S and the resistor R _S.

In the equivalent circuit of the secondary side LC oscillator shown in FIG. 6, the resistance value of the resistor R _e1 = −250Ω, the capacitance value of the capacitor C _e1 = 600 fF, the current value I _nX ² ￣ = 4 kTγ (0. 05 / 56.1), in the equivalent circuit of the primary side LC oscillator shown in FIG. 7, the equivalent impedance Z _{neg, eq} = −8.25Ω + 3.8j (= −8.25Ω + 0.38 nH), noise voltage source A voltage value of 40, V _{n, eq} ² ４０ = 4 kTγ * 2.64.

Here, in the equivalent circuit of the primary side LC oscillator shown in FIG. 7, the equivalent impedance Z _{neg, eq} is calculated by the following equation.
Z _{neg, eq} = (ωM) ² / (− R + 1 / jωC _x )
M is mutual inductance = 5 nH, −R is resistance value of the resistor R _e1 = −250Ω, j is an imaginary unit, ω is angular frequency = 10 ¹⁰ rad / s, and C _x is a capacitance value of the capacitor C _e1 = 600 fF.

If LC oscillator 50 in FIG. 10, the voltage value V _n of the noise voltage source _40, but the _eq ² ¯ = _4kTγ * 8.25, if the LC oscillator of FIG 7, the voltage of the noise voltage source 40 value V _{n , eq} ² ￣ = 4 kTγ * 2.64. That is, in order to obtain the resistance value of the negative resistance = −8.25Ω, the LC oscillator 50 of FIG. 10 generates thermal noise equal to the resistor of 8.25Ω, whereas the LC oscillator of FIG. It can be seen that only thermal noise equal to the resistor is generated.

  From the above results, it can be seen that, while the resistance value of the negative resistance obtained is −8.25Ω, the applied thermal noise is about the same as the resistor having the resistance value = 2.64Ω. When the negative resistance circuit 16 shown in FIG. 2 is used as the secondary-side negative resistance circuit, in order to obtain a negative resistance value of −8.25Ω, the resistance value is about the resistance of 8.25Ω. In view of the occurrence of noise, it can be seen that lower noise can be achieved with the negative resistance circuit 18 of FIG.

Here, when the same calculation is performed when both capacitors C ₁ and C ₂ are set to 1.4 pF, the obtained negative resistance value is −8.25Ω, whereas the added thermal noise is 8.4Ω. Since it is equivalent to the resistance, it is confirmed that the noise is reduced when the symmetry of the capacitance values of the capacitors C ₁ and C ₂ is broken.

Conversely, assuming that the capacitance value of the capacitor C ₁ is 2.5 pF, the capacitance value of the capacitor C ₂ is 800 fF, and the capacitor C ₁ and the capacitor C ₂ in FIG. Although the value does not change at 8.25Ω, the value of the capacitor C ₂ connected to the inverter output node (terminal 34 in FIG. 3) in which the device noise of the inverter appears has decreased, so that the noise characteristic of this negative resistance circuit has deteriorated. I can understand.

From the above, it can be seen that the capacitance value of the capacitor C ₂ may be made larger than the capacitance value of the capacitor C ₁ in order to reduce the noise as much as possible with the same negative resistance value.

  Next, the physical structure of the LC oscillator 10 shown in FIG. 1 will be described.

FIG. 8 is a perspective view showing the physical structure of the LC oscillator shown in FIG. 1, and FIG. 9 is a side sectional view showing the structure of the LC oscillator shown in FIG. In these figures, the LC oscillator 10 shown in FIG. 1 is configured on a semiconductor chip. The LC oscillator 10 includes a primary-side inductor L _p , a secondary-side inductor L _m1 , and two pattern ground shields (hereinafter referred to as PGS (Pattern Ground Shield)) 42 and 44.

The primary inductor L _p is formed of a metal wiring spirally wound in an upper wiring layer. On the other hand, the secondary-side inductor L _m1 is configured by a metal wiring spirally wound in the lower wiring layer. In each of the inductors L _p and L _m1 , the portion where the metal wirings intersect is a through hole and the winding via the metal wiring in the upper or lower wiring layer in which the inductor is formed. The terminal is pulled out to the outside.

The PGS 44 is made of polysilicon (Poly) and has a sheet shape having a size corresponding to the sizes of the inductors L _p and L _m1 . The PSG 44 is disposed on a semiconductor chip substrate. On the other hand, the PGS 42 is made of metal and has the same size as the PGS 44. The PGS 42 is disposed between the primary side inductor L _p and the secondary side inductor L _m1 . The inductors L _p and L _m1 are separated from the PGS 42 and the inductors L _m1 and PGS 44 are separated by an insulating layer (insulator).

The primary side inductor L _p may be provided on the lower layer side, and the secondary side inductor L _m1 may be provided on the upper layer side. In some cases, the PGS 42 may not be arranged in cases where the parasitic capacitance of the inductors L _p and L _m1 is increased and the increase in dielectric loss due to the low resistance of the metal wiring forming the inductor is a problem. Therefore, it is desirable to provide the PGS 42 as necessary.

  The present invention is basically suitable for an on-chip LC oscillator, that is, an LC oscillator mounted on a semiconductor integrated circuit, but can also be applied to LC oscillators other than those mounted on a semiconductor integrated circuit. It is a thing.

  In the embodiment, a part of the primary-side negative resistance circuit is moved to the secondary-side LC oscillator to form a secondary-side negative resistance circuit. You may move to the LC oscillator side of the secondary side. In this case, a negative resistance circuit on the primary side is not necessary. Further, the specific circuit configuration of the negative resistance circuit is not limited to the illustrated example, and any circuit having the same function can be used.

The present invention is basically as described above.
The LC oscillator according to the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the spirit of the present invention. .

It is the schematic of one Embodiment showing the structure of LC oscillator of this invention. FIG. 2 is a circuit diagram illustrating a configuration of a negative resistance circuit on a primary side of the LC oscillator illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration of a negative resistance circuit on the secondary side of the LC oscillator illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration of a Spice model of the primary-side LC oscillator illustrated in FIG. 1. It is a circuit diagram showing the structure of the Spice model of LC oscillator shown in FIG. FIG. 6 is a circuit diagram illustrating a configuration in which the secondary LC oscillator is replaced with an equivalent circuit in the Spice model of the LC oscillator illustrated in FIG. 5. FIG. 7 is a circuit diagram showing a configuration in which an equivalent circuit of a secondary LC oscillator is replaced with an equivalent circuit of a primary LC oscillator in the Spice model of the LC oscillator shown in FIG. 6. It is a perspective view showing the physical structure of the LC oscillator shown in FIG. It is a sectional side view showing the structure of the LC oscillator shown in FIG. It is the schematic of an example showing the structure of the conventional LC oscillator.

Explanation of symbols

10, 50 LC oscillator 12 Primary side LC oscillator 14 Secondary side LC oscillator 20, 22, 32, 34 Terminal 16, 18 Negative resistance circuit 24, 26 N-type MOS transistor (NMOS)
28 Constant Current Source 30 Inverter 38 Noise Current Source 40 Noise Voltage Source 42, 44 Pattern Ground Shield (PGS)
L _p , L _m1 , L _S inductors C _p , C ₁ , C ₂ , C _ox1 , C _ox2 , C _sub1 , C _sub2 , C _e1 capacitors R _S , R _sub1 , R _sub2 , R _e1 registers

Claims (3)

An LC tank including a first inductor and a capacitor connected in parallel, a primary LC oscillator including a first negative resistance circuit, and the first inductor by a mutual induction action that generates a mutual inductance. An oscillation comprising: a secondary LC oscillator including a coupled second inductor and a second negative resistance circuit, wherein only the primary LC oscillator is connected to both ends of the first inductor, respectively. An LC oscillator comprising two output terminals for outputting a signal, wherein the secondary LC oscillator does not have an output terminal for outputting an oscillation signal . The negative resistance circuit of the primary side LC oscillator outputs a symmetric signal between the output terminals connected to both ends of the first inductor, and the negative resistance circuit of the secondary side LC oscillator The LC oscillator according to claim 1, wherein an asymmetric signal is output between terminals connected to both ends of the second inductor. The negative resistance circuit of the secondary LC oscillator is connected between an inverter, a first capacitor connected between the input terminal of the inverter and the ground, and an output terminal of the inverter and the ground. A second capacitor,
The LC oscillator according to claim 1 or 2, wherein a capacitance value of the second capacitor is larger than a capacitance value of the first capacitor.

Images