WO2012055319A1

WO2012055319A1 - Method and device for dispatching tcam (telecommunication access method) query and refreshing messages

Info

Publication number: WO2012055319A1
Application number: PCT/CN2011/080616
Authority: WO
Inventors: 伍益荣; 李维民; 朱寅
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-10-29
Filing date: 2011-10-10
Publication date: 2012-05-03
Also published as: CN101986271B; CN101986271A

Abstract

A method and a device for dispatching TCAM (telecommunication access method) query and refreshing messages are provided. The method comprises that a FPGA (field-programmable gate array) places a query message into a query message queue after receiving the query message; the FPGA places a refreshing message into a refreshing message queue after receiving the refreshing message; and the FPGA respectively dispatches the query message in the query message queue and the refreshing message in the refreshing message queue. The problem of slow query response due to that the refresh priority is higher than the query priority can be solved by using the solution of the invention, the high-speed table search retransmission and the table item refreshing can be provided, the fast forwarding can be realized, the throughput capacity of a network device can be upgraded and the performances of the network device can be further improved.

Description

TECHNICAL FIELD The present invention relates to the field of network communication technologies, and in particular, to a method and apparatus for scheduling a TCAM (Ternary Content Addressable Memory) query and refresh message. Background technique

The TCAM is used to quickly search for ACLs (Access Control Lists) and routes. The TCAM lookup and refresh technology based on FPGA (Field Programmable Gate Array) provides table item update and query scheduling, in which the FPGA plays a relay role between the processor or the CPU and the TCAM. On interconnected devices such as routers and switches, TCAM applications are becoming more common in order to achieve fast table lookup forwarding. With the rapid development of broadband networks, the application of multi-core processors is becoming more and more extensive. Multiple processor cores can be combined to provide high processing power. In order to make full use of the resources of each single-core processor, it will be reported when forwarding. The processing of the text is distributed to each processor unit. Each processor unit needs to search for the ACL, routing, and other entries of the packet. At the same time, the CPU needs to perform the entry of the entry in the TCAM and the contents of the entry in the processor peripheral. Refresh operation, multiple processors need to access a single TCAM peripheral together, how to enable multiple processors to implement TCAM fast table lookup forwarding and table entry refresh, and balance the performance of each processor, this is FPGA-based TCAM Query and refresh the device to solve the problem. FIG. 1 is a structural block diagram of a related art FPGA-based TCAM query and refresh system, which includes a processor, a CPU interface, an FPGA, a TCAM unit, and an SSRAM (Serial Static Random Access Memory), and the SSRAM is used to store a routing table. The FPGA of the technology puts the TCAM query and the refresh request of the CPU for the table in the same queue, and schedules the request in the queue based on the priority of the query and the refresh, wherein the CPU has higher priority for refreshing the entry than the processing. The priority of the TCAM query. This method of prioritized scheduling makes the query and refresh coordination more compact. When there are a large number of entries, the response speed of the query will be very low, which will easily block the packets on the network and affect the throughput of the network device. . SUMMARY OF THE INVENTION The present invention provides a method and apparatus (including an FPGA device and a network device) for scheduling a TCAM query and refresh message to at least solve the above problem of slow query response caused by a refresh priority higher than a query priority. According to an aspect of the present invention, a method for scheduling a TCAM query and refresh message is provided, including: after receiving an inquiry message, the FPGA puts the query message into a query message queue; after receiving the refresh message, the FPGA refreshes the message. Put into the refresh message queue; the FPGA schedules the query message in the query message queue and the refresh message in the refresh message queue, respectively. Preferably, a plurality of query message queues are set on the FPGA, and the query message queues are in one-to-one correspondence with the processor;

The FPGA puts the query message into the query message queue, including: the FPGA puts the query message into the query message queue corresponding to the processor number carried in the query message; the FPGA schedules the query message in the query message queue to include: the FPGA adopts polling mode scheduling Multiple query message queues are used to queue the query messages in the scheduled query message queue. Preferably, the FPGA dequeues the query message in the scheduled query message queue, including:

The FPGA uses the first-in-first-out FIFO method to queue the query messages in the scheduled query message queue. Preferably, scheduling the refresh message in the refresh message queue by the FPGA comprises: the FPGA scheduling the refresh message in the refresh message queue by using a first-in-first-out FIFO. Preferably, after the FPGA queries the query message in the query message queue, the method further includes: receiving, by the FPGA, the query result of the query message, and returning the query result to the processor corresponding to the query message; the processor acquiring the routing information according to the query result, according to the route Information forwarding message. According to another aspect of the present invention, an FPGA device is provided, including: a query message enqueue module, configured to: after receiving a query message, put the query message into a query message queue; refresh the message enqueue module, set to receive After the message is refreshed, the refresh message is placed in the refresh message queue; the query scheduling module is configured to schedule the query message in the query message queue; and the refresh scheduling module is configured to schedule the refresh message in the refresh message queue. Preferably, the query message enqueue module includes: a queue determining unit, configured to: after receiving the query message, determine a corresponding query message queue according to the processor number carried in the query message; wherein, the FPGA device is configured with multiple query message queues, And the query message queue has a one-to-one correspondence with the processor; the enqueue unit is configured to put the query message into the query message queue determined by the queue determining unit; the query scheduling module includes: a polling scheduling unit, configured to use the polling mode to schedule multiple Query message queue; the dequeuing unit is set to perform queue processing on the query message in the query message queue scheduled by the polling scheduling unit. Preferably, the dequeuing unit comprises: a dequeue subunit, configured to perform a queue processing of the query message in the query message queue scheduled by the polling scheduling unit by using a first in first out FIFO. Preferably, the refresh scheduling module includes: a refresh scheduling unit configured to schedule a refresh message in the refresh message queue by using a first-in first-out FIFO. According to still another aspect of the present invention, a network device is provided, including the foregoing FPGA device, the network device further comprising: a processor, configured to send a query message to the FPGA device, and receive a query result returned by the FPGA device, according to the query result Obtaining routing information, and performing packet forwarding according to the routing information; the CPU is configured to send a refresh message to the FPGA device, where the refresh message carries indication information for performing a refresh operation on the scheduled tri-state content addressing memory TCAM. Through the invention, two branches are set on the FPGA, that is, the query processing branch and the refresh processing branch are used, and the two branches are separately processed without mutual interference, thereby solving the query response caused by the refresh priority being higher than the query priority. The slow problem can provide high-speed table lookup forwarding and table item refreshing, achieve fast forwarding, improve the throughput of network devices, and improve the performance of network devices. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, In the drawings: FIG. 1 is a structural block diagram of an FPGA-based TCAM query and refresh system according to the related art; FIG. 2 is a flow chart of a method for scheduling a TCAM query and refresh message according to Embodiment 1 of the present invention; FIG. 4 is a structural block diagram of a network device according to Embodiment 2 of the present invention; FIG. 5 is a flowchart of a method for querying message enqueue and dequeue scheduling according to Embodiment 2 of the present invention; FIG. 6 is a schematic diagram of a query message enqueue and dequeue schedule according to Embodiment 2 of the present invention; FIG. 7 is a flowchart of a method for querying a TCAM query entry according to Embodiment 2 of the present invention; FIG. 8 is a flowchart according to Embodiment 2 of the present invention; FIG. 9 is a block diagram showing the structure of an FPGA device according to Embodiment 3 of the present invention; FIG. 10 is a block diagram showing the structure of a network device according to Embodiment 4 of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. Embodiment 1 FIG. 2 is a flowchart of a method for scheduling a TCAM query and refresh message according to an embodiment of the present invention. The method includes the following steps: Step S202: After receiving a query message, the field programmable gate array FPGA queries The message is placed in the query message queue. Step S204, after receiving the refresh message, the FPGA puts the refresh message into the refresh message queue. Step S206: The FPGA separately schedules the query message in the query message queue and the refresh message in the refresh message queue. . The above FPGA stores the TCAM query and refresh messages in separate ways, which enables parallel scheduling query and refresh. In order to achieve equalization processing for each processor TCAM query for a multi-core processor, preferably, the plurality of query message queues are set on the FPGA, and the query message queue is in one-to-one correspondence with the processor; correspondingly, step S202 includes: The query message is placed in the query message queue corresponding to the processor number carried in the query message; the FPGA in step S206 schedules the query message in the query message queue to include: the FPGA uses a polling manner to schedule multiple query message queues, and the The query message in the scheduled query message queue is queued. The so-called polling scheduling means that each query message queue is sequentially scheduled in a certain order, and the number of times each query message queue is scheduled is substantially the same in a period of time. Preferably, the FPGA performs dequeue processing on the query message in the scheduled query message queue, including: the FPGA uses a first in first out (FIFO) manner to dequeue the query message in the scheduled query message queue. deal with. The FPGA schedules the refresh message in the refresh message queue to include: The FPGA uses the first-in-first-out FIFO to schedule the refresh message in the refresh message queue. After the FPGA queries the query message in the query message queue, the method may further include: the FPGA receiving the query result of the query message, and returning the query result to the processor corresponding to the query message; the processor acquiring the routing information according to the query result, according to the routing information Forward the message. In practical applications, when the user configuration changes or the link status changes in the network, the TCAM entry will be refreshed, and the frequency of these changes is low, which makes the prioritized scheduling redundant, so this implementation The example does not set the priority for the refresh schedule and the query schedule, but stores the two in different queues separately, and schedules the stored queues separately. FIG. 3 is a structural diagram of a cache queue according to an embodiment of the present invention. The cache queue includes a plurality of query message queues and a refresh message queue, wherein sl-s5 represents a query message, and ul-u4 represents a refresh message, which is specifically described as follows: The query message queue is multiple, corresponding to each processor setting, and one query message queue is used to cache the query message sent by the same processor. The query message in the embodiment of the present invention may include: a processor number, a type of the queryed item. , the size of the query content and the content of the query. The processor number is used to determine the queue number into which the query message is entered, and the processor returned by the query result; the entry type indicates whether the entry is an ACL or a route, or other entries; Indicates how many bits of the query, such as 144/256; the query content is the condition for input search, for example, the content of the route input is the destination IP, and the content of the ACL search input is the IP quintuple of the message, and the IP quintuple includes Source IP address, destination IP address, source port number, destination port number, and protocol type. When the query message is placed in the corresponding query message queue, a message number may be set for the query message to identify the sequence in which the query message enters in the query message queue. The message queue is refreshed. Multiple processors share a FIFO buffer queue. Only one cache queue is set. Because the CPU refreshes the TCAM entries in the actual application, the frequency is usually refreshed when the user configuration changes. The data structure of the refresh message includes refreshing the message number, refreshing the type of the entry, and refreshing the content. The length of the cache queue is the integer power of 2, and the location of the message in the cache queue can be found directly by using the query message number or the lower address of the refresh message number. For example, the length of the cache queue is 32, which is the 5th power of 2, and the message number is taken. The binary number is 5 bits lower as its position in the buffer queue. For example, the message number is 57, its binary number is 111001, the lower 5 bits are 11001, and the decimal is 25, then the message enters the position of the buffer queue 25. The above method can be applied to a multi-core processor or a plurality of processors using FPGA to perform TCAM query and refresh processing. Since two branches are set on the FPGA, that is, the query processing branch and the refresh processing branch, the two branches are separately processed. Do not interfere with each other, and solve the problem caused by the refresh priority being higher than the query priority. The problem of slow response is able to provide high-speed table lookup forwarding and table item refreshing, which enables fast forwarding, improves the throughput of network devices, and improves the performance of network devices. Embodiment 2 This embodiment provides a method for scheduling a TCAM query and a refresh message. The method is described as an example on the network device shown in FIG. 4. The network device shown in FIG. 4 includes the following functional units:

1) The processor unit is connected to the FPGA through the query channel, and includes a plurality of processors therein, respectively represented by the processor 1, the processor 2, the processor n, and the plurality of single-core processors or Multiple processors can simultaneously issue TCAM query requests for different entries. The query channel is responsible for transmitting the query request sent from each processor and the query result returned from the FPGA, and the processor accesses the entry stored in the processor peripheral according to the result of the query, and obtains information required for packet forwarding, Implement packet forwarding.

2) The CPU is connected to the FPGA through the refresh channel, and also adds, deletes, and updates the entries in the TCAM through the FPGA, and simultaneously modifies the entries in the processor peripheral.

3) processor peripherals, including SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and DDR (Double Data Rate) The result of the processor querying the TCAM is a pointer or index to the address of a particular entry stored in the peripheral, from which the corresponding entry information is read from the peripheral. When the CPU updates the TCAM entry, it also modifies the corresponding entry stored in the peripheral.

4) The FPGA, including the query processing unit and the refresh processing unit, respectively respond to the query and refresh request issued by the processor and the CPU, and the query processing and the refresh processing operate independently. When the CPU refreshes the TCAM entry, the processor can still perform TCAM query. The query processing unit sets a plurality of FIFO query cache queues according to the number of single core processors (corresponding to the query message queue in Embodiment 1), each processor corresponds to one FIFO queue, and polling scheduling is used between the queues. the rules. The query processing unit distributes the query message to the corresponding query queue according to the processor number. The function of the refresh processing unit is to quickly respond to the CPU update command and update the entries in the TCAM.

5) TCAM unit, configured to respond to a refresh message sent by the CPU through the FPGA, update the entry of the entry; and respond to the query message sent by the processor through the FPGA, and return the query result. Based on the network device shown in FIG. 4, this embodiment provides a method for querying message enqueue and dequeue scheduling. The query processing unit of the FPGA in this embodiment maintains a queue state vector, and the queue state vector is a binary. The value of the system, the corresponding position 1 indicates that the queue has messages, for example: the total number of queues is 8, the queue status vector 00001001 indicates that there are messages in queue 1 and queue 4 that need to be dequeued, and there are no messages in the other six queues that need to be dequeued, see 5, the method includes the following steps: Step S502, querying a message into a team, specifically: after receiving the query message, the query processing unit separately enqueues according to the processor number of the query message, and numbers the query message according to the queue of the enqueue The corresponding position of the queue state vector is 1, indicating that the queue has a message to be dequeued; in step S504, the query processing unit cyclically schedules each queue by polling, and schedules one query message in one queue per round; Step 1: Initialize the scheduling queue number to n=l, and start scheduling from the first queue. Step 2: If n is greater than the total number of queues, set n=l, that is, after the last queue performs scheduling, and then from the first queue. Start the round-robin scheduling; otherwise, the current round of the scheduling queue is n; Step 3, determine whether the corresponding bit of the queue status vector is set to 1, if 1. If the queue has a query message that needs to be dequeued, go to step 4. Otherwise, it means that the queue does not have a query message to be scheduled, and the next queue is scheduled to be executed, that is, step 5 is performed; Step 4, the internal scheduling of the queue, according to the query The message number is dequeued in sequence. If all the query messages of the queue are scheduled, the bits in the queue vector corresponding to the queue are cleared to 0. Step 5, n=n+l, execute the scheduling of the next queue, and skip to step 3. Referring to the schematic diagram of the query message enqueue and dequeue scheduling shown in FIG. 6, the FPGA puts the query message into the corresponding queue according to the processor number of the query message, and uses the polling manner to dequeue the query messages of each queue. Based on the network device shown in FIG. 4, FIG. 7 shows a flowchart of a method for querying a TCAM entry according to this embodiment, the method comprising the following steps: Step S702, processor 1, processor 2, ... The processor n issues a query message according to the need, the query message includes the processor number, the type of the queryed item, the size of the query content, and the query content, and the query message is transmitted to the FPGA through the query channel; Step S704, the FPGA identifies The query message is sent, and the query message is entered into the queue by the processor number; The query processing unit of the FPGA maintains multiple query message queues, each processor corresponds to one queue, and the query message is queued according to the processor number, and multiple query message queues are scheduled according to the polling manner, and each queue is internally FIFO-based. The principle is scheduled, the TCAM query is performed, and the query result is returned to the requesting processor. Step S706, the query processing unit dequeues the query message, enters the TCAM query, and returns the result of the query to the corresponding processor according to the processor number. Step S708, the processor according to the result of the TCAM query, that is, the entry information in the processor The address in the peripheral device reads the specific content of the entry. In step S710, the processor forwards the packet according to the content of the query entry. Based on the network device shown in FIG. 4, FIG. 8 is a flowchart of a method for a CPU to refresh an entry according to the embodiment. The method includes the following steps: Step S802, the CPU issues an entry refresh message, and refreshes the message. Including the type of the entry and the refreshed content, the refresh message is transmitted to the FPGA through the refresh channel; Step S804, the FPGA recognizes the refresh message, and the refresh message is queued; Step S806, the refresh message is scheduled to be dequeued according to the principle of first in first out; Step S808, the TCAM receives the refresh message to update the entry of the entry, including the adding, deleting, and modifying operations. Step S810, the CPU updates the entry in the processor peripheral entry, including the adding, deleting, and modifying operations. The processor in the above method uses the FPGA relay to perform the query access of the TCAM, and the FPGA returns a pointer or an index pointing to the address of the table entry in the peripheral, and the processor reads the entry in the processor peripheral according to the returned result; The CPU uses the FPGA relay to perform the TCAM refresh operation (ie, the update operation of the TCAM entry), and simultaneously updates the corresponding entry information in the processor peripheral. The scheduling method provided in this embodiment supports the parallel processing of the query and the refresh operation, and the entry of the entry can be performed at the same time as the query, and the entry of the entry can be queried at the same time. At the same time, the above method adopts a query message queue corresponding to the number of processors on the FPGA, which can solve the related technology that only supports single processor query, parallel query of multiple processors or multiple threads, and query of multiple entries. If the processing power is insufficient, if multiple single-core processors query multiple entries in parallel, the efficiency of the search will be higher; and because of the polling scheduling mode, the performance of each single-core processor is relatively balanced. Embodiment 3 FIG. 9 is a structural block diagram of an FPGA device according to an embodiment of the present invention. The device includes: a query message enqueue module 92, configured to place a query message into a query message queue after receiving a query message; The refresh message enqueue module 94 is configured to: after receiving the refresh message, put the refresh message into the refresh message queue; the query scheduling module 96 is connected to the query message enqueue module 92, and is configured to schedule the query message in the query message queue. The refresh scheduling module 98 is coupled to the refresh message enqueue module 94 and configured to schedule refresh messages in the refresh message queue. The query message enqueue module 92 includes: a queue determining unit, configured to: after receiving the query message, determine a corresponding query message queue according to the processor number carried in the query message; wherein the FPGA device is configured with multiple query message queues, and the query The message queue is in one-to-one correspondence with the processor; the enqueue unit is configured to put the query message into the query message queue determined by the queue determining unit; the query scheduling module 96 includes: a polling scheduling unit, configured to schedule multiple by using a polling manner Query message queue; the dequeuing unit is set to perform queue processing on the query message in the query message queue scheduled by the polling scheduling unit. Preferably, the dequeuing unit comprises: a dequeue subunit, configured to perform a queue out processing on the query message in the query message queue scheduled by the polling scheduling unit by using a first in first out FIFO. The refresh scheduling module 98 includes: a refresh scheduling unit configured to schedule a refresh message in the refresh message queue by using a first in first out FIFO. The query message includes: a processor number, a type of the queryed item, a size of the query content, and a query content. The processor number is used to determine the queue number to which the query message is entered, and the processor to which the query result is returned; the entry type identifier is the query of the entry, whether it is an ACL or a route, or other entries; How many queries, such as 144/256; The query content is the condition for input search. For example, the content of the route input is the destination IP, and the content of the ACL search input is the IP quintuple of the packet. The IP quintuple includes the source IP. Address, destination IP address, source port number, destination port number, and protocol type. When the query message is placed in the corresponding query message queue, a message number may be set for the query message to identify the sequence in which the query message enters in the query message queue. The multiple processors in this embodiment share a FIFO buffer queue. In this embodiment, only one refresh message queue is set because the CPU performs a refresh operation on the TCAM entry in a practical application, which is generally caused by a user configuration change. Refresh the entry. The data structure of the refresh message includes refreshing the message number, refreshing the type of the entry, and refreshing the content. The above FPGA device can be applied to a multi-core processor or a plurality of processors for performing TCAM query and refresh processing in an FPGA relay. Since two branches are set on the FPGA device, that is, a query processing branch and a refresh processing branch, the two branches are separately processed. It does not interfere with each other, and solves the problem that the query response is slow due to the refresh priority being higher than the query priority. It can provide high-speed table lookup forwarding and table item refreshing, realize fast forwarding, and improve the throughput capability of network devices. Improve the performance of network devices. Embodiment 4 FIG. 10 is a block diagram showing the structure of a network device including an FPGA device 102, a processor 104, and a CPU 106. The FPGA device 102 is connected to the processor 104 and the CPU 106, respectively, according to an embodiment of the present invention. The FPGA device 102 can be implemented in the manner of Embodiment 3, and will not be described in detail herein. The processor 104 is configured to send a query message to the FPGA device 102, and receive a query result returned by the FPGA device, obtain routing information according to the query result, and perform message forwarding according to the routing information;

The CPU 106 is configured to send a refresh message to the FPGA device 102, where the refresh message carries indication information for performing a refresh operation on the scheduling TCAM. The network device in this embodiment can also be implemented according to the network device shown in FIG. 4 in Embodiment 2. The specific functions are the same as those in the present embodiment, and details are not described herein again. The network device in this embodiment sets two branches on the FPGA device, that is, the query processing branch and the refresh processing branch, and separately processes the two branches without mutual interference, thereby solving the problem that the refresh priority is higher than the query priority. The slow response of the query can provide high-speed table lookup forwarding and table item refreshing, enabling fast forwarding, improving the throughput of network devices, and improving the performance of network devices. Compared with the prior art, the technology provided by the foregoing embodiment, by separately processing the query and the refresh, makes the processing of the query and the refresh do not interfere with each other, and improves the efficiency of the query and the refresh; separately separates the query messages of different processors into The team implements parallel query, query queue polling scheduling of each single core processor, and balances the performance of each single core processor. It can quickly respond to the processor's query to TCAM and refresh the entries, achieve fast forwarding, improve the throughput of network devices, and improve the performance of network devices. Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. The steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claim

A method for scheduling a three-state content addressing memory TCAM query and refresh message, comprising:

After receiving the query message, the field programmable gate array FPGA puts the query message into the query message queue;

After receiving the refresh message, the FPGA puts the refresh message into the refresh message queue; the FPGA separately schedules the query message in the query message queue and the refresh message in the refresh message queue.

2. The method according to claim 1, wherein the FPGA is provided with a plurality of query message queues, and the query message queues are in one-to-one correspondence with the processor;

The loading, by the FPGA, the query message into the query message queue includes: the FPGA placing the query message into a query message queue corresponding to a processor number carried by the query message;

The scheduling of the query message in the query message queue by the FPGA includes: the FPGA scheduling the multiple query message queues in a polling manner, and performing queue processing on the query messages in the scheduled query message queue.

3. The method according to claim 2, wherein the out-of-queue processing of the query message in the scheduled query message queue by the FPGA comprises:

The FPGA performs queued processing on the query message in the scheduled query message queue by using a first-in-first-out FIFO.

4. The method according to claim 1, wherein the scheduling of the refresh message in the refresh message queue by the FPGA comprises:

The FPGA schedules the refresh message in the refresh message queue by using a first-in-first-out FIFO.

The method according to any one of claims 1-4, wherein, after the FPGA schedules the query message in the query message queue, the method further includes:

Receiving, by the FPGA, a query result of the query message, and returning the query result to a processor corresponding to the query message;

The processor obtains routing information according to the query result, and forwards the packet according to the routing information. A field programmable gate array FPGA device, comprising:

Querying the message enqueue module, and setting the query message to the query message queue after receiving the query message;

Refreshing the message enqueue module, and setting the refresh message to the refresh message queue after receiving the refresh message;

The query scheduling module is configured to schedule the query message in the query message queue; and the refresh scheduling module is configured to schedule the refresh message in the refresh message queue. The apparatus according to claim 6, wherein

The query message enqueue module includes: a queue determining unit, configured to: after receiving the query message, determine a corresponding query message queue according to a processor number carried in the query message; wherein, the FPGA device is configured Query message queues, and the query message queues are in one-to-one correspondence with the processor; the enqueue unit is configured to put the query message into the query message queue determined by the queue determining unit;

The query scheduling module includes: a polling scheduling unit configured to schedule the plurality of query message queues by using a polling manner; and a dequeuing unit configured to query the query message queues scheduled by the polling scheduling unit The message is queued. The apparatus according to claim 7, wherein the dequeuing unit comprises:

The dequeue sub-unit is configured to perform a queue-out processing on the query message in the query message queue scheduled by the polling scheduling unit by using a first-in-first-out FIFO. The device according to claim 6, wherein the refresh scheduling module comprises:

The refresh scheduling unit is configured to schedule the refresh message in the refresh message queue by using a first in first out FIFO. A network device, comprising the field programmable gate array FPGA device of any one of claims 6-9, the network device further comprising:

a processor, configured to send a query message to the FPGA device, and receive a query result returned by the FPGA device, obtain routing information according to the query result, and forward the message according to the routing information;

The CPU is configured to send a refresh message to the FPGA device, the refresh message carrying indication information for performing a refresh operation on the tempered tri-state content addressed memory TCAM.