JP2016139978A - Packet processing system, communication system, packet processor, packet processing method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the processing for outputting the packets subjected to parallel processing while establishing a sequence, efficiently, in a system performing the processing for the packets in parallelization.SOLUTION: A packet processing system for processing packets in parallel includes numbering means numbering the inputted packets for indicating the order thereof, processing means for executing parallel processing of the packets numbered by the numbering means, and control means for outputting the packets processed by the processing means in the order of the number given by the numbering means. The control means includes a buffer for temporarily storing the packets, that are made to standby the output order, out of the packets outputted from the processing means.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a technique for processing sequentially input packets in parallel and sequentially outputting the processed packets.

  Currently, a VPN (Virtual Private Network) that realizes a virtual private network on the Internet has become widespread. A communication device that implements VPN communication executes processing such as packet encryption and encapsulation, but in order to increase the speed of VPN communication, the processing performance such as encryption / decryption in the communication device should be improved. is necessary.

  As an effective approach for improving the processing performance, there is a technique for parallelizing processes such as encryption / decryption using, for example, a plurality of CPUs. In addition, there exists patent document 1 as a prior art document relevant to this application.

Patent 4648290

  However, in a communication program such as VPN software that operates on the communication device, if processing for handling packets is simply performed in parallel, the order of outgoing packets is reversed, which affects user communication.

  Therefore, it is conceivable to temporarily store the packets after parallel processing in a buffer and send them out of order (reordered), but it is as simple as sorting and sending all packets. In this method, buffer processing becomes a bottleneck, and the performance improvement rate of parallel processing is reduced.

  The present invention has been made in view of the above points, and in a system in which processing for packets is performed in parallel, processing for arranging and outputting packets after parallel processing can be efficiently performed. The purpose is to provide technology.

According to an embodiment of the present invention, a packet processing system for processing packets in parallel,
Numbering means for assigning a number indicating the order of the packets to the input packet;
Processing means for executing parallel processing on the packets numbered by the number assigning means;
Control means for outputting packets processed by the processing means in the order of the numbers given by the number giving means,
The control means includes a buffer for temporarily storing a packet that waits for an output order among the packets output from the processing means. A packet processing system is provided.

Moreover, according to the embodiment of the present invention, a communication system for transmitting packets in parallel through a plurality of paths on a network,
A first packet transfer device that assigns a number indicating a packet order to a packet received from upstream, and sends the numbered packet to a plurality of paths;
A second packet transfer device that receives the packets from the plurality of paths and sends the packets downstream in the order of the numbers assigned by the first packet transfer device;
The second packet transfer apparatus includes a buffer for temporarily storing a packet that waits for a downstream transmission order among packets received from the plurality of paths. Is done.

Moreover, according to the embodiment of the present invention, a packet processing method executed by a packet processing system that processes packets in parallel,
A numbering step for assigning a number indicating the order of the packets to the input packet;
A processing step of performing parallel processing on the packets numbered by the numbering step;
A control step for outputting the packets after the processing by the processing step in the order of the numbers given in the numbering step;
In the control step, a packet processing method is provided in which, among the processed packets, packets that wait for the output order are temporarily stored in a buffer.

Moreover, according to the embodiment of the present invention, a packet processing device that processes packets in parallel,
Numbering means for assigning a number indicating the order of the packets to the input packet;
Processing means for executing parallel processing on the packets numbered by the number assigning means;
Control means for outputting packets processed by the processing means in the order of the numbers given by the number giving means,
The control unit includes a buffer for temporarily storing a packet that waits for an output order among the packets output from the processing unit. A packet processing device is provided.

Further, according to the embodiment of the present invention, the number assigning unit that assigns a number indicating the order of the packets to the input packet, and the parallel processing is executed on the packet that is given the number by the number assigning unit. A packet processing apparatus that inputs a packet output from a processing system having processing means and executes processing of the packet,
A control means for outputting packets processed by the processing means in the order of the numbers given by the number giving means;
The control unit includes a buffer for temporarily storing a packet that waits for an output order among the packets output from the processing unit. A packet processing device is provided.

  According to the embodiment of the present invention, in a system that performs processing on packets in parallel, a technique is provided that enables efficient processing of arranging and outputting packets after parallel processing. .

It is a block diagram of the packet processing system which concerns on embodiment of this invention. It is a figure which shows the other structural example of a packet processing system. It is a figure for demonstrating the example of a buffer. It is a flowchart which shows operation | movement of a buffer control part. It is a figure for demonstrating the example of buffer transmission when the arrival waiting packet comes. It is a figure for demonstrating the example of buffer storage. It is a figure for demonstrating the example of packet discard. It is a figure for demonstrating the example of a timeout process.

  Embodiments of the present invention will be described below with reference to the drawings. The embodiment described below is only an example, and the embodiment to which the present invention is applied is not limited to the following embodiment.

  The “packet” described below means a group of data, and is not limited to a specific type of packet such as an IP packet or an Ethernet packet. “Packet” may be rephrased as “data”.

(System configuration)
FIG. 1 shows a configuration diagram of a packet processing system 100 according to an embodiment of the present invention. In the present embodiment, it is assumed that the packet processing system 100 is a communication device for realizing VPN communication, but this is only an example. The present invention is not limited to such a communication apparatus, and can be applied to a technique for performing various packet (data) processing.

  The packet processing system 100 according to the present embodiment includes a function of transmitting / receiving packets to / from the network (IF function), a function of performing encapsulation / decapsulation, and the like in order to realize VPN communication. Since such a function is a general function for VPN communication, such a general function is not shown in FIG. 1, and only a function particularly relevant to the present invention is shown.

  As shown in FIG. 1, the packet processing system 100 includes a number assigning unit 101, a queue 102, a packet processing unit 103, a queue 104, and a buffer control unit 105. The number assigning unit 101 assigns numbers to the packets received from the outside (for example, the user terminal side network) in the order received. The queue 102 is a FIFO memory that temporarily stores packets. The packets numbered by the number assigning unit 101 are sequentially stored in the queue 102, and sequentially read from the packet processing unit 103 in the order in which they are stored (may be expressed as pruning).

  There are a plurality of packet processing units 103, which execute processing on packets in parallel. The processing for the packet is, for example, encryption or decryption of the packet.

  The queue 104 is also a FIFO memory that temporarily stores packets. Each packet processing unit 103 sequentially stores the processed packets in the queue 104. Packets stored in the queue 104 are sequentially read from the buffer control unit 105 in the order of storage.

  The buffer control unit 105 includes a buffer (memory) having a predetermined length for storing a packet read from the queue 104, and reads and transmits the packet from the buffer according to a predetermined processing procedure, thereby maintaining the packet order. This is a functional unit that enables high-speed transmission processing. The processing operation of the buffer control unit 105 will be described in detail later.

  The packet processing system 100 can be realized by executing a program corresponding to each functional unit in a computer having one CPU, or can be realized by physically using a plurality of computers. When implemented by a plurality of computers, for example, the number assigning unit 101 and the queue 102 are configured by one computer, each packet processing unit 103 is configured by one computer, and the queue 104 and the buffer control unit 105 are configured by one computer. Can be realized.

  Further, the packet processing system 100 is configured as a single device equipped with a plurality of CPUs. For example, one CPU is assigned to each of the number assigning unit 101, each packet processing unit 103, and the buffer control unit 105, and The packet processing system 100 can also be realized by executing a program corresponding to the processing content in the CPU.

  The buffer control technique according to the present embodiment can also be applied to a network system as shown in FIG.

  The system shown in FIG. 2 has a configuration in which, for example, a packet transfer device 201 and a packet transfer device 202 are provided as edge devices of a network 200 that performs relay. For convenience, consider packet transfer in the direction from the packet transfer apparatus 201 to the packet transfer apparatus 202. The packet transfer apparatus 201 corresponds to the number assigning unit 101 of the packet processing system shown in FIG. 1, receives packets transmitted from the upstream (transmission side), assigns numbers to the packets in the order received, The assigned packet is transmitted to the network 200 through a plurality of routes. For example, packet 1 is transmitted via path 1 and packet 2 is transmitted via path 2, so that packet transfer is speeded up by transmitting in parallel.

  The packet transfer apparatus 202 includes functions corresponding to the queue 104 and the buffer control unit 105 of the packet processing system shown in FIG. 1, stores packets received from the network 200 in the queue in the order received, and is similar to the buffer control unit 105. And the packet is sent downstream (reception side) in the order of the packet number (= the order received from the upstream). Such processing enables high-speed transmission by parallel transmission while maintaining the packet order.

  The packet transfer apparatus 202 can be realized by causing a computer (communication apparatus) including a CPU to execute a program corresponding to the processing contents of the queue 104 and the buffer control unit 105. The packet transfer apparatus 202 may further include the function of the number assigning unit 101 as a function on the packet transmission side. Hereinafter, the contents of the process performed by the packet control unit 105 will be described in more detail.

(Details of processing of packet control unit 105)
FIG. 3 shows an example of a buffer provided in the packet control unit 105. The buffer is a memory area having a predetermined length as the number of buffer elements. In the present embodiment, packets are numbered in order of packet arrival, but an upper limit is set in advance for the number, and the upper limit is referred to as a numbering maximum value. The first number (1 in this embodiment) is assigned to the packet next to the packet with the maximum numbering value.

  In the program that executes the processing of the packet control unit 105, the data structure of the buffer is represented as an array, and the number of buffer elements is the number of array elements. In addition, the packet is stored in an array position with a remainder obtained by dividing the packet number by the number of array elements as an index. In this way, by performing the storing process using the remainder when the number is divided by the number of elements in the array as an index, the number of elements in the array to be prepared can be limited, and the memory to be secured can be reduced.

  In this embodiment, a Wait pointer and a Max pointer are used as an array index in the buffering process. The Wait pointer is a remainder obtained by dividing the current waiting packet number by the number of array elements. The Max pointer is a remainder obtained by dividing the maximum number of packets stored in the buffer by the number of array elements.

  In the example shown in FIG. 3, the number of buffer elements is set to 10, and the maximum numbering value is set to 100. Also, the buffer at the time shown in FIG. 3 is waiting for the arrival of the 65th packet, and the 68th, 69th, 70th, 72th and 73rd packets are already stored in the buffer. Since 73 is the maximum at this time, the remainder 3 of 73 ÷ 10 becomes the Max pointer (denoted as “M”). Since the 65th packet is awaited, the remainder 5 of 65 ÷ 10 becomes the Wait pointer (indicated as “W”).

(Buffering processing contents)
FIG. 4 is a flowchart illustrating a procedure related to buffering processing executed by the buffer control unit 105. In FIG. 4, symbols such as S <b> 1 and S <b> 2 are reference symbols for referring to each process. Wait is the number of a packet that is currently waiting for arrival (specifically, waiting for being stored in the queue 104) (not a wait pointer but an actual number). max is the maximum number of packets stored in the buffer (actual number, not Max pointer). num is the number of the packet read (cut) from the queue 104. “time” is the time when the latest buffer transmission processing is performed, and “now” is the current time. LEN is the number of array elements (for example, 10). NUM_MAX is a numbering maximum value (example: 100).

  In the following, the processing executed by the buffer control unit 105 is divided into buffer transmission processing, buffer storage processing, packet discard processing, and timeout processing, and each will be described using a specific example and a flowchart.

<Packet transmission processing when an incoming packet arrives>
First, processing when a packet is read from the buffer and transmitted will be described with reference to FIG. FIG. 5A shows Example 1 of packet transmission when an arrival waiting packet arrives.

  In Example 1, the arrival of the 65th packet is awaited immediately before the arrival of the packet, and the 68th, 69th, 70th, 72th, and 73rd packets are already stored in the buffer. In this state, when the 65th packet comes (when the packet is cut from the queue 104), the packet is transmitted. Since the 66th packet, which is the next to the 65th, has not arrived, the 66th packet is waited for arrival. Therefore, the W pointer is shifted by one.

  FIG. 5B shows a second example of packet transmission when an arrival waiting packet arrives. In Example 2, the arrival of the 65th packet is awaited immediately before the arrival of the packet, and the 66th, 68th, 69th, 70th, 72th, and 73rd packets are already stored in the buffer. In this state, when the 65th packet arrives, the packet and the stored packet (66th) continuous with the packet are transmitted, and the W pointer is shifted by the number of packets to be transmitted.

  Examples 1 and 2 of the packet transmission described above are examples of the buffer transmission process of S21 in the flowchart of FIG. That is, the packet is pruned from the queue 104 at S9 in FIG. 4, and wait (eg: 65 waiting for arrival) is compared with num (eg: 65 arrived) at S10. As a result, wait is equal to num. The process is executed, and the time is updated to the current time (time when the packet was transmitted) in S22. As illustrated in Example 2 above, in the packet transmission process, all of a series of packets that are continuous with the arrival packet among the packets that have already arrived are transmitted together with the arrival packet.

<Buffer storage processing>
Next, the buffer storage process will be described with reference to FIG. FIG. 6A shows Example 1 of the buffer storage process.

  In Example 1, when the 65th packet is waiting to arrive and the 68th, 69th, 70th, 72th, and 73rd packets are already stored in the buffer, the 66th packet larger than the 65th packet When is received, the packet is stored in a buffer (array). There is no change in the M pointer and W pointer.

  FIG. 6B shows a second example of buffer storage processing. In Example 2, when the 65th packet is waiting to arrive and the 66th, 67th, 68th, 69th, 70th, 72th, and 73th packets are already stored in the buffer, the 77th packet Suppose that In this case, since an arrival waiting packet with a number smaller than 77 has not arrived, the 77th packet is stored in the array.

  However, in order to store the 77th packet in the array element number smaller than the maximum numbering value, packets of (77-10 (number of array elements)) or less are transmitted. However, since No. 65 is not stored, No. 65 is treated as being discarded, and Nos. 66 and 67 are transmitted. Further, the 68th, 69th and 70th consecutive numbers are sent, and the W pointer is shifted to 71. Since No. 77 is the largest in the waiting packets, the M pointer is also shifted to 77.

  Examples 1 and 2 of the packet storage described above are examples of the buffer addition process of S23 and the buffer transmission processes of S25 and S26 in the flowchart of FIG.

  That is, if the result of determination in S9 of FIG. 4 is wait <num <wait + LEN (example: 65 <66 <65 + 10), the packet of num (example: 66) is added to the buffer in S23, and max is determined in S24. Update. That is, when the packet control unit 105 obtains from the queue 104 a packet that should be output after the arrival waiting packet within a predetermined number of packets, the packet control unit 105 stores the packet in the buffer.

  Further, when wait + LEN <= num <wait + LEN × 2 (example: 65 + 10 <= 77 <65 + 10 × 2), packets up to num-LEN (example: 77-10) in S25 and S26 (example: No. 66, No. 67 packet) and subsequent packets (eg, No. 68, No. 69, No. 70 packet) are transmitted, time is updated in S27, and max is updated in S24. That is, when the buffer control unit 105 acquires a packet (77) that is more than the number of elements after the arrival waiting packet (65), the buffer control unit 105 stores the packet in the buffer and the element that stores the packet. The packet stored in the index (6, 7) below the index (7) and the packet stored in the index (8, 9, 0) continuous thereto are output.

  The above example is an example in which wait <num. However, in the case of num <wait, similar packet addition and transmission processing is performed in S14, S17, and S18. This is substantially the same as the above example, but corresponds to the case where the numbering of the arrival packet has passed the maximum value, returned to the beginning, and has become a small value.

  If the result of the determination in S11 is num <wait−NUM_MAX + LEN × 2 (example: 1 <100−100 + 10 × 2), NUM_MAX is added to num in S12 (example: num = 1 + 100). As a result of the determination in S13, if wait <num <wait + LEN (eg, 100 <101 <100 + 10), the packet is added to the buffer in S14, and max is updated in S15 and S16.

  When wait + LEN <= num <wait + LEN × 2 (example: 100 + 10 <= 112 <100 + 10 × 2), packets up to num-NUM_MUX-LEN (example: 112-100-10) are transmitted in S17 and S18. Then, time is updated in S19, and max is updated in S15 and S16.

<Buffer discard process>
Next, the buffer discarding process will be described with reference to FIG. FIG. 7A shows Example 1 of the buffer discard process.

  In Example 1, when the 65th packet is awaited and the 68th, 69th, 70th, 72th, and 73rd packets are already stored in the buffer, the 63rd is slightly smaller than the 65th. If a packet arrives, discard that packet. There is no change in the M pointer and W pointer.

  FIG. 7B shows an example 2 of the buffer discard process. In example 2, when waiting for the arrival of the 65th packet and the 68th, 69th, 70th, 72nd, and 73th packets are already stored in the buffer, 85 is larger than the 65th by 85 or more. When the packet numbered comes, the packet is discarded.

  Examples 1 and 2 of the packet discard described above are examples of the buffer discard process (drop) of S20 and S28 in the flowchart of FIG.

  That is, if num> = wait−NUM_MUX + LEN × 2 (eg 63> = 65−100 + 10 × 2) as a result of the determination in S10 and S11 of FIG. 4, the packet with the num number is discarded in S20.

  If the result of determination in S10 is wait + LEN × 2 <= num (eg, 65 + 10 × 2 <= 85), the packet with the num number is discarded in S28.

  The buffer storage and discarding procedures described so far are summarized as follows.

  When a packet with a number larger than the packet waiting for arrival arrives, the number is confirmed and compared with the total value (A) obtained by adding the number of packets waiting for arrival and the number of elements in the array. When it is smaller than the total value (A), the storage processing is performed using the remainder obtained by dividing the number by the number of elements as an index. If it is larger than the total value (A), it is further compared with the total value (B) obtained by adding the number of elements to the total value. If it is larger than the total value (B), the packet is discarded. When it is smaller than the total value (B), all the packets stored between the index of the waiting packet to the arrived packet and the packets continuously stored beyond the index of the arrived packet are stored. In some cases, all packets up to one before the unstored index are transmitted, the arrival packet is stored, and the number of the last transmitted packet number + 1 is set as an arrival wait.

  When a packet having a number smaller than the arrival waiting packet arrives, first, the maximum numbering value is subtracted from the arrival waiting packet number and compared with a value (C) obtained by adding twice the number of elements. If it is larger than the value (C), it is discarded, and if it is smaller, a value (D) obtained by adding the numbering maximum value to the number of the arrived packet and a value obtained by adding the number of elements of the array to the number of the waiting packet (E ), And if the value of (D) is smaller than the value of (E), it is stored in the buffer, and if it is larger, all packets stored between the indexes obtained by subtracting the number of elements from the arrival packet number have arrived. If there are packets stored continuously beyond the packet index, send all packets up to one before the unstored index, store the incoming packets, and add the last packet number + 1 The number is waiting for arrival.

<Timeout processing>
Next, an example of timeout processing will be described with reference to FIG. In the example shown in FIG. 8, the 65th packet is awaited, and the 68th, 69th, 70th, 72th, and 73th packets are already stored in the buffer, and the 65th packet is received even after a certain period of time. If the packet does not arrive, it is determined that a timeout has occurred, and as a timeout process, the 65th, 66th, and 67th packets are treated as being discarded, and the 68th, 69th, and 70th packets are transmitted. At this time, since the waiting packet changes, the waiting pointer is shifted to 71.

  That is, in the present embodiment, the buffer control unit 105 performs a timeout process when a waiting packet does not arrive for a certain time in the buffering process. When the load is high, the queue before and after processing may overflow and burst loss may occur. If timeout processing is performed in units of packets at the time of burst loss, multiple timeout processing is performed at once, and packet transmission is stopped for a long time. Therefore, once a timeout occurs, the packet is transmitted from there by skipping to the beginning of the packet accumulated in the buffer. In the above example, since the 68th packet corresponds to the head of the packet accumulated in the buffer, the 68th packet and the continuous 69th and 70th packets are transmitted at the time of timeout processing. Yes.

  Also, in this embodiment, if a time-out process is performed when no packets are stacked in the buffer, the time-out process is not performed because a packet that arrives after a certain period of time is discarded. .

  The example of the timeout process is an example of the timeout process of S6 in the flowchart of FIG.

  That is, the result of determination in S2 of FIG. 4 is wait <max (for example, 65 <73), and in S4, when “0 <= wait <LEN && NUM_MAX−LEN <max <= NUM_MAX” is not satisfied, time is determined in S5. A comparison is made between (previous packet transmission time) and now (current time), and when the waiting time has passed, a time-out process is performed in S6, and time is updated in S7. If the waiting time has not passed and the packet remains in the queue 104 in S5, the packet is pruned from the queue 104 and the process is performed (S8, S9-).

  If “0 <= wait <LEN && NUM_MAX−LEN <max <= NUM_MAX” is satisfied in S4, the process proceeds to S8 without performing a timeout process.

  As a result of the determination in S2 of FIG. 4, wait> max is satisfied. In S3, when “0 <= max <LEN && NUM_MAX−LEN <wait <= NUM_MAX” is satisfied, time (previous time, packet transmission time) in S5 Now (current time) is compared, and when the waiting time has passed, a time-out process is performed in S6, and time is updated in S7. If the waiting time has not passed and the packet remains in the queue 104 in S5, the packet is pruned from the queue 104 and the process is performed (S8, S9-).

  If “0 <= max <LEN && NUM_MAX−LEN <wait <= NUM_MAX” is not established in S3, the process proceeds to S8 without performing timeout processing.

  Note that the case of “False” in S3 of FIG. 4 and the case of “True” in S4 correspond to the case where no packet is loaded in the buffer as described above, and the time-out process is not performed.

<Dummy packet transmission when parallelized processing fails>
If the packet is discarded when the processing fails, the discarded packet does not reach the buffering process and a timeout occurs. In this embodiment, in order to prevent this, a buffering process is performed by putting a dummy packet (which is given the packet number) into the queue 104 when the process fails, and an operation is performed to discard the packet. Specifically, for example, when it is determined in the above processing procedure that a dummy packet is transmitted, the dummy packet is discarded without being transmitted.

(Summary of the embodiment, effects, etc.)
As described above, in this embodiment, the packet processing system processes packets in parallel, and includes a numbering unit that assigns a number indicating the order of packets to an input packet, and the numbering unit. Processing means for executing parallel processing on the numbered packets, and control means for outputting the packets processed by the processing means in the order of the numbers given by the number giving means, the control means Is provided with a buffer for temporarily storing a packet that waits for an output order among the packets output from the processing means.

  When the control unit acquires a packet waiting for arrival from the processing unit, the control unit outputs the packet, and among the packets stored in the buffer, a series of packets whose number is consecutive with the acquired packet. It is good also as outputting.

  The control unit may store the packet in the buffer when a packet to be output after the arrival waiting packet is acquired from the processing unit within a predetermined number of packets.

  For example, an array can be used as the data structure of the buffer in the control means.

  The number of elements in the array is, for example, smaller than the maximum number assigned to the packet, and the control means stores the packet in an element whose index is a remainder obtained by dividing the packet number by the number of elements in the array. To do.

  When the control means obtains a packet after the number of elements more than the number of elements waiting for arrival from the processing means, the control means stores the packet in the buffer and is equal to or less than the index of the element storing the packet. A packet stored in the index and a series of packets in which the stored packet and number are consecutive may be output.

  The control means skips to the head of the packet stored in the buffer and outputs the head packet and the head packet when a timeout occurs because the next packet cannot be output after outputting the packet. A series of packets with consecutive numbers may be output.

  The control means may use a dummy packet having the same number as the packet when the processing of the packet in the processing means fails.

  In the present embodiment, a program for causing a computer to function as the packet control means in the packet processing system can also be provided.

  Further, according to the present embodiment, a communication system that transmits packets in parallel through a plurality of routes on the network, the packet received from the upstream is assigned a number indicating the order of the packets, and the numbered packets A first packet transfer device that sends the packet to the second route, and a second packet transfer device that receives the packet from the plurality of routes and sends the packet downstream in the order of the numbers assigned by the first packet transfer device. And the second packet transfer device includes a buffer for temporarily storing a packet that waits for a downstream transmission order among packets received from the plurality of paths. A communication system is provided.

  Further, according to the present embodiment, a packet processing apparatus for processing packets in parallel, the number assigning means for assigning a number indicating the order of the packets to the input packet, and the number assigned by the number assigning means Processing means for executing parallel processing on packets, and control means for outputting packets processed by the processing means in the order of numbers assigned by the number assigning means, wherein the control means comprises the processing means A packet processing apparatus is provided that includes a buffer for temporarily storing a packet that waits for an output order among packets output from.

  Further, according to the present embodiment, a number assigning unit that assigns a number indicating a packet order to an input packet, and a processing unit that executes parallel processing on the packet assigned a number by the number assigning unit. A packet processing apparatus that inputs a packet output from a processing system having the packet and executes processing of the packet, and outputs a packet after processing by the processing unit in the order of numbers assigned by the number assigning unit The control means is provided with a packet processing device comprising a buffer for temporarily storing packets that wait for the output order among the packets output from the processing means. This packet processing apparatus corresponds to, for example, an apparatus (computer) having a queue 104 and a buffer control unit 105 in the case where the packet processing system 100 described above is composed of a plurality of computers. Further, this packet processing apparatus corresponds to, for example, the packet transfer apparatus 202 shown in FIG.

  In addition, according to the present embodiment, a program for causing a computer to function as control means in the packet processing apparatus is provided.

  According to the technology described in the embodiment (for example, the packet processing system in FIG. 1 and the packet transfer apparatus 202 in FIG. 2), parallel processing can be performed by deploying queues before and after a module for which parallel processing is to be performed. Enables each packet to be numbered in the functional unit before parallel processing (including parallel transmission), and after parallel processing is performed, the buffering processing is performed to output the packets in the numbered order. be able to.

  In addition, by performing buffer storage / transmission processing and the like according to the procedure shown in FIG. 4, high-speed buffering processing is possible, and processing efficiency can be improved while maintaining the order. Furthermore, the processing efficiency can be maintained even when processing fails (for example, reception of a broken encrypted packet). In addition, it is possible to prevent a long-time processing stop in the case of a temporary high load (eg, burst traffic).

  The present invention is not limited to the above-described embodiments, and various modifications and applications are possible within the scope of the claims.

DESCRIPTION OF SYMBOLS 100 Packet processing system 101 Number assignment part 102 Queue 103 Packet processing part 104 Queue 105 Buffer control part 200 Network 201 Packet transfer apparatus 202 Packet transfer apparatus

Claims (14)

A packet processing system for processing packets in parallel,
Numbering means for assigning a number indicating the order of the packets to the input packet;
Processing means for executing parallel processing on the packets numbered by the number assigning means;
Control means for outputting packets processed by the processing means in the order of the numbers given by the number giving means,
The control means comprises a buffer for temporarily storing packets that wait for the output order among the packets output from the processing means. When the control unit acquires a packet waiting for arrival from the processing unit, the control unit outputs the packet, and among the packets stored in the buffer, a series of packets whose number is consecutive with the acquired packet. The packet processing system according to claim 1, wherein the packet processing system outputs the packet. The control unit stores the packet in the buffer when a packet to be output after the arrival waiting packet is acquired from the processing unit within a predetermined number of packets. 3. The packet processing system according to 2. The packet processing system according to any one of claims 1 to 3, wherein an array is used as a data structure of the buffer in the control means. The number of elements in the array is smaller than the maximum number assigned to the packet, and the control means stores the packet in an element whose index is a remainder obtained by dividing the packet number by the number of elements in the array. The packet processing system according to claim 4. When the control means obtains a packet after the number of elements more than the number of elements waiting for arrival from the processing means, the control means stores the packet in the buffer and is equal to or less than the index of the element storing the packet. The packet processing system according to claim 5, wherein the packet stored in the index and a series of packets whose numbers are consecutive with the stored packet are output. The control means skips to the head of the packet stored in the buffer and outputs the head packet and the head packet when a timeout occurs because the next packet cannot be output after outputting the packet. The packet processing system according to claim 1, wherein a series of packets having consecutive numbers are output. The packet according to any one of claims 1 to 7, wherein the control unit uses a dummy packet having the same number as the packet when the processing of the packet in the processing unit fails. Processing system. A communication system for transmitting packets in parallel through a plurality of paths on a network,
A first packet transfer device that assigns a number indicating a packet order to a packet received from upstream, and sends the numbered packet to a plurality of paths;
A second packet transfer device that receives the packets from the plurality of paths and sends the packets downstream in the order of the numbers assigned by the first packet transfer device;
The second packet transfer apparatus includes a buffer for temporarily storing a packet that waits for a downstream transmission order among packets received from the plurality of paths. A packet processing method executed by a packet processing system for processing packets in parallel,
A numbering step for assigning a number indicating the order of the packets to the input packet;
A processing step of performing parallel processing on the packets numbered by the numbering step;
A control step for outputting the packets after the processing by the processing step in the order of the numbers given in the numbering step;
A packet processing method characterized in that, in the control step, a packet that waits for an output order among the processed packets is temporarily stored in a buffer.   The program for functioning a computer as a control means in the packet processing system of any one of Claims 1 thru | or 8. A packet processing device for processing packets in parallel,
Numbering means for assigning a number indicating the order of the packets to the input packet;
Processing means for executing parallel processing on the packets numbered by the number assigning means;
Control means for outputting packets processed by the processing means in the order of the numbers given by the number giving means,
The packet processing apparatus, wherein the control means includes a buffer for temporarily storing packets that wait for the output order among the packets output from the processing means. A packet output from a processing system having numbering means for assigning a number indicating the order of the packets to the input packet and processing means for executing parallel processing on the packet numbered by the numbering means Is a packet processing device that executes processing of the packet,
A control means for outputting packets processed by the processing means in the order of the numbers given by the number giving means;
The packet processing apparatus, wherein the control means includes a buffer for temporarily storing packets that wait for the output order among the packets output from the processing means.   The program for functioning a computer as a control means in the packet processing apparatus of Claim 12 or 13.

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