WO2012051799A1 - 一种高介电常数栅介质材料及其制备方法 - Google Patents

一种高介电常数栅介质材料及其制备方法 Download PDF

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WO2012051799A1
WO2012051799A1 PCT/CN2011/001727 CN2011001727W WO2012051799A1 WO 2012051799 A1 WO2012051799 A1 WO 2012051799A1 CN 2011001727 W CN2011001727 W CN 2011001727W WO 2012051799 A1 WO2012051799 A1 WO 2012051799A1
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layer
film
deposition
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王文武
赵超
韩锴
陈大鹏
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58—After-treatment
    • C23C14/5806—Thermal treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment

Definitions

  • the invention relates to the field of semiconductor materials and preparation thereof, and in particular to a gate dielectric material with high dielectric constant and a preparation method thereof. Background technique
  • High-k gate dielectric materials have received wide attention and application in CMOS (Complementary Metal Oxide Semiconductor) processes, especially those of 45 nm and below.
  • CMOS Complementary Metal Oxide Semiconductor
  • the introduction of the high-k gate dielectric material can effectively increase the physical thickness of the gate shield under the same equivalent oxide thickness (EOT), thereby achieving the purpose of suppressing the gate leakage current.
  • EOT equivalent oxide thickness
  • HfO 2 is currently considered to be one of the most likely high-k gate dielectric materials to be used in CMOS processes.
  • the relative dielectric constant k of Hf ⁇ 2 is between 16-25, the band gap is about 5.8 eV, and the conduction band offset is about 1.4 eV.
  • Hf0 2 has obvious advantages and application prospects as high-k gate dielectric materials
  • Hf02 also exposes some shortcomings, such as lower recrystallization, as the feature size of MOS devices is further reduced, especially into the technology nodes of 32 nm and below.
  • Temperature (400 ° C - 500 ° C) thermal instability with the substrate Si, k value to be further improved, and the like. Therefore, how to solve the above deficiencies becomes the key to determine whether Hf0 2 can be applied in the next process node.
  • Hf0 2 has three different crystal structures, namely a monoclinic phase (k value of about 16, stable at room temperature), a tetragonal phase (k value of about 33, 1800 ° C or so stable), and a cubic phase (k)
  • k value of about 16, stable at room temperature
  • tetragonal phase k value of about 33, 1800 ° C or so stable
  • k cubic phase
  • the value is about 29, stable around 2700 °C, as shown in Figure 1. It has been reported that the polycrystalline structure of the Hf-based high-k gate dielectric material does not cause excessive leakage current density, and Intel has confirmed this conclusion in its industrial production of 45nm technology. Therefore, how to design an Hf-based high-k gate dielectric with a fixed crystal structure through material and process optimization is improved. One of the methods of k value and enhanced thermal stability.
  • the thickness of the gate dielectric film is required to be higher, and for an ultrathin film (such as 1-3 nm), the existing process is generally difficult to form a continuous crystal structure, and therefore, The crystallization problem of thin films is also a problem to be solved.
  • the object of the present invention is to solve at least one of the above technical problems, in particular to provide a Hf-based gate dielectric material having a large band gap, a higher k value and a high thermal stability, and to solve the problem of crystallization of an ultra-thin film. .
  • the present invention provides a high dielectric constant gate dielectric material Hf ⁇ x Si x O y , characterized in that: Hf 1-x Si x Oy has a cubic phase or a tetragonal phase, The dielectric constant is 18-34, and the X ranges from 0.02 to 0.1.
  • the present invention provides a method for preparing a high dielectric constant gate dielectric material Hf Si x O y comprising the steps of: material A containing Hf source and material B containing Si source or containing Hf source and Si
  • the source material C is deposited on the semiconductor substrate by a film formation process; annealing, annealing temperature is 500-800.
  • an Hf!-xSixOy film having a cubic crystal phase or a tetragonal crystal phase is formed, wherein the x ranges from 0.02 to 0.1.
  • the annealing temperature is 650-800° (.
  • the annealing time is 5-300 s, preferably 20-120 s.
  • the annealing atmosphere is N 2 or N 2 + 02, wherein, when the annealing atmosphere is N 2 + 02, the content is 0.1% to 02 --1% (volume).
  • the film forming process comprises: any one of physical vapor deposition PVD, metal organic chemical vapor deposition MOCVD, and atomic layer deposition ALD.
  • the film formation manner includes the following two: co-sputtering the target of the material A and the target of the material B, or sputtering the material a target of C, forming an amorphous phase or a monoclinic phase of Hf] -x Si x O y film on the semiconductor substrate; respectively sputtering the target of the material A and the material B layer by layer a target to form one or more deposition cycle layers on the semiconductor substrate, each of the deposition cycle layers including one of the material A layer and one of the material B layers.
  • the material A comprises Hf0 2 or Hf
  • the material B comprises SiO 2 or Si
  • the material C comprises a ternary oxide Hf 1-a Si a O b , wherein a ranges from 0.02 to 0.1.
  • the formed Hf 1 is formed by controlling the sputtering power of each of the targets or controlling the relative deposition thickness of each material in each of the deposition cycle layers.
  • the X of the -x Si x O y film ranges from 0.02 to 0.1.
  • the film formation manner includes the following two types: the material A and the material B are simultaneously introduced into the reaction chamber, Forming an amorphous phase or a monoclinic phase of Hf 1-x Si x O y film; separately layer-by-layer deposition to form one or more deposition cycle layers, each of said deposition cycle layers comprising an Hf0 2 layer And a SiO 2 layer, wherein the Hf0 2 layer is formed by the reaction of the material A, and the SiO 2 layer is formed by the reaction of the material B.
  • the material A comprises an organic metal source Hf(N(CH 3 ) 2 ) 4 ( TMDEAH ) , Hf(NC 2 H 5 CH 3 ) 4 (TEMAH ) , Hf(N(C 2 H 5 ) 2 ) 4 (TDEAH) or a combination of any one or more of inorganic metal sources HfCl 4 including an organic source C 8 H 22 N 2 Si (SAM24 ) , HSi[N(CH 3 ) 2 ] 3 ( 3DMAS a combination of any one or more of them.
  • the relative deposition thickness with the Si0 2 layer is such that the formed Hf 1-x Si x O y film has a range of X of 0.02 to 0.1.
  • the invention obtains Hf 1-x Si x O y having a cubic phase or a tetragonal crystal phase by incorporating a specific amount of SiO 2 component in the high-k gate dielectric material Hf0 2 and combining an optimized heat treatment process, thereby obtaining a comparison High-k gate dielectric film material with large band gap, higher k value and thermal stability.
  • the ultra-thin film having a continuous crystal structure is easily formed by the method proposed by the present invention, which is advantageous for solving the problem of crystallization of the ultra-thin film.
  • Figure 1 shows three crystal structures of a high-k gate shield material Hf0 2 ;
  • FIGS. 2-4 are schematic views showing a method of preparing a gate dielectric material Hf ⁇ SixOy according to an embodiment of the present invention. detailed description
  • the structure of the first feature described below on the "on" of the second feature may include embodiments in which the first and second features are prepared for direct contact, and may also include additional features between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • the invention provides a high-k dielectric constant gate dielectric material Hf x Si 1-x O y having a cubic phase or a tetragonal phase, wherein X ranges from 0.02 to 0.1 and the dielectric constant is from 18 to 34.
  • the gate dielectric material proposed by the present invention has a larger band gap, a higher k value, and a higher thermal stability than a conventional Hf-based high-k gate dielectric material such as Hf0 2 .
  • the preparation method of the gate dielectric material Hf x Si x O y will be described in detail below with reference to FIGS. 2-4, including the following steps: the material A containing the Hf source and the material B containing the Si source or the Hf source and Si
  • the source material C is deposited on the semiconductor substrate by a film formation process; then, thermal annealing is performed, and the annealing temperature is 500-800. C, thereby forming a cubic phase or a tetragonal phase
  • X ranges from 0.02 to 0.1.
  • the annealing temperature is optimized to be 650-800 ° C; the annealing time is 5-300 s, and the optimum is 20 - 120 s; the annealing atmosphere is N 2 or 0 2 and the volume content is 0.1% - 1% of N 2 + 0 2 The combination.
  • the film forming process needs to control the Si content in Hf 1-x Si x O y to have a X range of 0.02-0.1, which can be adjusted by adjusting the composition of the material A containing the Hf source and the material B containing the Si source. Ratio, or adjust the composition ratio of the Hf source and the Si source in the material C.
  • the film formation process may be physical vapor deposition (PVD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD) or other suitable Any of the methods.
  • PVD physical vapor deposition
  • PLD pulsed laser deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • the preparation method of the high-k dielectric constant gate dielectric material Hf 1-x Si x O y will be specifically described by taking PVD, metal organic chemical vapor deposition (MOCVD) and ALD processes as examples. It should be noted that these examples are not intended to limit the invention, and those skilled in the art, in combination with other suitable film forming processes, may be used in the same manner as defined in the present invention, as long as they are applied to the process conditions and material components defined in the present invention.
  • the film materials Hf, -x Si x O y of physical properties are all included
  • the film formation is performed by a PVD method
  • the process pressure may be 0.2-lPa
  • the sputtering atmosphere may be Ar gas
  • the flow rate may be 15-50 sccm
  • the semiconductor substrate temperature may range from room temperature to 400.
  • C then at 500-800.
  • the film formation method includes the following two types:
  • Method 1 co-sputtering a target of material H containing Hf source and material B containing Si source, or sputtering target of material C containing Hf source and Si source to form amorphous on the semiconductor substrate Phase or monoclinic phase Hf 1-x Si x O y film.
  • the materials A and B may be a simple material such as Hf and Si, or may be a binary oxide such as Hf0 2 and SiO 2
  • the material C may be a ternary oxide Hf 1-a Si a having a composition ratio. O b , wherein the a ranges from 0.02 to 0.1.
  • the sputtering atmosphere may be Ar+0 2 ; when depositing in a co-sputtering manner, by controlling the sputtering power of each of the targets,
  • the X of the formed Hf 1-x Si x O y film ranges from 0.02 to 0.1.
  • Method 2 sputtering a target of the material A containing the Hf source and the target containing the Si source layer by layer to form one or more deposition cycle layers on the semiconductor substrate, each deposition cycle layer Includes a material A layer and a material B layer.
  • the monoclinic phase Hf0 2 (material A) and the tetragonal phase SiO 2 (material B) may be deposited layer by layer according to a certain thickness ratio relationship, and then annealed according to the above annealing process to form the formed Hf.
  • the X of the 1-x Si x O y film ranges from 0.02 to 0.1 as shown in FIG.
  • the relationship is to separately deposit Hf (material A) and Si (material B), and the sputtering atmosphere may be pure Ar gas or Ar+0 2 mixed gas, and then annealed according to the above annealing process to form the formed Hf xSixOy film.
  • the range of X is 0.02-0.1, as shown in Figure 3.
  • the film is first deposited by MOCVD or ALD, and the reaction chamber temperature is 200-600. C, then at 500-800. Annealing at an C temperature, N 2 or an N 2 + 0 2 atmosphere containing 1% (by volume) 0 2 to form a Hi ⁇ x Si x O y film having a cubic phase or a tetragonal phase.
  • the film formation method includes the following two types:
  • Method 1 A material A containing an Hf source and a material B containing a Si source are simultaneously introduced into the reaction chamber to form an amorphous phase or a monoclinic phase Hf ⁇ SixOy film on the semiconductor substrate.
  • the material A includes an organic metal source Hf(N(CH 3 ) 2 ) 4 ( TMDEAH ), Hf(NC 2 H 5 CH 3 ) 4 (TEMAH), Hf(N(C 2 H 5 ) 2 ) 4 ( TDEAH) or a combination of any one or more of the inorganic metal sources HfCl 4
  • the material B includes an organic source C 8 H 22 N 2 Si (SAM24 ) , HSi[N(CH 3 ) 2 ] 3 ( 3DMAS )
  • the oxidizing agent may be one or more of H 2 0, 0 2 , NO, N 2 0 or 0 3 in any combination of one or more. It should be noted that during the reaction, the flow rate of the material A and the material B can be controlled so that the
  • Method 2 separately depositing layer by layer to form one or more deposition cycle layers, each of the deposition cycle layers comprising a monoclinic ⁇ 2 layer and a tetragonal SiO 2 layer, wherein The Hf0 2 layer is formed by the reaction of the material A, and the SiO 2 layer is formed by the reaction of the material B, as shown in FIG. Among them, the materials A and B, and the oxidizing agent required for the reaction can be selected by referring to the materials listed in the first embodiment of the present embodiment. It should be noted that during the reaction, the relative deposition thickness of the ⁇ 2 layer and the SiO 2 layer in each deposition cycle layer can be controlled so that the X of the formed Hf 1-x Si x O y film has a range of 0.02. -0.1.
  • the invention obtains Hf ⁇ x Si x O y having a cubic phase or a tetragonal crystal phase by incorporating a specific amount of SiO 2 component in the high-k gate dielectric material Hf0 2 and combining an optimized heat treatment process, thereby obtaining a larger High k gate dielectric film material with band gap, higher k value and thermal stability.
  • the ultra-thin film having a continuous crystal structure is easily formed by the method proposed by the present invention, which is advantageous for solving the problem of crystallization of the ultra-thin film.

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Description

一种高介电常数栅介质材料及其制备方法
优先权要求
本申请要求了 2010 年 10 月 21 日 提交的、 申请号为 201010520981.4 , 发明名称为 "一种高介电常数栅介质材料及其制备方 法" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体材料及其制备领域， 特别涉及一种高介电常数 的栅介质材料及其制备方法。 背景技术
高 k栅介质材料在 CMOS (互补金属氧化物半导体） 工艺， 尤其 是 45nm及以下的技术代中已经得到广泛关注及应用。高 k栅介质材料 的引入可以保证在相同等效氧化层厚度 （EOT ) 的情况下， 有效地增 加栅介盾的物理厚度， 从而可以达到抑制栅漏电流的目的。 HfO2是目 前被认为是最有可能被应用到 CMOS工艺中的高 k栅介质材料之一。 Hf〇2的相对介电常数 k值在 16-25之间， 带隙约为 5.8 eV, 导带偏移 量约为 1.4 eV， 这些电学性质符合 MOS器件对高 k栅介质材料选择的 要求， 并有望作为 MOS器件的栅介质层来降低栅极漏电流。
虽然 Hf02作为高 k栅介质材料具有明显优势和应用前景， 但随着 MOS器件特征尺寸进一步缩小， 尤其是进入 32nm及以下技术节点， Hf02也暴露出一些不足之处， 如较低的重结晶温度（ 400°C - 500°C )、 与衬底 Si之间的热不稳定性、 有待进一步提高的 k值等。 因而， 如何 解决上述的不足之处成为决定 Hf02能否在下一个工艺节点得到应用的 关键。
通常， Hf02有三种不同的晶体结构， 即单斜晶相 （k值约为 16, 室温下稳定） 、 四角晶相 （k值约为 33 , 1800。C左右稳定） 和立方晶 相 （k值约为 29, 2700°C左右稳定） ， 如图 1所示。 有报道指出， Hf 基高 k 栅介质材料的多晶结构并不会导致过大的漏电流密度， 英特尔 公司在其 45nm技术代的工业生产中也证实了该结论。 因此， 如何通过 材料及工艺优化而设计出具有固定结晶结构的 Hf基高 k栅介质是提高 k值和增强热稳定性的方法之一。
另一方面， 随着 M0S器件特征尺寸进一步缩小， 对栅介质薄膜的 厚度要求更高， 而对于超薄薄膜（如 l -3nm ) , 现有工艺一般较难形成 连续的结晶结构， 因此， 超薄薄膜的结晶化问题也是待解决的问题之
发明内容
本发明的目的旨在至少解决上述技术问题之一， 特别是提供一种 具有较大带隙、 更高 k值和高热稳定性的 Hf基栅介质材料， 并解决了 超薄薄膜的结晶化问题。
为达到上述目的， 一方面， 本发明提出一种高介电常数栅介质材 料 Hf^xSixOy, 其特征在于： 所述 Hf1-xSixOy具有立方晶相或四角晶相， 介电常数为 18-34, 所述 X的范围为 0.02-0.1。
另一方面， 本发明提出一种高介电常数栅介质材料 Hf SixOy的制 备方法， 包括以下步骤： 将含 Hf源的材料 A与含 Si源的材料 B或者 将含 Hf源和 Si源的材料 C通过成膜工艺淀积在半导体衬底上； 退火， 退火温度为 500-800。 (：， 形成具有立方晶相或四角晶相的 Hf!-xSixOy薄 膜， 其中， 所述 x的范围为 0.02-0.1。
优选地， 所述退火温度为 650-800° ( 。
可选地， 退火时间为 5-300s, 优选的为 20-120s。
可选地， 退火氛围为 N2或 N2 + 02， 其中， 当所述退火氛围为 N2 + 02时， 02的含量为 0.1 %— 1 % (体积） 。
可选地， 所述成膜工艺包括： 物理气相淀积 PVD、 金属有机化学 气相淀积 MOCVD和原子层淀积 ALD中的任意一种工艺。
可选地， 采用所述物理气相淀积 PVD工艺成膜时， 成膜方式包括 以下两种： 共溅射所述材料 A的靶材和所述材料 B的靶材， 或者溅射 所述材料 C 的靶材， 以在所述半导体衬底上形成非晶相或单斜晶相的 Hf] -xSixOy薄膜；分别逐层溅射所述材料 A的靶材和所述材料 B的靶材， 以在所述半导体衬底上形成一个或多个淀积循环层， 每个所述淀积循 环层包括一个所述材料 A层和一个所述材料 B层。 其中， 所述材料 A 包括 Hf02或 Hf， 所述材料 B包括 Si02或 Si, 所述材料 C包括三元氧 化物 Hf1-aSiaOb, 其中 a的范围为 0.02-0.1。 并且， 采用所述物理气相淀积 PVD工艺成膜时， 通过控制各个所 述靶材的溅射功率或者控制每个所述淀积循环层中各材料的相对淀积 厚度， 使形成的 Hf1-xSixOy薄膜的 X的范围为 0.02-0.1。
可选地， 采用所述金属有机化学气相淀积 MOCVD和原子层淀积 ALD工艺成膜时， 成膜方式包括以下两种： 在反应室中同时通入所述 材料 A和所述材料 B, 以形成非晶相或单斜晶相的 Hf1-xSixOy薄膜； 分 别逐层淀积以形成一个或多个淀积循环层， 每个所述淀积循环层包括 一个 Hf02层和一个 Si02层， 其中， 所述 Hf02层由所迷材料 A反应生 成， 所述 Si02层由所述材料 B反应生成。 其中， 所述材料 A包括有机 金属源 Hf(N(CH3)2)4 ( TMDEAH ) 、 Hf(NC2H5CH3)4 ( TEMAH ) 、 Hf(N(C2H5)2)4 (TDEAH ) 或无机金属源 HfCl4 中的任意一种或多种的 组合， 所述材料 B包括有机物源 C8H22N2Si ( SAM24 ) 、 HSi[N(CH3)2]3 ( 3DMAS ) 中的任意一种或多种的组合。
并且， 采用所述金属有机化学气相淀积 MOCVD 和原子层淀积 ALD工艺成膜时， 通过控制所述材料 A和所述材料 B的流速或者控制 每个所述淀积循环层中 Hf02层和 Si02层的相对淀积厚度， 使形成的 Hf1-xSixOy薄膜的 X的范围为 0.02-0.1。
本发明通过在高 k栅介质材料 Hf02中掺入特定量的 Si02成分，并 结合优化的热处理工艺形成具有立方晶相或四角晶相的 Hf1-xSixOy, 进 而获得具有较大带隙、 更高 k值和热稳定性的高 k栅介质薄膜材料。 并且， 利用本发明提出工艺方法易于形成具有连续结晶结构的超薄薄 膜， 有利于解决超薄薄膜的结晶化问题。
本发明附加的方面和优点将在下面的描述中部分给出， 部分将从 下面的描述中变得明显， 或通过本发明的实践了解到。 附图说明
本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的 描述中将变得明显和容易理解， 本发明的附图是示意性的， 因此并没 有按比例绘制。 其中：
图 1为高 k 栅介盾材料 Hf02的三种晶体结构；
图 2-4 为本发明实施例的栅介质材料 Hf^SixOy的制备方法示意 图。 具体实施方式
下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或 类似功能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用 于解释本发明， 而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不 同结构。 为了简化本发明的公开， 下文中对特定例子的部件和设置进 行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 /或字母。 这种重复是为了简 化和清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关 系。 此外， 本发明提供了的各种特定的工艺和材料的例子， 但是本领 域普通技术人员可以意识到其他工艺的可应用于性和 /或其他材料的使 用。 另外， 以下描述的第一特征在第二特征之 "上" 的结构可以包括 第一和第二特征制备为直接接触的实施例， 也可以包括另外的特征制 备在第一和第二特征之间的实施例， 这样第一和第二特征可能不是直 接接触。
本发明提出一种高 k介电常数栅介质材料 HfxSi1-xOy, 具有立方晶 相或四角晶相， 其中 X的范围为 0.02-0.1， 介电常数为 18-34。 相对于 普通 Hf基高 k栅介质材料（如 Hf02 )而言， 本发明提出的栅介质材料 具有较大带隙、 更高 k值和高热稳定性的。
以下将结合附图 2-4详细说明所述栅介质材料 Hf xSixOy的制备方 法， 包括以下步骤： 将含 Hf源的材料 A与含 Si源的材料 B或者将含 Hf源和 Si源的材料 C通过成膜工艺淀积在半导体衬底上；然后进行热 退火， 退火温度为 500-800。C, 从而形成具有立方晶相或四角晶相的
Figure imgf000005_0001
薄膜， X 的范围为 0.02-0.1。 其中， 退火温度最优化为 650-800°C; 退火时间为 5-300s， 最优化为 20 - 120s; 退火氛围为 N2 或 02的体积含量为 0.1%-1%的 N2 + 02的组合。
需要指出的是， 如果 Hf1-xSixOy中的 Si含量不够高， 则很难利用 退火工艺将非晶或单斜晶相结构的 HfSiOz转变成立方或四角晶相， 如 果 Si含量过高， 那么在随后的热退火过程中， HfSiOz中会出现相分离 反应 HfSiOz→Hf02 + Si02， Si02的分离将影响整个材料的相结构和电 学特性， 如介电常数 k值。 因此， 成膜工艺阶段需要控制 Hf1-xSixOy中 的 Si含量， 使其 X的范围为 0.02-0.1 , 可通过调节含 Hf源的材料 A与 含 Si源的材料 B的组分比， 或者调节材料 C中 Hf源和 Si源的组分比 实现。
成膜工艺可以是物理气相淀积 （PVD ) 、 脉冲激光淀积 （PLD ) 、 化学气相淀积 （CVD ) 、 原子层淀积 （ALD ) 、 等离子体增强原子层 淀积 （PEALD ) 或者其他合适的方法中的任意一种。 以下将以 PVD、 金属有机化学气相淀积 （MOCVD ) 和 ALD工艺为例具体说明高 k介 电常数栅介质材料 Hf1-xSixOy的制备方法。 需说明地是， 这些实施例并 不局限本发明， 本领域的技术人员结合其他合适的成膜工艺， 只要运 用于本发明所限定的工艺条件和材料组分， 形成与本发明所限定的相 同物理性质的薄膜材料 Hf , -xSixOy , 均包含在本发明的保护范围之内。
实施例一 （PVD成膜） ：
首先利用 PVD方法淀积成膜， 工艺压力可以为 0.2-lPa， 溅射氛围 可以为 Ar气， 流量可以为 15-50sccm, 半导体衬底温度范围可以为室 温 -400。C, 然后在 500-800。C温度下、 N2或含 1% (体积比） 02的 N2 + 02的退火氛围中退火， 以形成具有立方晶相或四角晶相的
Figure imgf000006_0001
薄膜。 其中， 成膜方式包括以下两种：
方式一： 共溅射含 Hf源的材料 A与含 Si源的材料 B的靶材， 或 者溅射含 Hf 源和 Si源的材料 C的靶材， 以在所述半导体衬底上形成 非晶相或单斜晶相的 Hf1-xSixOy薄膜。 具体地， 材料 A和 B可以是 Hf 和 Si等单质材料， 也可以是 Hf02和 Si02等二元氧化物， 材料 C可以 是配好组分比的三元氧化物 Hf1-aSiaOb，其中，所述 a的范围为 0.02-0.1。 需注意的是， 如果靶材为 Hf 和 Si 等单质材料， 则溅射氛围可以为 Ar+02; 以共溅射的方式淀积时， 通过控制各个所述靶材的溅射功率， 使形成的 Hf1-xSixOy薄膜的 X的范围为 0.02-0.1。
方式二： 分别逐层溅射含 Hf 源的材料 A的靶材和含 Si源的的靶 材， 以在所述半导体衬底上形成一个或多个淀积循环层， 每个淀积循 环层包括一个材料 A层和一个材料 B层。 具体地， 可以按照一定的厚 度比例关系分别逐层淀积单斜晶相的 Hf02(材料 A )和四方晶相的 Si02 (材料 B ) , 然后按照上述退火工艺进行退火， 使形成的 Hf1-xSixOy薄 膜的 X的范围为 0.02-0.1 , 如图 2所示。 可选地， 按照一定的厚度比例 关系分别逐层淀积 Hf (材料 A ) 和 Si (材料 B ) , 溅射氛围可以为纯 Ar气或 Ar+02混合气体， 然后同样按照上述退火工艺进行退火， 使形 成的 Hf xSixOy薄膜的 X的范围为 0.02-0.1 , 如图 3所示。
实施例二 （ MOCVD或 ALD成膜） ：
首先利用 MOCVD 或 ALD 方法淀积成膜， 反应室温度为 200-600。C, 然后在 500-800。C温度下、 N2或含 1% (体积比） 02的 N2 + 02的退火氛围中退火， 以形成具有立方晶相或四角晶相的 Hi^xSixOy 薄膜。 其中， 成膜方式包括以下两种：
方式一：在反应室中同时通入含 Hf源的材料 A与含 Si源的材料 B , 以在所述半导体衬底上形成非晶相或单斜晶相的 Hf^SixOy薄膜。 具体 地，材料 A包括有机金属源 Hf(N(CH3)2)4 ( TMDEAH )、 Hf(NC2H5CH3)4 (TEMAH) 、 Hf(N(C2H5)2)4 (TDEAH) 或无机金属源 HfCl4中的任意 一种或多种的组合， 材料 B 包括有机物源 C8H22N2Si ( SAM24 ) 、 HSi[N(CH3)2]3 ( 3DMAS ) 中的任意一种或多种的组合， 氧化剂可以为 H20、 02、 NO、 N20或 03中的一种或多种。 需注意的是， 反应过程中， 可以通过控制材料 A和材料 B 的流速， 使形成的 Hf^SixOy薄膜的 X 的范围为 0.02-0.1。
方式二： 分别逐层淀积以形成一个或多个淀积循环层， 每个所述 淀积循环层包括一个单斜晶向的 ΗίΌ2层和一个四方晶相的 Si02层，其 中， 所述 Hf02层由所述材料 A反应生成， 所述 Si02层由所述材料 B 反应生成， 如图 4所示。 其中， 材料 A和材料 B以及反应所需的氧化 剂的选择可以参考本实施例的方式一所列举的材料。 需注意的是， 反 应过程中，可以通过控制每个淀积循环层中 ΗίΌ2层和 Si02层的相对淀 积厚度， 使形成的 Hf1-xSixOy薄膜的 X的范围为 0.02-0.1。
本发明通过在高 k栅介质材料 Hf02中掺入特定量的 Si02成分，并 结合优化的热处理工艺形成具有立方晶相或四角晶相的 Hf^xSixOy, 进 而获得具有较大带隙、 更高 k值和热稳定性的高 k栅介质薄膜材料。 并且， 利用本发明提出工艺方法易于形成具有连续结晶结构的超薄薄 膜， 有利于解决超薄薄膜的结晶化问题。
尽管已经示出和描述了本发明的实施例， 对于本领域的普通技术 人员而言， 可以理解在不脱离本发明的原理和精神的情况下可以对这 些实施例进行多种变化、 修改、 替换和变型， 本发明的范围由所附权 利要求及其等同限定。

Claims

权 利 要 求
1、 一种高介电常数栅介质材料 Hf1-xSixOy， 其特征在于： 所述 Hf1-xSixOy具有立方晶相或四角晶相， 介电常数为 18-34 , 所述 X 的范 围为 0.02-0. 1。
2、 一种高介电常数栅介盾材料 Hf1-xSixOy的制备方法， 包括以下 步骤：
将含 Hf源的材料 A与含 Si源的材料 B或者将含 Hf源和 Si源的 材料 C通过成膜工艺淀积在半导体衬底上；
退火， 退火温度为 500-800。C, 形成具有立方晶相或四角晶相的 Hf!-xSixOy薄膜， 其中， 所述 X的范围为 0.02-0. 1。
3、 如权利要求 2所述的制备方法， 其特征在于， 所述退火温度为 650-800。C。
4、如权利要求 2所述的制备方法，其特征在于，退火时间为 5-300s。
5、 如权利要求 4所述的制备方法， 其特征在于， 所迷退火时间为 20-120s。
6、 如权利要求 2 所述的制备方法， 其特征在于， 退火氛围为 N2 或 N2 + 02, 其中， 当所述退火氛围为 N2 + 02时， 02的体积含量为 0.1 %— 1 %。
7、 如权利要求 2所述的制备方法， 其特征在于， 所述成膜工艺包 括： 物理气相淀积 PVD、 金属有机化学气相淀积 MOCVD和原子层淀 积 ALD中的任意一种工艺。
8、 如权利要求 7所述的制备方法， 其特征在于， 采用所述物理气 相淀积 PVD工艺成膜时， 成膜方式包括以下两种：
共溅射所述材料 A的靶材和所述材料 B的靶材， 或者溅射所述材 料 C 的耙材， 以在所述半导体衬底上形成非晶相或单斜晶相的 Hf1-xSixOy薄膜；
分别逐层溅射所述材料 A的靶材和所述材料 B的耙材， 以在所述 半导体衬底上形成一个或多个淀积循环层， 每个所述淀积循环层包括 一个所述材料 A层和一个所述材料 B层。
9、 如权利要求 8所述的制备方法， 其特征在于， 所述材料 A包括 ΗίΌ2或 Hf， 所述材料 B包括 Si02或 Si, 所述材料 C包括三元氧化物 Hf1-aSiaOb, 其中， 所述 a的范围为 0.02-0.1。
10、 如权利要求 8 所述的制备方法， 其特征在于， 采用所述物理 气相淀积 PVD工艺成膜时， 通过控制各个所述靶材的溅射功率或者控 制每个所述淀积循环层中各材料的相对淀积厚度， 使形成的 Hf1-xSixOy 薄膜的 X的范围为 0.02-0. U
1 1、 如权利要求 7 所述的制备方法， 其特征在于， 采用所述金属 有机化学气相淀积 MOCVD和原子层淀积 ALD工艺成膜时，成膜方式 包^ "以下两种：
在反应室中同时通入所述材料 A和所述材料 B , 以形成非晶相或 单斜晶相的 Hf^SixOy薄膜；
分别逐层淀积以形成一个或多个淀积循环层， 每个所述淀积循环 层包括一个 Hf02层和一个 Si02层， 其中， 所述 ΗίΌ2层由所述材料 A 反应生成， 所述 Si02层由所述材料 B反应生成。
12、 如权利要求 11所述的制备方法， 其特征在于， 所述材料. A包 括有机金属源 Hf(N(CH3)2)4、 Hf(NC2H5CH3)4、 Hf(N(C2H5)2)4或无机金 属源 HfCl4 中的任意一种或多种的组合， 所述材料 B 包括有机物源 C8H22N2Si、 HSi[N(CH3)2]3中的任意一种或多种的组合。
13、 如权利要求 1 1所述的制备方法， 其特征在于， 采用所述金属 有机化学气相淀积 MOCVD和原子层淀积 ALD工艺成膜时，通过控制 所述材料 A和所述材料 B的流速或者控制每个所述淀积循环层中 ΗίΌ2 层和 Si02层的相对淀积厚度， 使形成的 Hf^xSixOy薄膜的 X的范围为 0.02-0.1。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL245656B (en) 2016-05-16 2018-02-28 Technion Res & Dev Foundation Polymer structures with high absorption capacity
WO2018002916A1 (en) 2016-06-26 2018-01-04 Technion Research & Development Foundation Limited Hhh
IL247302B (en) 2016-08-16 2019-03-31 Technion Res & Dev Foundation Systems for releasing materials based on polymer emulsions
US11193206B2 (en) * 2017-03-15 2021-12-07 Versum Materials Us, Llc Formulation for deposition of silicon doped hafnium oxide as ferroelectric materials
US11081337B2 (en) * 2017-03-15 2021-08-03 Versum Materials U.S., LLC Formulation for deposition of silicon doped hafnium oxide as ferroelectric materials
WO2019016816A1 (en) 2017-07-19 2019-01-24 Technion Research & Development Foundation Limited HYDROGELS WITH EMULSION MATRIX DOUBLELY RETICULATED BY REVERSIBLE METAL COORDINATION
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US20190206691A1 (en) * 2018-01-04 2019-07-04 Applied Materials, Inc. High-k gate insulator for a thin-film transistor
CN108597996A (zh) * 2018-06-08 2018-09-28 德淮半导体有限公司 半导体器件的形成方法
CN112713081A (zh) * 2019-10-24 2021-04-27 夏泰鑫半导体(青岛)有限公司 半导体元件及其制备方法
TWI777179B (zh) * 2020-06-20 2022-09-11 聯華電子股份有限公司 閘極介電層的製作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003006702A1 (fr) * 2001-07-09 2003-01-23 Nikko Materials Company, Limited Cible de siliciure d'hafnium servant a former un film d'oxyde de grille et son procede de production
EP1756328A2 (en) * 2004-06-15 2007-02-28 Aviza Technology, Inc. System and method for forming multi-component dielectric films
CN101447420A (zh) * 2007-11-28 2009-06-03 中国科学院微电子研究所 一种制备高介电常数栅介质薄膜铪硅氧氮的方法
CN101660128A (zh) * 2009-09-27 2010-03-03 南京大学 一种栅电介质材料立方相HfO2薄膜及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009093171A1 (en) * 2008-01-23 2009-07-30 Nxp B.V. Improved phase control in hf- or zr-based high-k oxides
TW201003915A (en) * 2008-07-09 2010-01-16 Nanya Technology Corp Transistor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003006702A1 (fr) * 2001-07-09 2003-01-23 Nikko Materials Company, Limited Cible de siliciure d'hafnium servant a former un film d'oxyde de grille et son procede de production
EP1756328A2 (en) * 2004-06-15 2007-02-28 Aviza Technology, Inc. System and method for forming multi-component dielectric films
CN101447420A (zh) * 2007-11-28 2009-06-03 中国科学院微电子研究所 一种制备高介电常数栅介质薄膜铪硅氧氮的方法
CN101660128A (zh) * 2009-09-27 2010-03-03 南京大学 一种栅电介质材料立方相HfO2薄膜及其制备方法

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