WO2012041179A1 - Igbt structure integrating anti-parallel diode and manufacturing method thereof - Google Patents

Igbt structure integrating anti-parallel diode and manufacturing method thereof Download PDF

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Publication number
WO2012041179A1
WO2012041179A1 PCT/CN2011/079974 CN2011079974W WO2012041179A1 WO 2012041179 A1 WO2012041179 A1 WO 2012041179A1 CN 2011079974 W CN2011079974 W CN 2011079974W WO 2012041179 A1 WO2012041179 A1 WO 2012041179A1
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WIPO (PCT)
Prior art keywords
region
type
collector
doping
insulated layer
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PCT/CN2011/079974
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French (fr)
Inventor
Shida Wen
Xiuguang Xiao
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Byd Company Limited
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Publication of WO2012041179A1 publication Critical patent/WO2012041179A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors

Definitions

  • the present disclosure relates to a semiconductor device, and more particularly, to an IGBT (Insulated Gate Bipolar Junction Transistor) structure integrating an anti-parallel diode and a manufacturing method thereof.
  • IGBT Insulated Gate Bipolar Junction Transistor
  • the IGBT is rarely used independently. Especially under a condition of inductive load, the IGBT needs a fast recovery diode to freewheel. As shown in Fig.l, most IGBT products have an anti-parallel diode for the freewheeling functions to protect the IGBT.
  • a conventional IGBT with a built-in diode comprises: a collector terminal 210; a P type collector region 208 formed on a part of a first surface of the collector terminal; a N type collector region 209 formed on another part of the first surface of the collector terminal; a N- type drift region 207 formed on the P type collector region 208 and the N type collector region 209; a first P type well region 2061 formed on a part of the N- type drift region 207; a second P type well region 2062 formed on another part of the N- type drift region 207; a first N type active region 2051 formed in the first P type well region 2061; a second N type active region 2052 formed in the second P type region 2062; a first insulated layer 204 formed on the N- type drift region 207, the first P type well region 2061, the second P type well region 2062, the first N type active region 2051 and the second N type active region 2052; a gate terminal 203 formed on the first insulated
  • a snapback appears in an output characteristic curve of the conventional IGBT.
  • the diode in the IGBT does not turn on and the amount of the holes injected from the P type collector region to the N- type drift region is small so that the N type collector region and the N- type drift region show an impedance characteristic and the output characteristic curve shows a MOS characteristic; if the voltage is increased large enough to turn on the diode, the hole injecting efficiency greatly increases and the resistivity of the N- type drift region decreases because of the conductivity modulation effect generated in the N- type drift region.
  • a turning point (point A shown in Fig.3) appears in a voltage drop between the collector terminal and the emitter terminal despite that a current increases.
  • the voltage drop between the collector terminal and the emitter terminal decreases to a certain value so that a voltage drop between the P type collector region and the N- type drift region is not sufficient to maintain the diode on, with the increase of the current, the voltage drop between the collector terminal and the emitter terminal starts to increase again (point B shown in Fig.3).
  • the snapback phenomenon which usually appears several times before the IGBT reaches a stable output, may delay the output characteristic.
  • the IGBT comprises: an insulated groove 411, a collector terminal 410, a P type collector region 408, a N type collector region 409, a N- type drift region 407, a first P type well region 4061, a second P type well region 4062, a first N type active region 4051, a second N type active region 4052, a first insulated layer 404, a gate terminal 402, an emitter terminal 401.
  • the insulated groove 411 is formed between the P type collector region 408 and the N type collector region 409 and extends into an internal part of the N- type drift region.
  • the IGBT mentioned above depends on a complicated manufacturing technology which is hard to realize.
  • the present invention is directed to solve at least one of the problems existing in the prior art. Accordingly, an IGBT structure integrating an anti-parallel diode and a manufacturing method thereof are provided.
  • an IGBT structure integrating an anti-parallel diode comprising: a collector terminal; a P type collector region formed on a first part of a first surface of the collector terminal; a N type collector region formed on a second part of the first surface of the collector terminal; a third region formed on a third part of the first surface of the collector terminal and between the P type collector region and the N type collector region; a N- type drift region formed on the P type collector region, the N type collector region and the third region; a first P type well region formed in a first part of the N- type drift region; a second P type well region formed in a second part of the N- type drift region; a first N type active region formed in the first P type well region; a second N type active region formed in the second P type well region; a first insulated layer formed on the N- type drift region with two ends overlapped with a part of the first N type active region and a part of the second N type active region respectively; a
  • a method for manufacturing an IGBT structure integrating an anti-parallel diode comprising steps of: forming a first insulated layer on a top surface of a N- type drift region; forming a gate terminal on a part of the first insulated layer; etching the first insulated layer to form a first well region and a second well region; doping a P type impurity to the first well region to form a first P type region and to the second well region to form a second P type well region; doping a N type impurity to a part of the first well region to form a first N type active region and to a part of the second well region to form a second N type active region; growing a second insulated layer on the gate terminal, the first P type well region, the second P type well region, the first N type active region and the second N type active region; etching the second insulated layer to expose a part of the first P type well region, a part of the second P type well region
  • the present invention provides an IGBT structure comprising a third region between the N type collector region and the P type collector region.
  • the third region maintains an impedance characteristic of the N type collector region and the N- type drift region.
  • Fig. 1 is a circuit diagram of a conventional IGBT integrating an anti-parallel diode
  • Fig. 2 is a cross sectional view of the conventional IGBT integrating an anti-parallel diode
  • Fig. 3 is an output characteristic curve of the conventional IGBT integrating an anti-parallel diode
  • Fig. 4 is a cross sectional view of a conventional IGBT integrating an anti-parallel diode
  • Fig. 5 is a schematic diagram showing a comparison between output characteristic curves of the IGBT integrating an anti-parallel diode in an ideal state, in the prior art and according to one embodiment of the present invention
  • Fig. 6 is a cross sectional view of an IGBT integrating an anti-parallel diode according to a first embodiment of the present invention
  • Fig. 7 is a cross sectional view of an IGBT integrating an anti-parallel diode according to a second embodiment of the present invention.
  • Fig. 8 is a cross sectional view of an IGBT integrating an anti-parallel diode according to a third embodiment of the present invention.
  • Fig. 9 is a flow chart of a method for manufacturing an IGBT structure integrating an anti-parallel diode.
  • the IGBT structure integrating an anti-parallel diode comprises: a collector terminal 610; a P type collector region 608 formed on a first part of a first surface of the collector terminal 610; a N type collector region 609 formed on a second part of the first surface of the collector terminal 610; a third region 611 formed on a third part of the first surface of the collector terminal 610 and between the P type collector region 608 and the N type collector region 609; a N- type drift region 607 formed on the P type collector region 608, the N type collector region 609 and the third region 611; a first P type well region 6061 formed in a first part of the N- type drift region 607; a second P type well region 6062 formed in a second part of the N- type drift region 607; a first N type active region 6051 formed in the first P type well region 6061; a second N type active region 6052 formed in the second P type well region 6062;
  • the gate terminal and the emitter terminal are separated by the second insulated layer.
  • the first P type well region 6061 and the second P type well region 6062 are separated by the N- type drift region 607.
  • the third region 611 is a P- type third region, and a doping concentration of the P- type third region 611 is less than that of the P type collector region 608.
  • the third region 611 formed between the N type collector region 609 and the P type collector region 608 lowers a concentration of holes which are injected from the P type collector region 608 to the N type collector region 609 and the N- type drift region 607, and maintains an impedance characteristic of the N type collector region 609 and the N- type drift region 607.
  • the diode formed by the P type collector region 608 and the N- type drift region 607 keeps on so as not to affect a state voltage drop of the IGBT, and the snapback in an output characteristic curve may be avoided.
  • curve c is the output characteristic curve of the IGBT in the prior art
  • curve b is the output characteristic curve of the IGBT according one embodiment of the present invention
  • curve a is an ideal output characteristic curve of the IGBT.
  • the IGBT structure integrating an anti-parallel diode comprises: a collector terminal 710, a P type collector region 708, a N type collector region 709, a third region 711, a N- type drift region 707, a first P type well region 7061, a second P type well region 7062, a first N type active region 7051, a second N type active region 7052, a first insulated layer 704, a gate terminal 703, a second insulated layer 702, and an emitter terminal 701.
  • the structure of the IGBT is the same as the structure shown in Fig. 6. except that in this embodiment, the third region 711 is a N+ type third region, and the doping concentration of the N+ type third region 711 is larger than that of the N type collector region 709.
  • IGBT structure integrating an anti-parallel diode comprises: a collector terminal 810, a P type collector region 808, a N type collector region 809, a third region, a N- type drift region 807, a first P type well region 8061, a second P type well region 8062, a first N type active region 8051, a second N type active region 8052, a first insulated layer 804, a gate terminal 803, a second insulated layer 802, and an emitter terminal 801.
  • the structure of the IGBT is the same as the structure shown in Fig.
  • the third region is consisted of a P- type third region 811 and a N+ type third region 812, and the doping concentration of the P- type third region 811 is less than that of the P type collector region 808 and the doping concentration of the N+ type third region 812 is larger than that of the N type collector region 809.
  • the P- type third region 811 is adjacent to the
  • the N+ type third region 812 is adjacent to the P- type third region 811 and the N type collector region 809 is adjacent to the N+ type third region 812.
  • Fig. 9 is a flow chart of a method for manufacturing an IGBT structure integrating an anti-parallel diode according to some embodiments of the present invention. The method comprises the following steps.
  • Step S101 forming a first insulated layer on a top surface of a N- type drift region.
  • Step SI 02 forming a gate terminal on a part of the first insulated layer.
  • Step SI 03 etching the first insulated layer to form a first well region and a second well region.
  • Step SI 04 doping a P type impurity to the first well region to form a first P type region and to the second well region to form a second P type well region.
  • Step SI 05 doping a N type impurity to a part of the first well region to form a first N type active region and to a part of the second well region to form a second N type active region.
  • Step SI 06 forming a second insulated layer on the gate terminal, the first P type well region, the second P type well region, the first N type active region and the second N type active region.
  • Step SI 07 etching the second insulated layer to expose a part of the first P type well region, a part of the second P type well region, a part of the first N type active region and a part of the second N type active region.
  • Step S108 forming an emitter terminal on the second insulated layer, the first P type well region, the second P type well region, the first N type active region and the second N type active region.
  • Step SI 09 doping a N type impurity to a first part of a bottom surface of the N- type drift region to form a N type collector region.
  • Step S110 masking the N type collector region and dope a semiconductor impurity to a second part of the bottom surface of the N- type drift region to form a third region.
  • Step Sill masking the N type collector region and the third region and dope a P type impurity to the bottom surface of the N- type drift region to form a P type collector region.
  • Step SI 12 forming a collector terminal on the N type collector region, the third region and the P type collector region.
  • the first P type well region and the second P type well region are separated by the N- type drift region; the gate terminal and the emitter terminal are separated by the second insulated layer.
  • the collector terminal and the emitter terminal are formed of metal.
  • the gate terminal is formed of polysilicon.
  • doping a third impurity to a second part of the bottom surface of the N- type drift region to form a third region comprises: doping a P type third impurity to the second part of the bottom surface of the N- type drift region to form a P- type third region.
  • a doping concentration of the P- type third region is less than that of the P type collector region.
  • doping a third impurity to a second part of the bottom surface of the N- type drift region to form a third region comprises: doping a N type third impurity to the second part of the bottom surface of the N- type drift region to form a N+ type third region.
  • a doping concentration of the N+ type third region is larger than that of the N type collector region.
  • doping a third impurity to a second part of the bottom surface of the N- type drift region to from a third region comprises: doping a N type third impurity to the second part of the bottom surface of the N- type drift region to form a n+ type third region; and masking the N type collector region, the N+ type third region and doping a P type third impurity to the third part of the bottom surface of the N- type drift region to form a P- type third region.
  • a doping concentration of the P- type third region is less than that of the P type collector region and a doping concentration of the N+ type third region is larger than that of the N type collector region.
  • the P- type third region is adjacent to the P type collector region, the N+ type third region is adjacent to the P- type third region and the N type collector region is adjacent to the N+ type third region.

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Abstract

An IGBT structure integrating an anti-parallel diode and the method thereof are provided. The structure comprises: a collector terminal (610); a P type collector region (608) and an N type collector region (609) formed on separated parts of the collector terminal (610); a third region (611) formed between the P type collector region (608) and the N type collector region (609); an N- type drift region (607) formed on the P type collector region (608), the N type collector region (609) and the third region (611); two P type well regions(6061,6062) with two N type active regions (6051,6052) respectively formed in separated parts of the N- type drift region (607); a first insulated layer (604) covering the N- type drift region (607); a gate terminal (603) formed on the first insulated layer (604); a second insulated layer (602) covering the gate terminal (603); and an emitter terminal (601).

Description

IGBT STRUCTURE INTEGRATING ANTI-PARALLEL DIODE AND
MANUFACTURING METHOD THEREOF
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to, and benefits of Chinese Patent Application Serial No. 201010506011.9, filed with the State Intellectual Property Office of P. R. C. on September 30, 2010, the entire contents of which are incorporated herein by reference.
FIELD
The present disclosure relates to a semiconductor device, and more particularly, to an IGBT (Insulated Gate Bipolar Junction Transistor) structure integrating an anti-parallel diode and a manufacturing method thereof.
BACKGROUND
Combining advantages of a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and a power transistor, an IGBT with high frequency, simple control circuit, high current density and low state voltage drop is widely applied in power fields such as frequency conversion, inversion, etc.
The IGBT is rarely used independently. Especially under a condition of inductive load, the IGBT needs a fast recovery diode to freewheel. As shown in Fig.l, most IGBT products have an anti-parallel diode for the freewheeling functions to protect the IGBT.
Referring to Fig.2, a conventional IGBT with a built-in diode comprises: a collector terminal 210; a P type collector region 208 formed on a part of a first surface of the collector terminal; a N type collector region 209 formed on another part of the first surface of the collector terminal; a N- type drift region 207 formed on the P type collector region 208 and the N type collector region 209; a first P type well region 2061 formed on a part of the N- type drift region 207; a second P type well region 2062 formed on another part of the N- type drift region 207; a first N type active region 2051 formed in the first P type well region 2061; a second N type active region 2052 formed in the second P type region 2062; a first insulated layer 204 formed on the N- type drift region 207, the first P type well region 2061, the second P type well region 2062, the first N type active region 2051 and the second N type active region 2052; a gate terminal 203 formed on the first insulated layer 204; a second insulated layer 202 formed on the gate terminal 203; and an emitter terminal 201 formed on the first P type well region 2061, the second P type well region 2062, the first N type active region 2051, the second N type active region 2052 and the second insulated layer 202.
Referring to Fig.3, a snapback appears in an output characteristic curve of the conventional IGBT. When a gradually increased voltage is applied to the collector terminal, if the voltage is small, the diode in the IGBT does not turn on and the amount of the holes injected from the P type collector region to the N- type drift region is small so that the N type collector region and the N- type drift region show an impedance characteristic and the output characteristic curve shows a MOS characteristic; if the voltage is increased large enough to turn on the diode, the hole injecting efficiency greatly increases and the resistivity of the N- type drift region decreases because of the conductivity modulation effect generated in the N- type drift region. Thus a turning point (point A shown in Fig.3) appears in a voltage drop between the collector terminal and the emitter terminal despite that a current increases. When the voltage drop between the collector terminal and the emitter terminal decreases to a certain value so that a voltage drop between the P type collector region and the N- type drift region is not sufficient to maintain the diode on, with the increase of the current, the voltage drop between the collector terminal and the emitter terminal starts to increase again (point B shown in Fig.3). The snapback phenomenon, which usually appears several times before the IGBT reaches a stable output, may delay the output characteristic.
To avoid the snapback, an IGBT integrating an anti-parallel diode is provided. Referring to Fig.4, the IGBT comprises: an insulated groove 411, a collector terminal 410, a P type collector region 408, a N type collector region 409, a N- type drift region 407, a first P type well region 4061, a second P type well region 4062, a first N type active region 4051, a second N type active region 4052, a first insulated layer 404, a gate terminal 402, an emitter terminal 401. A difference from Fig.2 is that the insulated groove 411 is formed between the P type collector region 408 and the N type collector region 409 and extends into an internal part of the N- type drift region. However, the IGBT mentioned above depends on a complicated manufacturing technology which is hard to realize. SUMMARY
The present invention is directed to solve at least one of the problems existing in the prior art. Accordingly, an IGBT structure integrating an anti-parallel diode and a manufacturing method thereof are provided.
According to an aspect of the present invention, an IGBT structure integrating an anti-parallel diode is provided, comprising: a collector terminal; a P type collector region formed on a first part of a first surface of the collector terminal; a N type collector region formed on a second part of the first surface of the collector terminal; a third region formed on a third part of the first surface of the collector terminal and between the P type collector region and the N type collector region; a N- type drift region formed on the P type collector region, the N type collector region and the third region; a first P type well region formed in a first part of the N- type drift region; a second P type well region formed in a second part of the N- type drift region; a first N type active region formed in the first P type well region; a second N type active region formed in the second P type well region; a first insulated layer formed on the N- type drift region with two ends overlapped with a part of the first N type active region and a part of the second N type active region respectively; a gate terminal formed on the first insulated layer; a second insulated layer formed on the gate terminal, a part of the first N type active region, a part of the second N type active region respectively; and an emitter terminal formed on the second insulated layer, a part of the first P type well region, a part of the first N type active region, and a part of the second P type well region and a part of the second N type active region respectively, wherein the gate terminal and the emitter terminal are separated by the second insulated layer.
According to another aspect of the present invention, a method for manufacturing an IGBT structure integrating an anti-parallel diode is provided, comprising steps of: forming a first insulated layer on a top surface of a N- type drift region; forming a gate terminal on a part of the first insulated layer; etching the first insulated layer to form a first well region and a second well region; doping a P type impurity to the first well region to form a first P type region and to the second well region to form a second P type well region; doping a N type impurity to a part of the first well region to form a first N type active region and to a part of the second well region to form a second N type active region; growing a second insulated layer on the gate terminal, the first P type well region, the second P type well region, the first N type active region and the second N type active region; etching the second insulated layer to expose a part of the first P type well region, a part of the second P type well region, a part of the first N type active region and a part of the second N type active region; forming an emitter terminal on the second insulated layer, the first P type well region, the second P type well region, the first N type active region and the second N type active region; doping a N type impurity to a first part of a bottom surface of the N- type drift region to form a N type collector region; masking the N type collector region and doping a semiconductor impurity to the second part of the bottom surface of the N- type drift region to form a third region; masking the N type collector region and the third region and doping a P type impurity to the bottom surface of the N- type drift region to form a P type collector region; and forming a collector terminal on the N type collector region, the third region and the P type collector region.
The present invention provides an IGBT structure comprising a third region between the N type collector region and the P type collector region. The third region maintains an impedance characteristic of the N type collector region and the N- type drift region. When a gradually increased voltage is applied to the collector terminal, the diode formed by the P type collector region and the N- type drift region keeps on so as not to affect a state voltage drop of the IGBT, and snapbacks in an output characteristic curve may be avoided.
Additional aspects and advantages of the embodiments of present invention will be given in part in the following descriptions, become apparent in part from the following descriptions, or be learned from the practice of the embodiments of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other features and advantages of the invention will be better understood from the following detailed descriptions taken in conjunction with the accompanying drawings, in which:
Fig. 1 is a circuit diagram of a conventional IGBT integrating an anti-parallel diode; Fig. 2 is a cross sectional view of the conventional IGBT integrating an anti-parallel diode; Fig. 3 is an output characteristic curve of the conventional IGBT integrating an anti-parallel diode;
Fig. 4 is a cross sectional view of a conventional IGBT integrating an anti-parallel diode;
Fig. 5 is a schematic diagram showing a comparison between output characteristic curves of the IGBT integrating an anti-parallel diode in an ideal state, in the prior art and according to one embodiment of the present invention;
Fig. 6 is a cross sectional view of an IGBT integrating an anti-parallel diode according to a first embodiment of the present invention;
Fig. 7is a cross sectional view of an IGBT integrating an anti-parallel diode according to a second embodiment of the present invention;
Fig. 8 is a cross sectional view of an IGBT integrating an anti-parallel diode according to a third embodiment of the present invention; and
Fig. 9 is a flow chart of a method for manufacturing an IGBT structure integrating an anti-parallel diode.
DETAILED DESCRIPTION OF THE EMBODIMENTS
Reference will be made in detail to embodiments of the present disclosure. The embodiments described herein with reference to drawings are explanatory, illustrative, and used to generally understand the present disclosure. The embodiments shall not be construed to limit the present disclosure.
Referring to Fig.6, according to an embodiment of the present invention, the IGBT structure integrating an anti-parallel diode, comprises: a collector terminal 610; a P type collector region 608 formed on a first part of a first surface of the collector terminal 610; a N type collector region 609 formed on a second part of the first surface of the collector terminal 610; a third region 611 formed on a third part of the first surface of the collector terminal 610 and between the P type collector region 608 and the N type collector region 609; a N- type drift region 607 formed on the P type collector region 608, the N type collector region 609 and the third region 611; a first P type well region 6061 formed in a first part of the N- type drift region 607; a second P type well region 6062 formed in a second part of the N- type drift region 607; a first N type active region 6051 formed in the first P type well region 6061; a second N type active region 6052 formed in the second P type well region 6062; a first insulated layer 604 formed on the N- type drift region 607 with two ends overlapped with a part of the first N type active region 6051 and a part of the second N type active region 6052 respectively; a gate terminal 603 formed on the first insulated layer 604; a second insulated layer 602 formed on the gate terminal 603, a part of the first N type active region 6051, a part of the second N type active region 6052 respectively; and an emitter terminal 601 formed on the second insulated layer 602, a part of the first P type well region 6061, a part of the first N type active region 6051, a part of the second P type well region 6062 and a part of the second N type active region 6052 respectively. The gate terminal and the emitter terminal are separated by the second insulated layer. The first P type well region 6061 and the second P type well region 6062 are separated by the N- type drift region 607. In this embodiment, the third region 611 is a P- type third region, and a doping concentration of the P- type third region 611 is less than that of the P type collector region 608.
In the above embodiment, the third region 611 formed between the N type collector region 609 and the P type collector region 608 lowers a concentration of holes which are injected from the P type collector region 608 to the N type collector region 609 and the N- type drift region 607, and maintains an impedance characteristic of the N type collector region 609 and the N- type drift region 607. When a gradually increased voltage is applied to the collector terminal 610, the diode formed by the P type collector region 608 and the N- type drift region 607 keeps on so as not to affect a state voltage drop of the IGBT, and the snapback in an output characteristic curve may be avoided. Referring to Fig.5, curve c is the output characteristic curve of the IGBT in the prior art, curve b is the output characteristic curve of the IGBT according one embodiment of the present invention, and curve a is an ideal output characteristic curve of the IGBT.
Referring to Fig.7, according to an embodiment of the present invention, the IGBT structure integrating an anti-parallel diode comprises: a collector terminal 710, a P type collector region 708, a N type collector region 709, a third region 711, a N- type drift region 707, a first P type well region 7061, a second P type well region 7062, a first N type active region 7051, a second N type active region 7052, a first insulated layer 704, a gate terminal 703, a second insulated layer 702, and an emitter terminal 701. The structure of the IGBT is the same as the structure shown in Fig. 6. except that in this embodiment, the third region 711 is a N+ type third region, and the doping concentration of the N+ type third region 711 is larger than that of the N type collector region 709.
Referring to Fig.8, according to a third embodiment of the present invention, the
IGBT structure integrating an anti-parallel diode comprises: a collector terminal 810, a P type collector region 808, a N type collector region 809, a third region, a N- type drift region 807, a first P type well region 8061, a second P type well region 8062, a first N type active region 8051, a second N type active region 8052, a first insulated layer 804, a gate terminal 803, a second insulated layer 802, and an emitter terminal 801. The structure of the IGBT is the same as the structure shown in Fig. 6 except that in this embodiment, the third region is consisted of a P- type third region 811 and a N+ type third region 812, and the doping concentration of the P- type third region 811 is less than that of the P type collector region 808 and the doping concentration of the N+ type third region 812 is larger than that of the N type collector region 809. The P- type third region 811 is adjacent to the
P type collector region 808, the N+ type third region 812 is adjacent to the P- type third region 811 and the N type collector region 809 is adjacent to the N+ type third region 812.
Fig. 9 is a flow chart of a method for manufacturing an IGBT structure integrating an anti-parallel diode according to some embodiments of the present invention. The method comprises the following steps.
Step S101, forming a first insulated layer on a top surface of a N- type drift region.
Step SI 02, forming a gate terminal on a part of the first insulated layer.
Step SI 03, etching the first insulated layer to form a first well region and a second well region.
Step SI 04, doping a P type impurity to the first well region to form a first P type region and to the second well region to form a second P type well region.
Step SI 05, doping a N type impurity to a part of the first well region to form a first N type active region and to a part of the second well region to form a second N type active region.
Step SI 06, forming a second insulated layer on the gate terminal, the first P type well region, the second P type well region, the first N type active region and the second N type active region.
Step SI 07, etching the second insulated layer to expose a part of the first P type well region, a part of the second P type well region, a part of the first N type active region and a part of the second N type active region.
Step S108, forming an emitter terminal on the second insulated layer, the first P type well region, the second P type well region, the first N type active region and the second N type active region.
Step SI 09, doping a N type impurity to a first part of a bottom surface of the N- type drift region to form a N type collector region.
Step S110, masking the N type collector region and dope a semiconductor impurity to a second part of the bottom surface of the N- type drift region to form a third region.
Step Sill, masking the N type collector region and the third region and dope a P type impurity to the bottom surface of the N- type drift region to form a P type collector region.
Step SI 12, forming a collector terminal on the N type collector region, the third region and the P type collector region.
In some embodiment of the present invention, the first P type well region and the second P type well region are separated by the N- type drift region; the gate terminal and the emitter terminal are separated by the second insulated layer. In one embodiment of the present invention, the collector terminal and the emitter terminal are formed of metal. In one embodiment of the present invention, the gate terminal is formed of polysilicon.
In one embodiment of the present invention, doping a third impurity to a second part of the bottom surface of the N- type drift region to form a third region comprises: doping a P type third impurity to the second part of the bottom surface of the N- type drift region to form a P- type third region. A doping concentration of the P- type third region is less than that of the P type collector region.
In one embodiment of the present invention, doping a third impurity to a second part of the bottom surface of the N- type drift region to form a third region comprises: doping a N type third impurity to the second part of the bottom surface of the N- type drift region to form a N+ type third region. A doping concentration of the N+ type third region is larger than that of the N type collector region.
In one embodiment of the present invention, doping a third impurity to a second part of the bottom surface of the N- type drift region to from a third region comprises: doping a N type third impurity to the second part of the bottom surface of the N- type drift region to form a n+ type third region; and masking the N type collector region, the N+ type third region and doping a P type third impurity to the third part of the bottom surface of the N- type drift region to form a P- type third region. A doping concentration of the P- type third region is less than that of the P type collector region and a doping concentration of the N+ type third region is larger than that of the N type collector region. The P- type third region is adjacent to the P type collector region, the N+ type third region is adjacent to the P- type third region and the N type collector region is adjacent to the N+ type third region.
Although explanatory embodiments have been shown and described, it would be appreciated by those skilled in the art that changes, alternatives, and modifications can be made in the embodiments without departing from spirit and principles of the invention. Such changes, alternatives, and modifications all fall into the scope of the claims and their equivalents.

Claims

WHAT IS CLAIMED IS:
1. An IGBT structure integrating an anti-parallel diode, comprising:
a collector terminal;
a P type collector region formed on a first part of a first surface of the collector terminal;
a N type collector region formed on a second part of the first surface of the collector terminal;
a third region formed on a third part of the first surface of the collector terminal and between the P type collector region and the N type collector region;
a N- type drift region formed on the P type collector region, the N type collector region and the third region;
a first P type well region formed in a first part of the N- type drift region;
a second P type well region formed in a second part of the N- type drift region;
a first N type active region formed in the first P type well region;
a second N type active region formed in the second P type well region;
a first insulated layer formed on the N- type drift region with two ends overlapped with a part of the first N type active region and a part of the second N type active region respectively;
a gate terminal formed on the first insulated layer;
a second insulated layer formed on the gate terminal, a part of the first N type active region and a part of the second N type active region respectively; and
an emitter terminal formed on the second insulated layer, a part of the first P type well region, a part of the first N type active region, a part of the second P type well region and a part of the second N type active region respectively, wherein the gate terminal and the emitter terminal are separated by the second insulated layer.
2. The IGBT structure according to claim 1, wherein the third region is a P- type third region, and a doping concentration of the P- type third region is less than that of the P type collector region.
3. The IGBT structure according to claim 1, wherein the third region is a N+ type third region, and a doping concentration of the N+ type third region is larger than that of the N type collector region.
4. The IGBT structure according to claim 1, wherein the third region comprises a P- type third region and a N+ type third region, and a doping concentration of the P- type third region is less than that of the P type collector region and a doping concentration of the N+ type third region is larger than that of the N type collector region.
5. The IGBT structure according to claim 4, wherein the P- type third region is adjacent to the P type collector region, the N+ type third region is adjacent to the P- type third region and the N type collector region is adjacent to the N+ type third region.
6. The IGBT structure according to claim 1, wherein the first P type well region and the second P type well region are separated by the N- type drift region.
7. A method for manufacturing an IGBT structure integrating an anti-parallel diode, comprising steps of:
forming a first insulated layer on a top surface of a N- type drift region;
forming a gate terminal on a part of the first insulated layer;
etching the first insulated layer to form a first well region and a second well region; doping a P type impurity to the first well region to form a first P type region and to the second well region to form a second P type well region respectively;
doping a N type impurity to a part of the first well region to form a first N type active region and to a part of the second well region to form a second N type active region respectively;
forming a second insulated layer on the gate terminal, the first P type well region, the second P type well region, the first N type active region and the second N type active region;
etching the second insulated layer to expose a part of the first P type well region, a part of the second P type well region, a part of the first N type active region and a part of the second N type active region; forming an emitter terminal on the second insulated layer, the first P type well region, the second P type well region, the first N type active region and the second N type active region;
doping a N type impurity to a first part of a bottom surface of the N- type drift region to form a N type collector region;
masking the N type collector region and doping a third impurity to a second part of the bottom surface of the N- type drift region to form a third region;
masking the N type collector region and the third region and doping a P type impurity to a third part of the bottom surface of the N- type drift region to form a P type collector region; and
forming a collector terminal on the N type collector region, the third region and the P type collector region.
8. The method according to claim 7, wherein the step of doping a third impurity to a second part of the bottom surface of the N- type drift region to form a third region comprises:
doping a P type third impurity to the second part of the bottom surface of the N- type drift region to form a P- type third region.
9. The method according to claim 7, wherein doping a third impurity to a second part of the bottom surface of the N- type drift region to form a third region comprises:
doping a N type third impurity to the second part of the bottom surface of the N- type drift region to form a N+ type third region.
10. The method according to claim 7, wherein doping a third impurity to a second part of the bottom surface of the N- type drift region to from a third region comprises: doping a N type third impurity to the second part of the bottom surface of the N- type drift region to form a N+ type third region; and
masking the N type collector region, the N+ type third region and doping a P type third impurity to the third part of the bottom surface of the N- type drift region to form a P- type third region.
PCT/CN2011/079974 2010-09-30 2011-09-21 Igbt structure integrating anti-parallel diode and manufacturing method thereof WO2012041179A1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103377919A (en) * 2012-04-27 2013-10-30 无锡维赛半导体有限公司 Insulated gate bipolar transistor and manufacturing method thereof
CN103377920A (en) * 2012-04-27 2013-10-30 无锡维赛半导体有限公司 Insulated gate bipolar transistor and manufacturing method thereof
US9960250B2 (en) 2012-04-24 2018-05-01 Semiconductor Components Industries Llc Power device and method of manufacturing the same
US10707321B2 (en) 2012-04-24 2020-07-07 Semiconductor Components Industries, Llc Power device with multiple field stop layers

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10181513B2 (en) 2012-04-24 2019-01-15 Semiconductor Components Industries, Llc Power device configured to reduce electromagnetic interference (EMI) noise
DE102014009384A1 (en) * 2013-06-27 2014-12-31 Fairchild Korea Semiconductor Ltd. Power device and method for producing selbiger
CN105206656A (en) * 2015-08-25 2015-12-30 电子科技大学 Reverse conducting IGBT device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5178370A (en) * 1991-08-05 1993-01-12 Motorola Inc. Conductivity modulated insulated gate semiconductor device
US5729031A (en) * 1996-01-16 1998-03-17 Mitsubishi Denki Kabushiki Kaisha High breakdown voltage semiconductor device
CN1201378C (en) * 2000-05-05 2005-05-11 国际整流器公司 Hydrogenimplant for buffer of punch-through non EPI IGBT
US20070080407A1 (en) * 2005-10-06 2007-04-12 Sanken Electric Co., Ltd. Insulated gate bipolar transistor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0430476A (en) * 1990-05-25 1992-02-03 Fuji Electric Co Ltd Insulated gate bipolar transistor
JPH05152574A (en) * 1991-11-29 1993-06-18 Fuji Electric Co Ltd Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5178370A (en) * 1991-08-05 1993-01-12 Motorola Inc. Conductivity modulated insulated gate semiconductor device
US5729031A (en) * 1996-01-16 1998-03-17 Mitsubishi Denki Kabushiki Kaisha High breakdown voltage semiconductor device
CN1201378C (en) * 2000-05-05 2005-05-11 国际整流器公司 Hydrogenimplant for buffer of punch-through non EPI IGBT
US20070080407A1 (en) * 2005-10-06 2007-04-12 Sanken Electric Co., Ltd. Insulated gate bipolar transistor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9960250B2 (en) 2012-04-24 2018-05-01 Semiconductor Components Industries Llc Power device and method of manufacturing the same
US10707321B2 (en) 2012-04-24 2020-07-07 Semiconductor Components Industries, Llc Power device with multiple field stop layers
CN103377919A (en) * 2012-04-27 2013-10-30 无锡维赛半导体有限公司 Insulated gate bipolar transistor and manufacturing method thereof
CN103377920A (en) * 2012-04-27 2013-10-30 无锡维赛半导体有限公司 Insulated gate bipolar transistor and manufacturing method thereof

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