WO2012033664A2

WO2012033664A2 - Methods and circuits for precise termination

Info

Publication number: WO2012033664A2
Application number: PCT/US2011/049586
Authority: WO
Inventors: Kambiz Kaviani; Amir Amirkhany; Aliazam Abbasfar
Original assignee: Rambus Inc.
Priority date: 2010-09-10
Filing date: 2011-08-29
Publication date: 2012-03-15
Also published as: WO2012033664A4; WO2012033664A3

Abstract

Described are integrated signal interfaces that include receive amplifiers and termination elements. Termination control circuitry calibrates the impedances through the termination elements to take into account the transconductance of the receive amplifiers. Transconductance bias circuitry can be used to bias the receive amplifiers, and the bias can be derived from a reference voltage. The interfaces can derive the common-mode voltage from received signals as the reference voltage, rather than from a dedicated voltage reference.

Description

METHODS AND CIRCUITS FOR PRECISE TERMINATION

Kambiz Kaviani

Amir Amirkhany

Aliazam Abbasfar

TECHNICAL FIELD

[0001] The subject matter presented herein relates generally to high-speed electronic signaling within and between integrated-circuit devices, and more particularly to method and circuits for terminating signal channels.

BACKGROUND

[0001] Computer systems typically include integrated-circuit devices (ICs) that communicate over signal channels, which may include one or more transmission lines.

Transmission lines exhibit some "impedance" to the flow of electrical current, and discontinuities in this impedance can create signal reflections that interfere with transmitted signals, and consequently degrade the performance of the signal channel. Components known as "terminators" or "termination elements" are commonly coupled to signal channels to reduce impedance discontinuities, and thus allow for improved communication speed and reliability.

[0002] Termination elements can be integrated with the transmitting or receiving ICs.

It is difficult to create precise resistances on integrated circuits, however, so ICs that include integrated termination elements often include some form of control circuitry to calibrate the termination elements. These solutions work well in many applications. High-speed circuits are in a very competitive market, however, and must achieve ever greater performance levels to satisfy customer demand.

BRIEF DESCRIPTION OF THE FIGURES

[0003] Figure 1 details a portion of an integrated circuit (IC) 100 in accordance with one embodiment.

[0004] Figure 2 depicts an IC 200 in accordance with another embodiment. IC 200 is in some ways like IC 100 of Figure 1, with like-identified elements being the same or similar.

[0005] Figure 3 depicts a receive interface 300 in accordance with an embodiment that supports pairs of differential signals or coded differential signals. DETAILED DESCRIPTION

[0006] Figure 1 details a portion of an integrated circuit (IC) 100 in accordance with one embodiment. IC 100 includes a number of differential signal interfaces 105, each of which includes a pair of input nodes InN and InP that can be AC or DC coupled to a respective differential communication channel (not shown) to receive a differential input signal. An amplifier 107 amplifies the differential signal to produce a level-shifted differential output signal OutP/OutN.

[0007] Input nodes InN and InP are terminated to a common-mode voltage VCM via respective termination elements 110, each of which is adjustable over a range of termination impedances responsive to a control signal Rtrm<3:0>. IC 100 additionally includes termination control circuitry 115 and a replica termination element 120 that together determine the value of control signal Rtrm<3:0>. Replica termination element 120 includes two impedance replicas, a termination replica 125 that replicates the impedance through each termination element 110 and a receiver replica 130 that replicates the input impedance of amplifier 107. The inclusion of replicas for both the termination elements and the receiver produces a better impedance match at the inputs to amplifier 107, and consequently reduces signal reflections and attendant performance reductions.

[0008] Each interface 105 may be a receiver input stage that supports near-ground differential signaling, in which case amplifier 107 level shifts the incoming signal InN/InP using a differential pair of transistors 135. The control terminals of transistors 135 are coupled to a bias voltage Vbias, and each transistor includes a first current-handling terminal coupled to a supply node VDD via a respective load resistor RL and a second current- handling terminal coupled to a second supply node (ground) via a source resistor Rs.

Transistors 135 are NMOS transistors in a common-gate configuration in this example, but may be other types of transistors and configurations in other embodiments.

[0009] In the common-gate configuration, the impedance at each input of amplifier

107 is the parallel combination of resistance Rs and the transresistance Rm of one of transistors 135, where transresistance Rm is the ratio of the voltage change across transistor 135 relative to the change in current there through. The impedances at nodes InN and InP are therefore functions of termination resistance Rterm, resistance Rs, and transresistance Rm, all of which can vary with process, voltage, and temperature (PVT).

[0010] Replica termination element 120 includes termination replica 125 to replicate termination resistance Rterm, and includes replica receiver 130 to replicate the effects of resistance Rs and transresistance Rm on the termination impedance at nodes InN and InP. In operation, control circuit 115 drives equivalent calibration currents (not shown) through termination element 120 and an external reference resistor Rext, and then compares the voltages developed across them. Control circuit 115 adjusts control signal Rtrm<3:0> until the voltages dropped across replica termination element 120 and external resistor Rext are equal or nearly so, which indicates that the resistance through replica termination element 120 matches that of the external resistor.

[0011] Termination elements 110 are fabricated to be the same as replica 125, so control signal Rtrm<3:0> will set the impedance through each termination element 110 equal to the impedance through replica 125. The combined impedances of replicas 125 and 130 are set equal to the value of external resistor Rext. In this embodiment, replica receiver 130 is connected in parallel with termination replica 125, so the impedance through replica 125 will be greater than the value of external resistor Rext. The value of external resistor Rext need not be equal to the impedance through termination element 120; in other embodiments, control circuit 115 can maintain some other proportion between the two. Resistors can take many forms, and may be suitably biased transistors. Either or both of replica termination element 120 and control circuit 115 may be part of or associated with one or more other circuits, such as transmit interfaces, that rely on the same or different termination elements as well as transmit replicas.

[0012] Figure 2 depicts an IC 200 in accordance with another embodiment. IC 200 is in some ways like IC 100 of Figure 1, with like-identified elements being the same or similar. The signal interface circuitry of IC 200 differs from that of IC 100 in that a transconductance (g_m) bias circuit 205 is included to develop bias voltage Vbias for differential transistors 135 of amplifier 107. Transconductance bias circuit 205 sets the transresistance (l/g_m) of transistors 135 to a known function of resistor Rg through a feedback mechanism.

[0013] The transconductance g_m of a transistor is the ratio of the current change at the output node to the voltage change at the input node. Bias circuit 205 develops bias voltage Vbias to set the transconductance g_m of a transistor 210 at a value of oc/Rg, where a is a fixed design parameter of the feedback circuit and Rg is the resistance of a like-designated resistor in bias circuit 205. Transistors 135 in amplifier 107 are identical to transistor 210, and so respond to the same bias voltage Vbias by exhibiting the same transconductance g_m.

[0014] Transresistance R_m is the reciprocal of transconductance (R_m=l/gm=Rg/ot). As with the example of Figure 1 , the impedances at nodes InN and InP are functions of termination resistance Rterm, resistance Rs, and transresistance Rm. IC 200 includes a replica termination element 220 that includes a termination replica 125 to replicate termination resistance Rterm, as in the example of Figure 1, and a replica receiver 230 to replicate the effects of resistance Rs and transresistance R_m on the termination impedances at nodes InN and InP. In this embodiment replica receiver 230 is depicted as parallel resistors, either or both of which can be implemented using one or more transistors with an appropriately controlled bias voltage or voltages. While only one amplifier 107 is shown, multiple amplifiers can be included and can share bias and termination control signals.

[0015] Amplifier 107 is a differential amplifier, and receives a differential input signal on nodes InP and InN. The common-mode voltage VCM need not be provided by a reference- voltage source, but can instead be derived from the incoming signal. In such embodiments both bias circuit 205 and amplifier 107 automatically adapt to changes in the common-mode voltage of the input signal. Voltage VCM can be provided by a reference within or external to IC 200 in other embodiments that can also include single-ended signaling with the reference as the mid-point of the input signal excursion.

[0016] As in the prior example, control circuit 115 adjusts control signal Rtrm<3:0> until the voltages dropped across replica termination element 220 and external resistor Rext are equal or nearly so, which indicates that the resistance through replica termination element 220 matches that of the external resistor. The control signal Rtrm<3:0> used to obtain this equivalence is then distributed to the termination elements associated with one or more signal interfaces, the impedances of which are thus fixed in proportion to the value of external resistor Rext irrespective of process variations, voltage changes, and temperature

fluctuations.

[0017] Figure 3 depicts a receive interface 300 in accordance with an embodiment that supports pairs of differential signals or coded differential signals. IC 300 is in some ways like ICs 100 and 200 of respective Figures 1 and 2, with like-identified elements being the same or similar. Interface 300 includes four input nodes InA, InB, InC, and InD, each of which is connected to a common-mode-voltage node VCM via a respective termination element 305. The input nodes are additionally coupled to respective inputs of an amplifier 310, which additionally includes four output nodes OutA, OutB, OutC, and OutD. Control circuitry and impedance replicas are omitted from this figure, but can be implemented as detailed previously.

[0018] A waveform diagram 350 illustrates an example in which the input signals are balanced, and can thus be summed to produce a relatively constant common-mode voltage VCM. The horizontal axis, Time, is divided into unit intervals, each of which represent a time slot during which each of the four signals expresses a symbol as either a relatively high or a relatively low voltage. The sum of the signaling levels is the same during each unit interval, and

[0019] Various coding schemes can be used to present data on input nodes InA, InB,

InC, and InD. So long as these are balanced, common-mode voltage VCM will remain relatively constant without connection to a reference. The common-mode voltage VCM in interface 300 can therefore be derived from the incoming signal, rather than from some voltage reference. Deriving the common-mode voltage from the incoming signal or signals eliminates the requirement of a separate reference and allows bias circuit 205 and amplifier 310 to automatically adapt to changes in the input signal. In one embodiment voltage VCM is approximately zero volts, and each signal is less than one volt peak-to-peak.

[0020] While the present invention has been described in connection with specific embodiments, variations of these embodiments are also contemplated. Still other variations will be obvious to those of ordinary skill in the art. Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection, or "coupling," establishes some desired electrical communication. Such coupling may often be accomplished in many ways using various types of intermediate components and circuits, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. For U.S. applications, only those claims specifically reciting "means for" or "step for" should be construed in the manner required under the sixth paragraph of 35 U.S.C. Section 112.

Claims

CLAIMS What is claimed is:

1. An integrated circuit comprising:

an input node to receive an input signal;

an adjustable termination element coupled to the input node and having a termination control port, wherein the adjustable termination element is adjustable over a range of termination impedances;

a replica termination element having a replica control port, wherein the replica termination element is adjustable over a range of replica impedances; and

a termination control circuit coupled to the termination control port to select a termination impedance within the range of termination impedances and to the replica control port to select a replica impedance different from the termination impedance and within the range of replica impedances.

2. The integrated circuit of claim 1 , wherein the replica impedance is less than the

termination impedance.

3. The integrated circuit of claim 1, further comprising a receiver coupled to the input node and having a receiver input impedance, wherein the replica termination element includes a termination replica of the termination impedance and a receiver replica of the receiver input impedance.

4. The integrated circuit of claim 1 , wherein the receiver includes a first transistor having a first current-handling terminal coupled to the input node and a first control terminal coupled to a bias voltage, and the receiver replica includes a second transistor having a second control terminal coupled to the termination replica and a second control terminal coupled to the bias voltage.

5. The integrated circuit of claim 1, further comprising a second input node to receive a second input signal complementary to the first-mentioned input signal and a second adjustable termination element connected to the second input node and having a second termination control port coupled to the termination control circuit.

6. The integrated circuit of claim 1 , further comprising a transistor and a transistor-bias circuit, the transistor having a current-handling terminal coupled to the input node and a control terminal coupled to the transistor-bias circuit to receive a bias voltage.

7. The integrated circuit of claim 1, further comprising a receiver having a receiver input coupled to the input node and a bias node to receive a bias voltage, the receiver including a resistor coupled between the receiver input and a DC node and a transistor having a current-handling terminal coupled to the receiver input and a control terminal coupled to the bias node.

8. The integrated circuit of claim 7, wherein the transistor exhibits a transresistance and the resistor a resistance at the input node.

9. The integrated circuit of claim 8, wherein the replica impedance is of a value equal to a parallel combination of the transresistance, the resistance, and the termination impedance.

10. The integrated circuit of claim 9, further comprising a transconductance bias circuit coupled to the bias node to produce the bias voltage.

11. The integrated circuit of claim 10, wherein the transconductance bias circuit includes a second transistor having a second control terminal and a second current-handling terminal coupled to the bias node.

12. The integrated circuit of claim 11, wherein the second transistor is a replica of the first- mentioned transistor.

13. A method for calibrating a termination element coupled to an input of an amplifier, wherein the termination element exhibits a termination resistance and the amplifier exhibits a transresistance, the method comprising:

replicating the termination resistance and the transresistance;

adjusting at the replicated termination resistance; and

calibrating the termination resistance responsive to the replicated termination resistance.

14. The method of claim 13, wherein adjusting the replicated termination resistance

comprises comparing the replicated termination resistance and the transresistance with a reference resistance.

15. The method of claim 14, wherein the termination element and amplifier are instantiated on an integrated circuit, and the reference resistance is exhibited by a reference resistor external to the integrated circuit.

16. The method of claim 13, further comprising calibrating at least one additional

termination resistance responsive to the replicated termination resistance.

17. The method of claim 13, further comprising biasing the amplifier to adjust the

transresistance based on an adjustable resistance

18. The method of claim 17, wherein the replicated termination impedance comprises the adjustable resistance in parallel with the replicated termination resistance.

19. A receiver comprising:

first, second, and third input nodes to receive respective first, second, and third input signals that express series of symbols using alternative voltages, wherein the sum of the input signals a common-mode voltage; and

first, second, and third termination elements disposed between a common node and the respective first, second, and third input nodes, the common node held at the common-mode voltage by the input signals.

20. The receiver of claim 19, further comprising a bias circuit coupled to the common node to receive the common-mode voltage, the bias circuit to derive a bias voltage from the common-mode voltage.

21. The receiver of claim 20, further comprising an amplifier having a bias node coupled to the bias circuit to receive the bias voltage, and having first, second, and third amplifier node to receive the first, second, and third input signals.

22. The receiver of claim 20, wherein the bias circuit is a transconductance bias circuit.

23. A method of providing a bias voltage for an amplifier, the method comprising:

summing at least two input signals to derive a common-mode voltage; deriving the bias voltage from the common-mode voltage; and

conveying the bias voltage to the amplifier.

24. The method of claim 23, wherein summing the input signals comprising conveying the input signals to a common node via respective termination elements.

25. The method of claim 23, wherein deriving the bias voltage from the common- mode voltage comprising conveying the common-mode voltage to and the bias voltage from a transconductance bias circuit.

The method of claim 23, wherein the amplifier comprises a transistor, for each of the input signals, having a control terminal to receive the bias voltage and a current- handling terminal to receive the respective input signal.