WO2012022927A1 - Capteur d'image - Google Patents

Capteur d'image Download PDF

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Publication number
WO2012022927A1
WO2012022927A1 PCT/GB2011/001166 GB2011001166W WO2012022927A1 WO 2012022927 A1 WO2012022927 A1 WO 2012022927A1 GB 2011001166 W GB2011001166 W GB 2011001166W WO 2012022927 A1 WO2012022927 A1 WO 2012022927A1
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WO
WIPO (PCT)
Prior art keywords
reset
sensor
configurable
control
pixel elements
Prior art date
Application number
PCT/GB2011/001166
Other languages
English (en)
Inventor
Thalis Anaxagoras
Grigore Moldovan
Angus Ian Kirkland
Original Assignee
Isis Innovation Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Isis Innovation Limited filed Critical Isis Innovation Limited
Publication of WO2012022927A1 publication Critical patent/WO2012022927A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/571—Control of the dynamic range involving a non-linear response
    • H04N25/575—Control of the dynamic range involving a non-linear response with a response composed of multiple slopes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/53—Control of the integration time
    • H04N25/533—Control of the integration time by using differing integration times for different sensor regions
    • H04N25/535—Control of the integration time by using differing integration times for different sensor regions by dynamic region selection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/58—Control of the dynamic range involving two or more exposures
    • H04N25/581—Control of the dynamic range involving two or more exposures acquired simultaneously
    • H04N25/583—Control of the dynamic range involving two or more exposures acquired simultaneously with different integration times
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/766—Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present invention relates to an image sensor.
  • Image sensors may be used to detect electromagnetic (EM) radiation of a wide range of energies and to detect particles, for example electrons, of a range of energies.
  • Typical image sensors may comprise an array of sensor devices formed in a sheet of semiconductor material, for example using CMOS (complimentary metal oxide semiconductor) technology.
  • the image sensor further comprises a sensor circuit comprising pixel elements in respect of the sensor device, which pixel elements comprise semiconductor device formed in the semiconductor material.
  • the sensor circuit may be configured to operate under the control of control lines connected to each pixel element to provide signals on readout lines representative of the charge accumulated by each sensor device.
  • Such image sensors are designed to provide desired sensor response characteristics, such as frame rate, gain and reset voltage, that are suitable for the EM radiation and/or particles being detected. Often, this involves some compromise to provide adequate detective quantum efficiency for the EM radiation and/or particles of a range of energies that might be detected in practice in a desired use. The design is therefore related to the intended application.
  • a known techniques that allows an image sensor to sense images with a high dynamic range is to use a variable integration time.
  • such techniques effectively involve discarding signal during exposure in some regions of the image, which again reduce the detective quantum efficiency.
  • an image sensor comprising: an array of sensor devices formed in a sheet of semiconductor material; and a sensor circuit comprising:
  • each sensor device comprising semiconductor devices formed in the semiconductor material and connected to the sensor device
  • the sensor circuit being configured to provide signals representative of the charge accumulated by each sensor device on the readout lines
  • the pixel elements are configurable to provide sensor response characteristics that are different in different regions of the array of sensor devices.
  • the present invention provides the image sensor with a sensor circuit having an architecture in which the pixel elements are configurable across at least part or the entirety of the array of sensor devices.
  • the configurable pixel elements comprise semiconductor devices that are configurable to select a sensor response characteristic, such as sampling rate. It allows the sensor response characteristic to be configured to be different in different regions of the array sensor devices. Different regions of the image sensor may be configured to have sensor response characteristics appropriate to the image being detected in that region. This allows the image sensor to be adapted to more optimally sense images having a high degree of variation in intensity.
  • a region of the image sensor expected to receive EM radiation or particles of relatively high intensity may be configured to operate at a high frame rate whilst the remainder of the image sensor, for example the weak peripheral region of a diffraction study, may be configured to operate with a slow frame rate. That improves the detective quantum efficiency of the resultant image by increasing the SNR in the regions of low intensity, without the region of high intensity becoming saturated. This permits the full capture of images with localised regions of high brightness and provides the potential to acquire images with a more uniform quality specification.
  • This architecture has the advantage over a variable integration time image sensor that no light is discarded during exposure.
  • the sensor circuit may further comprise configuration control lines connected to each configurable pixel element, for example a passive matrix of sampling control lines and column select control lines connected to rows and columns of sensor devices in said array.
  • the respective configurable pixel elements are configured to provide a sensor response characteristic in accordance with configuration control signals on the configuration control lines connected thereto, for example by comprising an AND gate having inputs connected to the sampling control line and the column select control line, the respective configurable pixel elements being configured to provide a sensor response characteristics in accordance with the output of the AND gate.
  • the configurable pixel elements may comprise respective memory cells arranged to store data representing the configuration of the pixel element, and the configurable pixel elements being configured in accordance with the stored data.
  • a memory cell within the configurable pixel elements, it is possible to store the data representing the configuration of those individual pixel elements. It allows the data up-sending the configuration to the stored in those memory cells in advance of the operation (image capturing). This means it is straightforward to make the different regions any shape without restriction to rectangular shapes. This is very advantageous, particularly where the image is likely to have a non-rectangular region requiring different sensor response characteristics. This is the case, for example, in diffraction studies where the central region of high brightness is often circular or elongate.
  • the sensor circuit may comprise configuration control lines arranged to control the data stored in the memory cells, for example data control lines and a passive matrix of sampling control lines and column select control lines connected to the pixel elements of rows and columns of sensor devices in said array.
  • the respective memory cells are arranged to store the data present on the data line connected thereto when a predetermined control signal is present on the sampling control line and the column select control line connected thereto.
  • one sensor response characteristic that may be configured is the frame rate.
  • the sensor response characteristic that may be configured is an electrical characteristic.
  • One such electrical characteristic is the gain of the sensor device.
  • This may be configured by the configurable pixel elements comprising a gain circuit capable of changing the gain of the sensor device, for example a capacitor.
  • the respective configurable pixel elements are arranged to selectively connect the gain circuit to the sensor device, for example using a gain switching arrangement.
  • reset voltage is another such electrical characteristic.
  • This may be configured by the sensor circuit comprising plural sources of reset voltage connected to each pixel element.
  • the configurable pixel elements are configurable to selectively supply a reset voltage from one of the sources to the sensor device on reset, for example using a reset source switching arrangement.
  • diode Another such electrical characteristic is diode.
  • the dominating noise source in a 3T pixel is the kTC noise (sampling noise), which can be reduced by using a smaller diode capacitance. This will allow setting the pixel array such that the bright regions may use the big diode (since these are dominated by shot noise) and the dark regions may use the small diode (since these are dominated by the kTC noise).
  • Particular advantage is achieved by providing the pixel elements with configurable electrical characteristics as an alternative or addition to other sensor response characteristics such as the frame rate. This allows the pixel element to be configured in other respects than the frame rate.
  • Fig. 1 is a diagram of an image sensor showing a pixel element in a sensor circuit
  • Fig. 2 is a timing diagram of control signals applied to the sensor circuit
  • Figs. 3 to 9 are diagrams of modified pixel elements
  • Fig. 10 is a block diagram of an IC chip that incorporates the image sensor
  • Fig. 1 1 is a diagram of a further modified pixel element; and Fig. 12 is a diagram of a modification to the pixel element.
  • the image sensor 1 comprises an array of sensor devices 10 formed in a layer 2 of semiconductor material. Associated with each sensor device 10 is a pixel element 1 1 of a sensor circuit 20 that comprises semiconductor devices 12-14 that are formed in the same, or different, layer 2 of semiconductor material and are connected to the sensor device 10. For clarity, Fig. 1 illustrates only a single sensor device 10 and its associated pixel element 1 1, but in fact an array of sensor device 10 are formed, arranged in a regular array of rows and columns.
  • the sensor device 10 is arranged to accumulate a sensing charge when the EM radiation or particles of interest are incident thereon.
  • the sensor device 10 may have any suitable construction for this.
  • the sensor device 10 is a diode.
  • the sensor device 10 may have a simple PIN diode construction. More complicated constructions, such as an avalanche construction, are equally possible.
  • the sensor device 10 and the pixel element 1 1 may be formed using any suitable technology for example CMOS technology so that the sensor device 10 and the semiconductor devices 12-14 are CMOS devices.
  • the array of sensor devices 10 is typically regular so that the pixel elements 1 1 have a regular pitch, but in some embodiments the array of sensor devices 10 is irregular so that the pixel elements 1 1 have a variable pitch.
  • the semiconductor material may typically be silicon, although other semiconductor materials can alternatively be used.
  • the layer of semiconductor material 2 is rigid, but equally it may be flexible.
  • the layer 2 of the semiconductor material may be formed on a substrate that is an insulator. After fabrication, the substrate may be thinned to improve detective quantum efficiency and device for reliability, particularly where the image sensor 1 is to be used for direct detection of charged particles such as electrons. Further, the image sensor 1 may equally be arranged as an indirect sensor of particles such as electrons.
  • the control circuit 20 further comprises reset control lines 21, sampling control lines 22 and readout lines 23.
  • the reset control lines 21 and sampling control lines 22 are operational control lines that are provided in respect of each row of sensor device 10, connected to the pixel elements 1 1 of each sensor device 10 in the respective row.
  • readout lines 23 are provided in respect of each column of sensor devices 10, connected to the pixel elements 1 1 of each sensor device 10 in the respective column.
  • the rows are shown as being horizontal and the columns are shown as being vertical, but the rows and columns could equally be transposed.
  • the pixel element 1 1 is arranged as follows to provide signals on the respective readout lines 23 representative of the charge accumulated by the sensor device 10.
  • the pixel element 1 1 includes the reset device 12 that operates as a reset switching arrangement to selectively apply the reset voltage from a reset voltage source 24 that is connected to each pixel element 1 1.
  • the input (gate) of the reset switching device 12 is connected to the respective reset control line 21 of the sensor circuit 20 to control its switching.
  • the reset switching device 12 closes to apply the reset voltage to the sensor device 10 resets it at the desired reverse bias voltage. Thereafter, the sensor device 10 accumulates charge when EM radiation or particles are incident thereon. This causes the output voltage PD of the sensor device 10 to decrease.
  • the pixel element 1 1 further comprises a buffer device 13 whose input (gate) is connected to the sensor device 10 to detect the output voltage PD.
  • the buffer device 13 acts as a source follower together with a load device 25 of the sensor circuit 20 that is described further below.
  • the drain of the buffer device 13 is connected to a supply voltage VDD whereas the output (source) of the buffer device 13 is connected to the respective readout line 23 for buffering the output voltage PD on the readout line 23.
  • This connection to the respective readout line 23 is through a select device 14.
  • the input (gate) of the select device is connected to the respective sampling control line 22. When a sampling control signal is applied to the sampling control line 22, the sampling device 14 is closed to allow the output of the buffer device 13 to buffer the output voltage PD of the sensor device 10 on the readout line 23.
  • the sensor circuit 20 further comprises the following components associated with each of the readout lines 23.
  • the load device 25 mentioned above is connected to the readout line 23.
  • the input (gate) of the load device 25 is supplied with a bias voltage Vbias to operate as a load to enable the buffer device 13 to operate as a source follower.
  • Vbias bias voltage
  • the readout voltage Vr that appears on the readout line 23 is the output voltage PD of the sensor device 10 in the row of the array in which a sampling control signal is being applied on the sampling control line 22.
  • the control circuit 20 further comprises a sample-hold circuit 26 comprising a capacitor 27 and a sampling switch 28 connected between the capacitor 27 and the readout line 23.
  • the sampling switch 28 is controlled by a sampling signal Vs to sample the readout voltage Vr and hold it on the capacitor 27.
  • a reset control signal Reset is applied to the reset control line 21.
  • a sampling control signal Select is applied to the sampling control line 22 to readout the voltage of each sensor device 10 in the row onto the readout line 23 of the corresponding column.
  • a sensor sampling signal Sample is applied to the sample-hold circuit 27 to hold the readout voltage Vr on the capacitor 27.
  • All the pixel elements 1 1 may be made configurable across the entirety of the array of sensor devices 10, or alternatively the pixel elements 1 1 may be made configurable across only part of the array of sensor devices 10 to provide a smaller area within which the sensor response characteristics may be configured.
  • the modified forms of the pixel elements 1 1 share several components that are the same as shown in Fig. 1. For brevity, such common components are given the same reference numerals and a description thereof will not be repeated.
  • Fig. 3 shows the sensor circuit 20 being modified so that the configurable pixel elements 11 are configured to operate at two sampling rates.
  • the control circuit 20 is modified to replace the reset control line 21 by two reset control lines 3 la and 31b and to replace the sampling control line 22 by two sampling control lines 32a and 32b.
  • Each of the reset control lines 31a and 3 lb with a corresponding one of the sampling control lines 32a and 32b forms a set for supplying operational control signals for controlling the operation of the sensor device 10 at two different frame rates, which will be referred to using the labels S and F for slow and fast.
  • the reset control line 31a supplies a slow reset control signal Reset_S and the sampling control signal supplies a slow sampling control signal Row_Sel_S.
  • the reset control line 3 lb supplies a fast reset control signal Reset F and the sampling control line 32b supplies a fast sampling control signal Row Sel F.
  • the fast and slow operational control signals are simultaneously applied to the reset control lines 3 la and 31b and the sampling control lines 32a and 32b.
  • the configurable pixel elements 1 1 are arranged to be configurable to operate under the control of either one of sets of operational control lines, as follows.
  • the sensor circuit 20 further comprises a passive matrix of row select control lines 34 connected to the pixel elements 1 1 of each respective row of sensor devices 10 and column select control lines 35 connected to the pixel elements 1 1 of each respective column of sensor devices 10.
  • the row select control lines 34 and column select control lines 35 are used to address the pixel elements that are configured to operate at the fast frame rate.
  • Each configurable pixel element 1 1 comprises an AND gate 36 formed by an arrangement of devices 37.
  • the AND gate 36 has two inputs that are connected respectively to the sampling control line 34 connected to that pixel element 1 1 and to the column select control line 35 connected to that pixel element 1 1.
  • the AND gate 36 produces an output consisting of two output signals AND and NAND.
  • the pixel element 1 1 is configured to operate in accordance with the output signals AND and NAND as follows.
  • the sensor device 10, the reset device 12 and the buffer device 13 are arranged in the same manner as Fig. 1. However, in place of the reset control line 21 being connected directly to the input of the reset device 12, the reset control lines 31a and 31b are connected in parallel to the input of the reset device 12 through a reset control switching arrangement 38 that is configured to connect one of the reset control lines 3 la and 3 lb selectively to the input of the reset device 12, in accordance with the output signals AND and NAND of the AND gate 36.
  • the switching arrangement 38 comprises, in respect of each of the reset control lines 31a and 3 lb: a first complementary pair of devices 39 and a second
  • the reset control lines 3 la and 3 lb are connected to the inputs (gates) of the respective first complementary pair of devices 39.
  • the output signals AND and NAND of the AND gate 36 are connected to the inputs (gates) of the second complementary pair of devices 40, but with inverted polarity as between the two reset control lines 31a and 31b.
  • the state of the outputs AND and NAND of the AND gate 36 controls which one of the reset signals Reset S and Reset F on the reset control lines 3 la and 3 lb are applied to the input of the reset device 12.
  • the reset device 12 when the pixel element 1 1 is addressed by both the configuration control signal Config_F_r on the row select control line 34 and the configuration control signal Config F c on the column select control line 35 being high, then the reset device 12 is configured to operate under the control of the fast reset control signal Reset F on the control line 3 lb. Otherwise the reset device 12 is configured to operate under the control of the slow reset control signal Reset s on the reset control line 31a.
  • the sensor circuit 20 further comprises two readout lines 41a and 41b in respect of each column of sensor devices 10.
  • the readout lines 41a and 41b are each connected to each pixel element 1 1 in the respective column.
  • the purpose of the two readout lines 41a and 41b is to receive respective readout voltages Vr_S and Vr_F when the pixel element 1 1 is configured to operate at the two frame rates.
  • the sampling device 14 is replaced by two sampling devices 42a and 42b which are connected in parallel to the buffer device 13 and are each connected to a respective one of the readout lines 41a and 41b.
  • the inputs to the sampling devices 43a and 43b are respectively connected to the sampling control lines 32a and 32b to act as a sampling switching arrangement that switches under the control of the sampling control signals Row_Sel_S and Row_Sel_F.
  • the pixel element 1 1 further comprises sampling devices 43a and 43b arranged in series with the sampling devices 42a and 42b between the buffer device 13 and the respective readout lines 41a and 41b.
  • the sampling devices 43a and 43b operate as a switching arrangement for selectively isolating the sampling devices 42a and 42b from the buffer device 13.
  • the sampling device 43a and 43b can equally be swapped with the sampling devices 42a and 42b for selectively isolating the sampling devices 42a and 42b from the readout lines 41a and 41b.
  • the inputs to the sampling devices 43a and 43b are connected to the output signals NAND and AND of the AND gate 36 so that only one of the sampling devices 42a and 42b is operated under the control of the respective sampling signal
  • Row Sel S or Row Sel F of the frame rate for which the pixel element is configured corresponding to the reset control signal Reset S or Reset F used to reset the reset device 12.
  • the pixel element 1 1 shown in Fig. 3 is modified to make it configurable to operate at two different frame rates under the control of the configuration control signals Config_F_r and Config F c appearing on the configuration control lines 34 and 35.
  • pixel element 1 1 may be modified in other ways to produce a similar effect.
  • Figs 4 to 6 illustrate configurable pixel elements 1 1 that are much simpler than the pixel element 1 1 shown in Fig. 3, in particular being modified by requiring a much smaller number of additional devices within the pixel element 1 1.
  • the configurable pixel elements shown in Figs. 4 to 6 are simpler in the following respects.
  • the column select control line 35 is supplied with a configuration control signal Config_F_c that indicates whether a pixel element 11 is to be operated at the fast frame rate.
  • the configuration control signal Config_F_c is changed in synchronisation with the scanning of each row of sensor devices 10.
  • the configuration control signal Config_F_c is changed to indicate the configuration of the pixel in that row.
  • the arrangement for reset switching of the pixel elements 1 1 is simplified as follows.
  • the reset control switching arrangement 38 of the pixel element 1 1 of Fig. 3 is not used at all. Instead, the reset device 12 shown in Fig. 1 is replaced by two reset devices 51a and 51b which each act as a reset switching arrangement in respect of one of the frame rates.
  • the inputs to the reset devices 51a and 51 b are respectively connected to the reset control lines 3 la and 31 b so that the reset devices 51 a and 51 b are respectively controlled to operate under the control of the slow reset control signal Reset S and the fast reset control signal Reset_F.
  • the reset devices 51a and 5 lb are connected in parallel between the reset voltage source 24 and the sensor device 10 in a similar manner to the reset device 12 of Fig. 1.
  • a reset control switch device 52 is connected in series with the reset device 51b.
  • the reset control switch device 52 operates as a reset control switching arrangement for selectively isolating the reset device 51b from the reset voltage source 24.
  • the reset control switch device 52 and the reset device 51b could be reversed so that the reset control switch device 52 selectively isolates the reset device 51b from the sensor device 10.
  • the input to the reset control switch device 52 is connected to the column select control line 35 so that its switching is controlled in accordance with the configuration control signal Config F c supplied thereon.
  • the resetting of the sensor device 10 in accordance with the fast reset control signal Reset F only occurs when the configuration control signal Config F c supplied on the column select control line 35 at the same time configures the pixel element 1 1 to operate at a fast frame rate.
  • a further reset control switch device 53 is provided in series with the reset device 5 la that is controlled in accordance with the slow reset control signal Reset_ S.
  • the input of the further reset control switch device 53 is connected to the further column select control line 50 that is supplied with supplied with a configuration control signal Config S c that indicates whether a pixel element 1 1 is to be operated at the slow frame rate.
  • the configuration control signal Config_S_c is changed in synchronisation with the scanning of each row of sensor devices 10.
  • the configuration control signal Config_S_c is changed to indicate the configuration of the pixel in that row.
  • the further reset control switch device 53 operates as a reset control switching arrangement for selectively isolating the reset device 51a from the reset voltage source 24.
  • the further reset control switch device 53 and the reset device 51a could be reversed so that the further reset control switch device 53 selectively isolates the reset device 51 b from the sensor device 10.
  • the input to the further reset control switch device 53 is controlled in accordance with the configuration control signal Config S c.
  • the resetting of the sensor device 10 in accordance with the slow reset control signal Reset s only occurs when the configuration control signal Config_S_c supplied on the further column select control line 50 at the same time configures the pixel element 1 1 to operate at a slow frame rate.
  • the configurable pixel element 1 1 of Fig. 4 also differs from the configurable pixel element of Fig. 3 in that it omits the sampling devices 43a and 43b that selectively isolate the output of the buffer device 13 from the readout lines 41a and 41 b in accordance with the frame rate at which the pixel element 1 1 is configured.
  • the configurable pixel elements 1 1 of Figs. 5 and 6 maintain the sampling device 43b in series with the sampling device 42b that receives the fast sampling signal Row Sel F.
  • the output voltage of the sensor device 10 is only transferred onto the readout line 41 b for the fast frame rate when the pixel element 1 1 is configured to operate at the fast frame rate.
  • the output voltage of the sensor device 10 is transferred onto the readout line 41a at the timing of the slow sampling control signal Row_Sel_S not only when the pixel element 1 1 is configured to operate at the slow frame rate but also when the pixel element 1 1 is configured to operate at the fast frame rate.
  • this is of low significance because of the relatively infrequent occurrence of sampling at the slow frame rate as compared to the fast frame rate.
  • the voltage swing on reset when the pixel element 1 1 is configured to operate at a fast frame rate is reduced due to the presence of two devices, namely the reset device 51b and the reset control switch device 52 in series between the reset voltage source 24 and the sensor device 10.
  • the reset control switch device 52 which is an NMOS device by a PMOS device and supplying reverse column reset control signal Config_F_c and a reverse reset signal Reset_F.
  • the alternative arrangements of the configurable pixel elements 1 1 shown in Figs. 4 to 6 have the advantage of including a much smaller number of devices than the configurable pixel element 1 1 of Fig. 3.
  • the changes to the reset switching control, in particular omitting the switching arrangement 38 results in the leakage current onto the sensor device 10 being increased.
  • Fig. 7 illustrates a further modified form of the configurable pixel circuit 1 1 which incorporates a memory cell 60 that is configurable to store data representing the configuration of the pixel element 1 1.
  • the configurable pixel element 11 of Fig. 7 is modified as compared to that of Fig. 3 as follows
  • each pixel element 1 1 of Fig. 3 the configuration of each pixel element 1 1 is controlled by the passive matrix of the row select control lines 34 and column select control lines 35.
  • the configuration control signals Config F r and Config F c are continuously applied to address the region configured to operate at a high frame rate, this arrangement means that it is only possible to provide different frame rates in regions that are rectangular. Although this is acceptable for some applications, there are other applications where it is preferable to have more flexible control over the regions where the frame rate differs. This is achieved in the configurable pixel element 1 1 of Fig. 7 by the use of the memory cell 60 that replaces the AND gate 36.
  • the memory cell 60 stores data in the form of two signals Mem and Mem_b that are the inverse of each other and represent the configuration of the pixel element 1 1.
  • the memory cell 60 comprises a first complimentary pair of devices 63 arranged as a NOT gate in series with a second complimentary pair of devices 64 also arranged as a NOT gate connected in series to the output of the first pair of complimentary devices 63.
  • the output of the first complimentary pair of devices 63 stores the signal Mem b and the output of the second complimentary devices 64 stores the signal Mem.
  • the signal Mem being high and the signal Mem_b being low indicates that the pixel element 1 1 is configured to operate at a fast frame rate whereas the signal Mem being low and the signal Mem b being high indicates that the pixel element 1 1 is configured to operate at the slow frame rate.
  • the signals Mem and Mem b representing the configuration are used to control the switching of the devices in the pixel element 1 1, instead of the output signals and AND and NAND of the AND gate 36 in the pixel element 1 1 of Fig. 3 as follows.
  • the reset device 12 shown in Fig. 1 is replaced by two reset devices 61a and 61b which each act as a reset switching arrangement in respect of one of the frame rates.
  • the inputs to the reset devices 61a and 61b are respectively connected to the reset control lines 3 la and 31b so that the reset devices 61a and 61b are respectively controlled to operate under the control of the slow reset control signal Reset S and the fast reset control signal Reset_F.
  • the reset devices 61a and 61b are connected in parallel between the reset voltage source 24 and the sensor device 10 in a similar manner to the reset device 12 of Fig. 1.
  • the reset control switching arrangement 38 of the pixel element 1 1 of Fig. 3 is not used at all.
  • a reset control switch devices 62a and 62b are respectively connected in series with the reset devices 61a and 61b.
  • the reset control switch devices 62a and 62b operates as a reset control switching arrangement for selectively isolating the reset devices 61a and 61b from the reset voltage source 24.
  • the reset control switch devices 62a and 62b and the reset devices 61a and 61b could be reversed so that the reset control switch devices 62a and 62b selectively isolate the reset devices 61a and 61b from the sensor device 10.
  • the inputs to the reset control switch devices 62a and 62b are connected respectively to the signals Mem b and Mem stored in the memory cell 60 so that their switching are controlled in accordance with the configuration represented thereby.
  • the resetting of the sensor device 10 in accordance with the fast reset control signal Reset_F and the slow reset control signal Reset_S occurs when the configuration stored in the memory cell 60 represents respectively the fast frame rate and the slow frame rate.
  • the signals Mem and Mem_b are used as inputs to the sampling devices 43a and 43b that control the transfer of the output voltage form the sensor device 10 to the readout lines 41a and 41b at the slow and fast sampling rates.
  • the configurable pixel 11 of Fig. 7 is further configured as follows to write data to the memory cell 60.
  • the sensor circuit 20 includes data line 65, row select control lines 66 and column select control lines 67, that all act as configuration control lines.
  • the data lines are each connected to the pixel elements 1 1 of a column of sensor devices 10.
  • the row select control lines 66 are connected to the pixel elements 1 1 of rows of sensor devices 10 and the column select control lines of 67 are connected to the pixel elements 1 1 of columns of sensor devices 10.
  • the row select control lines 66 and column select control lines 67 are used to address the memory cell 60 of the pixel elements 1 1.
  • the configurable memory cells 11 comprise an AND gate 68 formed by an arrangement of devices 69 and having its two inputs connected to the row select control lines 66 and the column select control line 67.
  • the AND gate 68 provides output signals AND and NAND that are high and low respectively when the control signals Config_r and Config c on the row select control line 66 and column select control line 67 are both high.
  • the configurable pixel element 1 1 further comprises a latch circuit 69 formed by a first pair of complimentary switch devices 70 and a second pair of complimentary switch devices 71.
  • the first pair of complimentary switch devices 70 are connected between the data line 65 and the input to the memory cell 60 and are controlled by the output signals AND and NAND of the AND gate 68.
  • the second pair of complimentary switch devices 71 are connected between the output of the memory cell 60 and the input to the memory cell 60 in a feedback arrangement.
  • the second complimentary pair of switch devices 71 are also controlled by the output signals AND and NAND of the AND gate 68, but in an inverse manner from the first complimentary pair of switch devices 70.
  • the first complimentary pair of switch devices 70 are closed which has the effect of transferring the data signal data on the data line 65 into the memory cell 60.
  • the second complimentary pair of switch devices 71 are open and thus have no effect.
  • the first complimentary pair of switch devices 70 are open and the second pair of complimentary switch devices 71 are closed so that the feedback provided thereby stores the data transferred from the data line 65 in the memory cell 60.
  • the data may be stored in the memory cells 60 of.the pixel elements 1 1 to individually set the configuration of each pixel element 1 1. Thereafter, the pixel element 1 1 remains configured operate on the basis of the configuration represented by that data.
  • the use of such a memory cell 60 offers greater advantage of providing complete flexibility regarding the regions that are configured to have a different sampling rate. Rectangular regions can be configured very quickly as the entire rectangular region can be simultaneously addressed by the control signals Config r and Config_c on both the row select control line 66 and the column select control line 67. Non-rectangular regions need to be set row-by-row by addressing successive rows using the control signals Config r on successive row select control lines 66.
  • the data representing the configuration may be stored in the memory cells 60 of the pixel elements 1 1 either during an initialisation phase prior to operation of the image sensor 10, or alternatively on-the-fly during operation.
  • the reset control switch devices 62a and 62b are connected in series with the reset devices 61a and 61b, the leakage current onto the sensor device 10 is increased as compared to the use of the switching arrangement 38 in the pixel element of Fig. 3. To combat this, it is preferable to increase the size of the sensor device 10 as compared to Fig. 3 in order to reduce the degree of charge injection.
  • the reset control switch devices 62a and 62b can be replaced by the reset switching arrangement 38 shown in Fig. 3 but with the inputs to the switching devices 40 connected to the output signals Mem and Mem b of the memory cell 60 instead of to the output signals AND and NAND of the AND gate 36.
  • the modified pixel elements shown in Figs. 3 to 7 as described above are configurable to provide different frame rates.
  • the pixel element 1 1 may additionally or alternatively be modified to be configurable to provide different sensor characteristics of types other than the frame rate, in particular electrical characteristics such as the gain of the sensor device 10 or the reset voltage used for resetting. Examples of modified pixel elements 1 1 that achieve this will now be described.
  • Fig. 8 illustrates a configurable pixel element 1 1 that has been modified to provide a configurable gain for the sensor device 10.
  • the pixel element 11 comprises a capacitor 80 that is of a suitable size for changing the gain of the sensor device 10 on connection thereto.
  • a gain switch device 81 is connected between the capacitor 80 and the sensor device 10. The gain switch device 81 may be switched to selectively connect the capacitor 80 and sensor device 10 together.
  • Each configurable pixel element 11 comprises an AND gate 36 formed by an arrangement of devices 37, in the same manner as the pixel element 1 1 of Fig. 3.
  • the AND gate 36 has two inputs that are connected respectively to the sampling control line 34 connected to that pixel element 1 1 and to the column select control line 35 connected to that pixel element 1 1.
  • the AND gate 36 produces an output consisting of two output signals AND and NAND.
  • the pixel element 1 1 is configured to operate in accordance with the output signal AND, by the input of the gain switch device 81 being connected to the output signal AND of the AND gate 36.
  • the state of the output signal AND of the AND gate 36 controls whether or not the capacitor 80 is connected to the sensor device 10.
  • the reset device 12 when the pixel element 1 1 is addressed by both the configuration control signal Config_F_r on the row select control line 34 and the configuration control signal Config F c on the column select control line 35 being high, then the reset device 12 is configured to operate under the control of the fast reset control signal Reset F on the control line 3 lb. Otherwise, the reset device 12 is configured to operate under the control of the slow reset control signal Reset_S on the reset control line 3 1a.
  • Fig. 9 illustrates a configurable pixel element 1 1 that has been modified to provide a configurable reset voltage for the sensor device 10.
  • the sensor circuit 20 comprises two reset voltage sources 85a and 85b that supply different reset voltages Vresetl and Vreset2.
  • the configurable pixel element 1 1 is modified by the reset device 12 being connected to each of the reset voltage sources 85a and 85b through respective reset voltage switch devices 86a and 86b that are switched inversely to selectively connect the reset device 12 to one of the reset voltage sources 85a and 85b.
  • Each configurable pixel element 1 1 comprises an AND gate 36 formed by an arrangement of devices 37, in the same manner as the pixel element 1 1 of Fig. 3.
  • the AND gate 36 has two inputs that are connected respectively to the sampling control line 34 connected to that pixel element 1 1 and to the column select control line 35 connected to that pixel element 1 1.
  • the AND gate 36 produces an output consisting of two output signals AND and NAND.
  • the pixel element 1 1 is configured to operate in accordance with the output signals AND and NAND, by the inputs of the reset voltage switch devices 86a and 86b being connected respectively to the output signals AND and NAND of the AND gate 36.
  • the reset device 12 When the output signal AND is low and the output signal NAND is high, the reset device 12 is connected to the reset voltage source 85a that supplies reset voltage Vresetl , whereas when the output signal AND is low and the output signal NAND is high, the reset device 12 is connected to the reset voltage source 85b that supplies reset voltage Vreset2. The reset device 12 then supplies the received reset voltage Vresetl or Vreset2 when it is switched under the control of the reset control signal Reset. This has the effect that the reset voltage is configured in accordance with the configuration control signals on the row select control line 34 and the column select control line 35.
  • the reset device 12 when the pixel element 1 1 is addressed by both the configuration control signal Config F r on the row select control line 34 and the configuration control signal Config F c on the column select control line 35 being high, then the reset device 12 is configured to supply the reset voltage Vresetl . Otherwise, the reset device 12 is configured to supply the reset voltage Vreset2.
  • each pixel element 1 1 of Figs. 9 and 10 the configuration of each pixel element 1 1 is controlled by the passive matrix of the row select control lines 34 and column select control lines 35.
  • the configuration control signals Config F r and Config_F_c are continuously applied to address the region configured to operate at a high frame rate, this arrangement means that it is only possible to provide different frame rates in regions that are rectangular. Although this is acceptable for some applications, there are other applications where it is preferable to have more flexible control over the regions where the frame rate differs. This may be achieved by modifying the configurable pixel element 1 1 to replace the AND gate 36 by a memory cell 60 in the same manner as disclosed above with reference to Fig. 7.
  • the image sensor 1 described above is implemented in an IC chip 100 that is shown in Fig. 10.
  • the image sensor 1 comprises the following components that are all implemented in the same IC chip 100 as the image sensor 1.
  • the image sensor 1 comprises row address decoders 101a and 101b used to address individual rows in the pixel array by generating the operational control signals that are supplied to the operational control lines connected to rows of pixel elements 1 1 , such as the reset control lines 31a and 31b and the sampling control lines 32a and 32b, which control the different phases of pixel operation.
  • the row address decoder 101a is connected to the operational control lines that operate at the slower frame rate, for example the reset control line 3 l a and the sampling control line 32a
  • the row address decoder 101 b is connected to the operational control lines that operate at the faster frame rate, for example the reset control line 3 lb and the sampling control line 32b.
  • a timing circuit 102 supplied with a clock signal from a clock circuit 103 generates row address signals that are supplied to each of the row address decoders 101a and 101b to specify the rows to be addressed at the appropriate timings.
  • the image sensor 1 also comprises a row memory 104 and a column memory 105 that are respectively connected to the configuration control lines that are connected to rows and column of pixel elements, for example the row select control lines 34 and column select control lines 35.
  • the row memory 104 and column memory 105 store the configuration control signals that specify which pixel elements 1 1 are configured to operate at the faster frame rate.
  • the row memory 104 and column memory 105 are used when the pixel element 1 1 is supplied with configuration control signals that remain constant for a given configuration, as is possible for example with the pixel element 1 1 of Fig. 1. However, when the pixel element 1 1 is supplied with configuration control signals that change, as for example with the pixel element 1 1 of Fig.
  • the row memory 104 and/or column memory 105 may be modified to include address decoders supplied with address signals from the timing circuit 102.
  • the image sensor 1 also comprises a sample-hold circuit blockl06, being an array of sample-hold circuits having the same construction as the sample-hold circuit 26 connected to respective ones of the readout lines such as readout line 23 or readout lines 41a and 41b.
  • the sample-hold circuit block 106 operate to sample rows of pixel elements 1 1 at the column level and then buffer the data from there sequentially to the outputs of the IC chip 100.
  • Differential amplifiers 107 are used to amplify and supply the output of the sample- hold circuit block 106, in a configuration that depends of the desired read out speed, under the control of column address decoders 108a and 108b in respect of the different frame rates.
  • Fig. 10 illustrates an example wherein there are four differential amplifiers 107 in respect of each frame rate so that sampling (addressing) of the output of four columns of pixel elements 1 1 is performed at a time, one on each of the four amplifiers.
  • the output signals are supplied from the IC chip 100 in a time-multiplexed manner.
  • Fig. 10 illustrates an example wherein there is only analog output from the IC chip 100, but alternatively digital outputmay be provided by including analog-to-digital converters on the IC chip 100.
  • the image sensor 1 can be used in a wide range of scientific applications to detect EM radiation of a wide range of energies and to detect particles, for example electrons, of a range of energies.
  • the design of the sensor devices 10 is chosen having regard to the application.
  • One image sensor 1 may be manufactured using a 0.18 ⁇ CMOS process to provide an array of 1024x1024 sensor devices 10 with a 20mm pixel pitch and operating in a rolling shutter mode.
  • Such an image sensor 1 may have applications for sensing soft x-rays (e.g. 8-20keV) or electrons (e.g. 5-60keV) and high-energy electrons (e.g. 120-400keV) and may be used in a front-illumination configuration for radiation that is absorbed deep inside the imager, or may be used in a back-illuminated configuration for radiation that is absorbed at the surface of the imager.
  • the pixel elements 11 are configured to have different sensor response characteristics, such as frame rate, gain and reset voltage, in different regions of the image, the sensor response characteristics being selected to optimise the response of the image sensor 1 in each region.
  • a region of the image sensor 1 expected to receive EM radiation or particles of relatively high intensity for example the central part of a diffraction study, may be configured to operate with appropriate sensor response characteristics such as a high frame rate, a low gain and a low reset voltage.
  • other regions of the image sensor 1 expected to receive EM radiation or particles of relatively low intensity for example the remainder of a diffraction study, may be configured to operate with appropriate sensor response characteristics such as a low frame rate, a high gain and a high reset voltage.
  • the difference in intensity between the brightest region and the peripheral region can be significant, thereby requiring
  • the slow frame rate is desirably in the range from 1Hz to lOHz and the fast frame rate is desirably greater than lOHz, typically at least 100Hz and up to around 1kHz or 10kHz, although the technology used to make the image sensor 1 and the size of the array of sensor devices 10 may place a limit on the frame rates achievable.
  • the above mentioned image sensor 1 manufactured using a 0.18 ⁇ CMOS process to provide an array of 1024x1024 sensor devices 10 might achieve a maximum frame rate of around 7.5kHz in a region of 50x50 pixels and a maximum frame rate of 30Hz in the remaining regions.
  • Fig. 12 illustrates a modification to the pixel element 1 1 of Fig. 3 to deal with an issue that there is a charge injection at the output (source) of the buffer device 13 caused by the sampling control signal of the opposite frame rate from which the pixel element 1 1 is configured.
  • the slow sampling control signal causes such charge injection and vice versa. This is due to the output (source) of the buffer device 13 being a floating node at which the circuit arrangement is causing a charge injection which is recovering very slowly and is affecting the diode voltage (signal).
  • the arrangement of Fig. 12 is to have a circuit that connects that floating node to the voltage supply VDD so that it is not floating any more.
  • This connection is through two switch devices 90 and 91 (which are PMOS devices, the other devices being NMOS devices) arranged in series, the first switch device 90 having its input (gate) connected to the sampling control line 32a to be switched by slow sampling control signal Row Sel S, and the second switch device 91 having its input (gate) connected to the output signal AND of the AND gate 36 so that it is switched in an inverse manner from the sampling device 43 a.
  • This protects the pixel element 1 1 when configured to operate at the slow frame rate from charge injection caused by switching of the sampling control device 42b in respect of the fast frame rate. This is because when the pixel element 1 1 is configured to operate at the fast frame rate, there is sufficient signal to ignore the effect of switching of the sampling control device 42a in respect of the slow frame rate.
  • Fig. 1 1 shows a pixel element 11 that is modified as compared to the pixel element of Fig. 4 to be configurable to operate at three frame rates. This is achieved by adding the following further devices in respect of an additional fast frame rate: a reset device 5 lc, a reset control switch device 54, a sampling device 43c in series with a sampling device 42b and a readout line 41c.
  • Another possible modification is to combine two or more image sensors 1 as shown in Fig. 10 in the same IC chip 100.
  • the combined image sensors 1 may effectively form one combined image sensor. For example four image sensors 1 having 2048 by 2048 pixels may be combined to form a combined image sensor having 4096 by 4096 pixels.
  • the image sensors 1 may be combined by being tiled adjacent one another or by interlacing the sensor devices 10 thereof.
  • the image data from the combined image sensors 1 can be combined together to provide image data of the combined image sensor.
  • each of the combined image sensors 1 has its own independent control as illustrated in Fig. 10 and described above.
  • each of the combined image sensors 1 is configurable to operate with different sensor response characteristics in two (or in general any number) of regions, so the combined image sensor is configurable to operate with different sensor response characteristics in a greater number of regions, for example in eight regions if four image sensors with two regions are combined. This forms a convenient method to multiply the number of available speeds, although there are restrictions on the geometry of the regions of interest if this is to be maintained.
  • region of interest i.e. the configuration is mirrored along the diagonals of the pixel arrays. Availability of these tiled imagers allows for selection of four unambiguous regions of interest, as long as only one region of interest is placed in any one of the image sensors 1.

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Abstract

L'invention porte sur un capteur d'image qui comprend un ensemble de dispositifs de capteur formé dans une feuille de matériau semi-conducteur et un circuit de capteur comprenant des éléments de pixel en ce qui concerne chaque dispositif de capteur, et des lignes de commande et des lignes de lecture connectées à chaque élément de pixel de l'ensemble, pour fournir des signaux représentatifs de la charge accumulée par chaque dispositif de capteur sur les lignes de lecture. Les éléments de pixel peuvent être configurés, comprenant des dispositifs à semi-conducteurs qui peuvent être configurés pour fournir des caractéristiques de réponse de capteur, telles qu'une fréquence d'image, un gain ou une tension de réinitialisation, qui sont différentes dans différentes régions de l'ensemble de dispositifs de capteur. Les éléments de pixel configurables peuvent comprendre des cellules de mémoire respectives conçues pour stocker des données représentant la configuration de l'élément de pixel, les éléments de pixel configurables étant configurés conformément aux données stockées.
PCT/GB2011/001166 2010-08-17 2011-08-03 Capteur d'image WO2012022927A1 (fr)

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US11809613B2 (en) 2018-11-12 2023-11-07 Magic Leap, Inc. Event-based camera with high-resolution frame output
US11889209B2 (en) 2019-02-07 2024-01-30 Magic Leap, Inc. Lightweight cross reality device with passive depth extraction
US11985440B2 (en) 2018-11-12 2024-05-14 Magic Leap, Inc. Depth based dynamic vision sensor
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