GB2441236A

GB2441236A - Pixel imager arrays and reading methods utilising automatic light control and pixels having three and four transistor characteristics

Info

Publication number: GB2441236A
Application number: GB0718400A
Authority: GB
Inventors: Moholt Jorgen
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2005-09-01
Filing date: 2005-09-01
Publication date: 2008-02-27
Anticipated expiration: 2025-09-01
Also published as: GB0718400D0; GB2441236A9; GB2441236B

Abstract

A pixel array comprises plural pixels in a row for providing image capture signals in which at least one pixel in the row provides an automatic light control signal; a first line resets the image capture pixels and a second reset line resets the automatic light control pixel. A similar arrangement is also independently claimed where the imaging pixels have transfer transistors between a photosensor and floating diffusion region that transfers charge at the end of an integration period; each auto light control pixel also has a photosensor coupled to a floating diffusion region during charge integration. An alternative imager control method performs automatic light control with pixels having three-transistor (3T) characteristics and imaging using correlated double sampling on plural four-transistor (4T) pixels; also independently claimed is a method of reading and resetting an imager array in which a percentage of the pixels have three-transistor characteristics. A further method simply comprises imaging with a first pixel set and performing automatic light control with signals from a second pixel set. Methods of forming at least some of these arrangements are also claimed.

Description

METHOD AND APPAPATUS PROVIDING PIXEL ARPAY HAVING

AUTOMATIC LIGHT CONTROL P1XELS AND IMAGE CAPTURE PIXELS

FIELD OP Th INVENTION

[0001] The invention relates generally to imaging devicei and more particularly to a pixel array providing automatic light control for accuratc exposure control in an imaging device.

BACKGROUND OF THE INVENTION

(0002] A CMOS imagcr circuit indudes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate. photoconductor or a photod.iodc overlying a substratc for accwnulating pboto-gcncratcd charge in the underlying portion of the substrate. Each pixcL cell has a readout circuit that indudes at least an output field efct transistor formed in the substrate and a charge storage region formed on the substrate connected to the gate of an output transstor. The charge storage region may bc constructed as a floating diffusion region.

[0003] In a CMOS irnager, the active elements cia pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumuLation of image charge; (3) transfer of accumulated charge to a storage region, typically operated as a floating diffusion region; (4) rcsctdng the storage region to a known state; (5) selection of a pixel for readout; and (6) output and amplification of a signal repres&iting pixel charge. The charge at the storage region is typically converted to a pixel output voltagc by the capacitance of the storage region and a source follower output transistor.

100041 CMOS imagers of the typc discussed above are generally known as discussed, for example, in U.S. Patent no. 6,140,630, U.S. Patent no. 6,376,868, tJ,S, Patent no. 6,310,366, U.S. Patent no. 6,326,652, U.S. Patent no. 6,204,524 and US.

* Patent no. 6,333,205, assigned to Micron Technology, Inc., which arc hereby incoiporated by reference in their entirety.

D5MD.9O5O83.l [0005] PIG. 1 iflustrates a blocl diagram for a CMOS imager 10, The ixnager 10 includes a pixel array 20. The pixel array 20 comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixeLs of cach row in array 20 arc all turncd on at the same rime by a row sclcct line and the pixels of each column arc selectively output by a column select line. A plurality of row and column lines arc provided for the entire array 20.

(0006] Thc row lines arc selectively activated by the row driver 32 in response to row address decoder 30 and the column sclcct lines are selectively activated by the column driver 36 in response to column address decoder 34. Thus, a row and column address is provided for each pixel. The CMOS irnagcr 10 is operated by the control circuit 40, which controls address decodcrs 30, 34 for selecting the appropriate row and column lines for pixel rcadout, and row and column driver circuitsy 32, 36, which apply driving voltagc to the drive transistors of the selected row and column lines.

[0007] Each column contains sampling capacitors and switches in a sample and hold (S/H) circuit 38 associated with the column driver 36 reads a pixel reset signal V and a pixel image signal V318 for each selected pixel. A diffrenual signal (Vrst-V8) is produced by differential anipli er 42 for each pixel. The signal is digitized by analog-to-digital converter 45 (.ADC). The analog-to.digital converrcr 45 supplies thc digitized pixel signals to an imagc processor 50, which forms a digital image output 52.

[0008] Typical CMOS imager pixel cells have either a three transistor (3T) or four transistor (4T) design, though pixel cells having a larger number of transistors arc also known. A 4T or higher Tpixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region nd one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transfcrcnce.

[0009] A 3T pixel does not typically include a transistor for transferring charge from the photosensor to the storage region. A 3T pixel typically contains a photo-conversion device for supplying photogenerated charge to the storage region; a reset transistor for resetting the storage region; a sourcc follower transistor having a gatc connected to the storage region, for producing an output signal; and a row sclcct transistor for sclcctively connecting the sourcc follower transistor to a column line of a pixel array. In a 3Tpixel cell, the charge accumulated by a photoconversion devicc may be read out prior to resetting the dcvicc to a predetermined voltage. These 3T pixel cclls may be used to support automatic light control (ALC) operations. ALC is uscd to control the amount of light integrated by a pixel ccli. ALC opcrations may determine a time for readout based on the amount of ch4rgc generated by the photo.

conversion device and may adjust the image integration time and thus the amount of charge further gencratcd by the photo-conversion device in response to the charge present on the photo-conversion device at a particular time.

[0010] Although the 3T design (or 4T pixel operated in a 3T mode) may be used to support ALC operations, the 4T pixel configuration is prcfcrrcd over thc 3T pixel configuration because it reduces the number of "hot" pixels in an array (those that experience increased dark current), and it dixnini.shes the kTC noise that 3Tpixels may experience with thc readout signals.

(0011] Since light conditions may change spatially and over tim; automatic light control is advantageous to ensure that the best image is obtained by controlling the image sensor's exposure to the light. In some imager applications, there is a need to use the prescrit illumination during the actual exposure of an image in a current frame to control the exposure because the use of the imager's illumination in a prior frame may not be sufficicnt for thc intended application. Puither discussion on ALC a.nd real-time exposure control may bc found in US Patent Application Serial Nos. 10/846,513, filcd on May 17. 2004, and 11/052,217, fIled on February 8, 2005, assigned to Micron Technology, Inc., both of which are incorporated by reference herein.

(0012] Correlated double sampling (CDS) Is a technique used to reduce noise and obtain a more accurate pixel signal. For CDS, the storage region, also termed DSMDa.1905013.2 herein as the floating diffusion region, begins at a prcdeterrnined reset voltage level by turning on a reset transistoç thereafrcr, the reset voltage produced by the source follower transistor is rcad out through the row select transistor as a pixel reset signal V,,. Then, intcgratcd photo-gcncratcd charge from the photosensor is transferred to the floating disIon region by operation of a transfer transistor and a pixel image signal V produced by the source follower transistor is read out through the row select transistor. The two values, V and V,, are subtracted thereby reducing common noise. The reset signal Vrn and image signal are obtained during thc same image frame in a CDS operation.

(0013] In a conventional IT pixel cdl, because the transfer transistor transfers the photo-generated charge from thc photosensor to the floating diffusion region and, therefbre, to readout circuitry, it is not possible to read out photo-generated chargc without altering the charge on the photosensor. Thus, when a 4T readout path is employed to monitor charge level in an ALC opcratlon, the transfer of charge carriers through the transfer transistor tends to destroy or alter the image signal, thereby resulting in a degraded image. Therefore, ALC is not readily used with a conventional 4Tpixel cell.

[0014] Accordingly, there is a desire and need for automatic light control in a device with low dark current and kT/C noise during an cxposurc pcriod that uses present iilurnination., yet does not alter the image signal during the charge integration time of the photosensor in the process.

BRIEF SUMMARX OF THE iNVENTION (0015] In various exemplary embodiments, the invention provides accurate exposure control in a pixel array comprising imaging pixeLs having a transfer gate and four or more transistors and using CDS while using pixels that do not usc a transfer gate for automatic light control. These embodiments allow monitoring of multiple pixel cells of the array to obtain sample data indicating the amount of light reaching the array, while allowing the image pisels to provide proper image data.

DSMoL1O%a3.

10016] in one exemplazy embodiment, a small percentage of the pixels in a four-transistor (4T) pixel (or pixci having more than four transistors) array is replaced with pixcis that do nor use a transfer gate, such as 3Tpixe]s. The pixel array is provided with two reset lines for each row one reset line controls the reset for the 4Tor higher T pixeLs while the other rsct line controls thc rcset for the 3T pixels.

(0017) In another exemplary embodiment, a small percentage of the pixels in a 4T or higher T pixel array arc operated in a 3T mode, with the transfer transistor always turned on. The pixel array is provided with two reset lines for each row; one resct line controls the rcscc for the conventional operation of 4T or higher T pixels, while the other reset line controls the reset for the 4T pixels that are operated in 3T mode.

BRIEF DESCRUTION OP THE DBAWIGS

100181 The foregoing and other advantages and features of the invention will become more apparent from the detailed description of the exemplary embodiments provided below with reference to the accompanying drawings, in which: [0019) FIG. 1 is a block diagram of a CMOS imagcr (0020] FIG. 2 is a block diagram of a CMOS irnager constructed in accordance with an cmbodiment of the invention; (0021) FIG. 3 is a schematic diagram for a section of a row in a pixel array Constructed in accordance with an cmbodiment of the invention; (0022] FIG. 4 is a schematic diagram for a section of a row in a pixel array constructed in accordance with another eznbodinienr of the invention; [00Z3) FIG. 5 is an exemplary timing diagram for a CMOS irnagcr constructed in accordance with an embodiment of the invention; (0024) FIG. 6 is a plan view of a section of a pixel array constructed in accordance with an embodiment of the invention; and $ (0025] FIG. 7 is a block diagram for a processor-base system constructed in arcordance with az embodiment of the invention.

DETAILED DESCRIPTION OF THE]NVENTION

[0026] In the following detailed description, rTeference is madc to the accompanying drawings, which form a part hereof and show by way of illustration specific exemplary embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical, and electrical change may. be made without departing from the spirit and scope of the prescnt invention. The described pro grcssion of processing and operating steps exemplifies embodiments of the invention; however, the sequence of steps is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps necessarily occurring in a certain order.

(0027] The terms "pixel" and "pixci ccli," as used herein, refer to a photo-element unit cell containing a photo-conversion device and associated &cuitry for converting photons to an clcctrical signal. The pixels discussed herein are fflusrzated and described with reference to using three transistor (3T) and four transistor (4T) pixel circuits for the sake of example only. It shottid be undcrstood that the invention may be used with respect to other imaging pixel arrangements having more (e.g., 5T, 6T) than four transistors or with pixel arrangements using devices other than transistors to providc output signals. Accordingly, in the following discussion it should be noted that whenever 4T pixels arc discussed, pixels having additional transistors, used for example, for an anti-blooming, conversion gain, or shutter gate may be uscd. Likcwisc, aLthough 3T pixels are discussed for providing automatic light control, ir should be noted that any pixel that enables the integrating charge on a photosensor to be read during a charge integration period may be used. The following detailed description is, therefore, not to be taken in a limiting sense DSMDRZ9OSOSSJ [0028] Referring to the figures, where like reference numbers designate like dements, PIG. 2 shows an exemplary ixnager 110 having an automatic light control fu.nction constructed in accordance with the invention. Thc imager 110 includes a pixel array 120 containing 4T pixels and a small pcrccntagc of ST pixels (or 4Tpixels operated in 3T mode with the transfer transistors always turned on, as discussed below in more detail) for automatic light control. Bach row of the pixel array 120 has two reset lincs 131, 133 controlling the reset operations for thc pixels of the row; reset line 131, for cxamplc, may control the reset of the 3Tpixds in the row, while reset line 133, for example, may control the reset of the 4T pixels in the row. The row lines are selectively activated by the row driver 132 in response to row address decoder. A column is also addrcssed and sclcctcd for pixel readout Thus, a row and column address is provided for each pixci.

(0029] The CMOS imager 110 is operated by the control circuit 140, which controls address dccodcrs 130, 134 for selecdng the appropriate row and column tines for pixd readout, a.nd row and column driver circuitry 132, 136, which apply driving voltage to the drive transistors for the selected row and column lines.

[0030] Each column contains sampling capacitors and switches in a sample and hold (S/H) circuit 138 associated with the column driver 136 that reads a picd reset signal Vrst and a pixel image signal Vsig for selected pixels. A differential signal (Vrst -Vaig) is produced by differential amplifier 140 for each pixel. The signal is digitized by analog-to-digital converter 145 (ADC). The analog-to-digital converter 145 supplies thc digitized pixel signatc to an image processor 150, which forms a digital image output 152.

[0031] As mentioned above, pixel array 120 contains 4T pixels and a small percentage of 3T pixels. For example, approximately 1% of the pixels in array 120 arc 3T pixels. 4T pixels provide low dark current and true correlated double sampling and.

are imaging pixels. 3Tpixels are ideally suited for auxoxnatic light control, which is the ability to monitor the signal level so that exposure time can be well-controlled r each frame without altering the image signal.

[0032] 4Tpixcl have a different, often shorter, integration time than 3TpixcLs.

Therefore) the 3T and 4T pixels typically cannot bc reset at the same time. To accommodate the two types of pixds having different reset times, two reset lines iai, 133 for each row are routedinto the pixel array 120. The two reset lines 131,133 arc routed to each array row, although each pixel in a row is only conncctcd to one of the two react lines 131, 133, depending on whether the pixel is a 3Tpixcl or a 4T pixcL The 3T pixels arc connected to reset line 131 and the 4T pixels are connected to reset line 133.

[0033] While the reset level must be sampled at different times, the image signal level can bc samplcd at the same time for both 3T and 4T pixels. Therefore, extra logic is introduced in the column circuitty to enable different reset level sampling times.

[0034] The connections of 3T and 4T pixels of pixel array 120 to reset and column lines are shown in FIGs. 3 and 4. An exemplary embodiment of the invention depicted in PIG. 3 combines the 4T pixel 70 with a 3T pixel 60 in the same row described below. The 3T pixel comprises a reset transistor 61, source follower transistor 62, and a row select transistor 63 and can be formed by any suitable method.

The 4T pixel 70 compcs transfer transistor 76, rcsct ansistor 71, source follower transistor 72, and a row select transistor 73. In other cmbodiincnts of the invention, these pixels may employ more transistors than the illustrated 3T and 4T design (ST, 6T, etc.). Similarly, other embodiments could provide pixel arrangements using devices other that transistors to provide output signIc; another alternative includes a capacitor (not shown) electrically coupled to thc floating diffu.sion regions 64, 74 for assiting the floating diffaaion regions 64,74 ui storing the transferred charges.

(0035] A pbotosensor 65 converts incident light into charge. A floating diffusion region 64 receives charge from the photosensor 65 and is connected to the reset DSMDL19oso.2 transistor 61 and the gate oldie source follower transistor 62. The source follower transistor 62 outputs at different nines a reset signal V, and an image signal V, (coliccr. ivcly shown in Fig. 3 as Vout). Vout (cithcr V or V1) represents the charge present at the floating diffusion region 64 which is provided to a sample and hold circuit 138 (PIG. 2) when the row select transistor 63 is turned on. The reset transistor 61 resets the floating diffusion region 64 to a known pote.ntial aftcr tran.sfer of chargc from the photosensor 65 (when 1.ST-1 is applied). The photosensor 65 may be a photodiode, a photogatc, a photoconductor, or othcr type of photosensor. Por ALC operation, it is not necessary to output a react sample V from the 3T pixci, in which case the row select transistor 63 may be operated to only outit V4 as the output signal Vout.

[0036] Imaging pixel 70 is a four transistor (4T) pixci. The four transistors include a transfer transistor 76, reset transistor 71, source follower transistor 72, and a row select transistor 73. A photosensor 75 converts incident light into charge. A floating diffusion region 74 rcccives charge from the photosensor 75 through the transfer transistor 76 (when activated by control signal TG) and is connected to the reset transistor 71 and the gate of the sourcc follower transistor 72. The source follower transistor 72 outputs a reset signal V and an irnagc signal V (collectively shown as Vout). Vout represents the charge present in the floating diffusion region 74 which is provided to a sample and hold circuit 138 (FIG. 2) when the row select transistor 73 is turned on. The react transistor 7]. resets the floating diffusion region 74 to a known potential prior to transfcr of charge from the photosensor 75 (when RST-2 is applied). Sirnihr to photoscn.sor 65, the photosensor 75 may be a photodiode, a photogate, a photocondtictor, or other type of photose.n.sor.

f0037] Thc two pixcls 60, 70 are provided in the same row having reset lincs 13], 133. Reset transistor 6]. of pixel 60 is connected to reset line 131, which controls the react transistor for all 3T pixels in the row. Reset transistor 71 of pixel 70 is D$MD34O5O$33 connected to rcsct line 133, which controls the reset transistor for all 4Tpixels in the row.

(0038) PIG. 4 is a schematic diagram of two pixels 80, 70 in a single row of another embodiment of pixel array 120. Pixels 80,70 are both 4Tpixels. Pixel 70 is as described above with respect to FIG. 3. Pixel 80 is a four transistor (4T) pixel that is operated in 3T mode. The four transistora of pixel 80 include a transfer transistor 86, reset transistor 81, source follower transistor 82, and a row select transistor 83.

Transfer transistor 86 is always turned on to operate the pixel 80 in 3T mode. A photoscnsor 85 converts incident light into charge. A floating diffusion region 84 receives charge from the photosensor 85 through thc activated transfer transistor 86 and is Connected to the rcsct transistor 8] and thc gate of the source follower transistor 82. The source follower transistor 82 outputs a reset signal V a.nd an image signal V (collectively shown in Fig. 3 Vout). Vout (either V,. or V) represents the charge present at the floating diff.uion region 84 to a sample and hold circuit 138 (FIG. 2) when the row select tiansjstor 83 is turncd on. The reset tran.sistor 81 resets the floating diffusion region 84 to a known potential prior to transfer of charge front the photoscnsor 85. Sirnjla.r to pixel 70, the photosensor 85 may bc a photodiode, a photogate, a photoconductor, or other type of photosensor. Also, like the Pig. 3 3T pixel, pixel 80 may be opcratcd so that only the image signal V is output and sampled for ALC operation.

[0039] As described above with respect to FIG 3, the two pixels 80,70 arc provided in the sarnc row having reset lines 131, 133. Reset transistor 81 of pixel 80 is connected to reset line 131, which controls the reset transistor for all 4Tpixels in the row that are operated in 3T mode. Reset transistor 71 of pixel 70 is connected to reset line 133, which controls the reset transistor for all 4T pixels in the row that are opcratcd in 4T mode. Therefore, pixel 80 and pixel 70 may be reset at different nines.

[0040] The rcsct timing of the pixels 60,70 of FIG. 3 is illustrated in FIG. 5.

PIG. 51s an exempla.y timing diagram for a row having 3T pixels and 4T pixels, as DSMDaI OSO*3.1 controlled by thc timing and control circuit 140. For simplicity, pixel circuit operations arc described with rcfcrcncc to a single pair of pixci cclls 60, 70; however, each row of array 120 having pixeLs 60, 70 may operate as described below in conncction with FIG 5. Also, the exemplary th-ning diagram may be used fbr a row Kaving 4T pixels, some of which are operated in 3T mode by keeping the transfer transistor constantly on, such as the pair of pixels in a row illustrated in PIG. 4, wherein the timing of 3T pixel 60 (FIG. 3) may represent the timing of 4T pixel 80 (PIG. 4) that is being operated in 3T mode. Furthermore, signals B.S1, rst_4T. tx_4T, shr_4T, shs_4T, rst_3T, shs_3T, and shr_3T are provided to illustrate the timing of one exemplary operation and do not in any way limit the invention to the illustrated operation.

10041] FIG. 5 shows one cxcmplazy frame readout operation which may be used with the pixel arrays depicted in FIGs. 3 or 4 that begins at tune tO. The readout opcration begins by resetting the floating diusions 64,74 of pixels 60, 70, respectively. For each active row of the array 120, the timing and control circuitry 140 pulses a row select signal (RS1) high to turn on the row select transistors 63,73 of pixels 60, 70, respectively. Timing and control circuitry 140 pulses a reset signal (rst...4T) on reset linc 133 high to activate each 4T pixel's (pixel 70) reset transistor 71.

At this time, sampling capacitors of S/H circuit 138 store the reset voltage Vrst(4T) of the 4Tpixel 70 (when shr_4T is activated). Th.e reset voltage Vrst(4T) is read out in sequence for each row of the array 120 that includes 4Tpixels.

[00421 After an image integration period ends, timing and control circuitry 140 also pulses a transfer signal (cx...4T) to activate the transfer transistor 76 of pixel 70.

Any charge on the photosensor 75 of pixel 70 is thus transferred through transftr transistor 76 to the floating diff.ision region 74. This marks the end of the 4T integration period, or charge generating period, for the photosçn.sor 75. At this time, sampling capacitors of S/H circuit 138 store the signal voltages Vsig(4T) and Vsig(3T) of the 4T pixel 70 (when shs_4T is activated) amid ST pixel 60 (when shs_3T is activated), respectively. These are photo image signals related to the amount of Light DSMDL1SOSOI3.a incidcnt on the pixels. The sample voltages Vsig(4T) and Vsig(3T) axe read out in sequence for each row of the array 120 that indudes ST and 4T pixels. It should be noted that the sampling of Vsig for the 3T pixel may occur at any thne during charge integration of the 4T pixels to provide a signal for use in ALC opcradoris. Accordingly the sample and hold signal shs_3T is illustratcd with arrows in PIG. 5, denoting this flexibility.

[0043] Timing and control circuitry 140 then pulses the transfer transistor 76 of pixel 70 and reset transistors 61, 71 of pixels 60, 70, to reset the photosensors 65, 75 and floating diffusion regions 64, 74, respectively. Sampling capacitors 138 take the reset voltage Vrat(3T) of thc 3Tpixcl 60 (shr_3T). The reset voltage Vrst(3t) is read out in sequence for each row of the array 120 that includes 3Tpixds. After completion of readouts, all signals are returned to low; and the sequence of stcps is repeated row-by-row for each row of the pixel array 120. For simplicity, FIG. & shows only a single integration period of one representative row of pixels having 3T and 4Tpixels.

[0044] In the above-described embodiment, the photo signal level is sampled at the same rime for both 3T (or 4T operated in 3T mode) and 4Tpixels, while thc rcsct level is sampled at different times. Therefore, cxtra logic must be introduced in the column circuitry to bc able to select between at least., but not limited to, different reset level sampling time, depending on which row is slected. However, the timing of the frame readout operation is not limited to the above-described embodiment. For example, it is possible to read out the 3T signal level at the same tune as the 4T reset level, and vice versa. The start and stop time of the exposure would then be slightly differeat for the 3T and 4T pixels. Moreover, since the 3T and 4T pixels have integration periods, it is not cxiscia.l that the integration start and stop time be identical for the 3T and 4T pixels. Regardless of whcthcr their exposure rime begins and ends togcthcr, a gain factor should be applied to thc 3T pixcLs in order to calculate a readout voltage consistent with the surrounding 4Tpixds, as will bc described in further detail bdow.

DSMD).1905013.2 (0045) The 3Tpixels 60 may be provided along a row of 4T pixels 70 in a Configuration as illustrated in FIG. 6. PIG. 6 is a plan view of a sccon of a pixel array of PIG. 2. The pixel array 120 features pixels arranged in a Bayer pattern 300 consisting of alternating rows, one having alternating red and green pixcls, and the next having alternating green and blue pixels. All of the pixels shown in PIG. 6 arc 4Tpixcls having either red, green, or blue associated color filters, with the exception of a singic red 3TpixeJ 60. A.s mentioned above, approximately 1% of the red pixels may be rcplaccd with ST pixels. Thc 3T pixels arc constantly monitored and may be read out after the integration period of the 4T pixel ends.

(0046] Since the sensitivity, or responsivity, of 3T pixcis 60 is not the same as thc sensitivity of 4T pixels 70, a gain factor may be applied to the 3T pixel 60 to estimate what the readout of a 4T pixci would be at that location. An exemplary method of estimating the gain factor includcs an assumption that the average readout of the su.rrounding4T pixels 70 will be the same as the aver-agc rcadout voltage of the 3T pixel. Therefore, an average readout voltage is calculated by taking the average voltage of the surrounding red 4Tpixcls. For cxamplc, the average of four rcd 4T pixels Surrounding the red 3T pixel 60 would be calculated as follows: (0047] Vavg(4T) (V(A1) + V(A2) + V(A3) + V(A,))/4, [0048] In another example, the average of eight red 4TpixcLs surrounding the red 3Tpixel 60 would be calculated as follows: [0049] Vavg(4T) = ((V(A1) + V(A1) + V(A.) + V(A4) + V(B1) + V(B) + V(B3) + (0050] The gain factor is then calculated as follows: (0051] Gain factor Vavg(4T)/ Vavg(3T).

DSMDLI9OS0$3.2 (0052) Therefore, the readout voltage of the 3Tpixcls 60 would have the gain fctor applied to it by multiplying it by the ratio of average readout voltage of the surrounding 4Tpixcl.s, divided by the ratio of average readout voltage of the surrounding 3TpixcLs. Although the above gain fctor was described as being applied to a 3Tpixel, it shouldalso be noted that a gain factor would also be applied to a 4T pixel operated in 3T mode. It should also be noted that although the initial average rcadout voltage estimate will be inaccurate when the image sensors start capturing framcs, after several frames, the average estimate will improve since the average calcu1atio may be updated and performed for every fram;. Thc gain factor may be applied by the image proccssor 150 (FIG. 2) which receives the integrated pixel signals, or the image processor, Or other processor, can control the gain of amplier 142, or other amplifter in the analog pixel signal processing chain.

10053] The 3T signal, as originally read out, is used for automatic light control.

Automatic light control may be performed in accordance with the methods described in US Patent Application Serial Nos. 10/846,513, filed on May 17, 2004, and 11/052,217, flIed on February 8,2005, assigned to Micron Technology, mc, which are herein incorporated by reference.

10054] FIG, 7 illustrates a processor-based system 400 including the image sensor of FIG. 2 and employing the exemplary pixel array discussed with reference to Figs. 2-6. The proccasor-based system 400 is exemplary of a syste.rn having digital circuits that could include image sensor devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision, vehicle navigation, video phone, survcillance system, auto focus system, star tradcer system, motion detection system, image stabilization system, and other image sensing systems.

[0055] The processor-based system 400, for example a Camera system, generally compes a cenrxaj processing unit (CPU) 401, such as a microprocessor, that commuxucat with an input/output (I/O) dcvicc 402 over a bus 403. Image Sensor 400 also conrnujcates with the CPU 405 over bus 403. The processor-based system 900 also includes random access memory (RAM) 404, and can indudc rcrnovablc memory 405, such as flash memory, which also communicate with CPU 401 over the bus 403. Image sensor 400 may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, with or without memory storage on a single integrated circuit or on a different chip than the processor.

[0056] The proccsscs and devices described above illustrate preferred methods and typical devices of marty that could be used and produced. The above description and drawings illustrate embodiments, which achieve the objects, features, and advantages of the present invention. However, it is not intended that the prcscnr invention be stricdy limited to the above-described and illustrated embodiments. Any modification, though presently unforesecable, of thc present inventlon that comes within the spirit and scope of the following claims should bc considered part of the present invention.

Claims

CLAIMS.

1. A pixel array comprising: a plurality of pixels in a pixd row for providing image capture signals; at least one pixel in said pixel row for providing an automatic light control signal; a first reset line for resetting said plurality of image capture pixels; and a second reset line for resetting said at Icast one pixel for providing an automatic light control signal.

2. The pixel array of claim 1, wherein said plurality of image capture pixels comprise at least a photosezuor, a charge storage region, a reset transistor for resetting signal from said charge storagc region, and a transfer traasistor for selectively transfcrring charge from said photosen.sor to said chargc storage region aftcr an integration period.

3. The pixel array of claim i, wherein said at least one automatic light control pixel comprises at least a photosensor fbr providing charge to a charge storage region during charge integration, and a reset transistor frr rcsctting said charge storage region.

4. The pixel array of claim 3, wherein said at least one autorri;tic light control pixel is operated in three-cransLstor mode.

5. The pixel array of claim 1, firther comprising a control circuit PShWLI9co3.2 for providing a first reset signal on said first reset line at a different time than providing a second reset signal on said sccond reset line.

6. The pixci array of claim 5, wherein said plurality of image capturc pixels have different integration times than said at least one automatic light control pixel.

7. The pixel array of claim 1, wherein said at least one automatic * light control pixel has a calculated output voltage with an applied gain factor, based on a ratio ofan average output voltage of a group of said plurality oflinagc capture pixels surrounding said automatic light control pixel to an averagc output voltage of said automatic light control pixel.

8. A pixel array comprising: a plurality of image capture pixels, wherein each iniagc capture pixel has a transfer tra sistors betwecn a photosensor and a floating diffusion region for ansfrring charge at the end of an integration period; a plurality of automatic light control pixels, wherein each automatic light control pixel has a photosensor coupled to a flotlng diffusion region during an integration period; a first react line for resetting said plurality of image capture pixels; and a second rcsct line for resetting said plurality of automatic light control pixels.

D5MDLISOSQUJ 9. The pixel array of claim 8, further comprising a control circuit for providing a first rcscc signal on said first reset line at a different time than providing a second reset signal on said second reset line.

10. The pixel array of claim 9, whcrcin said plurality of automatic light control pixels has a different intcgradon rime than said plurality of image captu.rç pixels.

11. The pixel array of claim 9, wherein said one of said plurality of automatic light control pixels has a calculated output voltagc with an applied gain factor, based on a ratio of an average output voltage of a group of said plurality of image capture pixels surrounding said automatic light control pixel to an average output voltage of said automatic light control pixel.

12. A method of controlling art imager comprising an array of pixels having a plurality of four-fransjgtor pixels and a plurality of pixels having three-transistor characteristics, said method comprising the steps of: performing automatic light control with said plurality of pixels having three-transistor pixel charactcristics; and performing correlated double sampling to produce image capture signals with said plurality of four-transistor pixels.

DSMDLDOSO$3.2 13. The method of claim 12, further compzising resetting a first reset link connected to said plurality of fou.r-rransistor pixels and resetting a second rcsec line connected to said plurality of pixels having three-transistor characteristics.

14. A method of controlling an imagcr comprising an array of pixels, said method comprising the acts of obtaining a first set of pixel signals from a first set of pixels in the array; capturing an image signal with said first set of pixel signals; obtaining a second set of pixel signals om a second set of pixels in the array; and pc.rfbrniing automatic light control with said second set of pixel signals.

15. The method of claim 14, wherein said. act of obtaining a rst set of pixel signals is performed at a different dine than said act of obtaining a second set of pixel signals.

16. A mcthod for forming an imaging dcvicc, the method comprising: forming a plurality of image capture pixds; forming a plurality of automatic light control pixels, wherein at least one of said. automatic control pixels is on a same row as at least onc of said image capture pixels; * 19 D5MDfl.1o5OLLa connecting said plurality of image capture pixels to a first rcset line; connccting said plurality of automatic light control pixels to a second reset line.

17. The method of claim 16, i.rrher comprising providing a first readout circuit for reading out a signal from said plurality of image capturc pixels.

18 Thc method of daim 16, further comprising providing an automatic light control circuit for performing automatic light control based on a signal from said plurality of automatic light control pixels.

19* The method of claim 16, further comprising providing a circuit for calcuLating a readout voltage for said plurality of automatic light control pixels by applying a gain factor, bascd on a ratio of an avcrage output voltage of a group of said image capture pixels surrounding said plurality of automatic light control pixeLs to an average output voltage of said plurality of automatic light control pixels.

20. A pixel array comprising: at Icasz onc row of pixels comprising: a plurality of imaging pixeLs, each comprising a photoscnsor, a charge storage region, a reset transistor for resetting signal from said charge storage region, and a transfer transistor for selectively transferring charge from said photosensor to said charge storage region after an integration pcxiod; and at least one pixel comprising a phor.osensor for providing charge to a charge storage region du.ring charge integration, and a reset transistor for rcsctcing said charge storage region; a first reset control line connected operate thc rcsct transistor of said plurality Of pixels; and a second control react linc connected to operate the reset transistor of said at least one pixel.

21.. The pixel array of claim 2O,arthcr comprising a control circuit for resetting said first reset linc at different time than said sccond reset line.

22. The pixcl array ofcaim'2Owhercüi said at least one pixel is a three-transistor pixel.

23. The pixel array of dairn 20,wherein said at least one pixel is a four-transistor pixci operated in a thee-transistor pixel mode, 24. The pixel array of claim 23,whereixi said thrce-transjtor pixel mode has a transfer transistor that is always turned on.

25. The pixel array of claim2O,whercjxis at least one pixel has a calculated output voltage with an applied gain factor, based on a ratio of an average output voltage of a group of said plurality of pixels surrouridin said at lcast one pixel to an average output volragc of said at lca.st one pixel.

26. The pixel array of claim 20,whcrein said at east one pixel is * used for automatic light control of said plurality of pixcis.

27. Thc pixel array of claim 26,wherein said pixel array is a color pixel array with said plurality of and said at least one pixel arranged in a Bayer pattern.

28. The pixci array of claim 27,whcrcin a subset of pixels of one color of said Bayer pattern is used for automatic light control.

29. The pixel array of claim 28,wherein said color is red.

30. The pixd array of claim 28,wherein said subset of pixels is dispersed throughout the pixel array.

-31, The pixel array of claim 20,where at least 1% of the total pixcLs in said array has three-transistor characteristics.

32. Animagcscnsorcompg: an array of pixels comprising a plurality of pixels comprising at least a photosensor, a charge storage region, a reset transistor for resetting signal from said chargc storage region) and a transfer transistor for selectively ansferring charge from said photoscnsor to said charge storage region after an integration period, wherein a percentage of the pixels comprise pixels having thrcc-cransjstor pixel characteristics; means for resetthig said plurality of pixels; means for rcscrthig said thrcc-transistor charactcrisric pL'cels; means for reading out a readout voltage for said plurality of pixels; and DSMDB. 1505053.1 means for calculating a readout voltage of said threc-rra.nsistor characteristic pixels.

33. The image sensor of daim 32, wherein said percentage is approximately 1%.

34. The image sensor of claini 32, wherein said means for Calculating a readout voltage of said three-transistor characteristic pixels is in an image processor.

35. The image sensor of claim 32, wherein said means for calculating a readout voltage of said three-transistor characteristic pixels comprises applying a gain ftctor, based on a ratio of an average output voltage of a group of said plurality of pixels surrounding said three-transistor characteristic pixd to an average output voltage of said three-transistor characteristic pixel.

36. The image sensor of claim 32, wherein said means for resetting said plurality of pixels resets said three-transistor characteristic pixels at a different time.

37. The image sensor of claim 32 fAlrther comprising a means for reading out a readou.t voltage of said three-transistor characteristic pixels and using said readout voltage of said three-transistor characteristic pixels %r automatic light control.

38. A method of forming an imager comprising an array of pixels, said method comprising the steps of: providing a first plurality of pixels comprising at least a photosensor, a charge storage region, a reset transistor for resetting signal from said chargc storage region, and a transfer transistor for selcctivcly transferring charge from said photaseor to said charge storage region after an integration period in said array providing a second plurality of pixels having thrcc-transjstor charactenst in said array providing a first reset line for resetting said first plurality of pixels; and providing a second rcsct Jinc for resetting said second plurality of pixels.

39. The method of claim 38, wherein said second plurality of pixels makes up approximately 1% of said array.

40. Thc method of claim 38, further comprising providing a control circuit for resetting said first rcsct line and said second reset line at different timcs, 41 The method of claim 38, further comprising proiiding a circuit for calculating a readout voltage one of said second plurality of pixels by applying a gain fctor, bascd on a ratio of an average output voltagc of a group of said first plurality of pixels surrounding said one of said second plu.rality of pixels to an average output voltagc of said one of said second plurality of pixels. 24 42. An image processing system comprising: a processor; an imager structure comprising: at Icast one row of pi.xels, each row comprising: a first plurality of pixels, each comprising a photoscnsor, a charge storage region, a reset transistor for resetting signal from said charge storage region, and a transfer transistor for selectively transferring charge from said photoscasor to said charge storage region after an integration pcriod; at least one pixel comprising a photosensor for providing charge to a charge storage region during charge integration1 and a reset transistor for rcsctring said charge storage region; a first reset linc to opcratc the reset tra.nsistor of said first plurality of pixels and a second reset line to operate said the reset rzansLstor of said at least one pixel.

43. The image processing system of claim 42 further comprising a control circuit that resets said first reset line at a different tinie than said control circuit resets said second reset line.

44. The image processing system of claim 42, wherein said at least one pixel makes up about 1% of the total number of pixels in said imnager structure.

45. The image processing system of claim 42, wherein said at least one pixel has a calculated output voltage with an applied gain factor, based on a ratio of an average output voltage of a group of said first plurality of pbcds surrounding said at least one picl to an avenge output voltage of said at least one pixel.

46. The image processing system of claim 42, wherein said at icast one pixel is used for automatic light control of said first plurality of pixels.

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