WO2012017878A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2012017878A1
WO2012017878A1 PCT/JP2011/067034 JP2011067034W WO2012017878A1 WO 2012017878 A1 WO2012017878 A1 WO 2012017878A1 JP 2011067034 W JP2011067034 W JP 2011067034W WO 2012017878 A1 WO2012017878 A1 WO 2012017878A1
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Prior art keywords
region
diode
semiconductor device
groove
transistor
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PCT/JP2011/067034
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French (fr)
Japanese (ja)
Inventor
達広 鈴木
哲也 林
滋春 山上
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日産自動車株式会社
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Publication of WO2012017878A1 publication Critical patent/WO2012017878A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8618—Diodes with bulk potential barrier, e.g. Camel diodes, Planar Doped Barrier diodes, Graded bandgap diodes

Definitions

  • the present invention relates to a semiconductor device used as a switching element.
  • Patent Document 1 discloses a semiconductor device that includes a MOS field effect transistor (MOSFET) formed on a silicon carbide semiconductor substrate and a unipolar diode having a heterojunction and functions as a switching element. Are listed.
  • MOSFET MOS field effect transistor
  • the channel of the MOSFET is formed on the side surface of the gate electrode adjacent to the diode.
  • the spread of the current flowing through the channel formed adjacent to the diode is larger than the spread of the current flowing through the portion where the gate electrodes of the MOSFETs are adjacent to each other. For this reason, since the current density flowing through the channel is lower in the channel formed adjacent to the diode, the voltage drop becomes smaller and the current flows more easily. As a result, there is a possibility that current is concentrated on the MOSFET formed on the side surface of the gate electrode adjacent to the diode, which easily causes element destruction.
  • an object of the present invention is to provide a semiconductor device that suppresses element destruction due to current concentration.
  • one embodiment of the present invention is a semiconductor device including a transistor portion including a plurality of transistor units adjacent to each other and a diode adjacent to the transistor portion.
  • Each of the plurality of transistor units includes a first conductivity type drift region serving as a drain region of the transistor unit, a second conductivity type well region formed on the drift region, and a first conductivity type formed in the drift region and the well region.
  • a gate electrode formed through an insulating film and a source region of a first conductivity type formed on the well region in contact with the first trench are provided inside the one trench.
  • the source region provided in the transistor unit adjacent to the diode is formed only on the other adjacent transistor unit side with the first groove as a boundary.
  • the width of the source region formed on the diode side is narrower than the width of the source region formed on the other adjacent transistor unit side.
  • FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 2 is a first process cross-sectional view illustrating an example of a method for manufacturing the semiconductor device of FIG.
  • FIG. 3 is a second process cross-sectional view illustrating an example of a method of manufacturing the semiconductor device of FIG.
  • FIG. 4 is a third process cross-sectional view illustrating an example of a method for manufacturing the semiconductor device of FIG.
  • FIG. 5 is a fourth process cross-sectional view illustrating an example of a method of manufacturing the semiconductor device of FIG.
  • FIG. 6 is a fifth process cross-sectional view illustrating an example of the method for manufacturing the semiconductor device of FIG. FIG.
  • FIG. 7 is a sixth process cross-sectional view illustrating an example of the method for manufacturing the semiconductor device of FIG.
  • FIG. 8 is a seventh process cross-sectional view illustrating an example of a method of manufacturing the semiconductor device of FIG.
  • FIG. 9 is an eighth process cross-sectional view illustrating an example of a method of manufacturing the semiconductor device of FIG.
  • FIG. 10 is a ninth process cross-sectional view illustrating an example of the method for manufacturing the semiconductor device of FIG. 11 is a cross-sectional view of a tenth process showing an example of the method for manufacturing the semiconductor device of FIG. 12 is an eleventh process cross-sectional view illustrating an example of a method for manufacturing the semiconductor device of FIG. FIG.
  • FIG. 13 is a diagram showing a current spreading state I13 when the source region 5 is formed only on one side of the trench of the MOSFET unit 101 of FIG.
  • FIG. 14 is a diagram showing current spreading states I13 and I14 when the source region 5 is formed on both sides of the trench of the MOSFET unit 101 of FIG.
  • FIG. 15 is a graph showing current-voltage characteristics in the semiconductor device according to Embodiment 1 of the present invention and the semiconductor device according to the related art.
  • (A1) to (a5) of FIG. 16 are diagrams showing the size of the channel region when the MOSFETs are not continuously arranged, and (b1) to (b5) of FIG. 16 are the MOSFETs arranged continuously. It is a figure which shows the magnitude
  • FIG. 17 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 18 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 3 of the present invention.
  • FIG. 19 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 4 of the present invention.
  • FIG. 20 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 5 of the present invention.
  • FIG. 21 is a cross-sectional view of a cross section taken along line AA of FIG. 20 as viewed from above.
  • FIG. 22 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 6 of the present invention.
  • FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention.
  • the semiconductor device of the first embodiment shown in FIG. 1 includes a MOSFET unit 100 composed of a plurality of MOS FETs (field effect transistors) connected in parallel and a unipolar diode unit 200. Yes.
  • FIG. 1 only one combination of the MOSFET unit 100 and the diode unit 200 is illustrated, but the semiconductor device includes a plurality of combinations of the MOSFET unit 100 and the diode unit 200.
  • the MOSFET unit 100 is configured by connecting a plurality of MOSFET units 101 to 104 in parallel. Although four MOSFET units 101 to 104 are shown in FIG. 1, the number of MOSFET units constituting the MOSFET unit 100 is not limited to four, and the drive to be obtained by the MOSFET unit 100 It is set appropriately according to the force. Therefore, in FIG. 1, a plurality of MOSFETs (not shown) similar to those of the MOSFET unit 104 are formed adjacent to the MOSFET unit 104 in the left direction of FIG. 1.
  • the MOSFET unit 101 and the MOSFET units 102 to 104 have slightly different structures. That is, the MOSFET unit 100 is configured to include two types of MOSFETs having different structures. First, the MOSFET units 102 to 104 will be described.
  • an N ⁇ -type drift region 2 serving as the drain region of MOSFET units 102 to 104 is formed on the surface side of the N ⁇ type drift region 2.
  • a P ⁇ type well region 3 in which the channels of the MOSFET units 102 to 104 are formed is formed on the surface side of the well region 3.
  • a P + -type first well contact region 4 and N + -type source regions 5 of the MOSFET units 102 to 104 are formed.
  • a trench (groove) deeper than the well region 3 and reaching the drift region 2 is formed so as to be sandwiched between the source regions 5, and the gates of the MOSFET units 102 to 104 are formed in the trench.
  • An insulating film 6 and a gate electrode 7 are formed.
  • the source region 5 is in contact with the side surface of the trench, and is formed on both sides of the trench with the trench as a boundary.
  • the first well contact region 4 and the source region 5 are arranged along the direction in which the trenches are arranged.
  • An ohmic electrode 9 is formed in the first well contact region 4 and the source region 5 so as to make an ohmic connection with low resistance.
  • a source electrode 12 is formed on the ohmic electrode 9. The source electrode 12 and the gate electrode 7 are insulated by the interlayer insulating film 8.
  • a drain electrode 10 is formed in an ohmic connection with low resistance.
  • each of the MOSFET units 102 to 104 includes a common gate electrode 7 formed in the trench and a drift region 2 as a drain region, and one source region 5 formed on the left and right sides of the trench. Two MOSFETs are provided.
  • the MOSFET unit 101 is different from the MOSFET units 102 to 104 in that the source region 5 is not formed on the side surface of the trench adjacent to the diode unit 200, as compared with the configuration of the MOSFETs 102 to 104. That is, the source region 5 included in the MOSFET unit 101 adjacent to the diode part 200 is formed only on the adjacent MOSFET unit 102 side with the trench as a boundary. In other words, the source region 5 included in the MOSFET unit 101 adjacent to the diode unit 200 includes the MOSFET side surface of the MOSFET unit 101 that is close to the trench of the diode unit 200 and the MOSFET that is far from the trench of the diode unit 200.
  • the MOSFET unit 101 includes one MOSFET including the gate electrode 7 and the drain region formed inside the trench, and the source region 5 formed on one side of the trench with the trench as a boundary. Thereby, a MOSFET channel is not formed in the well region 3 between the diode part 200 and the trench in which the gate electrode 7 is formed.
  • the unipolar diode unit 200 will be described.
  • a trench (groove) having a depth deeper than the well region 3 and reaching the drift region 2 is formed in the same manner as the trench in the MOSFET portion 100, and the diode portion 200 is formed inside the trench.
  • An anode electrode 13 is formed. Therefore, the diode part 200 is configured as one diode having the anode electrode 13 and the drift region 2 as a cathode.
  • Anode electrode 13 is made of a material having a band gap different from that of silicon carbide substrate 1.
  • N - consists -type silicon carbide epitaxial layer N - -type drift region 2.
  • Silicon carbide substrate 1 has a thickness of about several tens to several hundreds of ⁇ m.
  • the drift region 2 is formed, for example, with an impurity concentration of about 10 14 to 10 18 cm ⁇ 3 and a thickness of about several ⁇ m to several tens of ⁇ m.
  • an insulating film (not shown) serving as a mask material is deposited on the drift region 2.
  • a silicon oxide film can be used as the insulating film, and a thermal CVD method or a plasma CVD method can be used as the deposition method.
  • a resist (not shown) is patterned on the insulating film.
  • a patterning method a general photolithography method can be used.
  • the insulating film is etched using the patterned resist as a mask.
  • etching method wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used.
  • P type impurities are ion-implanted using the insulating film as a mask to form a P ⁇ type well region 3.
  • Aluminum or boron can be used as the P-type impurity.
  • the insulating film is removed by etch etching using, for example, hydrofluoric acid.
  • the depth of the well region 3 needs to be shallower than that of the N ⁇ -type drift region 2. It can be several ⁇ m to several ⁇ m.
  • the steps of mask material formation, mask material patterning, impurity implantation, and mask material removal are repeated twice, and the P + type well contact region 4 and N in the well region 3 are repeated.
  • a + type source region 5 is formed.
  • an impurity to be implanted to form the well contact region 4 aluminum or boron can be used as in the process shown in FIG.
  • Nitrogen or phosphorus can be used as an impurity to be implanted to form the source region 5.
  • the depth of the well contact region 4 and the source region 5 must be shallower than that of the well region 3. The depth can be about several ⁇ m to several ⁇ m.
  • the impurities implanted in the steps shown in FIGS. 3 and 4 are activated by heat treatment.
  • a temperature of about 1700 ° C. can be used as the heat treatment temperature, and argon or nitrogen can be suitably used as the atmosphere.
  • the drift region 2 and the well region 3 are parallel to the cross section of FIG. 1 in the depth direction by dry etching using a resist patterned by the photophysographic technique as a mask.
  • the trench 14 is formed by deeply removing and deepening.
  • the source region 5 and the drift region 2 are electrically connected to each other through an inversion layer formed on the side surface of the gate electrode 7 formed in the trench 14.
  • the gate insulating film 6 is deposited on the inner wall of the trench 14 and the drift region 2 to a thickness of about 10 to 100 nm, for example.
  • a silicon oxide film is preferably used as the gate insulating film 6, and a thermal oxidation method, a thermal CVD method, a plasma CVD method, a sputtering method, or the like is used as a deposition method.
  • an annealing process is performed in an atmosphere of about 1000 ° C. such as nitrogen, argon, N 2 O 2 or the like in order to reduce the interface state at the interface between the drift region 2 and the gate insulating film 6. May be performed.
  • the gate insulating film 6 of the trench 14 in which the anode electrode 13 of the diode part 200 is formed is removed.
  • a removing method a general photolithography method can be used. That is, the gate insulating film 6 is selectively etched and removed using the patterned resist as a mask.
  • an etching method wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used. Thereafter, the resist is removed with oxygen plasma or sulfuric acid.
  • a deposition method a general low-pressure CVD method can be used.
  • the entire surface is etched back to remove the polycrystalline silicon other than the inside of the trench 14.
  • a resist pattern is formed on the polycrystalline silicon, the polycrystalline silicon is patterned using, for example, dry etching, and polycrystalline silicon other than the inside of the trench 14 is selectively removed.
  • productivity can be improved by forming the gate electrode 7 and the anode electrode 13 simultaneously.
  • an interlayer insulating film 8 is formed on the entire surface.
  • a silicon oxide film is preferably used.
  • an insulating film can be deposited by a thermal CVD method, a plasma CVD method, a sputtering method, or the like.
  • the interlayer insulating film 8 other than the upper part of the trench 14 is selectively removed, so that the interlayer insulating film 8 remains only on the upper part of the trench 14 and the periphery of the gate electrode 7 is insulated. Insulated with a membrane.
  • a selective removal method a resist pattern is formed on the interlayer insulating film 8, and the interlayer insulating film 8 other than the upper portion of the trench 14 is selectively removed using the resist pattern as a mask.
  • the polycrystalline silicon of the gate electrode 7 is thermally oxidized to form the interlayer insulating film 8 on the gate electrode 7. It can also be formed selectively.
  • an ohmic electrode 9 is formed so as to be in ohmic contact with the well contact region 4, the source region 5 and the anode electrode 13 with low resistance, and on the back surface of the silicon carbide substrate 1 with ohmic resistance with low resistance.
  • a drain electrode 10 is formed so as to be connected.
  • nickel silicide is preferably used, but metals such as cobalt silicide and titanium silicide may be used.
  • nickel is deposited in a region inside the well region 3 and then selectively removed by patterning.
  • nickel is similarly deposited on the back surface of the silicon carbide substrate 1.
  • annealing is performed at a temperature of about 1000 ° C., and SiC and nickel are alloyed to form nickel silicide.
  • the ohmic electrode 9 and the drain electrode 10 are formed.
  • a method for depositing nickel As a method for depositing nickel, vapor deposition, sputtering, CVD, or the like can be used.
  • a patterning method As a patterning method, a lift-off method can be preferably used, but a dry etching method or a wet etching method may be used.
  • a metal to be the source electrode 12 is deposited, and the metal deposited in the region such as the outer periphery is selectively removed by patterning and electrically connected to the ohmic electrode 9.
  • a source electrode 12 is formed.
  • a patterning method dry etching, wet etching, a lift-off method, or the like using a resist as a mask can be used.
  • Such a diode built-in type MOSFET can be used as a power conversion element of a power conversion device such as an inverter for driving a motor of an electric vehicle or the like.
  • the MOSFET with a built-in diode functions as a switching element in the forward direction operation, and functions as a passive element in the reverse direction operation that is a so-called reflux operation.
  • the diode-embedded MOSFET functions as a transistor by controlling the potential of the gate electrode 7 with a predetermined positive potential applied to the drain electrode 10 with the potential of the source electrode 12 as a reference.
  • the diode built-in type MOSFET functions as a free-wheeling diode because a reverse current flows from the drain electrode 10 to the source electrode 12 through the diode unit 200. To do.
  • the diode part 200 is formed with the gate electrode 7 as a boundary.
  • a source region is not formed in the well region 3 on the adjacent side. That is, in the MOSFET unit 101, no MOSFET is formed on the diode part 200 side with the gate electrode 7 as a boundary. Therefore, when the transistor is in the ON state, as shown in FIG. 13, no channel is formed in the well region 3 on the side adjacent to the diode part 200, and no channel is formed in the well region 3 on the side adjacent to the MOSFET unit 102. It is formed. Therefore, the current of the MOSFET spreads and flows from the well region 3 where the channel is formed to the drift region 2 as indicated by reference numeral I13 in FIG.
  • the diode part 200 side is also provided.
  • a MOSFET is formed. Therefore, a channel is also formed on the diode part 200 side with the gate electrode 7 as a boundary.
  • the current flowing through the channel formed adjacent to the diode portion 200 is as indicated by reference numeral I14 in FIG. That is, since no current flows in the diode part 200, the current flowing through the channel formed adjacent to the diode part 200 is easily diffused and spread to the diode part 200 side of the drift region 2.
  • the current spread indicated by reference numeral I14 is larger than the current spread indicated by reference numeral I13. For this reason, since the current density of the current flowing through the channel formed adjacent to the diode part 200 is lower than the current flowing through the channel not formed adjacent to the diode part 200, the voltage drop is reduced, It becomes easier for current to flow. As a result, current may concentrate on the MOSFET adjacent to the diode part 200, which may easily cause element destruction.
  • the current spread in the drift region 2 when turned on is as indicated by reference numeral I13 in FIG. . That is, the currents flowing through the channels in the MOSFETs adjacent to each other interfere with each other and do not spread greatly in the lateral direction. For this reason, the current density is higher than the case where the current spreads as indicated by reference numeral I14 in FIG. 14, the voltage drop is increased accordingly, and the current does not flow easily.
  • the currents in the MOSFETs constituting the MOSFET units 101 to 104 are all uniform, and it is possible to avoid a problem that the current is concentrated on a specific element. Thereby, destruction of the element due to current concentration can be prevented.
  • the inversion layer disappears and changes from the on state to the off state, thereby interrupting the current.
  • the inversion layer functions as a transistor of a switching element that conducts / cuts off current.
  • This reflux operation is an operation required in a circuit such as an inverter having an inductance such as an electric motor as a load.
  • a predetermined negative potential is applied to the drain electrode 10 with reference to the potential of the source electrode 12.
  • the transistor of the first embodiment includes a PN-type diode formed by an N ⁇ -type drift region 2 and a P ⁇ -type well region 3 and a unipolar diode portion 200.
  • the anode electrode 13 is formed so that the ON voltage of the diode section 200 is, for example, an ON voltage lower than about 2.5 V that is the ON voltage of the PN diode.
  • the reflux current mainly flows through the diode part 200 having a low on-voltage. Therefore, the on-voltage can be lowered and the steady loss can be further reduced as compared with the case where the unipolar diode unit 200 is not incorporated.
  • the diode part 200 is a unipolar type, it has the advantageous characteristic effect that there are few reverse recovery electric charges compared with bipolar type diodes, such as a PN diode. Therefore, it is possible to further reduce the switching loss when switching from the state in which the current flows through the diode unit 200 to the state in which the current is interrupted.
  • the time for which the MOSFET constituting the inverter that supplies power to the electric motor is in the on state is longer than the time in the free state where the free wheel diode is in the on state.
  • FIG. 15 shows an example of electrical characteristics in the conductive state and the reflux state in the semiconductor device having the configuration shown in FIG.
  • reference symbols D1 and M1 indicated by broken lines indicate semiconductors of related technology in which switching transistors and free-wheeling diodes are connected in parallel at a ratio of 1: 1 as described in Japanese Patent No. 40669946. The characteristics of the device are shown.
  • Reference symbol D1 indicates the current-voltage characteristic of the unipolar diode (circulation state), and M1 indicates the current-voltage characteristic (conduction state) of the MOSFET.
  • symbols D2 and M2 indicated by solid lines indicate the characteristics of the semiconductor device that is employed in the first embodiment and includes the switching transistor and the reflux diode at a ratio of n: 1. n represents a number larger than 2. Symbol D2 indicates the current-voltage characteristic (reflux state) of the diode section 200, and M2 indicates the current-voltage characteristic (conduction state) of the MOSFET.
  • the symbol D3 indicates the current-voltage characteristic of the built-in PN diode included in the MOSFET described above.
  • the current region serving as the operating point is assumed to be I1.
  • the on-voltage of the MOSFET is the driving point MP1
  • the on-voltage of the diode is the driving point DP1.
  • the MOSFET originally has a higher on-voltage and a higher time ratio at which the MOSFET is in a conductive state. For this reason, the MOSFET tends to be lossy. That is, the sum of the conduction loss and the return loss increases the loss of the MOSFET portion having a high time ratio, so that the loss of the entire device is large.
  • the driving point MP2 of the MOSFET unit 100 is lower than the driving point DP2 of the diode unit 200 in the current region I1. That is, the on-resistance of the MOSFET unit 100 is reduced by increasing the ratio of the MOSFETs connected in parallel constituting the MOSFET unit 100 with respect to one diode unit 200 as compared with the related art. Thereby, the resistance ratio which the MOSFET part 100 in the whole apparatus occupies can be restrained low. Thereby, the loss of a conduction
  • the area of the region where the plurality of MOSFET units 101 to 104 are formed on the surface of the silicon carbide substrate 1 may be larger than the area of the region where the diode part 200 is formed. Thereby, the on-resistance of the MOSFET part 100 can be reduced.
  • the resistance ratio of the entire device is lost as a ratio as shown below, for example. Try to estimate.
  • the resistance ratio in the related art is 1 (MOSFET): 1 (diode).
  • the resistance ratio in the first embodiment is about 0.6 (MOSFET portion 100): 1.4 (diode portion 200). It becomes possible.
  • the ratio of the time during which the MOSFET is in the on state and the time during which the diode is in the on state is, for example, about 0.66: 0.34.
  • the loss during operation of the entire device is 10 times that of the related art. % Can be reduced.
  • the diode part 200 is formed so that the drive point DP2 of the diode part 200 is lower than the drive point DP3 of the built-in PN diode.
  • the drive point DP2 is lower than DP3
  • the return current flows to the diode unit 200.
  • the trench in which the anode electrode 13 of the diode part 200 is formed is preferably disposed between the MOSFET parts 100. Thereby, the number of trenches of the MOSFET unit adjacent to the trench of the diode part 200 can be reduced. As a result, the formation region of the MOSFET portion 100 can be increased.
  • the source region 5 provided in the MOSFET unit 101 adjacent to the diode part 200 is formed only on the adjacent MOSFET unit 102 side. In this case, it is desirable that four or more trenches (gate electrodes 7) of the MOSFET unit are formed continuously.
  • M represents one trench constituting the gate electrode of the MOSFET unit
  • a vertical line below it represents a channel of the MOSFET
  • “D” represents a diode. Therefore, in FIG. 16, when there are two vertical lines corresponding to the trench represented by “M”, this indicates that two MOSFET channel regions are formed on both sides of the trench. In the case of one, one channel region of the MOSFET is formed only on one side of the trench (the side far from the diode).
  • (a1) to (a5) show a configuration related to a related technique in which MOSFETs and diodes are alternately arranged, and (b1) to (b5) are embodiments in which MOSFETs are continuously formed. 1 is shown.
  • the number of MOSFET channels is four as shown in FIG. 16 (b1).
  • the same number of MOSFETs and diodes as in FIG. 16B1 are alternately formed, six channels of MOSFETs are formed as shown in FIG. 16A1.
  • FIG. 16 (b2) when four MOSFETs are formed continuously, six channels of MOSFETs are formed as shown in FIG. 16 (b2).
  • FIG. 16 (a2) when the same number of MOSFETs and diodes as in FIG. 16 (b2) are alternately formed, six channels of MOSFETs are formed as shown in FIG. 16 (a2).
  • the number of MOSFET channels is eight as shown in FIG. 16 (b3).
  • the number of MOSFET channels is 8 as shown in FIG. 16A3.
  • the number of MOSFET channels is ten.
  • the number of MOSFET channels is 8 as shown in FIG. 16 (a4).
  • the size of the channel region of the MOSFET unit 100 as a whole can be obtained without forming two MOSFETs in the MOSFET unit 101 adjacent to the diode unit 200. Can be ensured to be equal to or more than the related technology.
  • FIG. 17 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 2 of the present invention.
  • the semiconductor device of the second embodiment is different from the configuration of the first embodiment in the following points. That is, the distance L 2 between the trench of the MOSFET unit 101 at the end of the MOSFET unit 100 and the anode electrode 13 of the diode unit 200 is shorter than the distance L 1 between the trenches of the MOSFET unit 100. As a result, the degree of integration of the semiconductor device can be further increased, and the chip can be miniaturized.
  • FIG. 18 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 3 of the present invention.
  • the semiconductor device of the third embodiment is different from the configuration of the first embodiment in the following points. That is, the width L3 of the trench of the diode part 200 is larger than the width L4 of the trench of the MOSFET part 100. Thereby, even if the number of the diode parts 200 is reduced, the area of the diode part 200 can be increased, so that an increase in the on-resistance of the diode part 200 can be prevented.
  • FIG. 19 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 4 of the present invention.
  • the semiconductor device of the fourth embodiment is different from the configuration of the first embodiment in the following points. That is, the P + -type second well contact region 16 is provided on the surface of the well region 3 so as to be in contact with the ohmic electrode 9 between the diode portion 200 and the MOSFET portion 100. Thereby, the electrical resistance between the source electrode 12 and the anode electrode 13 of the diode part 200 can be reduced.
  • the depletion layer extending from the anode electrode 13 of the diode part 200 to the drift region 2 is stabilized, and the stability at the time of off can be improved. it can.
  • FIG. 20 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 5 of the present invention
  • FIG. 21 is a cross-sectional view seen from the upper surface (source electrode 12) side along the line AA in FIG.
  • the semiconductor device of the fifth embodiment is different from the configuration of the first embodiment in the following points. That is, the source region 5 is formed so as to be in contact with and sandwiched by the trench of the MOSFET unit 100. Further, as shown in FIG. 21, the well contact region 4 is formed so as to be in contact with and sandwiched by the trench of the MOSFET portion 100.
  • the source regions 5 and the well contact regions 4 are alternately and continuously arranged in a direction orthogonal to the direction in which the first grooves are arranged.
  • the source region 5 and the well contact region 4 can be formed even when the interval between the trenches of the MOSFET portion 100 is narrower than the interval between the trenches shown in FIG. .
  • the formation density of the MOSFET portion 100 can be increased, and the device can be miniaturized.
  • FIG. 22 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 6 of the present invention.
  • the semiconductor device of the sixth embodiment is different from the configuration of the first embodiment in the following points. That is, each of the plurality of MOSFET units 101 to 104 includes a source region 5 formed on the well region 3 in contact with the trench and formed on both sides of the trench with the trench as a boundary.
  • the plurality of MOSFET units among the source regions 5 included in the transistor unit 101 adjacent to the diode unit 200, the width of the source region 5 formed on the diode unit 200 side is formed on the other adjacent MOSFET unit 102 side. The width of the source region 5 is narrower.
  • the spread I15 of the current flowing through the channel of the MOSFET formed on the diode section 200 side is smaller than I13 shown in FIG. 14 and I14 shown in FIG.
  • the current density of the MOSFET adjacent to the diode part 200 is increased, the voltage drop is increased accordingly, and the current is less likely to flow. Therefore, current concentration on the MOSFET adjacent to the diode portion 200 is suppressed, and element destruction due to current concentration can be prevented.
  • the chip area can be reduced and the formation cost of the source region 5 can be reduced.
  • the source region included in the transistor unit adjacent to the diode is formed only on the other adjacent transistor unit side with the first groove as a boundary. ing.
  • the width of the source region formed on the diode side is narrower than the width of the source region formed on the other adjacent transistor unit side.

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Abstract

Provided is a semiconductor device having: a transistor section which is provided with a plurality of transistor units that are adjacent to each other; and a diode which is adjacent to the transistor section. Each of the transistor units is provided with a first conductivity type drift region to be a drain region, a second conductivity type well region formed on the drift region, a gate electrode formed inside of a first trench, and a first conductivity type source region formed on the well region by being in contact with the first trench. The source region provided in the transistor unit adjacent to the diode is formed only on the side of other adjacent transistor unit by having the first trench as a boundary. Alternatively, in the source region provided in the transistor unit adjacent to the diode, the width of the source region formed on the diode side is smaller than that of the source region formed on the side of other adjacent transistor unit.

Description

半導体装置Semiconductor device
　本発明は、スイッチング素子として用いられる半導体装置に関する。 The present invention relates to a semiconductor device used as a switching element.
　従来、この種の技術としては、例えば以下に示す文献に記載されたものが知られている（特許文献１参照）。特許文献１には、炭化珪素の半導体基板に形成された、ＭＯＳ型の電界効果トランジスタ（ＭＯＳＦＥＴ）と、ヘテロ接合を有するユニポーラ型のダイオードとを備えて構成され、スイッチング素子として機能する半導体装置が記載されている。 Conventionally, as this type of technology, for example, those described in the following documents are known (see Patent Document 1). Patent Document 1 discloses a semiconductor device that includes a MOS field effect transistor (MOSFET) formed on a silicon carbide semiconductor substrate and a unipolar diode having a heterojunction and functions as a switching element. Are listed.
特許第４０６６９４６号公報Japanese Patent No. 40669946
　ダイオードに隣接するＭＯＳＦＥＴにおいて、ゲート電極を境にしてダイオード側のウェル領域にソース領域を形成した場合には、ダイオードに隣接する側のゲート電極の側面にＭＯＳＦＥＴのチャネルが形成される。ダイオードに隣接して形成されるチャネルを流れる電流の拡がりは、ＭＯＳＦＥＴのゲート電極同士が隣接する部分に流れる電流の拡がりに比べて大きくなる。このため、チャネルを流れる電流密度は、ダイオードに隣接して形成されるチャネルの方が低いため、電圧降下が小さくなり、電流が流れやすくなる。この結果、ダイオードに隣接する側のゲート電極の側面に形成されるＭＯＳＦＥＴに電流が集中して、素子破壊を招きやすくなるおそれがあった。 In the MOSFET adjacent to the diode, when the source region is formed in the well region on the diode side with the gate electrode as a boundary, the channel of the MOSFET is formed on the side surface of the gate electrode adjacent to the diode. The spread of the current flowing through the channel formed adjacent to the diode is larger than the spread of the current flowing through the portion where the gate electrodes of the MOSFETs are adjacent to each other. For this reason, since the current density flowing through the channel is lower in the channel formed adjacent to the diode, the voltage drop becomes smaller and the current flows more easily. As a result, there is a possibility that current is concentrated on the MOSFET formed on the side surface of the gate electrode adjacent to the diode, which easily causes element destruction.
　そこで、本発明は、電流集中による素子の破壊を抑制する半導体装置を提供することを目的とする。 Therefore, an object of the present invention is to provide a semiconductor device that suppresses element destruction due to current concentration.
　上記目的を達成するために、本発明の一態様は、互いに隣接する複数のトランジスタユニットを備えるトランジスタ部と、トランジスタ部に隣接するダイオードと、を有する半導体装置である。複数のトランジスタユニットの各々は、トランジスタユニットのドレイン領域となる第１導電型のドリフト領域と、ドリフト領域上に形成された第２導電型のウェル領域と、ドリフト領域およびウェル領域に形成された第１の溝の内部に、絶縁膜を介して形成されたゲート電極と、第１の溝に接してウェル領域上に形成された第１導電型のソース領域と、を備える。複数のトランジスタユニットのうち、ダイオードに隣接するトランジスタユニットが備えるソース領域は、第１の溝を境にして、隣接する他のトランジスタユニット側にのみ形成されている。或いは、ダイオードに隣接するトランジスタユニットが備えるソース領域のうち、ダイオード側に形成されたソース領域の幅は、隣接する他のトランジスタユニット側に形成されたソース領域の幅よりも狭い。 In order to achieve the above object, one embodiment of the present invention is a semiconductor device including a transistor portion including a plurality of transistor units adjacent to each other and a diode adjacent to the transistor portion. Each of the plurality of transistor units includes a first conductivity type drift region serving as a drain region of the transistor unit, a second conductivity type well region formed on the drift region, and a first conductivity type formed in the drift region and the well region. A gate electrode formed through an insulating film and a source region of a first conductivity type formed on the well region in contact with the first trench are provided inside the one trench. Among the plurality of transistor units, the source region provided in the transistor unit adjacent to the diode is formed only on the other adjacent transistor unit side with the first groove as a boundary. Alternatively, among the source regions included in the transistor unit adjacent to the diode, the width of the source region formed on the diode side is narrower than the width of the source region formed on the other adjacent transistor unit side.
　本発明の一態様によれば、特定の素子に電流が集中することが抑制され、これにより、電流集中による素子の破壊を抑制することができる。 According to one embodiment of the present invention, it is possible to suppress current concentration on a specific element, thereby suppressing element destruction due to current concentration.
図１は、本発明の実施形態１に係る半導体装置の構成を示す断面図である。FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. 図２は、図１の半導体装置の製造方法の一例を示す第１の工程断面図である。FIG. 2 is a first process cross-sectional view illustrating an example of a method for manufacturing the semiconductor device of FIG. 図３は、図１の半導体装置の製造方法の一例を示す第２の工程断面図である。FIG. 3 is a second process cross-sectional view illustrating an example of a method of manufacturing the semiconductor device of FIG. 図４は、図１の半導体装置の製造方法の一例を示す第３の工程断面図である。FIG. 4 is a third process cross-sectional view illustrating an example of a method for manufacturing the semiconductor device of FIG. 図５は、図１の半導体装置の製造方法の一例を示す第４の工程断面図である。FIG. 5 is a fourth process cross-sectional view illustrating an example of a method of manufacturing the semiconductor device of FIG. 図６は、図１の半導体装置の製造方法の一例を示す第５の工程断面図である。FIG. 6 is a fifth process cross-sectional view illustrating an example of the method for manufacturing the semiconductor device of FIG. 図７は、図１の半導体装置の製造方法の一例を示す第６の工程断面図である。FIG. 7 is a sixth process cross-sectional view illustrating an example of the method for manufacturing the semiconductor device of FIG. 図８は、図１の半導体装置の製造方法の一例を示す第７の工程断面図である。FIG. 8 is a seventh process cross-sectional view illustrating an example of a method of manufacturing the semiconductor device of FIG. 図９は、図１の半導体装置の製造方法の一例を示す第８の工程断面図である。FIG. 9 is an eighth process cross-sectional view illustrating an example of a method of manufacturing the semiconductor device of FIG. 図１０は、図１の半導体装置の製造方法の一例を示す第９の工程断面図である。FIG. 10 is a ninth process cross-sectional view illustrating an example of the method for manufacturing the semiconductor device of FIG. 図１１は、図１の半導体装置の製造方法の一例を示す第１０の工程断面図である。11 is a cross-sectional view of a tenth process showing an example of the method for manufacturing the semiconductor device of FIG. 図１２は、図１の半導体装置の製造方法の一例を示す第１１の工程断面図である。12 is an eleventh process cross-sectional view illustrating an example of a method for manufacturing the semiconductor device of FIG. 図１３は、図１のＭＯＳＦＥＴユニット１０１のトレンチの片側にのみソース領域５が形成されている場合における、電流の拡がりの様子Ｉ１３を示す図である。FIG. 13 is a diagram showing a current spreading state I13 when the source region 5 is formed only on one side of the trench of the MOSFET unit 101 of FIG. 図１４は、図１のＭＯＳＦＥＴユニット１０１のトレンチの両側にソース領域５が形成されている場合における、電流の拡がりの様子Ｉ１３、Ｉ１４を示す図である。FIG. 14 is a diagram showing current spreading states I13 and I14 when the source region 5 is formed on both sides of the trench of the MOSFET unit 101 of FIG. 図１５は、本発明の実施形態１に係る半導体装置及び関連技術に係わる半導体装置における、電流－電圧特性を示すグラフである。FIG. 15 is a graph showing current-voltage characteristics in the semiconductor device according to Embodiment 1 of the present invention and the semiconductor device according to the related art. 図１６の（ａ１）～（ａ５）は、ＭＯＳＦＥＴを連続して配置しない場合のチャネル領域の大きさを示す図であり、図１６の（ｂ１）～（ｂ５）は、ＭＯＳＦＥＴを連続して配置した場合のチャネル領域の大きさを示す図である。(A1) to (a5) of FIG. 16 are diagrams showing the size of the channel region when the MOSFETs are not continuously arranged, and (b1) to (b5) of FIG. 16 are the MOSFETs arranged continuously. It is a figure which shows the magnitude | size of the channel area | region in the case of doing. 図１７は、本発明の実施形態２に係る半導体装置の構成を示す断面図である。FIG. 17 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 2 of the present invention. 図１８は、本発明の実施形態３に係る半導体装置の構成を示す断面図である。FIG. 18 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 3 of the present invention. 図１９は、本発明の実施形態４に係る半導体装置の構成を示す断面図である。FIG. 19 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 4 of the present invention. 図２０は、本発明の実施形態５に係る半導体装置の構成を示す断面図である。FIG. 20 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 5 of the present invention. 図２１は、図２０のＡ－Ａ線に沿った断面を上面からみた断面図である。FIG. 21 is a cross-sectional view of a cross section taken along line AA of FIG. 20 as viewed from above. 図２２は、本発明の実施形態６に係る半導体装置の構成を示す断面図である。FIG. 22 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 6 of the present invention.
　以下、図面を用いて本発明を実施するための実施形態を説明する。 Hereinafter, an embodiment for carrying out the present invention will be described with reference to the drawings.
（実施形態１）
　図１は本発明の実施形態１に係る半導体装置の構成を示す断面図である。図１に示す実施形態１の半導体装置は、並列接続されたの複数のＭＯＳ型のＦＥＴ（電界効果トランジスタ）で構成されたＭＯＳＦＥＴ部１００と、ユニポーラ型のダイオード部２００とを備えて構成されている。なお、図１ではＭＯＳＦＥＴ部１００とダイオード部２００との組み合わせが１組だけ図示されているが、半導体装置は、ＭＯＳＦＥＴ部１００とダイオード部２００との組み合わせを複数組備えて構成されている。 (Embodiment 1)
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. The semiconductor device of the first embodiment shown in FIG. 1 includes a MOSFET unit 100 composed of a plurality of MOS FETs (field effect transistors) connected in parallel and a unipolar diode unit 200. Yes. In FIG. 1, only one combination of the MOSFET unit 100 and the diode unit 200 is illustrated, but the semiconductor device includes a plurality of combinations of the MOSFET unit 100 and the diode unit 200.
　ＭＯＳＦＥＴ部１００は、複数のＭＯＳＦＥＴユニット１０１～１０４が並列接続されて構成されている。なお、図１では４つのＭＯＳＦＥＴユニット１０１～１０４が図示されているが、ＭＯＳＦＥＴ部１００を構成するＭＯＳＦＥＴユニットの数は、４つに限定されることはなく、ＭＯＳＦＥＴ部１００で得ようとする駆動力に応じて適宜設定される。したがって、図１において、ＭＯＳＦＥＴユニット１０４には図１の左方向へ隣接して、ＭＯＳＦＥＴユニット１０４と同様のＭＯＳＦＥＴ（図示せず）が複数形成されている。 The MOSFET unit 100 is configured by connecting a plurality of MOSFET units 101 to 104 in parallel. Although four MOSFET units 101 to 104 are shown in FIG. 1, the number of MOSFET units constituting the MOSFET unit 100 is not limited to four, and the drive to be obtained by the MOSFET unit 100 It is set appropriately according to the force. Therefore, in FIG. 1, a plurality of MOSFETs (not shown) similar to those of the MOSFET unit 104 are formed adjacent to the MOSFET unit 104 in the left direction of FIG. 1.
　ここで、ＭＯＳＦＥＴ部１００を構成する図示されているＭＯＳＦＥＴユニット１０１～１０４の内、ＭＯＳＦＥＴユニット１０１とＭＯＳＦＥＴユニット１０２～１０４とはその構造が若干異なる。すなわち、ＭＯＳＦＥＴ部１００は、構造が異なる２種類のＭＯＳＦＥＴを備えて構成されている。先ず始めに、ＭＯＳＦＥＴユニット１０２～１０４について説明する。 Here, of the MOSFET units 101 to 104 shown in the figure constituting the MOSFET unit 100, the MOSFET unit 101 and the MOSFET units 102 to 104 have slightly different structures. That is, the MOSFET unit 100 is configured to include two types of MOSFETs having different structures. First, the MOSFET units 102 to 104 will be described.
　図１において、Ｎ＋型の炭化珪素基体１の表面（一方の主面）上には、ＭＯＳＦＥＴユニット１０２～１０４のドレイン領域となるＮ－型のドリフト領域２が形成されている。Ｎ－型のドリフト領域２の表面側には、ＭＯＳＦＥＴユニット１０２～１０４のチャネルが形成されるＰ－型のウェル領域３が形成されている。ウェル領域３の表面側には、Ｐ＋型の第１のウェルコンタクト領域４およびＭＯＳＦＥＴユニット１０２～１０４のＮ＋型のソース領域５が形成されている。 In FIG. 1, on the surface (one main surface) of an N + -type silicon carbide substrate 1, an N − -type drift region 2 serving as the drain region of MOSFET units 102 to 104 is formed. On the surface side of the N − type drift region 2, a P − type well region 3 in which the channels of the MOSFET units 102 to 104 are formed is formed. On the surface side of the well region 3, a P + -type first well contact region 4 and N + -type source regions 5 of the MOSFET units 102 to 104 are formed.
　ウェル領域３には、ウェル領域３の厚みよりも深くドリフト領域２に至る深さのトレンチ（溝）がソース領域５に挟まれるように形成され、このトレンチの内部にＭＯＳＦＥＴユニット１０２～１０４のゲート絶縁膜６とゲート電極７とが形成されている。ソース領域５は、トレンチの側面に接しており、また、トレンチを境として、トレンチの両側にそれぞれ形成されている。第１のウェルコンタクト領域４とソース領域５は、トレンチが並ぶ方向に沿って並べられている。 In the well region 3, a trench (groove) deeper than the well region 3 and reaching the drift region 2 is formed so as to be sandwiched between the source regions 5, and the gates of the MOSFET units 102 to 104 are formed in the trench. An insulating film 6 and a gate electrode 7 are formed. The source region 5 is in contact with the side surface of the trench, and is formed on both sides of the trench with the trench as a boundary. The first well contact region 4 and the source region 5 are arranged along the direction in which the trenches are arranged.
　第１のウェルコンタクト領域４およびソース領域５には、電気的に低抵抗でオーミック接続するようにオーミック電極９が形成されている。オーミック電極９上には、ソース電極１２が形成されている。ソース電極１２とゲート電極７とは、層間絶縁膜８で絶縁されている。 An ohmic electrode 9 is formed in the first well contact region 4 and the source region 5 so as to make an ohmic connection with low resistance. A source electrode 12 is formed on the ohmic electrode 9. The source electrode 12 and the gate electrode 7 are insulated by the interlayer insulating film 8.
　炭化珪素基体１の裏面（他方の主面）側には、ドレイン電極１０が電気的に低抵抗でオーミック接続されて形成されている。 On the back surface (the other main surface) side of the silicon carbide substrate 1, a drain electrode 10 is formed in an ohmic connection with low resistance.
　したがって、ＭＯＳＦＥＴユニット１０２～１０４の各々は、トレンチの内部に形成された共通のゲート電極７及びドレイン領域としてのドリフト領域２と、トレンチを挟んで左右に形成された一方のソース領域５とからなるＭＯＳＦＥＴを２つ備えている。 Therefore, each of the MOSFET units 102 to 104 includes a common gate electrode 7 formed in the trench and a drift region 2 as a drain region, and one source region 5 formed on the left and right sides of the trench. Two MOSFETs are provided.
　一方、ＭＯＳＦＥＴユニット１０１は、上記ＭＯＳＦＥＴ１０２～１０４の構成に比べて、ダイオード部２００に隣接している側のトレンチの側面にはソース領域５が形成されていない点がＭＯＳＦＥＴユニット１０２～１０４と異なる。すなわち、ダイオード部２００に隣接するＭＯＳＦＥＴユニット１０１が備えるソース領域５は、トレンチを境にして、隣接するＭＯＳＦＥＴユニット１０２側にのみ形成されている。換言すれば、ダイオード部２００に隣接するＭＯＳＦＥＴユニット１０１が備えるソース領域５は、ダイオード部２００のトレンチからの距離が近いＭＯＳＦＥＴユニット１０１のトレンチの側面と、ダイオード部２００のトレンチからの距離が遠いＭＯＳＦＥＴユニット１０１のトレンチの側面うち、ダイオード部２００のトレンチからの距離が遠いＭＯＳＦＥＴユニット１０１のトレンチの側面にのみ形成されている。したがって、ＭＯＳＦＥＴユニット１０１は、トレンチの内部に形成されたゲート電極７ならびにドレイン領域と、トレンチを境にトレンチの一方側に形成されたソース領域５とからなるＭＯＳＦＥＴを１つ備えている。これにより、ダイオード部２００とゲート電極７が形成されたトレンチとの間のウェル領域３には、ＭＯＳＦＥＴのチャネルが形成されることはない。 On the other hand, the MOSFET unit 101 is different from the MOSFET units 102 to 104 in that the source region 5 is not formed on the side surface of the trench adjacent to the diode unit 200, as compared with the configuration of the MOSFETs 102 to 104. That is, the source region 5 included in the MOSFET unit 101 adjacent to the diode part 200 is formed only on the adjacent MOSFET unit 102 side with the trench as a boundary. In other words, the source region 5 included in the MOSFET unit 101 adjacent to the diode unit 200 includes the MOSFET side surface of the MOSFET unit 101 that is close to the trench of the diode unit 200 and the MOSFET that is far from the trench of the diode unit 200. Of the side surfaces of the trench of the unit 101, the diode unit 200 is formed only on the side surface of the trench of the MOSFET unit 101 far from the trench. Therefore, the MOSFET unit 101 includes one MOSFET including the gate electrode 7 and the drain region formed inside the trench, and the source region 5 formed on one side of the trench with the trench as a boundary. Thereby, a MOSFET channel is not formed in the well region 3 between the diode part 200 and the trench in which the gate electrode 7 is formed.
　次に、ユニポーラ型のダイオード部２００について説明する。ウェル領域３には、先のＭＯＳＦＥＴ部１００におけるトレンチと同様に、ウェル領域３の厚みよりも深くドリフト領域２に至る深さのトレンチ（溝）が形成され、このトレンチの内部にダイオード部２００のアノード電極１３が形成されている。したがって、ダイオード部２００は、アノード電極１３とドリフト領域２をカソードとする１つのダイオードとして構成されている。アノード電極１３は、炭化珪素基体１とはバンドギャップが異なる材料で構成されている。 Next, the unipolar diode unit 200 will be described. In the well region 3, a trench (groove) having a depth deeper than the well region 3 and reaching the drift region 2 is formed in the same manner as the trench in the MOSFET portion 100, and the diode portion 200 is formed inside the trench. An anode electrode 13 is formed. Therefore, the diode part 200 is configured as one diode having the anode electrode 13 and the drift region 2 as a cathode. Anode electrode 13 is made of a material having a band gap different from that of silicon carbide substrate 1.
　次に、図２～図１２の工程断面図を参照して、上記図１に示す半導体装置の製造方法の一例を説明する。 Next, an example of a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to the process cross-sectional views of FIGS.
　まず、図２に示す工程においては、Ｎ＋型の炭化珪素基体１上に、Ｎ－型の炭化珪素エピタキシャル層からなるＮ－型のドリフト領域２を形成する。炭化珪素にはいくつかのポリタイプ（結晶多形）が存在するが、ここでは代表的な４Ｈとして説明する。炭化珪素基体１は、数十から数百μｍ程度の厚みを有する。ドリフト領域２は、例えば不純物濃度が１０１４～１０１８ｃｍ－３程度、厚さが数μｍ～数十μｍ程度として形成される。 First, in the step shown in FIG. 2, on the silicon carbide substrate 1 of the N + -type, N - consists -type silicon carbide epitaxial layer N - -type drift region 2. There are several polytypes (crystal polymorphs) in silicon carbide, but here it will be described as representative 4H. Silicon carbide substrate 1 has a thickness of about several tens to several hundreds of μm. The drift region 2 is formed, for example, with an impurity concentration of about 10 14 to 10 18 cm −3 and a thickness of about several μm to several tens of μm.
　次に図３に示す工程においては、ドリフト領域２上に、マスク材となる絶縁膜（図示せず）を堆積する。絶縁膜としてはシリコン酸化膜を用いることができ、堆積方法としては熱ＣＶＤ法やプラズマＣＶＤ法を用いることができる。 Next, in the step shown in FIG. 3, an insulating film (not shown) serving as a mask material is deposited on the drift region 2. A silicon oxide film can be used as the insulating film, and a thermal CVD method or a plasma CVD method can be used as the deposition method.
　続いて、絶縁膜上にレジスト（図示せず）をパターニングする。パターニングの方法としては、一般的なフォトリソグラフィー法を用いることができる。パターニングされたレジストをマスクにして、絶縁膜をエッチングする。エッチング方法としては、フッ酸を用いたウエットエッチングや、反応性イオンエッチングなどのドライエッチングを用いることができる。 Subsequently, a resist (not shown) is patterned on the insulating film. As a patterning method, a general photolithography method can be used. The insulating film is etched using the patterned resist as a mask. As an etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used.
　引き続いて、レジストを酸素プラズマや硫酸等で除去した後、絶縁膜をマスクにして、Ｐ型の不純物をイオン注入し、Ｐ－型のウェル領域３を形成する。Ｐ型の不純物としては、アルミやボロンを用いることができる。このときに、基体温度を６００℃程度に加熱した状態でイオン注入することで、注入領域に結晶欠陥が生じるのを抑制することができる。イオン注入後、絶縁膜を例えばフッ酸を用いたウエッチエッチングによって除去する。ウェル領域３の深さとしては、Ｎ－型のドリフト領域２より浅くする必要があり、０．数μｍ～数μｍ程度とすることができる。 Subsequently, after removing the resist with oxygen plasma, sulfuric acid or the like, P type impurities are ion-implanted using the insulating film as a mask to form a P − type well region 3. Aluminum or boron can be used as the P-type impurity. At this time, by performing ion implantation while the substrate temperature is heated to about 600 ° C., it is possible to suppress the occurrence of crystal defects in the implanted region. After the ion implantation, the insulating film is removed by etch etching using, for example, hydrofluoric acid. The depth of the well region 3 needs to be shallower than that of the N − -type drift region 2. It can be several μm to several μm.
　次に、図４に示す工程においては、マスク材の形成、マスク材のパターニング、不純物注入、マスク材の除去の工程を２回繰り返し、ウェル領域３内にＰ＋型のウェルコンタクト領域４ならびにＮ＋型のソース領域５を形成する。ウェルコンタクト領域４を形成するために注入する不純物は、先の図４に示す工程と同様にアルミやボロンを用いることができる。ソース領域５を形成するために注入する不純物は、窒素やリンを用いることができる。ウェルコンタクト領域４およびソース領域５の深さとしては、ウェル領域３より浅くする必要があり、０．数μｍ～数μｍ程度の深さとすることができる。 Next, in the step shown in FIG. 4, the steps of mask material formation, mask material patterning, impurity implantation, and mask material removal are repeated twice, and the P + type well contact region 4 and N in the well region 3 are repeated. A + type source region 5 is formed. As an impurity to be implanted to form the well contact region 4, aluminum or boron can be used as in the process shown in FIG. Nitrogen or phosphorus can be used as an impurity to be implanted to form the source region 5. The depth of the well contact region 4 and the source region 5 must be shallower than that of the well region 3. The depth can be about several μm to several μm.
　続いて、図３および図４に示す工程でイオン注入した不純物を熱処理することで活性化する。熱処理温度としては、１７００℃程度の温度を用いることができ、雰囲気としてはアルゴンや窒素を好適に用いることができる。 Subsequently, the impurities implanted in the steps shown in FIGS. 3 and 4 are activated by heat treatment. A temperature of about 1700 ° C. can be used as the heat treatment temperature, and argon or nitrogen can be suitably used as the atmosphere.
　次に、図５に示す工程においては、フォトフィソグラフィー技術によりパターニングしたレジストをマスクにして、ドライエッチングを用いて図１の断面に対して奥行き方向に平行に、ドリフト領域２ならびにウェル領域３を選択的に除去して深堀し、トレンチ（溝）１４を形成する。トレンチ１４の深さは、ウェル領域３より深く形成することで、トレンチ１４内に形成されるゲート電極７の側面に形成される反転層を介してソース領域５とドリフト領域２を電気的に導通させることができる。このとき、ゲート電極７が内部に形成されるゲート電極７用のトレンチ１４と、ユニポーラ型のダイオード部２００のアノード電極１３が形成されるアノード電極１３用のトレンチ１４を同時に形成することが可能である。これにより、生産性を向上することができる。 Next, in the step shown in FIG. 5, the drift region 2 and the well region 3 are parallel to the cross section of FIG. 1 in the depth direction by dry etching using a resist patterned by the photophysographic technique as a mask. Then, the trench 14 is formed by deeply removing and deepening. By forming the trench 14 deeper than the well region 3, the source region 5 and the drift region 2 are electrically connected to each other through an inversion layer formed on the side surface of the gate electrode 7 formed in the trench 14. Can be made. At this time, it is possible to simultaneously form the trench 14 for the gate electrode 7 in which the gate electrode 7 is formed and the trench 14 for the anode electrode 13 in which the anode electrode 13 of the unipolar diode portion 200 is formed. is there. Thereby, productivity can be improved.
　次に、図６に示す工程においては、トレンチ１４の内壁およびドリフト領域２上にゲート絶縁膜６を例えば１０～１００ｎｍ程度堆積する。ゲート絶縁膜６としてはシリコン酸化膜が好適に用いられ、堆積方法としては熱酸化法、熱ＣＶＤ法、プラズマＣＶＤ法、スパッタ法などが用いられる。なお、ゲート絶縁膜６を堆積後、ドリフト領域２とゲート絶縁膜６の界面の界面準位を低減するために、窒素、アルゴン、Ｎ２Ｏ 等の１０００℃程度の温度の雰囲気中でアニール処理を行ってもよい。 Next, in the process shown in FIG. 6, the gate insulating film 6 is deposited on the inner wall of the trench 14 and the drift region 2 to a thickness of about 10 to 100 nm, for example. A silicon oxide film is preferably used as the gate insulating film 6, and a thermal oxidation method, a thermal CVD method, a plasma CVD method, a sputtering method, or the like is used as a deposition method. After the gate insulating film 6 is deposited, an annealing process is performed in an atmosphere of about 1000 ° C. such as nitrogen, argon, N 2 O 2 or the like in order to reduce the interface state at the interface between the drift region 2 and the gate insulating film 6. May be performed.
　次に、図７に示す工程においては、ダイオード部２００のアノード電極１３が形成される一部のトレンチ１４のゲート絶縁膜６を除去する。除去方法としては、一般的なフォトリソグラフィー法を用いることができる。すなわち、パターニングされたレジストをマスクにして、ゲート絶縁膜６を選択的にエッチングして除去する。エッチング方法としては、フッ酸を用いたウエットエッチングや、反応性イオンエッチングなどのドライエッチングを用いることができる。その後、レジストを酸素プラズマや硫酸等で除去する。 Next, in the process shown in FIG. 7, the gate insulating film 6 of the trench 14 in which the anode electrode 13 of the diode part 200 is formed is removed. As a removing method, a general photolithography method can be used. That is, the gate insulating film 6 is selectively etched and removed using the patterned resist as a mask. As an etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used. Thereafter, the resist is removed with oxygen plasma or sulfuric acid.
　次に、図８に示す工程においては、ゲート電極７およびアノード電極１３を構成する、例えば不純物を導入した多結晶シリコン１５を全面に堆積し、多結晶シリコン１５でトレンチ１４を埋め込む。堆積方法としては一般的な低圧ＣＶＤ法を用いることができる。 Next, in the process shown in FIG. 8, for example, polycrystalline silicon 15 into which the gate electrode 7 and the anode electrode 13 are introduced, for example, impurities are introduced, is deposited on the entire surface, and the trench 14 is embedded with the polycrystalline silicon 15. As a deposition method, a general low-pressure CVD method can be used.
　次に、図９に示す工程においては、全面をエッチバックしてトレンチ１４の内部以外の多結晶シリコンを除去する。または、多結晶シリコン上にレジストパターンを形成し、例えばドライエッチングを用いて多結晶シリコンをパターニングし、トレンチ１４の内部以外の多結晶シリコンを選択的に除去する。このように、ゲート電極７およびアノード電極１３を同時に形成することで、生産性を向上することができる。 Next, in the step shown in FIG. 9, the entire surface is etched back to remove the polycrystalline silicon other than the inside of the trench 14. Alternatively, a resist pattern is formed on the polycrystalline silicon, the polycrystalline silicon is patterned using, for example, dry etching, and polycrystalline silicon other than the inside of the trench 14 is selectively removed. Thus, productivity can be improved by forming the gate electrode 7 and the anode electrode 13 simultaneously.
　次に、図１０に示す工程においては、全面に層間絶縁膜８を形成する。層間絶縁膜８としては、シリコン酸化膜が好適に用いられる。形成方法としては、熱ＣＶＤ法、プラズマＣＶＤ法、スパッタ法などで絶縁膜を堆積して形成することができる。 Next, in the process shown in FIG. 10, an interlayer insulating film 8 is formed on the entire surface. As the interlayer insulating film 8, a silicon oxide film is preferably used. As a formation method, an insulating film can be deposited by a thermal CVD method, a plasma CVD method, a sputtering method, or the like.
　次に、図１１に示す工程においては、トレンチ１４の上部以外の層間絶縁膜８を選択的に除去することで、トレンチ１４の上部にのみ層間絶縁膜８が残り、ゲート電極７の周囲が絶縁膜で絶縁される。選択的に除去する方法としては、層間絶縁膜８上にレジストパターンを形成し、このレジストパターンをマスクにしてトレンチ１４の上部以外の層間絶縁膜８を選択的に除去する。もしくは、層間絶縁膜８を形成する際に、全面に層間絶縁膜８を形成するのに代えて、ゲート電極７の多結晶シリコンを熱酸化することで、ゲート電極７上に層間絶縁膜８を選択的に形成することもできる。 Next, in the process shown in FIG. 11, the interlayer insulating film 8 other than the upper part of the trench 14 is selectively removed, so that the interlayer insulating film 8 remains only on the upper part of the trench 14 and the periphery of the gate electrode 7 is insulated. Insulated with a membrane. As a selective removal method, a resist pattern is formed on the interlayer insulating film 8, and the interlayer insulating film 8 other than the upper portion of the trench 14 is selectively removed using the resist pattern as a mask. Alternatively, when forming the interlayer insulating film 8, instead of forming the interlayer insulating film 8 on the entire surface, the polycrystalline silicon of the gate electrode 7 is thermally oxidized to form the interlayer insulating film 8 on the gate electrode 7. It can also be formed selectively.
　その後、ウェルコンタクト領域４、ソース領域５ならびにアノード電極１３に電気的に低抵抗でオーミック接続するようにオーミック電極９を形成し、また、炭化珪素基体１の裏面に、電気的に低抵抗でオーミック接続するようにドレイン電極１０を形成する。オーミック電極９ならびにドレイン電極１０としては、ニッケルシリサイドが好適に用いられるが、コバルトシリサイド、チタンシリサイドなどの金属でも構わない。先ず、ニッケルをウェル領域３より内側の領域に堆積した後、パターニングして選択的に除去する。続いて、炭化珪素基体１の裏面に、同様にニッケルを堆積する。その後、１０００℃程度の温度でアニール処理を施し、ＳｉＣとニッケルを合金化させてニッケルシリサイドを形成する。これにより、オーミック電極９とドレイン電極１０が形成される。 Thereafter, an ohmic electrode 9 is formed so as to be in ohmic contact with the well contact region 4, the source region 5 and the anode electrode 13 with low resistance, and on the back surface of the silicon carbide substrate 1 with ohmic resistance with low resistance. A drain electrode 10 is formed so as to be connected. As the ohmic electrode 9 and the drain electrode 10, nickel silicide is preferably used, but metals such as cobalt silicide and titanium silicide may be used. First, nickel is deposited in a region inside the well region 3 and then selectively removed by patterning. Subsequently, nickel is similarly deposited on the back surface of the silicon carbide substrate 1. Thereafter, annealing is performed at a temperature of about 1000 ° C., and SiC and nickel are alloyed to form nickel silicide. Thereby, the ohmic electrode 9 and the drain electrode 10 are formed.
　ニッケルの堆積方法としては蒸着法、スパッタ法、ＣＶＤ法などを用いることができる。パターニング方法としては、リフトオフ法を好適に用いることができるが、ドライエッチング法、ウエットエッチング法を用いても構わない。 As a method for depositing nickel, vapor deposition, sputtering, CVD, or the like can be used. As a patterning method, a lift-off method can be preferably used, but a dry etching method or a wet etching method may be used.
　最後に、図１２に示す工程においては、ソース電極１２となる金属を堆積し、外周部等の領域に堆積した金属をパターニングして選択的に除去し、オーミック電極９に電気的に接続されたソース電極１２を形成する。パターニング方法としては、レジストをマスクとしたドライエッチングやウエットエッチング、リフトオフ法などを用いることができる。 Finally, in the process shown in FIG. 12, a metal to be the source electrode 12 is deposited, and the metal deposited in the region such as the outer periphery is selectively removed by patterning and electrically connected to the ohmic electrode 9. A source electrode 12 is formed. As a patterning method, dry etching, wet etching, a lift-off method, or the like using a resist as a mask can be used.
　以上の工程を経て、図１に示す本実施形態１で採用した構成の半導体装置が完成する。 Through the above steps, the semiconductor device having the configuration adopted in the first embodiment shown in FIG. 1 is completed.
　次に、上記図１に示す、ユニポーラ型のダイオード部２００がソース－ドレイン間に接続されたダイオード内蔵型のＭＯＳＦＥＴにおける基本的な動作について説明する。 Next, the basic operation of the diode built-in MOSFET in which the unipolar diode section 200 shown in FIG. 1 is connected between the source and drain will be described.
　このような、ダイオード内蔵型のＭＯＳＦＥＴの用途としては、例えば電気自動車等の電動機の駆動用インバータなどの電力変換装置の電力変換素子として用いることができる。このような場合、ダイオード内蔵型のＭＯＳＦＥＴは、順方向動作ではスイッチング素子として機能する一方、いわゆる還流動作となる逆方向動作では受動素子として機能する。 Such a diode built-in type MOSFET can be used as a power conversion element of a power conversion device such as an inverter for driving a motor of an electric vehicle or the like. In such a case, the MOSFET with a built-in diode functions as a switching element in the forward direction operation, and functions as a passive element in the reverse direction operation that is a so-called reflux operation.
　ダイオード内蔵型のＭＯＳＦＥＴは、ソース電極１２の電位を基準として、ドレイン電極１０に所定の正の電位を印加した状態でゲート電極７の電位を制御することで、トランジスタとして機能する。一方、ドレイン電極１０に所定の負の電位を印加した状態では、ダイオード内蔵型のＭＯＳＦＥＴは、ダイオード部２００を介してドレイン電極１０からソース電極１２側へと逆方向電流が流れ、還流ダイオードとして機能する。 The diode-embedded MOSFET functions as a transistor by controlling the potential of the gate electrode 7 with a predetermined positive potential applied to the drain electrode 10 with the potential of the source electrode 12 as a reference. On the other hand, in a state where a predetermined negative potential is applied to the drain electrode 10, the diode built-in type MOSFET functions as a free-wheeling diode because a reverse current flows from the drain electrode 10 to the source electrode 12 through the diode unit 200. To do.
　まず、スイッチング素子となるトランジスタとして機能する場合の動作を説明する。 First, the operation when functioning as a transistor serving as a switching element will be described.
　ゲート電極７とソース電極１２間の電圧を所定の閾値電圧以下とした場合には、ゲート電極７下のウェル領域３のチャネル部には空乏層が形成されるので遮断状態（オフ状態）となる。このような状態において、ゲート電極７とソース電極１２間の電圧を所定の閾値電圧以上にすると、ゲート電極７下のウェル領域３のチャネル部に反転層が形成される。これにより、トランジスタはオフ状態からオン状態となり、ソース電極１２からドレイン電極１０へ電流が流れる。 When the voltage between the gate electrode 7 and the source electrode 12 is set to a predetermined threshold voltage or less, a depletion layer is formed in the channel portion of the well region 3 under the gate electrode 7 and thus the cutoff state (off state) is established. . In such a state, when the voltage between the gate electrode 7 and the source electrode 12 is set to a predetermined threshold voltage or more, an inversion layer is formed in the channel portion of the well region 3 below the gate electrode 7. Accordingly, the transistor is turned on from the off state, and current flows from the source electrode 12 to the drain electrode 10.
　このとき、本実施形態１の図１に示す構成において、ＭＯＳＦＥＴ部１００の端部のダイオード部２００に隣接する位置に形成されたＭＯＳＦＥＴユニット１０１では、ゲート電極７を境にして、ダイオード部２００に隣接する側のウェル領域３にはソース領域を形成していない。すなわち、ＭＯＳＦＥＴユニット１０１において、ゲート電極７を境にして、ダイオード部２００側にはＭＯＳＦＥＴが形成されていない。したがって、トランジスタがオン状態のときには、図１３に示すように、ダイオード部２００に隣接する側のウェル領域３にはチャネルが形成されず、ＭＯＳＦＥＴユニット１０２に隣接する側のウェル領域３にはチャネルが形成される。したがって、ＭＯＳＦＥＴの電流は、チャネルが形成されたウェル領域３からドリフト領域２にかけて図１３の符号Ｉ１３に示すように拡がって流れることになる。 At this time, in the configuration shown in FIG. 1 of the first embodiment, in the MOSFET unit 101 formed at a position adjacent to the diode part 200 at the end of the MOSFET part 100, the diode part 200 is formed with the gate electrode 7 as a boundary. A source region is not formed in the well region 3 on the adjacent side. That is, in the MOSFET unit 101, no MOSFET is formed on the diode part 200 side with the gate electrode 7 as a boundary. Therefore, when the transistor is in the ON state, as shown in FIG. 13, no channel is formed in the well region 3 on the side adjacent to the diode part 200, and no channel is formed in the well region 3 on the side adjacent to the MOSFET unit 102. It is formed. Therefore, the current of the MOSFET spreads and flows from the well region 3 where the channel is formed to the drift region 2 as indicated by reference numeral I13 in FIG.
　一方、図１４に示すように、ＭＯＳＦＥＴユニット１０１において、ゲート電極７を境にして、ダイオード部２００に隣接する側のウェル領域３にソース領域５を形成した場合には、ダイオード部２００側にもＭＯＳＦＥＴが形成されることになる。このため、ゲート電極７を境にして、ダイオード部２００側でもチャネルが形成されることなになる。このような場合には、図１４に示すように、ダイオード部２００に隣接して形成されるチャネルを流れる電流は、図１４の符号Ｉ１４に示すようになる。すなわち、ダイオード部２００で電流が流れていないため、ダイオード部２００に隣接して形成されるチャネルを流れる電流は、ドリフト領域２のダイオード部２００側に拡散して拡がりやすくなる。よって、符号Ｉ１４で示す電流の拡がりは、符号Ｉ１３で示す電流の拡がりに比べて大きくなる。このため、ダイオード部２００に隣接して形成されるチャネルを流れる電流の電流密度は、ダイオード部２００に隣接して形成されていないチャネルを流れる電流に比べて低くなるため、電圧降下が小さくなり、電流が流れやすくなる。この結果、ダイオード部２００に隣接するＭＯＳＦＥＴに電流が集中して素子破壊を招きやすくなるおそれがあった。 On the other hand, as shown in FIG. 14, in the MOSFET unit 101, when the source region 5 is formed in the well region 3 adjacent to the diode part 200 with the gate electrode 7 as a boundary, the diode part 200 side is also provided. A MOSFET is formed. Therefore, a channel is also formed on the diode part 200 side with the gate electrode 7 as a boundary. In such a case, as shown in FIG. 14, the current flowing through the channel formed adjacent to the diode portion 200 is as indicated by reference numeral I14 in FIG. That is, since no current flows in the diode part 200, the current flowing through the channel formed adjacent to the diode part 200 is easily diffused and spread to the diode part 200 side of the drift region 2. Therefore, the current spread indicated by reference numeral I14 is larger than the current spread indicated by reference numeral I13. For this reason, since the current density of the current flowing through the channel formed adjacent to the diode part 200 is lower than the current flowing through the channel not formed adjacent to the diode part 200, the voltage drop is reduced, It becomes easier for current to flow. As a result, current may concentrate on the MOSFET adjacent to the diode part 200, which may easily cause element destruction.
　これに対して、本実施形態１で採用した構成では、すべてのＭＯＳＦＥＴユニット１０１～１０４におけるＭＯＳＦＥＴにおいて、オン状態のときにドリフト領域２における電流の拡がりは、図１３に符号Ｉ１３で示すようになる。すなわち、互いに隣接するＭＯＳＦＥＴにおいてチャネルに流れる電流は、電流間で干渉しあって横方向には大きく拡がらない。このため、電流密度は、図１４に符号Ｉ１４で示すように電流が拡がった場合に比べて高くなり、その分電圧降下も大きくなり、電流が流れにくくなる。そして、ＭＯＳＦＥＴユニット１０１～１０４を構成するＭＯＳＦＥＴにおける電流はすべて均一となり、特定の素子に電流が集中するといった不具合を招くことは回避される。これにより、電流集中による素子の破壊を防止することができる。 On the other hand, in the configuration adopted in the first embodiment, in the MOSFETs in all the MOSFET units 101 to 104, the current spread in the drift region 2 when turned on is as indicated by reference numeral I13 in FIG. . That is, the currents flowing through the channels in the MOSFETs adjacent to each other interfere with each other and do not spread greatly in the lateral direction. For this reason, the current density is higher than the case where the current spreads as indicated by reference numeral I14 in FIG. 14, the voltage drop is increased accordingly, and the current does not flow easily. The currents in the MOSFETs constituting the MOSFET units 101 to 104 are all uniform, and it is possible to avoid a problem that the current is concentrated on a specific element. Thereby, destruction of the element due to current concentration can be prevented.
　次に、ゲート電極７とソース電極１２間の電圧を所定の閾値電圧以下にした場合には、反転層が消滅してオン状態からオフ状態となり、電流が遮断される。このような動作により、電流を導通／遮断するスイッチング素子のトランジスタとして機能する。 Next, when the voltage between the gate electrode 7 and the source electrode 12 is set to a predetermined threshold voltage or less, the inversion layer disappears and changes from the on state to the off state, thereby interrupting the current. By such an operation, it functions as a transistor of a switching element that conducts / cuts off current.
　次に、ダイオード部２００が還流ダイオードとして機能する場合について説明する。この還流動作は、電動機等のインダクタンスを負荷としたインバータ等の回路で必要となる動作である。還流時には、ソース電極１２の電位を基準として、ドレイン電極１０に所定の負の電位が印加される。本実施形態１のトランジスタは、Ｎ－型のドリフト領域２とＰ－型のウェル領域３とで形成されるＰＮ型のダイオード、およびユニポーラ型のダイオード部２００を含んでいる。ここで、ダイオード部２００のオン電圧は、一例としてＰＮダイオードのオン電圧である約２．５Ｖ程度より低いオン電圧となるようにアノード電極１３が形成されているものとする。 Next, a case where the diode unit 200 functions as a free wheeling diode will be described. This reflux operation is an operation required in a circuit such as an inverter having an inductance such as an electric motor as a load. At the time of reflux, a predetermined negative potential is applied to the drain electrode 10 with reference to the potential of the source electrode 12. The transistor of the first embodiment includes a PN-type diode formed by an N − -type drift region 2 and a P − -type well region 3 and a unipolar diode portion 200. Here, it is assumed that the anode electrode 13 is formed so that the ON voltage of the diode section 200 is, for example, an ON voltage lower than about 2.5 V that is the ON voltage of the PN diode.
　ＭＯＳＦＥＴのゲート電極７の電位が閾値電圧以下でオフしている場合に、還流電流はオン電圧の低いダイオード部２００に主に流れる。したがって、ユニポーラ型のダイオード部２００を内蔵しない場合に比べてオン電圧を低下させ、定常損失をより低減することができる。また、ダイオード部２００は、ユニポーラ型であるため、ＰＮダイオードなどのバイポーラ型のダイオードに比べてより逆回復電荷が少ないという有利な特徴効果を有している。したがって、ダイオード部２００に電流が流れている状態から、電流が遮断される状態に切り替わるときのスイッチング損失をより低減することができる。 When the potential of the gate electrode 7 of the MOSFET is turned off below the threshold voltage, the reflux current mainly flows through the diode part 200 having a low on-voltage. Therefore, the on-voltage can be lowered and the steady loss can be further reduced as compared with the case where the unipolar diode unit 200 is not incorporated. Moreover, since the diode part 200 is a unipolar type, it has the advantageous characteristic effect that there are few reverse recovery electric charges compared with bipolar type diodes, such as a PN diode. Therefore, it is possible to further reduce the switching loss when switching from the state in which the current flows through the diode unit 200 to the state in which the current is interrupted.
　電気自動車等の電動機の駆動において、力行状態のときには、電動機に電力を供給するインバータを構成するＭＯＳＦＥＴがオン状態となる導通状態の時間は、還流ダイオードがオン状態となる還流状態の時間よりも長くなることが、発明者が行った実験、調査等により判明した。したがって、損失低減の観点においては、損失の割合に応じてＭＯＳＦＥＴ部１００とダイオード部２００の各領域の占める面積の設計自由度を高め、ダイオード部２００に比べてより損失比率の高いＭＯＳＦＥＴ部１００のオン抵抗を低減することが好ましい。 When driving an electric motor such as an electric vehicle, in the power running state, the time for which the MOSFET constituting the inverter that supplies power to the electric motor is in the on state is longer than the time in the free state where the free wheel diode is in the on state. This has been found by experiments and investigations conducted by the inventors. Therefore, in terms of loss reduction, the degree of freedom in designing the area occupied by each region of the MOSFET unit 100 and the diode unit 200 is increased in accordance with the loss ratio, and the MOSFET unit 100 having a higher loss ratio than the diode unit 200 can be used. It is preferable to reduce the on-resistance.
　図１５は図１に示す構成の半導体装置における導通状態および還流状態における電気特性の一例を示したものである。図１５において、破線で示した符号Ｄ１とＭ１は、特許第４０６６９４６号公報に記載されたような、スイッチング用のトランジスタと還流用のダイオードが１：１の割合で並列接続された関連技術の半導体装置の特性を示している。符号Ｄ１は、ユニポーラ型のダイオード（還流状態）の電流－電圧特性、Ｍ１はＭＯＳＦＥＴの電流－電圧特性（導通状態）を示している。 FIG. 15 shows an example of electrical characteristics in the conductive state and the reflux state in the semiconductor device having the configuration shown in FIG. In FIG. 15, reference symbols D1 and M1 indicated by broken lines indicate semiconductors of related technology in which switching transistors and free-wheeling diodes are connected in parallel at a ratio of 1: 1 as described in Japanese Patent No. 40669946. The characteristics of the device are shown. Reference symbol D1 indicates the current-voltage characteristic of the unipolar diode (circulation state), and M1 indicates the current-voltage characteristic (conduction state) of the MOSFET.
　これに対して、実線で示した符号Ｄ２とＭ２は、本実施形態１で採用した、スイッチング用のトランジスタと還流用のダイオードをｎ：１の割合で備えた半導体装置の特性を示している。ｎは２よりも大きい数を示す。符号Ｄ２は、ダイオード部２００の電流－電圧特性（還流状態）、Ｍ２はＭＯＳＦＥＴの電流－電圧特性（導通状態）を示している。 On the other hand, symbols D2 and M2 indicated by solid lines indicate the characteristics of the semiconductor device that is employed in the first embodiment and includes the switching transistor and the reflux diode at a ratio of n: 1. n represents a number larger than 2. Symbol D2 indicates the current-voltage characteristic (reflux state) of the diode section 200, and M2 indicates the current-voltage characteristic (conduction state) of the MOSFET.
　また、符号Ｄ３は、先に説明したＭＯＳＦＥＴが有する内蔵ＰＮダイオードの電流－電圧特性を示している。ここで、動作点となる電流領域をＩ１とする。 The symbol D3 indicates the current-voltage characteristic of the built-in PN diode included in the MOSFET described above. Here, the current region serving as the operating point is assumed to be I1.
　この電流領域Ｉ１において、関連技術においてＭＯＳＦＥＴのオン電圧は駆動点ＭＰ１であり、ダイオードのオン電圧は駆動点ＤＰ１である。このように、ＭＯＳＦＥＴの方が元々オン電圧が高く、かつ導通状態となる時間比率も高い。このため、ＭＯＳＦＥＴの方に損失が発生しやすい構成になっている。すなわち、導通損失と還流損失の和は、時間比率の高いＭＯＳＦＥＴ部の損失が大きくなるため、装置全体としての損失は大きくなっていた。 In this current region I1, in the related art, the on-voltage of the MOSFET is the driving point MP1, and the on-voltage of the diode is the driving point DP1. Thus, the MOSFET originally has a higher on-voltage and a higher time ratio at which the MOSFET is in a conductive state. For this reason, the MOSFET tends to be lossy. That is, the sum of the conduction loss and the return loss increases the loss of the MOSFET portion having a high time ratio, so that the loss of the entire device is large.
　一方、本実施形態１においては、電流領域Ｉ１において、ＭＯＳＦＥＴ部１００の駆動点ＭＰ２は、ダイオード部２００の駆動点ＤＰ２よりも低い。すなわち、１つのダイオード部２００に対して、ＭＯＳＦＥＴ部１００を構成する並列接続されたＭＯＳＦＥＴの割合を関連技術に比べて増やすことで、ＭＯＳＦＥＴ部１００のオン抵抗を低減している。これにより、装置全体におけるＭＯＳＦＥＴ部１００が占める抵抗割合を低く抑えることができる。これにより、導通状態および還流状態の損失を同程度に抑えることができ、装置全体として損失を低減することができる。更に、炭化珪素基体１の表面において、複数のＭＯＳＦＥＴユニット１０１～１０４が形成されている領域の面積は、ダイオード部２００が形成されている領域の面積よりも大きくてもよい。これにより、ＭＯＳＦＥＴ部１００のオン抵抗を低減することができる。 On the other hand, in the first embodiment, the driving point MP2 of the MOSFET unit 100 is lower than the driving point DP2 of the diode unit 200 in the current region I1. That is, the on-resistance of the MOSFET unit 100 is reduced by increasing the ratio of the MOSFETs connected in parallel constituting the MOSFET unit 100 with respect to one diode unit 200 as compared with the related art. Thereby, the resistance ratio which the MOSFET part 100 in the whole apparatus occupies can be restrained low. Thereby, the loss of a conduction | electrical_connection state and a recirculation | reflux state can be suppressed to the same level, and loss can be reduced as the whole apparatus. Further, the area of the region where the plurality of MOSFET units 101 to 104 are formed on the surface of the silicon carbide substrate 1 may be larger than the area of the region where the diode part 200 is formed. Thereby, the on-resistance of the MOSFET part 100 can be reduced.
　したがって、電気自動車の電動機に電力を供給制御するインバータに本実施形態１の装置を採用することで、電動機の駆動時における損失を低減することができる。 Therefore, by adopting the apparatus of the first embodiment for the inverter that controls the supply of electric power to the electric motor of the electric vehicle, it is possible to reduce the loss during driving of the electric motor.
　ここで、ＭＯＳＦＥＴとダイオードとが１：１の割合で構成された関連技術に係わる構成と本実施形態１で採用された構成とにおいて、装置全体にしめる抵抗割合が例えば以下に示すような割合として損失を試算してみる。関連技術における抵抗割合を、１（ＭＯＳＦＥＴ）：１（ダイオード）とする。これに対して、１つのダイオードに並列接続されるトランジスタの数を増やすことで、本実施形態１における抵抗割合は、０．６（ＭＯＳＦＥＴ部１００）：１．４（ダイオード部２００）程度とすることが可能となる。このような抵抗割合において、ＭＯＳＦＥＴがオン状態にある時間とダイオードがオン状態にある時間の割合が、例えば０．６６：０．３４程度とする。このような場合に、関連技術における装置全体としての動作時の損失は、（１×０．６６＋１×０．３４）＝１となる。これに対して、本実施形態１の同損失は、（０．６×０．６６＋１．４×０．３４）＝０．８７２となり、装置全体としての動作時の損失を関連技術に比べて１０％程度低減することが可能となる。 Here, in the configuration related to the related technology in which the MOSFET and the diode are configured at a ratio of 1: 1 and the configuration adopted in the first embodiment, the resistance ratio of the entire device is lost as a ratio as shown below, for example. Try to estimate. The resistance ratio in the related art is 1 (MOSFET): 1 (diode). In contrast, by increasing the number of transistors connected in parallel to one diode, the resistance ratio in the first embodiment is about 0.6 (MOSFET portion 100): 1.4 (diode portion 200). It becomes possible. In such a resistance ratio, the ratio of the time during which the MOSFET is in the on state and the time during which the diode is in the on state is, for example, about 0.66: 0.34. In such a case, the loss during operation of the related apparatus as a whole in the related art is (1 × 0.66 + 1 × 0.34) = 1. On the other hand, the loss in the first embodiment is (0.6 × 0.66 + 1.4 × 0.34) = 0.872, and the loss during operation of the entire device is 10 times that of the related art. % Can be reduced.
　図１５に示す電気的特性において、ダイオード部２００の駆動点ＤＰ２は内蔵ＰＮダイオードの駆動点ＤＰ３よりも低くなるように、ダイオード部２００が形成されている。このように、駆動点ＤＰ２がＤＰ３よりも低いことにより、還流電流はダイオード部２００に流れるようになる。この結果、ＰＮダイオードの順方向電流による劣化や、逆回復電流等の発生を防ぐことができる。 15, the diode part 200 is formed so that the drive point DP2 of the diode part 200 is lower than the drive point DP3 of the built-in PN diode. As described above, when the drive point DP2 is lower than DP3, the return current flows to the diode unit 200. As a result, it is possible to prevent the deterioration of the PN diode due to the forward current and the occurrence of the reverse recovery current.
　なお、ダイオード部２００のアノード電極１３が形成されるトレンチは、ＭＯＳＦＥＴ部１００間に配置されていることが望ましい。これにより、ダイオード部２００のトレンチに隣接するＭＯＳＦＥＴユニットのトレンチの数を減らすことが可能となる。この結果、ＭＯＳＦＥＴ部１００の形成領域を増やすことができる。 Note that the trench in which the anode electrode 13 of the diode part 200 is formed is preferably disposed between the MOSFET parts 100. Thereby, the number of trenches of the MOSFET unit adjacent to the trench of the diode part 200 can be reduced. As a result, the formation region of the MOSFET portion 100 can be increased.
　また、ダイオード部２００に隣接するＭＯＳＦＥＴユニット１０１が備えるソース領域５は、隣接するＭＯＳＦＥＴユニット１０２側にのみ形成されている。この場合、ＭＯＳＦＥＴユニットのトレンチ（ゲート電極７）は４つ以上連続して形成していることが望ましい。 Further, the source region 5 provided in the MOSFET unit 101 adjacent to the diode part 200 is formed only on the adjacent MOSFET unit 102 side. In this case, it is desirable that four or more trenches (gate electrodes 7) of the MOSFET unit are formed continuously.
　ここで、図１６を参照して、ゲート電極の両側にソース領域を形成しない構造において、ＭＯＳＦＥＴユニットのトレンチ（ゲート電極７）は４つ以上連続して形成した場合と連続して形成しない場合とで、チャネル領域の大きさをチャネル数の大小として比較してみる。 Here, referring to FIG. 16, in the structure in which the source region is not formed on both sides of the gate electrode, the case where four or more trenches (gate electrode 7) of the MOSFET unit are continuously formed, and the case where they are not formed continuously, Now, compare the size of the channel region as the number of channels.
　なお、図１６において、「Ｍ」はＭＯＳＦＥＴユニットのゲート電極を構成する１つのトレンチを表し、その下部の縦線はＭＯＳＦＥＴのチャネルを表し、「Ｄ」はダイオードを表している。したがって、図１６において、「Ｍ」で表されたトレンチに対応して、縦線が２本ある場合にはトレンチの両側にＭＯＳＦＥＴのチャネル領域が２つ形成されていることを示し、縦線が１本の場合には、トレンチの片側（ダイオードから遠い側）にのみＭＯＳＦＥＴのチャネル領域が１つ形成されていることを示している。また、図１６において、（ａ１）～（ａ５）はＭＯＳＦＥＴとダイオードが交互に配置されている関連技術に係わる構成を示し、（ｂ１）～（ｂ５）はＭＯＳＦＥＴが連続して形成された実施形態１を示している。 In FIG. 16, “M” represents one trench constituting the gate electrode of the MOSFET unit, a vertical line below it represents a channel of the MOSFET, and “D” represents a diode. Therefore, in FIG. 16, when there are two vertical lines corresponding to the trench represented by “M”, this indicates that two MOSFET channel regions are formed on both sides of the trench. In the case of one, one channel region of the MOSFET is formed only on one side of the trench (the side far from the diode). In FIG. 16, (a1) to (a5) show a configuration related to a related technique in which MOSFETs and diodes are alternately arranged, and (b1) to (b5) are embodiments in which MOSFETs are continuously formed. 1 is shown.
　先ず、ＭＯＳＦＥＴを連続して３つ形成した場合には、図１６（ｂ１）に示すようにＭＯＳＦＥＴのチャネル数は４チャネル形成される。これに対して、図１６（ｂ１）と同数のＭＯＳＦＥＴとダイオードを交互に形成した場合には、図１６（ａ１）に示すようにＭＯＳＦＥＴのチャネル数は６チャネル形成される。これにより、ＭＯＳＦＥＴを連続して３つ形成した場合には、ＭＯＳＦＥＴ部１００全体としてのチャネル領域の大きさは関連技術よりも少なくなる。 First, when three MOSFETs are formed in succession, the number of MOSFET channels is four as shown in FIG. 16 (b1). On the other hand, when the same number of MOSFETs and diodes as in FIG. 16B1 are alternately formed, six channels of MOSFETs are formed as shown in FIG. 16A1. Thereby, when three MOSFETs are formed in succession, the size of the channel region as a whole of the MOSFET unit 100 becomes smaller than that of the related art.
　次に、ＭＯＳＦＥＴを連続して４つ形成した場合には、図１６（ｂ２）に示すようにＭＯＳＦＥＴのチャネル数は６チャネル形成される。これに対して、図１６（ｂ２）と同数のＭＯＳＦＥＴとダイオードを交互に形成した場合には、図１６（ａ２）に示すようにＭＯＳＦＥＴのチャネル数は６チャネル形成される。これにより、ＭＯＳＦＥＴを連続して４つ形成した場合には、ＭＯＳＦＥＴ部１００全体としてのチャネル領域の大きさを関連技術と同等に確保することが可能となる。 Next, when four MOSFETs are formed continuously, six channels of MOSFETs are formed as shown in FIG. 16 (b2). On the other hand, when the same number of MOSFETs and diodes as in FIG. 16 (b2) are alternately formed, six channels of MOSFETs are formed as shown in FIG. 16 (a2). As a result, when four MOSFETs are formed in succession, the size of the channel region of the MOSFET unit 100 as a whole can be assured as that of the related art.
　また、ＭＯＳＦＥＴを連続して５つ形成した場合には、図１６（ｂ３）に示すようにＭＯＳＦＥＴのチャネル数は８チャネル形成される。これに対して、図１６（ｂ３）と同数のＭＯＳＦＥＴとダイオードを交互に形成した場合には、図１６（ａ３）に示すようにＭＯＳＦＥＴのチャネル数は８チャネル形成される。これにより、ＭＯＳＦＥＴを連続して５つ形成した場合には、ＭＯＳＦＥＴ部１００全体としてのチャネル領域の大きさを関連技術と同等に確保することが可能となる。 Further, when five MOSFETs are continuously formed, the number of MOSFET channels is eight as shown in FIG. 16 (b3). On the other hand, when the same number of MOSFETs and diodes as in FIG. 16B3 are alternately formed, the number of MOSFET channels is 8 as shown in FIG. 16A3. As a result, when five MOSFETs are formed in succession, the size of the channel region of the MOSFET unit 100 as a whole can be assured as that of the related art.
　同様に、ＭＯＳＦＥＴを連続して６つ形成した場合には、図１６（ｂ４）に示すようにＭＯＳＦＥＴのチャネル数は１０チャネル形成される。これに対して、図１６（ｂ４）と同数のＭＯＳＦＥＴとダイオードを交互に形成した場合には、図１６（ａ４）に示すようにＭＯＳＦＥＴのチャネル数は８チャネル形成される。これにより、ＭＯＳＦＥＴを連続して６つ形成した場合には、ＭＯＳＦＥＴ部１００全体としてのチャネル領域の大きさを関連技術以上に確保することが可能となる。 Similarly, when six MOSFETs are formed in succession, as shown in FIG. 16 (b4), the number of MOSFET channels is ten. On the other hand, when the same number of MOSFETs and diodes as in FIG. 16 (b4) are alternately formed, the number of MOSFET channels is 8 as shown in FIG. 16 (a4). As a result, when six MOSFETs are continuously formed, the size of the channel region of the MOSFET unit 100 as a whole can be secured more than the related art.
　同様に、ＭＯＳＦＥＴを連続して７つ形成した場合には、図１６（ｂ５）に示すようにＭＯＳＦＥＴのチャネル数は１２チャネル形成される。これに対して、図１６（ｂ５）と同数のＭＯＳＦＥＴとダイオードを交互に形成した場合には、図１６（ａ５）に示すようにＭＯＳＦＥＴのチャネル数は１０チャネル形成される。これにより、ＭＯＳＦＥＴを連続して７つ形成した場合には、ＭＯＳＦＥＴ部１００全体としてのチャネル領域の大きさを関連技術以上に確保することが可能となる。 Similarly, when seven MOSFETs are formed in succession, 12 channels of MOSFETs are formed as shown in FIG. 16 (b5). On the other hand, when the same number of MOSFETs and diodes as in FIG. 16 (b5) are alternately formed, the number of MOSFET channels is 10 as shown in FIG. 16 (a5). As a result, when seven MOSFETs are continuously formed, the size of the channel region of the MOSFET unit 100 as a whole can be secured more than the related art.
　このように、ＭＯＳＦＥＴユニットのトレンチを４つ以上連続して形成することで、ダイオード部２００に隣接するＭＯＳＦＥＴユニット１０１に２つのＭＯＳＦＥＴを形成しなくとも、ＭＯＳＦＥＴ部１００全体としてのチャネル領域の大きさを関連技術と同等もしくはそれ以上に確保することが可能となる。 In this way, by continuously forming four or more MOSFET unit trenches, the size of the channel region of the MOSFET unit 100 as a whole can be obtained without forming two MOSFETs in the MOSFET unit 101 adjacent to the diode unit 200. Can be ensured to be equal to or more than the related technology.
　（実施形態２）
　図１７は本発明の実施形態２に係る半導体装置の構成を示す断面図である。この実施形態２の半導体装置は、先の実施形態１の構成に対して次の点が相違する。すなわち、ＭＯＳＦＥＴ部１００の端部のＭＯＳＦＥＴユニット１０１のトレンチとダイオード部２００のアノード電極１３との距離Ｌ２は、ＭＯＳＦＥＴ部１００のトレンチ間の距離Ｌ１よりも短い。これにより、さらに半導体装置の集積度を高めることが可能となり、チップを小型化することができる。 (Embodiment 2)
FIG. 17 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 2 of the present invention. The semiconductor device of the second embodiment is different from the configuration of the first embodiment in the following points. That is, the distance L 2 between the trench of the MOSFET unit 101 at the end of the MOSFET unit 100 and the anode electrode 13 of the diode unit 200 is shorter than the distance L 1 between the trenches of the MOSFET unit 100. As a result, the degree of integration of the semiconductor device can be further increased, and the chip can be miniaturized.
　（実施形態３）
　図１８は本発明の実施形態３に係る半導体装置の構成を示す断面図である。この実施形態３の半導体装置は、先の実施形態１の構成に対して次の点が相違する。すなわち、ダイオード部２００のトレンチの幅Ｌ３は、ＭＯＳＦＥＴ部１００のトレンチの幅Ｌ４よりも大きい。これにより、ダイオード部２００の数を少なくしても、ダイオード部２００の面積を増やすことができるので、ダイオード部２００のオン抵抗の増加を防ぐことができる。 (Embodiment 3)
FIG. 18 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 3 of the present invention. The semiconductor device of the third embodiment is different from the configuration of the first embodiment in the following points. That is, the width L3 of the trench of the diode part 200 is larger than the width L4 of the trench of the MOSFET part 100. Thereby, even if the number of the diode parts 200 is reduced, the area of the diode part 200 can be increased, so that an increase in the on-resistance of the diode part 200 can be prevented.
　（実施形態４）
　図１９は本発明の実施形態４に係る半導体装置の構成を示す断面図である。この実施形態４の半導体装置は、先の実施形態１の構成に対して次の点が相違する。すなわち、ダイオード部２００とＭＯＳＦＥＴ部１００との間のオーミック電極９に接するように、ウェル領域３の表面にＰ＋型の第２のウェルコンタクト領域１６を設ける。これにより、ソース電極１２とダイオード部２００のアノード電極１３との電気的抵抗を減少させることができる。これにより、ドレイン電極１０に対してソース電極１２に負のバイアスを印加したときに、ダイオード部２００のアノード電極１３からドリフト領域２へ延びる空乏層が安定し、オフ時の安定性を高めることができる。 (Embodiment 4)
FIG. 19 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 4 of the present invention. The semiconductor device of the fourth embodiment is different from the configuration of the first embodiment in the following points. That is, the P + -type second well contact region 16 is provided on the surface of the well region 3 so as to be in contact with the ohmic electrode 9 between the diode portion 200 and the MOSFET portion 100. Thereby, the electrical resistance between the source electrode 12 and the anode electrode 13 of the diode part 200 can be reduced. Thereby, when a negative bias is applied to the source electrode 12 with respect to the drain electrode 10, the depletion layer extending from the anode electrode 13 of the diode part 200 to the drift region 2 is stabilized, and the stability at the time of off can be improved. it can.
　（実施形態５）
　図２０は本発明の実施形態５に係る半導体装置の構成を示す断面図であり、図２１は図２０のＡ－Ａ線に沿って上面（ソース電極１２）側から見た断面図である。この実施形態５の半導体装置は、先の実施形態１の構成に対して次の点が相違する。すなわち、ソース領域５をＭＯＳＦＥＴ部１００のトレンチに接し、且つトレンチで挟むように形成する。さらに、図２１に示すように、ウェルコンタクト領域４をＭＯＳＦＥＴ部１００のトレンチに接し、且つトレンチで挟むように形成する。そして、ソース領域５とウェルコンタクト領域４とを、前記第１の溝が並ぶ方向に直交する方向に交互に連続して配置する。このような構成とすることで、ＭＯＳＦＥＴ部１００のトレンチの間隔を先の図１に示すトレンチの間隔よりも狭めた場合であっても、ソース領域５ならびにウェルコンタクト領域４を形成することができる。これにより、ＭＯＳＦＥＴ部１００の形成密度を高めることが可能となり、装置の小型化を図ることができる。 (Embodiment 5)
FIG. 20 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 5 of the present invention, and FIG. 21 is a cross-sectional view seen from the upper surface (source electrode 12) side along the line AA in FIG. The semiconductor device of the fifth embodiment is different from the configuration of the first embodiment in the following points. That is, the source region 5 is formed so as to be in contact with and sandwiched by the trench of the MOSFET unit 100. Further, as shown in FIG. 21, the well contact region 4 is formed so as to be in contact with and sandwiched by the trench of the MOSFET portion 100. Then, the source regions 5 and the well contact regions 4 are alternately and continuously arranged in a direction orthogonal to the direction in which the first grooves are arranged. By adopting such a configuration, the source region 5 and the well contact region 4 can be formed even when the interval between the trenches of the MOSFET portion 100 is narrower than the interval between the trenches shown in FIG. . As a result, the formation density of the MOSFET portion 100 can be increased, and the device can be miniaturized.
　（実施形態６）
　図２２は本発明の実施形態６に係る半導体装置の構成を示す断面図である。この実施形態６の半導体装置は、先の実施形態１の構成に対して次の点が相違する。すなわち、複数のＭＯＳＦＥＴユニット１０１～１０４の各々は、トレンチに接してウェル領域３上に形成され、且つ、トレンチを境としてトレンチの両側にそれぞれ形成されたソース領域５を備える。複数のＭＯＳＦＥＴユニットのうち、ダイオード部２００に隣接するトランジスタユニット１０１が備えるソース領域５のうち、ダイオード部２００側に形成されたソース領域５の幅は、隣接する他のＭＯＳＦＥＴユニット１０２側に形成されたソース領域５の幅よりも狭い。このような構成とすることで、ダイオード部２００側に形成されるＭＯＳＦＥＴのチャネルを流れる電流の広がりＩ１５は、図１４に示したＩ１３や図２２のＩ１４に比べて小さくなる。このため、ダイオード部２００に隣接するＭＯＳＦＥＴの電流密度は高くなるので、その分電圧降下も大きくなり、電流は流れにくくなる。よって、ダイオード部２００に隣接するＭＯＳＦＥＴに電流が集中することが抑制され、電流集中による素子の破壊を防止することができる。また、チップ面積を小さくし、ソース領域５の形成コストを低減することができる。 (Embodiment 6)
FIG. 22 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 6 of the present invention. The semiconductor device of the sixth embodiment is different from the configuration of the first embodiment in the following points. That is, each of the plurality of MOSFET units 101 to 104 includes a source region 5 formed on the well region 3 in contact with the trench and formed on both sides of the trench with the trench as a boundary. Among the plurality of MOSFET units, among the source regions 5 included in the transistor unit 101 adjacent to the diode unit 200, the width of the source region 5 formed on the diode unit 200 side is formed on the other adjacent MOSFET unit 102 side. The width of the source region 5 is narrower. With this configuration, the spread I15 of the current flowing through the channel of the MOSFET formed on the diode section 200 side is smaller than I13 shown in FIG. 14 and I14 shown in FIG. For this reason, since the current density of the MOSFET adjacent to the diode part 200 is increased, the voltage drop is increased accordingly, and the current is less likely to flow. Therefore, current concentration on the MOSFET adjacent to the diode portion 200 is suppressed, and element destruction due to current concentration can be prevented. In addition, the chip area can be reduced and the formation cost of the source region 5 can be reduced.
　なお、上記各実施形態２～６は、それぞれ単独で実施してもむろんかまわないが、適宜組み合わせて実施してもよい。 It should be noted that the above embodiments 2 to 6 may be implemented independently, but may be implemented in combination as appropriate.
　本出願は、２０１０年８月２日に出願された日本国特許願第２０１０－１７３４５２号に基づく優先権を主張しており、この出願の内容が参照により本発明の明細書に組み込まれる。 This application claims priority based on Japanese Patent Application No. 2010-173452 filed on August 2, 2010, the contents of which are incorporated into the description of the present invention by reference.
　本発明の実施形態に係わる半導体装置が備える複数のトランジスタユニットのうち、ダイオードに隣接するトランジスタユニットが備えるソース領域は、第１の溝を境にして、隣接する他のトランジスタユニット側にのみ形成されている。或いは、ダイオードに隣接するトランジスタユニットが備えるソース領域のうち、ダイオード側に形成されたソース領域の幅は、隣接する他のトランジスタユニット側に形成されたソース領域の幅よりも狭い。これにより、特定の素子に電流が集中することが抑制され、これにより、電流集中による素子の破壊を抑制することができる。したがって、本発明の実施形態に係わる半導体装置は、産業上利用可能である。 Of the plurality of transistor units included in the semiconductor device according to the embodiment of the present invention, the source region included in the transistor unit adjacent to the diode is formed only on the other adjacent transistor unit side with the first groove as a boundary. ing. Alternatively, among the source regions included in the transistor unit adjacent to the diode, the width of the source region formed on the diode side is narrower than the width of the source region formed on the other adjacent transistor unit side. Thereby, it is possible to suppress the current from being concentrated on a specific element, thereby suppressing the destruction of the element due to the current concentration. Therefore, the semiconductor device according to the embodiment of the present invention can be used industrially.
　１…炭化珪素基体
　２…ドリフト領域
　３…ウェル領域
　４…ウェルコンタクト領域
　５…ソース領域
　６…ゲート絶縁膜
　７…ゲート電極
　８…層間絶縁膜
　９…オーミック電極
　１０…ドレイン電極
　１２…ソース電極
　１３…アノード電極
　１４…トレンチ
　１５…多結晶シリコン
　１６…ウェルコンタクト領域
　１００…ＭＯＳＦＥＴ部
　１０１～１０４…ＭＯＳＦＥＴユニット
　２００…ダイオード部 DESCRIPTION OF SYMBOLS 1 ... Silicon carbide base | substrate 2 ... Drift region 3 ... Well region 4 ... Well contact region 5 ... Source region 6 ... Gate insulating film 7 ... Gate electrode 8 ... Interlayer insulating film 9 ... Ohmic electrode 10 ... Drain electrode 12 ... Source electrode 13 ... Anode electrode 14 ... Trench 15 ... Polycrystalline silicon 16 ... Well contact region 100 ... MOSFET part 101-104 ... MOSFET unit 200 ... Diode part

Claims (14)

  1. 　互いに隣接する複数のトランジスタユニットを備えるトランジスタ部と、
    　前記トランジスタ部に隣接するダイオードと、を有する半導体装置であって、
    　前記複数のトランジスタユニットの各々は、
    　半導体基体に形成され、前記トランジスタユニットのドレイン領域となる第１導電型のドリフト領域と、
    　前記ドリフト領域上に形成された第２導電型のウェル領域と、
    　前記ドリフト領域および前記ウェル領域に形成された第１の溝の内部に、絶縁膜を介して形成されたゲート電極と、
    　前記第１の溝に接して前記ウェル領域上に形成された第１導電型のソース領域と、を備え、
    　前記複数のトランジスタユニットのうち、前記ダイオードに隣接するトランジスタユニットが備える前記ソース領域は、前記第１の溝を境にして、隣接する他のトランジスタユニット側にのみ形成され、
    　前記複数のトランジスタユニットのうち、その他のトランジスタユニットが備える前記ソース領域は、第１の溝を境として、第１の溝の両側にそれぞれ形成されている
    ことを特徴とする半導体装置。     A transistor unit including a plurality of transistor units adjacent to each other;
    A semiconductor device having a diode adjacent to the transistor portion,
    Each of the plurality of transistor units includes:
    A drift region of a first conductivity type formed on a semiconductor substrate and serving as a drain region of the transistor unit;
    A second conductivity type well region formed on the drift region;
    A gate electrode formed in the first trench formed in the drift region and the well region with an insulating film interposed therebetween;
    A first conductivity type source region formed on the well region in contact with the first groove,
    Of the plurality of transistor units, the source region included in the transistor unit adjacent to the diode is formed only on the other transistor unit side adjacent to the first groove,
    Of the plurality of transistor units, the source regions included in other transistor units are respectively formed on both sides of the first groove with the first groove as a boundary.
  2. 　前記ダイオードに隣接するトランジスタユニットが備える前記ソース領域は、前記第２の溝からの距離が近い前記第１の溝の側面と、前記第２の溝からの距離が遠い前記第１の溝の側面のうち、前記第２の溝からの距離が遠い前記第１の溝の側面にのみ形成されている
    ことを特徴とする請求項１に記載の半導体装置。     The source region included in the transistor unit adjacent to the diode includes a side surface of the first groove that is close to the second groove, and a side surface of the first groove that is far from the second groove. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed only on a side surface of the first groove that is far from the second groove.
  3. 　互いに隣接する複数のトランジスタユニットを備えるトランジスタ部と、
    　前記トランジスタ部に隣接するダイオードと、を有する半導体装置であって、
    　前記複数のトランジスタユニットの各々は、
    　半導体基体に形成され、前記トランジスタユニットのドレイン領域となる第１導電型のドリフト領域と、
    　前記ドリフト領域上に形成された第２導電型のウェル領域と、
    　前記ドリフト領域および前記ウェル領域に形成された第１の溝の内部に、絶縁膜を介して形成されたゲート電極と、
    　前記第１の溝に接して前記ウェル領域上に形成され、且つ、前記第１の溝を境として前記第１の溝の両側にそれぞれ形成された第１導電型のソース領域と、を備え、
    　前記複数のトランジスタユニットのうち、前記ダイオードに隣接するトランジスタユニットが備える前記ソース領域のうち、前記ダイオード側に形成されたソース領域の幅は、隣接する他のトランジスタユニット側に形成されたソース領域の幅よりも狭い
    ことを特徴とする半導体装置。     A transistor unit including a plurality of transistor units adjacent to each other;
    A semiconductor device having a diode adjacent to the transistor portion,
    Each of the plurality of transistor units includes:
    A drift region of a first conductivity type formed on a semiconductor substrate and serving as a drain region of the transistor unit;
    A second conductivity type well region formed on the drift region;
    A gate electrode formed in the first trench formed in the drift region and the well region with an insulating film interposed therebetween;
    A first conductivity type source region formed on the well region in contact with the first groove, and formed on both sides of the first groove with the first groove as a boundary,
    Of the plurality of transistor units, among the source regions included in the transistor unit adjacent to the diode, the width of the source region formed on the diode side is equal to the width of the source region formed on the other adjacent transistor unit side. A semiconductor device characterized by being narrower than the width.
  4. 　前記ダイオードは、
    　前記ダイオードのカソード領域となる前記ドリフト領域と、
    　前記ドリフト領域上に形成された前記ウェル領域と、
    　前記ドリフト領域および前記ウェル領域に形成された第２の溝の内部に形成されたアノード電極と、を備える
    ことを特徴とする請求項１～３のいずれか１項に記載の半導体装置。     The diode is
    The drift region to be the cathode region of the diode;
    The well region formed on the drift region;
    The semiconductor device according to any one of claims 1 to 3, further comprising: an anode electrode formed in a second groove formed in the drift region and the well region.
  5. 　前記複数のトランジスタユニットは並列接続され、前記ダイオードのアノード電極は、前記トランジスタユニットの前記ソース領域に電気的に接続され、ｎを２よりも大きい数とした場合、前記複数のトランジスタと前記ダイオードとの割合がｎ：１に設定されている
    ことを特徴とする請求項４に記載の半導体装置。     The plurality of transistor units are connected in parallel, the anode electrode of the diode is electrically connected to the source region of the transistor unit, and when n is a number greater than 2, the plurality of transistors and the diode The semiconductor device according to claim 4, wherein the ratio is set to n: 1.
  6. 　前記半導体基体の主表面において、前記複数のトランジスタユニットが形成されている領域の面積は、前記ダイオードが形成されている領域の面積よりも大きい
    ことを特徴とする請求項１～５のいずれか１項に記載の半導体装置。     The area of the region where the plurality of transistor units are formed on the main surface of the semiconductor substrate is larger than the area of the region where the diode is formed. The semiconductor device according to item.
  7. 　前記第１の溝は、少なくとも４つ以上連続して形成されている
    ことを特徴とする請求項１～６のいずれか１項に記載の半導体装置。     7. The semiconductor device according to claim 1, wherein at least four or more of the first grooves are continuously formed.
  8. 　前記第１の溝と前記第２の溝との距離は、前記第１の溝同士の距離よりも短い
    ことを特徴とする請求項１～７のいずれか１項に記載の半導体装置。     The semiconductor device according to any one of claims 1 to 7, wherein a distance between the first groove and the second groove is shorter than a distance between the first grooves.
  9. 　前記第２の溝の幅は、前記第１の溝の幅よりも大きい
    ことを特徴とする請求項１～８のいずれか１項に記載の半導体装置。     9. The semiconductor device according to claim 1, wherein a width of the second groove is larger than a width of the first groove.
  10. 　前記複数のトランジスタユニットの各々は、第１導電型のソース領域に電気的に接続されたソース電極を更に備え、
    　前記ダイオードは、前記第１の溝と前記第２の溝との間の前記ウェル領域に形成され、前記ソース電極と前記アノード電極とを電気的に接続する第２導電型の第２のウェルコンタクト領域を更に備える
    ことを特徴とする請求項１～９のいずれか１項に記載の半導体装置。     Each of the plurality of transistor units further includes a source electrode electrically connected to the source region of the first conductivity type,
    The diode is formed in the well region between the first groove and the second groove, and is a second conductivity type second well contact that electrically connects the source electrode and the anode electrode. 10. The semiconductor device according to claim 1, further comprising a region.
  11. 　前記複数のトランジスタユニットの各々は、
    　第１導電型のソース領域に電気的に接続されたソース電極と、
    　前記ウェル領域上に形成され、且つ前記ソース電極に電気的に接続された、前記ウェル領域よりも高い濃度の不純物が添加された第２導電型の第１のウェルコンタクトと、を更に備え、
    　前記第１のウェルコンタクト領域と前記ソース領域とは、前記第１の溝に挟まれて、前記第１の溝が並ぶ方向に直交する方向に交互に配置されている
    ことを特徴とする請求項１～１０のいずれか１項に記載の半導体装置。     Each of the plurality of transistor units includes:
    A source electrode electrically connected to the source region of the first conductivity type;
    A first well contact of a second conductivity type formed on the well region and electrically connected to the source electrode and doped with an impurity having a concentration higher than that of the well region;
    The first well contact region and the source region are alternately arranged in a direction perpendicular to a direction in which the first grooves are arranged, sandwiched between the first grooves. 11. The semiconductor device according to any one of 1 to 10.
  12. 　前記複数のトランジスタユニットの各々は、
    　第１導電型のソース領域に電気的に接続されたソース電極と、
    　前記ウェル領域上に形成され、且つ前記ソース電極に電気的に接続された、前記ウェル領域よりも高い濃度の不純物が添加された第２導電型の第１のウェルコンタクトと、を更に備え、
    　前記第１のウェルコンタクト領域と前記ソース領域とは、前記第１の溝が並ぶ方向に沿って並べられている
    ことを特徴とする請求項１～１０のいずれか１項に記載の半導体装置。     Each of the plurality of transistor units includes:
    A source electrode electrically connected to the source region of the first conductivity type;
    A first well contact of a second conductivity type formed on the well region and electrically connected to the source electrode and doped with an impurity having a concentration higher than that of the well region;
    11. The semiconductor device according to claim 1, wherein the first well contact region and the source region are arranged along a direction in which the first trenches are arranged.
  13. 前記ダイオードは、ユニポーラ型のダイオードであることを特徴とする請求項１～１２のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 12, wherein the diode is a unipolar diode.
  14. 　前記アノード電極は、前記半導体基体とはバンドギャップが異なる材料で構成されていることを特徴とする請求項１～１３のいずれか１項に記載の半導体装置。 The semiconductor device according to any one of claims 1 to 13, wherein the anode electrode is made of a material having a band gap different from that of the semiconductor substrate.
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