JP2002203966A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To downsize a vertical field effect transistor which has a trench structure with a built-in Schottky barrier diode. SOLUTION: For example, a trench structure of gate electrode 18 is made at the surface of an epitaxial layer 12 where a first base layer 13 and a source layer 15 are made. This gate electrode 18 is made with its form being contrived so that it may not subdivide the source layer 15. This obviates the necessity of supplying power severally to each of the source layers 15, so it becomes possible to omit the formation of the P layer (or P+ layer).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a vertical field effect transistor having a trench structure with a built-in Schottky barrier diode.

[0002]

2. Description of the Related Art Conventionally, a synchronous rectifier circuit using a field effect transistor is well known.

FIG. 7 shows an example of a synchronous rectifier circuit using a general field-effect transistor. In this synchronous rectifier circuit, when the gate of the field effect transistor 101 is turned off, a reverse current flows through the field effect transistor 102 due to the back electromotive force. In the case of this circuit, the field effect transistor 102 is turned on with a slight delay. Therefore, for a certain period of time, a forward current flows through the parasitic PN diode 102a, and a large power loss occurs. In order to suppress this power loss, in the conventional synchronous rectifier circuit, apart from the parasitic PN diode 102a,
Schottky barrier diode 103 with low power loss
Is provided externally.

[0004] FIG. 8 is a block diagram showing the configuration of the synchronous rectifier circuit.
1 shows a configuration example of a conventional vertical field effect transistor. FIG. 1A is a cross-sectional view of a main part, and FIG. 1B is a plan view showing a part of the main part in a see-through manner.

In FIGS. 1A and 1B, an N− type epitaxial layer 112 is provided on one surface of an N ++ type substrate 111.
Is provided. In the surface region of the epitaxial layer 112, a P-type base layer 113 is formed. The surface region of the base layer 113 includes an N + type source layer 11
4 and a P layer (or P + layer) 115 having a lateral diffusion region 115a.

The source layer 114 and the base layer 113 are provided on the surface of the epitaxial layer 112.
And a trench 116 having a depth reaching the epitaxial layer 112 is formed. Trench 1
A gate electrode 118 is buried in the gate via a gate oxide film 117. In this case, the gate electrode 118 is integrally formed so as to subdivide the source layer 114 as shown in FIG. A power source (“−” gate electric field) is supplied to each subdivided source layer 114 via a P layer (or P + layer) 115.

On the other hand, on the surface of the epitaxial layer 112, an insulating film 119 and an interlayer film 120 are provided. The insulating film 119 is provided so as to protect a boundary portion with the base layer 113 in a peripheral portion of the epitaxial layer 112. The interlayer film 120 is provided so as to cover the surface of the gate electrode 118. Further, the base layer 113, the source layer 114, and the P layer 115, including the surface of the insulating film 119 and the surface of the interlayer film 120, are provided with barrier metal films (eg, TiW) 121. , And a source electrode (for example, Al) 122 is commonly provided.

On the other surface of the substrate 111, a drain electrode 123 is provided on the entire surface.

[0009] FIG. 9 is a circuit diagram of the synchronous rectifier circuit.
1 shows a configuration example of a conventional Schottky barrier diode.

In FIG. 1, an N− type epitaxial layer 212 is provided on one surface of an N ++ type substrate 211. In the surface region of the epitaxial layer 212, a P-type base layer (guard ring) 213 is formed.

On the other hand, on the surface of the epitaxial layer 212, an insulating film 214 is provided. Insulating film 214
Is provided so as to protect a boundary portion with the base layer 213 in a peripheral portion of the epitaxial layer 212. Further, on the surface portions of the epitaxial layer 212 and the base layer 213, including on the insulating film 214, an anode electrode (for example, TiW, V, or Mo) is provided via a barrier metal film (for example, TiW, V, or Mo) 215. , Al) 216 are provided.

On the other surface of the substrate 211, a cathode electrode 217 is provided on the entire surface.

However, the external attachment of the Schottky barrier diode 103 has a disadvantage that the number of components on the circuit increases and the arrangement space increases.

[0014]

As a method of avoiding such a problem, it is conceivable to incorporate a Schottky barrier diode on the field effect transistor.

FIG. 10 shows a configuration example of a vertical field effect transistor having a built-in Schottky barrier diode.

In FIG. 1, an N− type epitaxial layer 312 is provided on one surface of an N ++ type substrate 311. In the surface region of the epitaxial layer 312, first and second P-type base layers 313 and 314 are formed. In the surface region of the first base layer 313, an N + type source layer 315 and a P layer (or P + layer) 316 having a lateral diffusion region 316a are arranged.

A trench 317 is formed in the surface of the epitaxial layer 312 so as to penetrate the source layer 315 and the first base layer 313 and have a depth reaching the epitaxial layer 312. I have. A gate electrode 319 is buried in the trench 317 via a gate oxide film 318.

On the other hand, on the surface of the epitaxial layer 312, an insulating film 320 and an interlayer film 321 are provided. The insulating film 320 is provided in a peripheral portion of the epitaxial layer 312 so as to protect a boundary portion with the second base layer 314. The interlayer film 321 is provided so as to cover the surface of the gate electrode 319. Further, the insulating film 320 and the interlayer film 32
1, the epitaxial layer 312, the first and second base layers 313, 314, and the source layer 31.
A source electrode (for example, Al) 323 also serving as an anode electrode is provided in common on each surface of the P layer 5 and the P layer 316 via a barrier metal film (for example, TiW) 322.

On the other surface of the substrate 311, a drain electrode 324 serving also as a cathode electrode is provided on the entire surface.

In the case of the vertical field-effect transistor incorporating the Schottky barrier diode, the first base region 313 forms a MOSFET region 325. Also, the second ring formed in a guard ring shape
Base region 314, the end of the first base region 313, and the first and second base regions 313, 314
The SBD region 326 is constituted by the above-mentioned epitaxial layer 312 between them.

However, in this vertical field-effect transistor, the chip size is merely the size of the combination of the vertical field-effect transistor and the Schottky barrier diode. Therefore, a significant effect cannot be expected in avoiding the adverse effect of increasing the arrangement space.

Accordingly, an object of the present invention is to provide a semiconductor device capable of reducing the chip size and the manufacturing cost and reducing the on-resistance.

[0023]

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type having a first surface and an opposing second surface; A first substrate provided on a first surface of the semiconductor substrate
A semiconductor layer of a conductivity type; first and second base regions of a second conductivity type selectively provided in a surface region of the semiconductor layer;
At least one source region of the first conductivity type selectively provided in a surface region of the first base region; and a depth penetrating the source region and the first base region and reaching the semiconductor layer. A plurality of gate electrodes having a trench structure provided with the semiconductor layer, the first and second gate electrodes,
A source electrode provided on a surface of the base region and the source region, and a drain electrode provided on a second surface of the semiconductor substrate, wherein the first base region;
A transistor region including the source region and the gate electrode and a diode region including the semiconductor layer between the first and second base regions and the first and second base regions are provided on the semiconductor substrate. It is characterized by being provided.

According to the semiconductor device of the present invention, the impurity region (P) of the second conductivity type in the vertical field effect transistor is provided.
Layer or P + layer) can be omitted. Thereby, it is possible to easily realize the simplification of the manufacturing process and the shortening of the trench interval.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 and 2 show a schematic configuration of a vertical field-effect transistor having a built-in Schottky barrier diode according to a first embodiment of the present invention. FIG. 1 is a cross-sectional view of a main part, and FIG.

In FIG. 1, an N− type epitaxial layer (first conductive type semiconductor layer) 12 is provided on one surface (first surface) of an N ++ type substrate (first conductive type semiconductor substrate) 11. ing. In the surface region of the epitaxial layer 12, first and second P-type base layers (first and second base regions of second conductivity type) 13 and 14 are formed. In the surface region of the first base layer 13, an N + type source layer (source region of the first conductivity type) 15 is arranged.

The source layer 15 and the first base layer 13 are provided on the surface of the epitaxial layer 12.
And a plurality of trenches 16 having a depth reaching the epitaxial layer 12. In each trench 16, via a gate oxide film 17,
Gate electrode 18 made of polysilicon or other metal
Are buried. In the case of this embodiment, for example, as shown in FIG. 2, each gate electrode 18 is formed to have a substantially comb-tooth shape that connects the source layers 15 to each other and does not subdivide. This allows, for example,
For each of the source layers 15 divided into a plurality of regions along the cross-sectional direction in the drawing, a power source ("-"
Gate electric field) can be supplied.

On the other hand, on the surface of the epitaxial layer 12, an insulating film 19 and an interlayer film 20 are provided.
The insulating film 19 is provided so as to protect the boundary with the second base layer 14 in the peripheral portion of the epitaxial layer 12. The interlayer film 20 is formed on the gate electrode 1.
8 are provided so as to cover the respective surfaces. Further, including the insulating film 19 and the interlayer film 20, the surface portions of the epitaxial layer 12, the first and second base layers 13, 14 and the source layer 15 are provided with barrier metal films ( For example, via a TiW) 21, a source electrode (for example, A
l) 22 is provided in common.

On the other surface (second surface) of the substrate 11, a drain electrode 23 also serving as a cathode electrode is provided on the entire surface.

In the case of a vertical field-effect transistor having a built-in Schottky barrier diode, the first
The MOSFET region 24 is constituted by the portion of the base region 13. Further, the second base region 14 formed in a guard ring shape, an end of the first base region 13, and the epitaxial layer 12 between the first and second base regions 13 and 14. Thus, a Schottky barrier diode (SBD) region 25 is configured.

According to such a configuration, power can be supplied to each of the continuous source layers 15 from one place. This makes it possible to omit a P layer (or a P + layer) made of, for example, a second conductivity type impurity region for supplying power to each of the source layers as in the related art. As a result, the manufacturing process can be greatly simplified, and the interval between the trenches 16 can be easily reduced.

As described above, in a vertical field effect transistor having a built-in Schottky barrier diode,
The P layer (or P + layer) can be omitted.
That is, by devising the shape of the gate electrode,
Power can be supplied from one location to each of the source layers. Thereby, the P which is conventionally provided for supplying power to each of the source layers is provided.
The layer (or P + layer) can be omitted. Therefore, the manufacturing process can be simplified and the chip size can be reduced as much as at least the P layer (or the P + layer) can be omitted. Therefore, the chip size and the manufacturing cost can be reduced, and the on-resistance can be easily reduced.

Specifically, a P layer between source layers (or
By omitting the (P + layer), an on-resistance reduction effect of about 18% was obtained with the same design rule as in the conventional device.

Further, as the step of forming the P layer (or P + layer) is not required, the process can be reduced by about 9%.

Further, when the Schottky barrier diode is built in the vertical field-effect transistor and integrated into one package, omitting the P layer (or P + layer) can reduce the substrate mounting area by about 25%. It was planned. As a result, it is possible to avoid the problem of increasing the number of components on the circuit and increasing the layout space as in the related art.

The shape of the gate electrode 18 is not limited to the comb-shaped basic pattern shown in the figure. For example, the supply position of the "-" gate electric field may be reduced by, for example, disposing the source layers in a staggered manner. Various possible pattern shapes can be arbitrarily adopted according to the application.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
1 shows a schematic configuration of a vertical field-effect transistor having a built-in Schottky barrier diode according to the embodiment.

In the vertical field effect transistor incorporating the Schottky barrier diode, a part of a P layer (or a P + layer) provided between source layers is arranged at a fixed interval (part is omitted). This is an example in the case of performing.

Specifically, on one surface (first surface) of an N ++ type substrate (first conductivity type semiconductor substrate) 11, an N− type epitaxial layer (first conductivity type semiconductor layer) 12 is provided. Is provided. In the surface region of the epitaxial layer 12, first and second P-type base layers (first and second base regions of second conductivity type) 13 and 14 are formed. In the surface region of the first base layer 13, a plurality of N + type source layers (source regions of the first conductivity type) 15 are arranged at equal intervals. Further, the surface area of the first base layer 13 includes:
A P layer (or P + layer) 31 as a second conductivity type impurity region having a lateral diffusion region 31a is arranged between each source layer 15.

Further, the source layer 15 and the first base layer 1 are provided on the surface of the epitaxial layer 12.
3, a plurality of trenches 16 are formed having a depth reaching the epitaxial layer 12. In each trench 16, a gate electrode 18 made of polysilicon or other metal is buried via a gate oxide film 17. In this embodiment,
Each gate electrode 18 is divided and formed for each source layer 15. Thus, for example, power is supplied from each location to each of the source layers 15 divided into a plurality of regions along the sectional direction in the drawing.

On the other hand, on the surface of the epitaxial layer 12, an insulating film 19 and an interlayer film 20 are provided.
The insulating film 19 is provided so as to protect the boundary with the second base layer 14 in the peripheral portion of the epitaxial layer 12. The interlayer film 20 is formed on the gate electrode 1.
8 are provided so as to cover the respective surfaces. Further, the epitaxial layer 12, the first and second base layers 13 and 14, the source layer 15, and the P layer 31 including on the insulating film 19 and the interlayer film 20.
A barrier metal film (for example, TiW)
A source electrode (for example, Al) 22 also serving as an anode electrode is provided in common via 21.

On the other surface (second surface) of the substrate 11, a drain electrode 23 also serving as a cathode electrode is provided on the entire surface.

In the case of the vertical field-effect transistor incorporating the Schottky barrier diode, the first
The MOSFET region 24 is constituted by the portion of the base region 13. Further, the second base region 14 formed in a guard ring shape, an end of the first base region 13, and the epitaxial layer 12 between the first and second base regions 13 and 14. Thus, a Schottky barrier diode (SBD) region 25 is configured.

In the case of such a structure, the first
Although the process reduction effect and the substrate area reduction effect are not as high as those of the transistor described in the first embodiment, a modest effect can be expected in the on-resistance reduction effect.

(Third Embodiment) FIG. 4 shows a third embodiment of the present invention.
1 shows a schematic configuration of a vertical field-effect transistor having a built-in Schottky barrier diode according to the embodiment. FIG. 2A is a cross-sectional view of a main part, and FIG. 2B is an enlarged view showing a portion surrounded by a circle in FIG.

The vertical field-effect transistor having the Schottky barrier diode built therein has, for example, a structure corresponding to MOSFET region 24 and an SBD region 25 in the structure shown in FIG. This is an example in which the material (film quality) is changed.

Specifically, the barrier metal film 21 is made of SB
A first barrier metal (eg, Mo) 21 a provided corresponding to D region 25 and a second barrier metal (eg, T) provided corresponding to MOSFET region 24.
iW) 21b. First barrier metal 2
The first barrier metal 1a and the second barrier metal 21b are disposed on the first base layer 13 such that their contact portions overlap each other. In this case, as shown in the figure, the second barrier metal 21 is not necessarily formed on the first barrier metal 21a.
b need not be located.

According to such a configuration, it is possible to further enhance the adhesion of the source electrode 22 to the underlying layer.

This configuration is not limited to the case where the present invention is applied to a vertical field-effect transistor having a built-in Schottky barrier diode having the configuration shown in FIG. 1. For example, the Schottky barrier diode having the configuration shown in FIG. The same can be applied to a built-in vertical field effect transistor.

(Fourth Embodiment) FIG. 5 shows a fourth embodiment of the present invention.
1 shows a schematic configuration of a vertical field-effect transistor having a built-in Schottky barrier diode according to the embodiment.

The vertical field-effect transistor incorporating the Schottky barrier diode has, for example, a structure corresponding to MOSFET region 24 and a region corresponding to SBD region 25 in the structure shown in FIG. This is an example where the film thickness is changed.

Specifically, the barrier metal film 21 is made of SB
A first barrier metal (for example, Mo) 21a provided corresponding to D region 25, and a third barrier metal (for example, Mo) provided on the entire surface of epitaxial layer 12 including on first barrier metal 21a. TiW) 21
c.

According to such a configuration, not only can the adhesion of the source electrode 22 to the underlying layer be further improved, but also the source electrode 22
Patterning can be performed simultaneously with c.

This configuration is not limited to the case where the present invention is applied to a vertical field-effect transistor having a built-in Schottky barrier diode having the configuration shown in FIG. 1. For example, the Schottky barrier diode having the configuration shown in FIG. The same can be applied to a built-in vertical field effect transistor.

(Fifth Embodiment) FIG. 6 shows a fifth embodiment of the present invention.
1 shows a schematic configuration of a vertical field-effect transistor having a built-in Schottky barrier diode according to the embodiment.

The vertical field-effect transistor having the built-in Schottky barrier diode includes, for example, a plurality of M
This is an example of a case where the SBD regions 25 are dispersedly arranged between the OSFET regions 24.

Specifically, on one surface (first surface) of an N ++ type substrate (first conductivity type semiconductor substrate) 11, an N− type epitaxial layer (first conductivity type semiconductor layer) 12 is provided. Is provided. In the surface region of the epitaxial layer 12, a plurality of P-type base layers (base regions of the second conductivity type) 1
3 are formed. In the surface area of each base layer 13,
N + type source layers (source regions of the first conductivity type) 15 are arranged.

The surface of the epitaxial layer 12 has a depth penetrating the source layer 15 and the base layer 13 and reaching the epitaxial layer 12.
A plurality of trenches 16 are formed. Each trench 16
In each of them, a gate electrode 18 made of polysilicon or other metal is buried via a gate oxide film 17. In the case of this embodiment, each of the source layers 15 divided into a plurality of regions has a shape capable of supplying power from one place, and
The gate electrode 18 is formed.

On the other hand, on the surface of the epitaxial layer 12, an insulating film 19 and an interlayer film 20 are provided.
The insulating film 19 is provided on the peripheral portion of the epitaxial layer 12 so as to protect the boundary with the base layer 13. The interlayer film 20 is provided so as to cover the surface of the gate electrode 18. Further, a barrier metal film (for example, on the surface of the epitaxial layer 12, the base layer 13, and the source layer 15, including the insulating film 19 and the interlayer film 20).
A source electrode (for example, Al) 22 also serving as an anode electrode is provided in common via TiW) 21.

On the other surface (second surface) of the substrate 11, a drain electrode 23 also serving as a cathode electrode is provided on the entire surface.

In the case of the vertical field-effect transistor incorporating the Schottky barrier diode, the MOSFET region 24 is formed in each portion of the base region 13. Each end of the base region 13 and the epitaxial layer 12 between the base regions 13 form a Schottky barrier diode (SBD) region 25, respectively.

As described above, when the SBD regions 25 are dispersedly arranged between the MOSFET regions 24, substantially the same effects as in the case of the first embodiment can be expected, and the current consumption can be reduced. With the increase, since the heat sources are not concentrated, the breakdown resistance can be improved by the effect of suppressing the temperature rise.

Further, in this configuration, like the vertical field-effect transistor having a built-in Schottky barrier diode (see FIG. 3) described in the second embodiment described above, a further selection is made between the source layers 15. P layer (or
It is also possible to arrange a (P + layer).

In addition, the present invention is not limited to the above-described embodiment, and can be similarly applied to a vertical field effect transistor having a built-in Schottky barrier diode, which employs a P-type substrate.

Further, the present invention is applicable to a field effect transistor having a built-in Schottky barrier diode having a structure in which a gate electrode is arranged on the surface of an element.

Furthermore, the present invention is not limited to the above embodiments, and various modifications can be made in the implementation stage without departing from the scope of the invention. Furthermore, the (each) embodiment includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example,
Even if some components are deleted from all the components shown in the embodiments, at least one of the problems described in the section of the problem to be solved by the invention can be solved, and the effects of the invention can be solved. (At least one of the effects described in the section)
Is obtained, a configuration from which the configuration requirement is deleted can be extracted as an invention.

[0068]

As described above, according to the present invention, the chip size and the manufacturing cost can be reduced.
A semiconductor device capable of reducing on-resistance can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a schematic configuration of a vertical field-effect transistor having a built-in Schottky barrier diode according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view showing a part of FIG.

FIG. 3 is a sectional view showing a schematic configuration of a vertical field-effect transistor having a built-in Schottky barrier diode according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a schematic configuration of a vertical field-effect transistor having a built-in Schottky barrier diode according to a third embodiment of the present invention.

FIG. 5 is a sectional view showing a schematic configuration of a vertical field-effect transistor having a built-in Schottky barrier diode according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view showing a schematic configuration of a vertical field-effect transistor having a built-in Schottky barrier diode according to a fifth embodiment of the present invention.

FIG. 7 is shown to explain the prior art and its problems;
FIG. 3 is a circuit configuration diagram of a synchronous rectifier circuit using a field effect transistor.

FIG. 8 is a configuration diagram showing an example of a vertical field-effect transistor used in the synchronous rectification circuit.

FIG. 9 is a cross-sectional view showing a configuration example of a Schottky barrier diode used in the synchronous rectification circuit.

FIG. 10 is a cross-sectional view showing a schematic configuration of a vertical field-effect transistor having a built-in Schottky barrier diode.

[Explanation of symbols]

 Reference Signs List 11 ... N ++ type substrate 12 ... N- type epitaxial layer 13 ... P type base layer (first) 14 ... P type base layer (second) 15 ... N + type source layer 16 ... trench 17 ... gate oxide film 18 ... gate Electrode 19 ... Insulating film 20 ... Interlayer film 21 ... Barrier metal film 21a ... First barrier metal 21b ... Second barrier metal 21c ... Third barrier metal 22 ... Source electrode 23 ... Drain electrode 24 ... MOSFET region 25 ... Shot Key barrier diode (SBD) region 31 ... P layer (or P + layer) 31a ... lateral diffusion region

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8234 H01L 27/06 102A 27/06 29/48 F 29/872 F term (Reference) 4M104 BB01 BB14 BB16 BB18 CC03 DD96 FF04 FF35 GG03 GG09 GG13 GG18 HH08 HH20 5F048 AA01 AA09 AC10 BA02 BA06 BB01 BB05 BB19 BC03 BC12 BD07 BF02 CB07

Claims (7)

[Claims] A first conductivity type semiconductor substrate having a first surface and an opposing second surface; a first conductivity type semiconductor layer provided on the first surface of the semiconductor substrate; First and second base regions of the second conductivity type selectively provided in the surface region of the semiconductor layer; and at least one first conductive material selectively provided in the surface region of the first base region A source region of a mold, penetrating the source region and the first base region,
A plurality of gate electrodes having a trench structure provided with a depth reaching the semiconductor layer; a source electrode provided on a surface of the semiconductor layer, the first and second base regions and the source region; A drain electrode provided on a second surface of the semiconductor substrate, the first base region, the transistor region including the source region and the gate electrode, the first and second base regions, A semiconductor device, wherein a diode region formed of the semiconductor layer between the first and second base regions is disposed on the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the plurality of gate electrodes are provided so as to connect the source regions between the gate electrodes to each other. 3. The semiconductor device according to claim 1, wherein a second conductivity type impurity region is selectively disposed between said source regions between said gate electrodes. 4. The semiconductor device according to claim 1, wherein the source electrode includes a first barrier metal provided corresponding to the diode region and a second barrier metal provided corresponding to the transistor region. The semiconductor device according to claim 1. 5. The first barrier metal and the second barrier metal.
5. The semiconductor device according to claim 4, wherein the barrier metals are arranged such that their contact portions overlap each other. 6. 6. The semiconductor device according to claim 5, wherein said contact portion is located on said first base region. 7. The semiconductor device according to claim 1, wherein the second base region forms a guard ring.