WO2012017535A1

WO2012017535A1 - Semiconductor device

Info

Publication number: WO2012017535A1
Application number: PCT/JP2010/063259
Authority: WO
Inventors: 新居　浩二; 塚本　康正
Original assignee: ルネサスエレクトロニクス株式会社
Priority date: 2010-08-05
Filing date: 2010-08-05
Publication date: 2012-02-09
Also published as: JP5433788B2; JPWO2012017535A1

Abstract

Provided is a semiconductor device (SCD) that has first and second access gates (AG1, AG2), first and second driver gates (DG1, DG2), and first and second load gates (LG1, LG2), all extending in the same direction in a planar layout. A first direction (D1) from one of a pair of first source/drains (SD1) towards the other and a second direction (D2) from one of a pair of second source/drains (SD2) towards the other are the same in the planar layout. The first directions (D1) for each of at least two SRAM memory cells (MC1, MC2) are the same direction and the second directions (D2) for each are also the same direction. As a result, a semiconductor device (SCD) with improved cell characteristics can be achieved by the reduction in SRAM variation.

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an SRAM.

A semiconductor device called SoC (System on Chip) in which a plurality of logic circuits and memory cells are mounted on one chip is used. In this semiconductor device, for example, an SRAM (Static Random Access Memory) is used as a memory cell.

The miniaturization of SRAM has been attempted due to the demand for mounting a large-capacity SRAM in SoC. This miniaturization increases the variation in the characteristics of the SRAM. Then, the increase in the variation reduces the operation margin of the SRAM. As one of the variations, there is a variation in threshold voltages of transistors constituting the SRAM. The threshold voltage variation includes local variation and global variation. Local variations are caused by the fluctuation of impurities in the transistor. Global variations are variations in processing dimensions due to microfabrication. For example, the gate length or gate width of a transistor occurs in the same direction throughout the chip. In order to reduce local variation and global variation, a layout structure with good symmetry and less bending is effective.

For example, Non-Patent Document 1 proposes an SRAM memory cell having a layout shape with good gate and diffusion layer symmetry and little bending. Since the SRAM memory cell of Non-Patent Document 1 has good symmetry, it is expected to reduce local variations caused by mask displacement. In addition, microfabrication is easy because of less bending. Therefore, reduction of global variation is expected. Non-Patent

Documents

2 and 3 propose SRAM memory cells in which a halo region is formed in order to adjust the threshold voltage. The SRAM memory cells of

Non-Patent Documents

2 and 3 are expected to improve both the read and write operation margins.

In the SRAM memory cell of Non-Patent Document 1, since the source / drains of the two access transistors are arranged in opposite directions, the directions of the currents are reversed. For this reason, the mismatch characteristics due to the cell layout become large, and there is a risk that the variation in cell characteristics becomes large.

Further, in the SRAM memory cell of Non-Patent Document 2, since the gate directions of the access transistor and the driver transistor are orthogonal to each other, there is a risk that local variation due to mask displacement increases. Further, since the direction of the gate is different, fine processing is not easy. For this reason, there is a risk that global variation becomes large.

In the SRAM memory cell of Non-Patent Document 3, since left and right asymmetrical MOSs (Metal Oxide Semiconductors) are separately configured, there is a problem that the amount of impurity implantation varies and local variation increases. In addition, the current directions of the left and right access transistors, driver transistors, and load transistors are reversed. Therefore, there is a problem that the variation in cell characteristics becomes large.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having improved cell characteristics by reducing variations in SRAM.

A semiconductor device according to an embodiment of the present invention is a semiconductor device having at least two static random access memory cells arranged adjacent to each other in a planar layout, and each of the at least two static random access memory cells includes: A first driver transistor having a first driver gate; a first load transistor having a first load gate and electrically connected to the first driver transistor at a first storage node; and a second driver gate having a second driver gate. A driver transistor; a second load transistor having a second load gate and electrically connected to the second driver transistor at a second storage node; and a first bit line and a second bit line for inputting / outputting data A first access gate and a pair of first source / drain One of the pair of first sources / drains is electrically connected to the first storage node, and the other of the pair of first sources / drains is electrically connected to the first bit line. A first access transistor; a second access gate; and a pair of second sources / drains, one of the pair of second sources / drains being electrically connected to the second storage node, and a second bit line And a second access transistor in which the other of the pair of second source / drain is electrically connected. In the planar layout, each of the first and second access gates, the first and second driver gates, and the first and second load gates extends in the same direction. In the planar layout, the first direction from one of the pair of first sources / drains to the other and the second direction from one of the pair of second sources / drains to the other are the same. The first directions of the at least two static random access memory cells are the same as each other, and the second directions are the same as each other.

According to the semiconductor device of one embodiment of the present invention, cell characteristics can be improved by reducing the variation in SRAM.

FIG. 3 is a schematic plan view showing an example of an arrangement relationship of the semiconductor device including the SRAM according to the first embodiment of the present invention. FIG. 2 is a schematic plan view showing the configuration of the SRAM memory cell in the dotted frame shown in FIG. 1 in the first embodiment of the present invention. 2 is a diagram showing an equivalent circuit of the SRAM memory cell in the first embodiment of the present invention. FIG. FIG. 3 is a plan view showing an arrangement pattern of SRAM memory cells in the first embodiment of the present invention. FIG. 5 is a schematic sectional view taken along line VV in FIG. 4. FIG. 5 is a schematic sectional view taken along line VI-VI in FIG. 4. FIG. 5 is a partially enlarged cross-sectional view showing an access transistor along the line VV in FIG. 4. FIG. 3 is a schematic plan view showing all layers of the multilayer line structure of the SRAM memory cell in the first embodiment of the present invention. FIG. 3 is a schematic plan view showing a lower layer of the SRAM memory cell in the first embodiment of the present invention. FIG. 3 is a schematic plan view showing the upper layer of the SRAM memory cell in the first embodiment of the present invention. It is a figure which shows the equivalent circuit matched with the planar layout of the SRAM cell in Embodiment 1 of this invention. FIG. 9 is a schematic plan view showing all layers of the multilayer line structure of the SRAM memory cell adjacent to the SRAM cell shown in FIG. 8 in the first embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing a first step of the method of manufacturing a semiconductor device in the first embodiment of the present invention, which is a schematic cross-sectional view along line VV in FIG. 4 and a line VI-VI in FIG. It is a schematic sectional drawing (B) in alignment with. It is a schematic plan view which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a schematic plan view which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. FIG. 5 is a schematic cross-sectional view showing a third step of the method of manufacturing a semiconductor device in the first embodiment of the present invention, which is a schematic cross-sectional view along line VV in FIG. 4 and a line VI-VI in FIG. It is a schematic sectional drawing (B) in alignment with. It is a schematic plan view which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. FIG. 6 is a schematic cross-sectional view showing a fifth step of the method of manufacturing a semiconductor device in the first embodiment of the present invention, which is a schematic cross-sectional view along line VV in FIG. 4 and a VI-VI line in FIG. It is a schematic sectional drawing (B) in alignment with. It is a schematic plan view which shows the 6th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. FIG. 8 is a schematic cross-sectional view showing a seventh step of the method of manufacturing a semiconductor device in the first embodiment of the present invention, which is a schematic cross-sectional view along line VV in FIG. 4 and a VI-VI line in FIG. It is a schematic sectional drawing (B) in alignment with. It is a schematic plan view which shows the 8th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. FIG. 9 is a schematic cross-sectional view showing a ninth step of the method of manufacturing a semiconductor device in the first embodiment of the present invention, which is a schematic cross-sectional view along line VV in FIG. 4 and a line VI-VI in FIG. It is a schematic sectional drawing (B) in alignment with. FIG. 10 is a schematic cross-sectional view showing a tenth step of the method of manufacturing a semiconductor device in the first embodiment of the present invention, which is a schematic cross-sectional view along line VV in FIG. 4 and a VI-VI line in FIG. It is a schematic sectional drawing (B) in alignment with. FIG. 6 is a schematic cross-sectional view showing an eleventh step of the method for manufacturing a semiconductor device in the first embodiment of the present invention, which is a schematic cross-sectional view along line VV in FIG. 4 and a line VI-VI in FIG. It is a schematic sectional drawing (B) in alignment with. FIG. 15 is a schematic cross-sectional view showing a twelfth step of the method of manufacturing a semiconductor device in the first embodiment of the present invention, which is a schematic cross-sectional view along line VV in FIG. 4 and a VI-VI line in FIG. It is a schematic sectional drawing (B) in alignment with. FIG. 3 is a plan view showing an arrangement of SRAM memory cells in the SRAM cell array of the semiconductor device in the first embodiment of the present invention. FIG. 3 is a plan view schematically showing the arrangement pattern of SRAM memory cells and the direction of current in the semiconductor device in the first embodiment of the present invention. It is a schematic plan view which shows the lower layer of the SRAM memory cell of the semiconductor device in Embodiment 1 of this invention, Comprising: It is a figure which shows the case where a gate is formed in round shape. FIG. 10 is a schematic plan view showing a lower layer of an SRAM memory cell according to a modified example in the first embodiment of the present invention. FIG. 30 is a schematic cross-sectional view taken along line XXX-XXX in FIG. 29. FIG. 30 is a schematic sectional view taken along line XXXI-XXXI in FIG. 29. It is a schematic plan view which shows the arrangement pattern of the SRAM memory cell of the semiconductor device in a comparative example. It is a figure which shows the equivalent circuit of the SRAM memory cell in a comparative example. It is a top view which shows typically the arrangement pattern and direction of an electric current of the SRAM memory cell of the semiconductor device in a comparative example. It is a schematic plan view which shows the lower layer of the SRAM memory cell of the semiconductor device in Embodiment 2 of this invention. It is a schematic plan view which shows all the layers of the multilayer line structure of the SRAM memory cell of the semiconductor device in Embodiment 3 of this invention. It is a schematic plan view which shows the lower layer of the SRAM memory cell of the semiconductor device in Embodiment 4 of this invention. FIG. 38 is a schematic sectional view taken along line XXXVIII-XXXVIII in FIG. FIG. 38 is a schematic sectional view taken along line XXXIX-XXXIX in FIG. 37. FIG. 38 is a partial enlarged cross-sectional view showing an access transistor along the line XXXVIII-XXXVIII in FIG. 37. 41 is a graph showing an impurity concentration profile in a halo region of the access transistor of FIG. 40. 38 is a schematic cross-sectional view showing a first step of the method of manufacturing a semiconductor device in the fourth embodiment of the present invention, and is a schematic cross-sectional view (A) taken along line XXXVIII-XXXVIII in FIG. 37 and a line XXXIX-XXXIX in FIG. It is a schematic sectional drawing (B) in alignment with. It is a schematic plan view which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 4 of this invention. 37 is a schematic cross-sectional view showing a step before the third step of the method for manufacturing a semiconductor device in the fourth embodiment of the present invention, which is a schematic cross-sectional view along the line XXXVIII-XXXVIII in FIG. 37; FIG. 6 is a schematic cross-sectional view (B) along the line XXXIX-XXXIX. 37 is a schematic cross sectional view showing a step after the third step of the method for manufacturing a semiconductor device in the fourth embodiment of the present invention, which is a schematic cross sectional view (A) taken along line XXXVIII-XXXVIII in FIG. FIG. 6 is a schematic cross-sectional view (B) along the line XXXIX-XXXIX. 38 is a schematic cross-sectional view showing a fourth step of the method of manufacturing a semiconductor device in the fourth embodiment of the present invention, which is a schematic cross-sectional view (A) along the line XXXVIII-XXXVIII in FIG. 37 and a line XXXIX-XXXIX in FIG. It is a schematic sectional drawing (B) in alignment with. It is a schematic plan view which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 4 of this invention. FIG. 38 is a schematic cross-sectional view showing a step before the sixth step of the method for manufacturing a semiconductor device in the fourth embodiment of the present invention, which is a schematic cross-sectional view along the line XXXVIII-XXXVIII in FIG. FIG. 6 is a schematic cross-sectional view (B) along the line XXXIX-XXXIX. It is a schematic plan view which shows the 7th process of the manufacturing method of the semiconductor device in Embodiment 4 of this invention. 37 is a schematic cross-sectional view showing a step before the seventh step of the method for manufacturing a semiconductor device in the fourth embodiment of the present invention, which is a schematic cross-sectional view along the line XXXVIII-XXXVIII in FIG. 37; FIG. 6 is a schematic cross-sectional view (B) along the line XXXIX-XXXIX. It is a schematic plan view which shows the 8th process of the manufacturing method of the semiconductor device in Embodiment 4 of this invention. 37 is a schematic cross-sectional view showing a step before the ninth step of the method for manufacturing a semiconductor device in the fourth embodiment of the present invention, which is a schematic cross-sectional view along the line XXXVIII-XXXVIII in FIG. 37; FIG. 6 is a schematic cross-sectional view (B) along the line XXXIX-XXXIX. 37 is a schematic cross sectional view showing a step before the tenth step of the method for manufacturing a semiconductor device in the fourth embodiment of the present invention, which is a schematic cross sectional view (A) along the line XXXVIII-XXXVIII in FIG. 37; FIG. 6 is a schematic cross-sectional view (B) along the line XXXIX-XXXIX. 37 is a schematic cross-sectional view showing a step before an eleventh step of the method for manufacturing a semiconductor device in the fourth embodiment of the present invention, which is a schematic cross-sectional view along the line XXXVIII-XXXVIII in FIG. 37; FIG. 6 is a schematic cross-sectional view (B) along the line XXXIX-XXXIX. FIG. 38 is a schematic cross-sectional view showing a step before the twelfth step of the method for manufacturing a semiconductor device in the fourth embodiment of the present invention, which is a schematic cross-sectional view along the line XXXVIII-XXXVIII in FIG. FIG. 6 is a schematic cross-sectional view (B) along the line XXXIX-XXXIX. It is the schematic which shows the electric current which flows into the access transistor in Embodiment 4 of this invention. It is a graph which shows the current characteristic with respect to the gate voltage in the access transistor in Embodiment 4 of this invention. It is a schematic plan view which shows the lower layer of the SRAM memory cell in Embodiment 5 of this invention. It is a schematic plan view which shows 1 process of the manufacturing method of the semiconductor device in Embodiment 5 of this invention. It is a schematic plan view which shows all the layers of the multilayer line structure of the SRAM memory cell in Embodiment 6 of this invention. It is a schematic plan view which shows the lower layer of the SRAM memory cell in Embodiment 6 of this invention. FIG. 62 is a schematic sectional view taken along line LXII-LXII in FIG. 61. It is a schematic plan view which shows the upper layer of the SRAM memory cell in Embodiment 6 of this invention. It is a figure which shows the equivalent circuit matched with the planar layout of the SRAM cell in Embodiment 6 of this invention. It is a schematic plan view which shows the lower layer of the SRAM memory cell of the modification in Embodiment 6 of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
First, the configuration of the semiconductor device according to the first embodiment of the present invention will be described. First, an example of a semiconductor device called SoC incorporating an SRAM will be described.

Referring to FIG. 1, the semiconductor device SCD mainly includes an SRAM unit SR, a logic circuit LC, and an IO (Input / Output) area IO. In the semiconductor device SCD, a micro control unit, an analog-digital converter, a digital-analog converter, a bus controller, etc., each of which is connected to a plurality of logic circuits LC that realize specific functions, and some of the logic circuits LC temporarily store data. The SRAM unit SR for storing is mounted on one chip. An IO region IO is formed so as to surround the logic circuit LC and the SRAM portion SR.

Referring to FIG. 2, SRAM section SR includes SRAM cell array MA having a plurality of memory cells arranged in a matrix, X decoder XD, Y decoder YD, sense amplifier SA, write driver WD, and main control circuit MC. Has mainly.

Next, an equivalent circuit of the SRAM memory cell will be described. Referring to FIG. 3, the SRAM memory cell includes a flip-flop obtained by cross-coupling two inverters, and a first access transistor NA1 and a second access transistor NA2. The flip-flop is provided with a first storage node SN1 and a second storage node SN2 that are cross-coupled.

The first access transistor NA1 and the second access transistor NA2 are connected between the first storage node SN1 and the second storage node SN2, the first bit line BL, and the second bit line / BL. When the first bit line BL is in the positive phase, the second bit line / BL is in the reverse phase. The gates of the first access transistor NA1 and the second access transistor NA2 are connected to the word line WL.

In the flip-flop, the first driver transistor ND1 and the third driver transistor ND3 are connected in parallel between the first storage node SN1 and the ground wiring (ground potential) VSS. A second driver transistor ND2 and a fourth driver transistor ND4 are connected in parallel between the second storage node SN2 and the ground wiring VSS.

Further, the first load transistor PL1 is connected between the first storage node SN1 and the power supply wiring VDD. The first load transistor PL1 is connected in series to each of the first driver transistor ND1 and the third driver transistor ND3. A second load transistor PL2 is connected between the second storage node SN2 and the power supply wiring VDD. The second load transistor PL2 is connected in series to each of the second driver transistor ND2 and the fourth driver transistor ND4. By providing the third driver transistor ND3 and the fourth driver transistor ND4, the current of the driver transistor can be increased.

The gates of the first driver transistor ND1 and the third driver transistor, the gate of the first load transistor PL1, and the second storage node SN2 are electrically connected to each other. Further, the gates of the second driver transistor ND2 and the fourth driver transistor ND4, the gate of the second load transistor PL2, and the first storage node SN1 are electrically connected to each other. The load transistors PL1 and PL2 are P-channel insulated gate field effect transistors, and the access transistors NA1 and NA2 and the drive transistors ND1 to ND4 are N-channel insulated gate field effect transistors.

In addition, although the case where the SRAM memory cell includes four driver transistors has been described above, it is sufficient that two driver transistors are provided. That is, although the case where the third driver transistor ND4 and the fourth driver transistor ND4 are provided in addition to the first driver transistor ND1 and the second driver transistor ND3 has been described, the third driver transistor ND3 and the fourth driver transistor ND4 are provided. It does not have to be.

Next, the structure of the SRAM memory cell will be described. FIG. 4 is a schematic plan view showing a planar layout of the transistors constituting the SRAM memory cell of the SRAM cell array and the contacts connected to the transistors. In FIG. 4, the first metal wiring electrically connected to the contact, the second metal wiring electrically connected to the first metal wiring through a via hole, and the second metal wiring electrically connected through the via hole. A third metal wiring is also shown.

Referring to FIG. 4, each of the areas surrounded by a dotted line constitutes one SRAM memory cell. One SRAM memory cell is arranged so that a part of the active region, contact, and metal wiring of another adjacent SRAM memory cell enter. The SRAM memory cell MC1 will be described as a representative example. As described above, the SRAM memory cell MC1 includes the first and second access transistors NA1 and NA2, the first to fourth driver transistors ND1 to ND4, and the first and second load transistors PL1 and PL2. .

In the planar layout, the SRAM memory cell MC2 is arranged adjacent to the SRAM memory cell MC1 in the direction in which the first bit line BL and the second bit line / BL extend across the SRAM memory cell MC1. In the SRAM memory cell MC1 and the SRAM memory cell MC2, the first to fourth driver transistors ND1 to ND4 and the first and second load transistors PL1 and PL2 respectively include the SRAM memory cell MC1 and the SRAM memory cell MC2 in the planar layout. Are arranged in line symmetry (mirror symmetry) with respect to a virtual boundary line VL.

On the main surface of the semiconductor substrate SS, element formation regions FRN and FRP that are electrically isolated from each other are defined by forming an element isolation region IR. The element formation region FRN is formed in an NMIS (N channel type Metal Insulator Semiconductor) region RN. In the element formation region FRN, first and second access transistors NA1 and NA2 and first to fourth driver transistors ND1 to ND4 are formed as n-channel MIS transistors.

The element formation region FRP is formed in a PMIS (P channel type Metal Insulator Semiconductor) region RP. In the element formation region FRP, first and second load transistors PL1 and PL2 are formed as p-channel type MIS transistors.

The first access transistor NA1 has a first access gate AG1 and a pair of first source / drain SD1. One of the pair of first source / drain SD1 is electrically connected to the first storage node SN1, and the other of the pair of first source / drain SD1 is electrically connected to the first bit line BL. The second access transistor NA2 has a second access gate AG2 and a pair of second source / drain SD2. One of the pair of second source / drain SD2 is electrically connected to the second storage node SN2, and the other of the pair of second source / drain SD2 is electrically connected to the second bit line / BL. .

The first driver transistor ND1 has a first driver gate DG1 and a pair of third source / drain SD3. One of the pair of third source / drain SD3 is electrically connected to the first storage node SN1, and the other of the pair of third source / drain SD3 is electrically connected to the ground wiring VSS. The second driver transistor ND2 has a second driver gate DG2 and a pair of fourth source / drain SD4. One of the pair of fourth source / drain SD4 is electrically connected to the second storage node SN2, and the other of the pair of fourth source / drain SD4 is electrically connected to the ground wiring VSS.

The third driver transistor ND3 has a third driver gate DG3 and a pair of fifth source / drain SD5. One of the pair of fifth source / drain SD5 is electrically connected to the first storage node SN1, and the other of the pair of fifth source / drain SD5 is electrically connected to the ground wiring VSS. The fourth driver transistor ND4 has a fourth driver gate DG4 and a pair of sixth source / drain SD6. One of the pair of sixth source / drain SD6 is electrically connected to the second storage node SN2, and the other of the pair of sixth source / drain SD6 is electrically connected to the ground wiring VSS.

The first load transistor PL1 has a first load gate LG1 and a pair of source / drain. The first load transistor PL1 is electrically connected to the first driver transistor ND1 at the first storage node SN1. The second load transistor PL2 has a first load gate LG2 and a pair of source / drain. The second load transistor PL2 is electrically connected to the second driver transistor ND2 at the second storage node SN2.

The first access gate AG1 of the first access transistor NA1, the second access gate AG2 of the second access transistor NA2, the first driver gate DG1 of the first driver transistor ND1, and the second driver gate DG2 of the second driver transistor ND2. The third driver gate DG3 of the third driver transistor ND3 and the fourth driver gate DG4 of the fourth driver transistor ND4 are formed so as to cross the element formation region FRN. The first load gate LG1 of the first load transistor PL1 and the second load gate LG2 of the second load transistor PL2 are formed so as to cross the element formation region FRP.

In the planar layout, each of the first access gate AG1 and the second access gate AG2 is formed to extend in the same direction. The first driver gate DG1, the second driver gate DG2, the third driver gate DG3, the fourth driver gate DG4, the first load gate LG1, and the second load gate LG2 are formed to extend in the same direction. Yes.

In the planar layout, the first direction D1 from one of the pair of first source / drain SD1 to the other and the second direction D2 from one of the pair of second source / drain SD2 to the other are the same. is there. The first directions D1 of the SRAM memory cell MC1 and the SRAM memory cell MC2 are the same direction, and the second directions D2 are the same direction.

In the planar layout, the third direction D3 from one of the pair of third source / drain SD3 toward the other is opposite to the fifth direction D5 from one of the pair of fifth source / drain SD5 toward the other. is there. Further, the fourth direction D4 from one of the pair of fourth source / drain SD4 to the other is opposite to the sixth direction D6 from one of the pair of sixth source / drain SD6 to the other.

In the planar layout, the fifth direction D5 from one of the pair of fifth source / drain SD5 to the other and the sixth direction D6 from one of the pair of sixth source / drain SD6 to the other are the same. is there. Further, the fifth directions D5 of the SRAM memory cell MC1 and the SRAM memory cell MC2 are the same as each other, and the sixth directions D6 are the same as each other. Note that “a pair of source / drain” simply means an impurity region that forms a pair of conduction terminals of a field effect transistor (an N-type impurity region for an N-channel transistor, a P-type for a P-channel transistor) The impurity regions of the pair of impurity regions do not necessarily mean that each of the pair of impurity regions becomes either a source terminal or a drain terminal.

5 is orthogonal to the extending direction of the first access gate AG1 so as to pass through the first access transistor NA1 of the SRAM memory cell MC1 and the contact C21 of the SRAM memory cell MC2 adjacent to the SRAM memory cell MC1 in FIG. FIG. 5 is a schematic cross-sectional view along a cross-sectional line VV.

An extension region ER, a first source / drain SD1, and a metal silicide film SCL are formed in a portion of the element formation region FRN located on the opposite side of the first access gate AG1 from the side where the dummy gate DU is located. ing.

In the element forming region FRN located between the first access gate AG1 and the dummy gate DU, the first source / drain SD1, the metal silicide film SCL, and the element isolation region IR are formed. The first source / drain SD1 and the metal silicide film SCL of the SRAM memory cell MC2 are formed in the element formation region FRN located on the opposite side of the dummy gate DU from the side where the first access gate AG1 is located. Has been.

A stress liner film SL such as a silicon nitride film is formed so as to cover the first access gate AG1 and the dummy gate DU. An interlayer insulating film IL1 such as a silicon oxide film (eg, TEOS (Tetra Ethyl Ortho Silicate) film) is formed so as to cover the stress liner film SL.

A plug PG1 penetrating the interlayer insulating film IL1 and the stress liner film SL and electrically connected to the metal silicide film SCL is formed. The plug PG1 includes a barrier metal film BA1 such as a TiN film and a tungsten film TL1. The plugs PG1 connected to the metal silicide film SCL constitute the contacts C1, C2, and C21 shown in FIG.

An etching stopper film ES1 such as a silicon nitride film is formed on the interlayer insulating film IL1 so as to cover the plug PG1. An interlayer insulating film IL2 such as a silicon oxide film is formed on the etching stopper film ES1. A copper wiring CW1 that penetrates through the interlayer insulating film IL2 and the etching stopper film ES1 and is electrically connected to the plug PG1 is formed. The copper wiring CW1 includes a barrier metal film BA2 such as a TaN film and a copper film CL1. Copper wirings CW1 connected to the plugs PG1 respectively constitute first metal wirings M1, M2, and M14 shown in FIG.

An interlayer insulating film IL3 such as a silicon oxide film is formed on the interlayer insulating film IL2 so as to cover the copper wiring CW1. A plug PG2 penetrating through the interlayer insulating film IL3 and electrically connected to the copper wiring CW1 is formed. The plug PG2 includes a barrier metal film BA3 such as a TiN film and a tungsten film TL2. The plugs PG2 connected to the copper wiring CW1 respectively constitute the via holes V1 and V11 shown in FIG.

A copper wiring CW2 electrically connected to the plug PG2 is formed on the interlayer insulating film IL3 so as to cover the plug PG2. The copper wiring CW2 includes a barrier metal film BA4 such as a TaN film and a copper film CL2. The copper wiring CW2 connected to the plug PG2 constitutes the second metal wiring M21 shown in FIG.

An interlayer insulating film IL4 such as a silicon oxide film is formed so as to cover the copper wiring CW2. An etching stopper film ES2 such as a silicon nitride film is formed on the interlayer insulating film IL4. On the etching stopper film ES2, an interlayer insulating film IL5 such as a silicon oxide film is formed. Copper wiring CW3 is formed through interlayer insulating film IL5 and etching stopper film ES2. The copper wiring CW3 includes a barrier metal film BA5 such as a TaN film and a copper film CL3. Copper interconnection CW3 constitutes third metal interconnection M31 shown in FIG.

FIG. 6 is a schematic sectional view taken along a sectional line VI-VI orthogonal to the extending direction of the first driver gate DG1 so as to pass through the first driver transistor ND1 and the third driver transistor ND3 of the SRAM memory cell MC1 in FIG. It is.

The extension region ER, the third source / drain SD3, and the metal silicide film SCL are formed in the element formation region FRN located on the opposite side of the first driver gate DG1 from the side where the third driver gate DG3 is located. Is formed.

An extension region ER, a third source / drain SD3, a fifth source / drain SD5, and a metal silicide film SCL are formed in a portion of the element formation region FRN located between the first driver gate DG1 and the third driver gate DG3. Has been.

The extension region ER, the fifth source / drain SD5, and the metal silicide film SCL are formed in the element formation region FRN located on the opposite side of the third driver gate DG3 from the side where the first driver gate DG1 is located. Is formed.

A stress liner film SL such as a silicon nitride film is formed so as to cover the first driver gate DG1 and the third driver gate DG3. An interlayer insulating film IL1 such as a silicon oxide film (for example, a TEOS film) is formed so as to cover the stress liner film SL. A plug PG1 penetrating through the interlayer insulating film IL1 and the stress liner film SL and electrically connected to the metal silicide film SCL is formed. The plug PG1 includes a barrier metal film BA1 such as a TiN film and a tungsten film TL1. The plugs PG1 connected to the metal silicide film SCL respectively constitute contacts C5, C6, C7 shown in FIG.

An etching stopper film ES1 such as a silicon nitride film is formed on the interlayer insulating film IL1 so as to cover the plug PG1. An interlayer insulating film IL2 such as a silicon oxide film is formed on the etching stopper film ES1. A copper wiring CW1 that penetrates through the interlayer insulating film IL2 and the etching stopper film ES1 and is electrically connected to the plug PG1 is formed. The copper wiring CW1 includes a barrier metal film BA2 such as a TaN film and a copper film CL1. The copper wirings CW1 connected to the plugs PG1 respectively constitute the first metal wirings M1, M4, M5 shown in FIG.

An interlayer insulating film IL3 such as a silicon oxide film is formed on the interlayer insulating film IL2 so as to cover the copper wiring CW1. A plug PG2 penetrating through the interlayer insulating film IL3 and electrically connected to the copper wiring CW1 is formed. The plug PG2 includes a barrier metal film BA3 such as a TiN film and a tungsten film TL2. The plugs PG2 connected to the copper wiring CW1 respectively constitute via holes V3 and V4 shown in FIG.

A copper wiring CW2 electrically connected to the plug PG2 is formed on the interlayer insulating film IL3 so as to cover the plug PG2. The copper wiring CW2 includes a barrier metal film BA4 such as a TaN film and a copper film CL2. The copper wiring CW2 connected to the plug PG2 constitutes the second metal wiring M22 shown in FIG.

Next, the structure of the access transistor will be described in detail. FIG. 7 shows a cross-sectional structure along a cross-sectional line corresponding to the VV line shown in FIG. The first access transistor NA1 will be described as an example of the access transistor structure, but the second access transistor NA2 has the same structure.

Referring to FIG. 7, the first access gate AG1 of the first access transistor NA1 formed so as to cross the element formation region FRN (see FIG. 4) is respectively formed on an interface layer (Inter Layer) SF such as SiON. A high-k film HK having a predetermined dielectric constant such as La-containing HfO ₂ and HfSiON, a metal film ML having a predetermined work function such as TiN, and a polysilicon (polycrystalline silicon) film PS are formed in a stacked manner; A metal silicide film SCL such as nickel silicide is further formed on the surface of the polysilicon film PS. On both side surfaces of first access gate AG1, offset spacers OS such as a silicon nitride film are formed. On the offset spacer OS, a sidewall spacer SW made of a silicon oxide film SO and a silicon nitride film SNI is formed.

The extension region ER, the source / drain SD1, and the metal silicide film SCL are formed in the element forming region in the direction orthogonal to the direction in which the first access gate AG1 extends (gate length direction).

Next, a multilayer wiring structure for electrically connecting the transistors will be described. FIG. 8 is a schematic plan view showing the connection relationship between each transistor of the SRAM memory cell and the third metal wiring. FIG. 9 is a schematic plan view showing a connection structure between each transistor and the first metal wiring. FIG. 10 is a plan view showing a connection structure between the second metal wiring and the third metal wiring. FIG. 11 is a diagram showing an equivalent circuit of the SRAM memory cell shown in accordance with the planar layout of FIG.

FIG. 12 is a schematic plan view showing a planar layout of the SRAM memory cell adjacent to the SRAM memory cell shown in FIG. 8 to 10 show a multilayer wiring structure for one SRAM memory cell. The multilayer wiring structure on the adjacent SRAM memory cell is shown in FIG. 8, as shown in FIG. Except for the transistors, the wiring pattern is formed in line symmetry (mirror symmetry) with respect to a virtual boundary line VL (see FIG. 4) between the adjacent SRAM memory cells. Therefore, the SRAM memory cell MC1 will be mainly described.

8 to 10, one of the first source / drain SD1 of the first access transistor NA1 is connected via the contact C1 (plug PG1), the first metal wiring M1 (copper wiring CW1) and the contact C5. One of the third source / drain SD3 of the first driver transistor ND1 and one of the fifth source / drain SD5 of the third driver transistor ND3 are electrically connected.

One of the first source / drain SD1 of the first access transistor NA1 is connected to one of the SD of the first load transistor PL1 and the second of the second load transistor PL2 via the contact C1, the first metal wiring M1, and the contact C9. The second load gate LG2, the second driver gate DG2 of the second driver transistor ND2, and the fourth driver gate DG4 of the fourth driver transistor ND4 are electrically connected.
The other of the first source / drain SD1 of the first access transistor NA1 is the second metal wiring as the bit line BL via the contact C2 (plug PG1), the first metal wiring M2 (copper wiring CW1) and the via hole V1. It is electrically connected to M21.

The first access gate AG1 of the first access transistor NA1 is connected to the third metal wiring M31 as the word line WL through the contact C4, the first metal wiring M3, the via hole V2, the second metal wiring M26, and the via hole V21. Electrically connected. The dummy gate DU is electrically connected to the third metal wiring M31 as the word line WL through the contact C3, the first metal wiring M3, the via hole V2, the second metal wiring M26, and the via hole V21.

The other of the third source / drain SD3 of the first driver transistor ND1 is electrically connected to a second metal wiring M22 as a ground wiring VSS to which a ground potential is applied via the contact C6, the first metal wiring M1 and the via hole V3. It is connected to the. The other of the fifth source / drain SD5 of the third driver transistor ND1 is electrically connected to the second metal wiring M22 as the ground wiring VSS to which the ground potential is applied through the contact C7, the first metal wiring M5 and the via hole V4. It is connected to the.

The other of the source / drain SD of the first load transistor PL1 is electrically connected to the second metal wiring M23 as the power supply wiring VDD through the contact C8, the first metal wiring M6, and the via hole V5.

One of the first source / drain SD2 of the second access transistor NA2 and one of the fourth source / drain SD4 of the second driver transistor ND2 and the fourth driver via the contact C11, the first metal wiring M8 and the contact C15. The transistor ND4 is electrically connected to one of the sixth source / drain SD6.

One of the second source / drain SD2 of the second access transistor NA2 is connected to one of the SD of the second load transistor PL2 and the first of the first load transistor PL1 via the contact C11, the first metal wiring M8, and the contact C18. The first load gate LG1, the first driver gate DG3 of the first driver transistor ND3, and the third driver gate DG3 of the third driver transistor ND3 are electrically connected.
The other of the second source / drain SD2 of the second access transistor NA2 is electrically connected to the second metal wiring M24 as the bit line / BL via the contact C12, the first metal wiring M9 and the via hole V6. Yes.

The second access gate AG2 of the second access transistor NA2 is connected to the third metal wiring M31 as the word line WL through the contact C14, the first metal wiring M10, the via hole V10, the second metal wiring M27, and the via hole V22. Electrically connected. The dummy gate DU is electrically connected to the third metal wiring M31 as the word line WL through the contact C13, the first metal wiring M10, the via hole V22, the second metal wiring M27, and the via hole V22.

The other of the fourth source / drain SD4 of the second driver transistor ND2 is electrically connected to the second metal wiring M25 as the ground wiring VSS to which the ground potential is applied through the contact C16, the first metal wiring M11, and the via hole V7. It is connected to the. The other of the sixth source / drain SD6 of the fourth driver transistor ND4 is electrically connected to the second metal wiring M25 as the ground wiring VSS to which the ground potential is applied through the contact C17, the first metal wiring M12, and the via hole V8. It is connected to the.

The other of the source / drain SD of the second load transistor PL2 is electrically connected to the second metal wiring M23 as the power supply wiring VDD through the contact C19, the first metal wiring M13, and the via hole V9.

Therefore, as shown in FIG. 4, the common word line WL is connected to the contacts C1 and C11 in the SRAM memory cell MC1. A ground wiring VSS is connected to the contacts C6, C7, C16, and C17. A power supply wiring VDD is connected to the contacts C8 and C19. Bit lines BL and / BL are connected to contacts C2 and C12, respectively. Contacts C1 and C5 constitute storage node SN1, and contacts C11 and C15 constitute storage node SN2.

In the SRAM memory cell MC2 adjacent to the SRAM memory cell MC1, the contact C21 is electrically connected to the bit line BL via the first metal wiring M14 and the via hole V11.

Next, a method for manufacturing the semiconductor device described above will be described. The semiconductor device includes a logic circuit in addition to the SRAM circuit. Here, a method for forming the access transistor and the driver transistor of the SRAM memory cell will be mainly described. In FIG. 13, FIG. 16, FIG. 18, FIG. 20, FIG. 22, and FIG. 23 to FIG. 25 referred to hereinafter, each figure (A) is a cross section taken along a cross-sectional line corresponding to the VV line shown in FIG. Each structure (B) shows a cross-sectional structure along a cross-sectional line corresponding to the VI-VI line shown in FIG.

First, referring to FIGS. 13A, 13B, and 14, element formation regions FRN and FRP that are electrically isolated from each other by forming element isolation region IR on the main surface of semiconductor substrate SS are provided. It is prescribed. The element formation regions FRN and FRP are formed so as to straddle regions that become SRAM memory cells adjacent to each other. Next, a p-well PW is formed in the element formation region FRN.

Next, a high-k film HK having a predetermined dielectric constant, a metal film ML having a predetermined work function, and a polysilicon film PS are stacked on the surface of the semiconductor substrate SS with an interface layer SF interposed therebetween. A gate structure G to be the first access gate AG1 and the dummy gate DU and a gate structure G to be the first driver gate DG1 and the third driver gate DG3 are formed. The gate structure G is formed so as to straddle a region to be an SRAM memory cell adjacent to each other. Next, for example, a silicon nitride film (not shown) is formed on the semiconductor substrate SS so as to cover the gate structure G. Next, the silicon nitride film is anisotropically etched to form offset spacers OS on both side surfaces of the gate structure G.

Next, referring to FIG. 15, by performing a predetermined photoengraving process, a resist mask RM1 that exposes NMIS region RN and covers PMIS region RP is formed. The resist mask RM1 exposes the gate structure G to be the first access gate AG1, the gate structure G to be the first driver gate DG1, and the gate structure G to be the third driver gate DG3 through one opening, and the second The gate structure G to be the access gate AG2, the gate structure G to be the second driver gate DG2, and the gate structure G to be the fourth driver gate DG4 are formed in a pattern exposed through one opening. That is, each opening of the resist mask RM1 is continuously formed so as to straddle the adjacent SRAM memory cell MC1 and SRAM memory cell MC2.

Next, referring to FIGS. 16A and 16B, using resist mask RM1 as an implantation mask, for example, phosphorus or arsenic is implanted into semiconductor substrate SS from a direction perpendicular to the main surface of semiconductor substrate SS. Thus, an extension region ER is formed from the exposed surface of the p-well PW to a predetermined depth (extension implantation). Thereafter, the resist mask RM1 is removed.

Next, referring to FIG. 17, a resist mask RM2 that covers NMIS region RN and exposes PMIS region RP is formed. Next, using the resist mask RM2 as an implantation mask, for example, boron is implanted into the semiconductor substrate SS from a direction perpendicular to the main surface of the semiconductor substrate SS, thereby forming an extension region (not shown). Thereafter, the resist mask RM2 is removed.

Next, for example, a silicon oxide film and a silicon nitride film (not shown) are sequentially formed so as to cover the gate structure G (first access gate AG1, dummy gate DU, first driver gate DG1, third driver gate DG3, etc.). It is formed. Next, referring to FIGS. 18A and 18B, anisotropic etching is performed on the silicon oxide film and the silicon nitride film to form the silicon oxide film SO on both side surfaces of the gate structure G. Sidewall spacers SW made of the silicon nitride film SNI are formed.

Next, referring to FIG. 19, a resist mask RM3 that exposes NMIS region RN and covers PMIS region RP is formed. Next, referring to FIGS. 20A and 20B, for example, phosphorus or arsenic is perpendicular to the main surface of semiconductor substrate SS using resist mask RM3 (FIG. 19) and sidewall spacer SW as an implantation mask. By injecting into the semiconductor substrate SS from the direction, the first source / drain SD1, the third source / drain SD3, and the fifth source / drain SD5 are formed from the exposed surface of the p-well PW to a predetermined depth. Thereafter, the resist mask RM3 is removed.

Next, referring to FIG. 21, a resist mask RM4 that covers NMIS region RN and exposes PMIS region RP is formed. Next, using the resist mask RM4 and the sidewall spacer SW as an implantation mask, for example, boron is implanted into the semiconductor substrate SS from a direction perpendicular to the main surface of the semiconductor substrate SS, thereby exposing the surface of the exposed element formation region FRP. A source / drain (not shown) is formed from a predetermined depth to a predetermined depth. Thereafter, the resist mask RM4 is removed.

Next, referring to FIGS. 22A and 22B, a predetermined annealing process is performed to thermally diffuse the implanted impurities, thereby providing a first source / drain SD1 and a third source / drain SD3. The fifth source / drain SD5 and the extension region ER are activated. At this time, the first source / drain SD1, the third source / drain SD3, the fifth source / drain SD5, and the extension region ER expand in the horizontal direction and the vertical (depth) direction due to the thermal diffusion of the impurities. Become.

Next, referring to FIGS. 23A and 23B, the exposed first source / drain SD1, third source / drain SD3, fifth source / drain SD5, first access gate are exposed by the salicide process. A metal silicide film SCL such as nickel silicide is formed on the surface of the polysilicon film PS of the AG1, dummy gate DU, first driver gate DG1, and third driver gate DG3. Next, referring to FIGS. 24A and 24B, for example, a silicon nitride film or the like is formed so as to cover first access gate AG1, dummy gate DU, first driver gate DG1 and third driver gate DG3. A stress liner film SL is formed. An interlayer insulating film IL1 such as a silicon oxide film (for example, a TEOS film) is formed so as to cover the stress liner film SL.

Next, referring to FIGS. 25A and 25B, by performing anisotropic etching on interlayer insulating film IL1, contact hole CH exposing metal silicide film SCL is formed. Next, a barrier metal film BA1 such as titanium nitride (TiN) is formed so as to cover the inner wall of the contact hole CH, and further, the tungsten film is filled on the barrier metal film BA1. TL1 is formed. Next, by performing a chemical mechanical polishing process (CMP: Chemical Mechanical Polishing), the barrier metal film and the tungsten film located on the upper surface of the interlayer insulating film IL1 are removed, and FIGS. As shown in B), a plug PG1 including a barrier metal film BA1 and a tungsten film TL1 is formed in the contact hole CH.

Next, as shown in FIGS. 5 and 6, an etching stopper film ES1 such as a silicon nitride film is formed so as to cover the plug PG1. An interlayer insulating film IL2 such as a silicon oxide film is formed on the etching stopper film ES1. Next, a groove exposing the surface of the plug PG1 is formed. Next, a barrier metal film BA2 such as tantalum nitride (TaN) is formed so as to cover the inner wall of the groove, and further, a copper film CL1 is formed on the barrier metal film BA2 so as to fill the groove. Is done. Next, a portion of the barrier metal film and the copper film located on the upper surface of the interlayer insulating film IL2 is removed by performing chemical mechanical polishing, and the barrier metal film BA2 and the copper film CL1 are included in the trench. Copper wiring CW1 is formed. Copper wiring CW1 corresponds to the first metal wiring.

Thereafter, an interlayer insulating film IL3 such as a silicon oxide film is formed on the interlayer insulating film IL2 so as to cover the copper wiring CW1. Via holes V1, V3, V4, and V11 are formed in the interlayer insulating film IL3 by a method similar to the method of forming the plug PG1. Next, an interlayer insulating film (not shown) is formed so as to cover the via holes V1, V3, V4, and V11. A copper wiring CW2 is formed in the interlayer insulating film by a method similar to the method of forming the copper wiring CW1. The copper wiring CW2 corresponds to the second metal wirings M21 and M22.

Next, an interlayer insulating film IL4 is formed so as to cover the copper wiring CW2. A via hole (not shown) is formed in the interlayer insulating film IL4 by a method similar to the method of forming the plug PG1. Next, an etching stopper film ES2 such as a silicon nitride film is formed so as to cover this via hole (not shown). An interlayer insulating film IL5 such as a silicon oxide film is formed on the etching stopper film ES2. A copper wiring CW3 is formed in the interlayer insulating film IL5 by the same method as the method of forming the copper wiring CW1. Copper wiring CW3 corresponds to third metal wiring M31. Thus, the main part of the SRAM memory cell is formed.

Next, the operation of the SRAM memory cell will be described. With reference to FIG. 3, the SRAM memory cell MC1 will be described as an example. Both the first bit line BL and the second bit line / BL are precharged to H level. In the read operation, current flows from the first bit line BL and the second bit line / BL at the H level to the first storage node SN1 and the second storage node SN2, respectively.

For example, assuming that the standard power supply voltage is 1V, when the retained data is 0, the first storage node SN1 of the SRAM memory cell is 0V and the second storage node SN2 is 1V. When the word line WL changes from the L level (0V) to the H level (1V) and the read operation starts, the first access transistor NA1 is in the ON state, and the first driver transistor ND1 and the third driver transistor ND3 are also in the ON state. Therefore, a current flows from the first bit line BL precharged to the H level (1V) in advance to the first storage node SN1. As a result, the potential of the first bit line BL is slightly lowered from 1V.

On the other hand, in the second bit line / BL, the second access transistor NA2 is in the ON state, but the second driver transistor ND2 and the fourth driver transistor ND4 are in the OFF state. No current flows through the node SN2. Therefore, the second storage node SN2 holds the precharged H level (1V).

As a result, a potential difference is generated between the first bit line BL and the second bit line / BL. This slight potential difference is amplified and output by a sense amplifier (not shown) connected to the first bit line BL and the second bit line / BL (complementary bit line). As a result, the data held in the desired SRAM memory cell MC1 is read. The case where 0 (0 data) is read as retained data has been described above. However, when 1 data is read, the potentials of the first storage node SN1 and the second storage node SN2 are opposite to those described above, and the first bit line BL The current flowing from the first storage node SN1 to the first storage node SN1 and the current flowing from the second bit line / BL to the second storage node SN2 are also reversed.

During the read operation, the direction of the current flowing through the first access transistor NA1 is the direction from the first bit line BL toward the first storage node SN1. The direction of the current flowing through the second access transistor NA2 is the direction from the second bit line / BL toward the second storage node SN2.

Referring to FIG. 4, the direction of current flowing through first access transistor NA1 is electrically connected to first storage node SN1 from the other one of first source / drain SD1 electrically connected to first bit line BL. The direction is toward one of the first source / drain SD1. The direction of the current flowing through the second access transistor NA2 is such that the second source / drain SD2 electrically connected to the second storage node SN2 from the other of the second source / drain SD2 electrically connected to the second bit line / BL. The direction is toward one of the drains SD2.

Since the current directions of the first access transistor NA1 and the second access transistor NA2 are the same and the current directions of the first access transistor NA1 and the second access transistor NA2 are aligned, the symmetry of the cell characteristics is improved. be able to. For this reason, an operation margin can be expanded.

Referring to FIG. 26, when SRAM memory cell MC1 having the layout shown in FIG. 8 is “Fodd” and SRAM memory cell MC2 having the layout shown in FIG. In the vertical direction, Fodd and Feven SRAM memory cells MC1 and MC2 are alternately arranged. Further, in the horizontal direction in the figure, a plurality of identical Fodds are arranged in odd columns, and a plurality of identical Fevens are arranged in even columns. In this way, SRAM memory cells MC1 and MC2 of M rows and N columns (M indicates the number of rows and N indicates the number of columns) are arranged in the SRAM cell array MA. In the SRAM memory cells MC1 and MC2, the bit line (first storage node SN1, first storage node SN2) from the impurity region of the storage node (first storage transistor NA1, second access transistor NA2) of the pair of access transistors (first access transistor NA1, second access transistor NA2). The direction of the 1 bit line BL and the second bit line / BL) toward the impurity region is the same direction.

Referring to FIG. 27, the SRAM memory cells MC1 and MC2 adjacent to each other have the same current direction in each of the first access transistor NA1 and the second access transistor NA2. For this reason, the mismatch characteristic resulting from a cell layout can be reduced.

Referring to FIG. 28, in the method of manufacturing an SRAM memory cell, as a result of the gate being etched, if the gate is bent in the planar layout, the gate may be formed in a round shape along the bend. In this case, the gate rounds on the diffusion layer, which may cause variations in the threshold voltage of the transistor. For this reason, as shown in the modification of the present embodiment, the gates may be electrically connected by the local interconnector LIC without bending the gates. Hereinafter, the modification is demonstrated.

FIG. 29 is a schematic plan view showing a connection structure between each transistor and the first metal wiring. Referring to FIG. 29, in the modification of the present embodiment, the gate structure G constituting the first driver gate DG1 of the first driver transistor ND1 and the gate structure constituting the third driver gate DG3 of the third driver transistor ND3. G is electrically connected to the local interconnector LIC. In other words, in the direction in which the first driver gate DG1 and the third driver gate DG3 extend, the gate structure G that constitutes the first driver gate DG1 and the gate structure G that constitutes the third driver gate are element formation regions FRN, The FRP is electrically connected by a local interconnector LIC.

Further, the gate structure G constituting the second driver gate DG2 of the second driver transistor ND2 and the gate structure G constituting the fourth driver gate DG4 of the fourth driver transistor ND4 are electrically connected by the local interconnector LIC. . That is, in the direction in which the second driver gate DG2 and the fourth driver gate DG4 extend, the gate structure G that constitutes the second driver gate DG2 and the gate structure G that constitutes the fourth driver gate DG4 form the element formation region FRN. , FRP are electrically connected by a local interconnector LIC.

Referring to FIGS. 30 and 31, the local interconnector LIC is formed on the element isolation region IR. A local interconnector LIC is formed so as to cover each metal silicide film SCL between the gate structure G constituting the first driver gate DG1 and the gate structure G constituting the third driver gate DG3 of the third driver transistor ND3. Yes. Interlayer insulating film IL1 is formed to cover local interconnector LIC.

The local interconnector LIC can be manufactured as follows. First, the interlayer insulating film IL1 is formed up to the height of the local interconnector LIC so as to cover the gate structure G. Subsequently, the grooves for forming the local interconnector LIC are etched. Further, for example, a tungsten film is formed so as to fill the groove. Next, a chemical mechanical polishing process is performed to remove a portion of the tungsten film located on the upper surface of the interlayer insulating film IL1. Thereby, a local interconnector LIC is formed. Thereafter, the method for manufacturing the semiconductor device SCD of the present embodiment is applied by forming the interlayer insulating film IL1.

In this modification, since the gate structures G are electrically connected by the local interconnector LIC, the gates can be formed linearly without being bent. Therefore, it is possible to suppress the gate from rounding on the diffusion layer. For this reason, the occurrence of variations in the threshold voltage of the transistor due to the round of the gate can be suppressed. In addition, since the gate is formed in a straight line, lithography becomes easy, so that the gate can be easily formed. Therefore, the precision of microfabrication can be improved.

Next, the effect of the semiconductor device of this embodiment will be described in comparison with a comparative example.
First, a comparative example will be described with reference to FIGS. 32 and 33. Referring to FIG. 32, each region surrounded by a dotted line forms one SRAM memory cell. The transistors and contacts of each SRAM memory cell are arranged in line symmetry (mirror target) with the adjacent SRAM memory cell. Referring to FIGS. 32 and 33, SRAM memory cell MC1 typically includes access transistors T1, T2, driver transistors T3, T4, and load transistors T5, T6.

Access gates AG1 and AG2 of access transistors T1 and T2, driver gates DG1 and DG2 of driver transistors T3 and T4, and load gates LG1 and LG2 of load transistors T5 and T6 all extend in the same direction. Is formed.

In the access transistor T1, a current flows in the direction of arrow A from one of the source / drain electrically connected to the first bit line BL toward the other of the source / drain electrically connected to the first storage node SN1. In access transistor T2, a current flows in the direction of arrow A from one of the source / drain electrically connected to second bit line / BL to the other of the source / drain electrically connected to second storage node SN2. Flowing. The direction of the current flowing through the access transistors T1 and T2 is opposite. For this reason, the mismatch characteristics due to the cell layout become large, and there is a risk that the variation in cell characteristics becomes large.

In the SRAM memory cell MC2 adjacent to the SRAM memory cell MC1, the direction of the current flowing through the access transistors T1 and T2 is reversed as in the SRAM memory cell MC1. Further, referring to FIGS. 32 and 34, in SRAM memory cell MC1 and SRAM memory cell MC2, the directions of currents of access transistors T1 and T2 arranged in adjacent directions are opposite to each other. For this reason, mismatch due to the cell layout between adjacent cells also increases, and there is a risk that variations in cell characteristics will increase.

As shown in FIG. 4, according to the semiconductor device SCD of the present embodiment, in the planar layout, the first direction D1 from one of the pair of first source / drain SD1 to the other and the pair of second sources. The second direction D2 from the one side of the source / drain SD2 to the other side is the same. The first directions D1 of the SRAM memory cell MC1 and the SRAM memory cell MC2 are the same direction, and the second directions D2 are the same direction.

Therefore, the current directions of the first access transistor NA1 and the second access transistor NA2 can be made the same direction. For this reason, mismatch characteristics due to cell layout can be reduced, and variations in cell characteristics can be reduced. Therefore, the operation margin can be expanded.

Further, the current directions of the first access transistor NA1 and the second access transistor NA2 of the SRAM memory cell MC1 and the SRAM memory cell MC2 can be made the same direction. Therefore, mismatch due to cell layout between adjacent cells can also be reduced. For this reason, the dispersion | variation in the cell characteristic of several cells can be reduced. Therefore, the operation margin can be further expanded.
In the planar layout, each of the first access gate AG1 and the second access gate AG2, the first driver gate DG1, the second driver gate DG2, the first load gate LG1, and the second load gate LG2 extends in the same direction. It is formed as follows. Therefore, impurity implantation can be performed in two steps (two directions) when forming the source / drain. That is, impurities for forming the source / drain can be implanted from two directions in which the source and drain are arranged with respect to the gate. Thereby, local variations due to impurity fluctuations can be reduced.

In addition, since the gates are formed in the same direction, it is possible to reduce that the source / drain is not sufficiently formed due to mask displacement. Therefore, local variations due to mask displacement can be reduced. Further, since the gates are formed in the same direction, fine processing can be facilitated. Therefore, global variation resulting from microfabrication can be reduced.

According to the semiconductor device SCD of the present embodiment, each of the first driver transistor ND1, the second driver transistor ND2, the first load transistor PL1, and the second load transistor PL2 in the SRAM memory cell MC1 and the SRAM memory cell MC2. In the planar layout, they are arranged in line symmetry (mirror symmetry).

Therefore, in the SRAM memory cell MC1 and the SRAM memory cell MC2, impurities can be implanted in order to form a source / drain using a linear resist mask covering the first driver transistor ND1 and the second driver transistor ND2. . Impurity implantation can be performed to form the source / drain using a linear resist mask covering the first load transistor PL1 and the second load transistor PL2.

Therefore, local variations due to impurity fluctuations can be reduced. In addition, the SRAM memory cell MC1 and the SRAM memory cell MC2 can share a part of the first load transistor PL1 and the second load transistor PL2. Therefore, the SRAM cell array MA can be reduced. Therefore, the SRAM portion SR can be reduced.

According to the semiconductor device SCD of the present embodiment, in the planar layout, the first driver gate DG1 and the second driver gate DG2, and the third driver gate DG3 and the fourth driver gate DG4 extend in the same direction. It is formed as follows.

In order to make the extending directions of the first access gate AG1, the second access gate AG2, the first driver gate DG1, the second driver gate DG2, the third driver gate DG3, and the fourth driver gate DG4 the same direction, The 1 access transistor NA1 and the second access transistor NA2 are arranged outside the first driver transistor ND1 and the second driver transistor ND2. Therefore, the third driver transistor ND3 and the fourth driver transistor ND4 can be provided in the direction in which the first bit line BL and the second bit line / BL extend. Thereby, the current of the driver transistor can be increased.

In general, it is desirable to increase the β ratio in order to ensure the read margin of the SRAM memory cell. The β ratio is expressed as a current ratio of the driver transistor to the access transistor (however, the source-to-gate voltage and the source-to-drain voltage are the same between the access transistor and the driver transistor). If the β ratio increases, an improvement of SNM (Static Noise Margin) is expected. The SNM is an index that indicates a margin when the SRAM memory cell operates by a voltage.

In the semiconductor device SCD of the present embodiment, currents of the third driver transistor ND3 and the fourth driver transistor ND4 flow in addition to the currents of the first driver transistor ND1 and the second driver transistor ND2. For this reason, the current of the driver transistor can be increased. Therefore, the β ratio can be increased. Thereby, a read margin of the SRAM memory cell can be ensured.

(Embodiment 2)
The semiconductor device according to the second embodiment of the present invention is mainly different from the semiconductor device according to the first embodiment in that the threshold voltage of the access transistor is different from the threshold voltage of the driver transistor. .

Referring to FIG. 35, the first access transistor NA1 is formed to have a different threshold voltage from the first driver transistor ND1 and the third driver transistor ND3. The second access transistor NA2 is formed to have a different threshold voltage than the second driver transistor ND2 and the fourth driver transistor ND4.

The channel impurity concentrations of the first access transistor NA1 and the second access transistor NA2 are different from the channel impurity concentrations of the first driver transistor ND1, the second driver transistor ND2, the third driver transistor ND3, and the fourth driver transistor ND4. The first and second access transistors NA1 and NA2 and the first to fourth driver transistors ND1 to ND4 are formed to have different threshold voltages.

In the method of manufacturing the semiconductor device SCD of the present embodiment, the first and second access transistors NA1, NA2 and the first to fourth driver transistors ND1 to ND4 are channel doped. Thereafter, a resist mask in which the first and second access transistors NA1, NA2 are opened is formed, and channel doping of the first and second access transistors NA1, NA2 is further performed. Thus, the channel impurity concentrations of the first and second access transistors NA1 and NA2 are set to be different from the channel impurity concentrations of the first to fourth driver transistors ND1 to ND4.

The first access transistor NA1 may be formed to have a threshold voltage (Hvth) higher than the threshold voltage (Lvth) of the first driver transistor ND1 and the third driver transistor ND3. The second access transistor NA2 may be formed to have a threshold voltage (Hvth) higher than the threshold voltage (Lvth) of the second driver transistor ND2 and the fourth driver transistor ND4.

In this case, the channel impurity concentration of the first access transistor NA1 is higher than the channel impurity concentration of the first driver transistor ND1 and the third driver transistor ND3. Further, the channel impurity concentration of the second access transistor NA2 is higher than the channel impurity concentrations of the second driver transistor ND2 and the fourth driver transistor ND4.

In addition, since the structure and manufacturing method of this embodiment other than this are the same as the structure and manufacturing method of Embodiment 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is not repeated.

According to the semiconductor device SCD of the present embodiment, the first access transistor NA1 and the second access transistor NA2 have threshold voltages different from the threshold voltages of the first driver transistor ND1 and the second driver transistor ND2. Is provided. Therefore, the β ratio can be changed. Therefore, it is possible to secure a read margin of the SRAM memory cell by increasing the β ratio.

Further, according to the semiconductor device SCD of the present embodiment, the first access transistor NA1 and the second access transistor NA2 have threshold voltages higher than the threshold voltages of the first driver transistor ND1 and the second driver transistor ND2. It is provided to have. Therefore, the β ratio can be increased. Thereby, a read margin of the SRAM memory cell can be ensured.

(Embodiment 3)
The semiconductor device according to the third embodiment of the present invention is mainly different from the semiconductor device according to the first embodiment in that the gate width of the access transistor is larger than the gate width of the driver transistor.

Referring to FIG. 36, the width of first access gate AG1 of first access transistor NA1 is the width WA1 of first driver gate DG1 of first driver transistor ND1 and the width of third driver gate DG3 of third driver transistor ND3. It is provided to be larger than WA3. The width of the second access gate AG2 of the second access transistor NA2 is larger than the width WA2 of the second driver gate DG2 of the second driver transistor ND2 and the width WA4 of the fourth driver gate DG4 of the fourth driver transistor ND4. Is provided.

In the method of manufacturing the semiconductor device SCD of the present embodiment, the first access transistor is determined by the width of the diffusion layer forming the third source / drain SD3 of the first driver transistor ND1 and the fifth source / drain SD5 of the third driver transistor ND3. By increasing the width of the diffusion layer forming the first source / drain SD1 of NA1, the width of the first access gate AG1 is made larger than the width WA1 of the first driver gate DG1 and the width WA3 of the third driver gate DG3. The Further, the diffusion for forming the second source / drain SD2 of the second access transistor NA2 from the width of the diffusion layer for forming the fourth source / drain SD4 of the second driver transistor ND2 and the sixth source / drain SD6 of the fourth driver transistor ND4. By increasing the layer width, the gate width of the second access gate AG2 is formed larger than the width WA2 of the second driver gate DG2 and the width WA4 of the third driver gate DG4.

According to the semiconductor device SCD of the present embodiment, the width of the first access gate AG1 of the first access transistor NA1 is equal to the width WA1 of the first driver gate DG1 of the first driver transistor ND1 and the third width of the third driver transistor ND3. The width of the second access gate AG2 of the second access transistor NA2 is set to be larger than the width WA3 of the driver gate DG3. The width WA2 of the second driver gate DG2 of the second driver transistor ND2 and the fourth driver transistor The fourth driver gate DG4 of ND4 is provided to be larger than the width WA4.

Since the third driver transistor ND3 and the fourth driver transistor ND4 are provided in addition to the first driver transistor ND1 and the second driver transistor ND2, the currents of the first driver transistor ND1 and the third driver transistor ND3 increase, The currents of the two driver transistor ND2 and the fourth driver transistor ND4 are also increased. Therefore, β ratio becomes large. Therefore, even if the first access gate AG1 is provided to be larger than the width WA1 of the first driver gate DG1 and the width WA3 of the third driver gate DG3, the third driver transistor ND3 is not provided. Therefore, the β ratio can be maintained in a large state.

Similarly, even when the second access gate AG2 is provided to be larger than the width WA2 of the second driver gate DG2 and the width WA4 of the fourth driver gate DG4, the fourth driver transistor ND4 is not provided. Thus, the β ratio can be maintained in a large state. Thereby, a read margin of the SRAM memory cell can be ensured.

Since the width WA1 of the first driver gate DG1 to the width WA4 of the fourth driver gate DG4 can be made smaller than the width of the first access gate AG1 and the width of the second access gate AG2, the area of the SRAM memory cell can be reduced. can do.

(Embodiment 4)
The semiconductor device according to the fourth embodiment of the present invention is mainly different from the semiconductor device according to the first embodiment in that an asymmetric halo region is provided.

Referring to FIG. 37, in each of the plurality of SRAM memory cells of semiconductor device SCD, first halo regions HR1 to HR1 are connected to first and second access transistors NA1 and NA2 and first to fourth driver transistors ND1 to ND4, respectively. A twelfth halo region HR12 is formed. The first halo region HR1 to the twelfth halo region HR12 are formed as p-type impurity regions. On the other hand, halo regions formed in first and second load transistors PL1 and PL2 described later are formed as n-type impurity regions.

The first access transistor NA1 is adjacent to the other of the first source / drain SD1, and has a first halo region HR1 having a second conductivity type impurity different from the first conductivity type impurity of the first source / drain SD1, A second halo region HR2 having a second conductivity type impurity having an impurity concentration higher than that of the first halo region HR1 is adjacent to one of the first source / drain SD1.

The second access transistor NA2 is adjacent to the other of the second source / drain SD2, and has a third halo region HR3 having a second conductivity type impurity different from the first conductivity type impurity of the second source / drain SD2. A fourth halo region HR4 having an impurity of a second conductivity type having an impurity concentration higher than the impurity concentration of the third halo region HR3 is adjacent to one of the second source / drain SD2.

The first driver transistor ND1 is adjacent to the other of the third source / drain SD3 and has a fifth halo region HR5 having a second conductivity type impurity different from the first conductivity type impurity of the third source / drain SD3, A sixth halo region HR6 having a second conductivity type impurity having an impurity concentration higher than that of the fifth halo region HR5 is adjacent to one of the third source / drain SD3.

The second driver transistor ND2 is adjacent to the other of the fourth source / drain SD4 and has a seventh halo region HR7 having a second conductivity type impurity different from the first conductivity type impurity of the fourth source / drain SD4, An eighth halo region HR8 having an impurity of a second conductivity type having an impurity concentration higher than that of the seventh halo region HR7 is adjacent to one of the fourth source / drain SD4.

The third driver transistor ND3 is adjacent to one of the fifth source / drain SD5 and has a ninth halo region HR9 having a second conductivity type impurity different from the first conductivity type impurity of the fifth source / drain SD5, A tenth halo region HR10 having a second conductivity type impurity having an impurity concentration higher than that of the ninth halo region HR9 is adjacent to the other of the fifth source / drain SD5.

The fourth driver transistor ND4 is adjacent to one of the sixth source / drain SD6 and has an eleventh halo region HR11 having a second conductivity type impurity different from the first conductivity type impurity of the sixth source / drain SD6, A twelfth halo region HR12 having a second conductivity type impurity having an impurity concentration higher than that of the eleventh halo region HR11 is adjacent to the other of the sixth source / drain SD6.

As will be described later, the first to twelfth halo regions HR1 to HR12 are formed by 2 Step Halo Impla (two-way halo implantation). In 2Step Halo Impla, a thin Halo Impla (halo implantation) is performed from one direction, and a deep Halo Impla (halo implantation) is performed from the other direction opposite to the one direction. Thereby, the asymmetric halo region HR is provided.

In the first access transistor NA1 and the second access transistor NA2, of the first halo region HR1 to the fourth halo region HR4 formed respectively, the side connected to the first storage node SN1 and the second storage node SN2 The impurity concentration of the second halo region HR2 and the fourth halo region HR4 is higher than the impurity concentration of the first halo region HR1 and the third halo region HR3 connected to the first bit line BL and the second bit line / BL. Is also set high.

In the first driver transistor ND1 and the second driver transistor ND2, of the fifth halo region HR5 to the eighth halo region HR8 formed respectively, the side connected to the first storage node SN1 and the second storage node SN2 The impurity concentration of the sixth halo region HR6 and the eighth halo region HR8 is greater than the impurity concentration of the fifth halo region HR5 and the sixth halo region HR6 on the side connected to the first bit line BL and the second bit line / BL. Is also set high.

In the third driver transistor ND3 and the fourth driver transistor ND4, of the ninth halo region HR9 to the twelfth halo region HR12 formed respectively, the tenth halo region HR10, twelfth on the side connected to the ground wiring VSS. The impurity concentration of the halo region HR12 is set higher than the impurity concentration of the ninth halo region HR9 and the eleventh halo region HR11 on the side connected to the first storage node SN1 and the second storage node SN2. Thus, a deep halo region DHI is formed in the second halo region HR2, the fourth halo region HR4, the sixth halo region HR6, the eighth halo region HR8, the tenth halo region HR10, and the twelfth halo region HR12.

FIG. 38 is a schematic cross sectional view taken along a cross sectional line XXXVIII-XXXVIII orthogonal to the extending direction of the first access gate AG1 so as to pass through the first access transistor NA1 of the SRAM memory cell MC1 in FIG.

The element formation region FRN located on the side opposite to the side where the dummy gate DU is located with respect to the first access gate AG1 includes the first halo region HR1, the extension region ER, the first source / drain SD1, and the metal A silicide film SCL is formed. First halo region HR1 is formed to reach a region immediately below first access gate AG1.

In the element formation region FRN located between the first access gate AG1 and the dummy gate DU, a second halo region HR2, an extension region ER, a first source / drain SD1, and a metal silicide film SCL are formed. . Second halo region HR2 is formed to reach a region immediately below second access gate AG2.

A stress liner film SL such as a silicon nitride film is formed so as to cover the first access gate AG1. An interlayer insulating film IL1 such as a silicon oxide film (for example, a TEOS film) is formed so as to cover the stress liner film SL. A plug PG1 penetrating through the interlayer insulating film IL1 and the stress liner film SL and electrically connected to the metal silicide film SCL is formed. The plug PG1 includes a barrier metal film BA1 such as a TiN film and a tungsten film TL1. The plugs PG1 connected to the metal silicide film SCL respectively constitute contacts C1 and C2 shown in FIG.

An etching stopper film ES1 such as a silicon nitride film is formed on the interlayer insulating film IL1 so as to cover the plug PG1. An interlayer insulating film IL2 such as a silicon oxide film is formed on the etching stopper film ES1. A copper wiring CW1 that penetrates through the interlayer insulating film IL2 and the etching stopper film ES1 and is electrically connected to the plug PG1 is formed. The copper wiring CW1 includes a barrier metal film BA2 such as a TaN film and a copper film CL1. The copper wiring CW1 connected to the plug PG1 constitutes the first metal wirings M1 and M2 shown in FIG.

39 is a schematic sectional view taken along a sectional line XXXIX-XXXIX orthogonal to the extending direction of the first driver gate DG1 so as to pass through the first driver transistor ND1 and the third driver transistor ND3 of the SRAM memory cell MC1 in FIG. It is.

The element formation region FRN located on the opposite side of the first driver gate DG1 from the side where the third driver gate DG3 is located includes a fifth halo region HR5, an extension region ER, and a third source / drain SD3. In addition, a metal silicide film SCL is formed. The fifth halo region HR5 is formed so as to reach a region immediately below the first driver gate DG1.

The element formation region FRN located between the first driver gate DG1 and the third driver gate DG3 includes a sixth halo region HR6, a ninth halo region HR9, an extension region ER, a third source / drain SD3, 5 source / drain SD5 and metal silicide film SCL are formed. The sixth halo region HR6 is formed so as to reach a region immediately below the first driver gate DG1. The ninth halo region HR9 is formed so as to reach a region immediately below the third driver gate DG3.

The element formation region FRN located on the opposite side of the third driver gate DG3 from the side where the first driver gate DG1 is located includes a tenth halo region HR10, an extension region ER, and a fifth source / drain SD5. Further, a metal silicide film SCL is formed. The tenth halo region HR10 is formed so as to reach a region immediately below the third driver gate DG3.

An etching stopper film ES1 such as a silicon nitride film is formed on the interlayer insulating film IL1 so as to cover the plug PG1. An interlayer insulating film IL2 such as a silicon oxide film is formed on the etching stopper film ES1. A copper wiring CW1 that penetrates through the interlayer insulating film IL2 and the etching stopper film ES1 and is electrically connected to the plug PG1 is formed. The copper wiring CW1 includes a barrier metal film BA2 such as a TaN film and a copper film CL1. The copper wirings CW1 connected to the plugs PG1 respectively constitute first metal wirings M1, M4, M5 shown in FIG. Each halo region other than the above is formed so as to reach a region immediately below each gate.

Next, the structure of the access transistor will be described in detail. 40 shows a cross-sectional structure taken along a cross-sectional line corresponding to the line XXXVIII-XXXVIII shown in FIG. The first access transistor NA1 will be described as an example of the access transistor structure, but the second access transistor NA2 has the same structure.

Referring to FIG. 40, first access gate AG1 of first access transistor NA1 formed so as to cross element formation region FRN (see FIG. 4) contains La on interface layer SF such as SiON. A high-k film HK having a predetermined dielectric constant, such as HfO ₂ or HfSiON, or a metal film ML having a predetermined work function, such as TiN, and a polysilicon film PS are formed in a stacked manner. A metal silicide film SCL such as nickel silicide is formed.

An offset spacer OS such as a silicon nitride film is formed on both side surfaces of the first access gate AG1. Over the offset spacer OS, a sidewall spacer SW made of a silicon oxide film SO and a silicon nitride film SNI is formed.

The element formation region in a direction (gate length direction) orthogonal to the direction in which the first access gate AG1 extends includes a first halo region HR1, a second halo region HR2, an extension region ER, and a first source / drain SD1. In addition, a metal silicide film SCL is formed.

As shown in FIG. 40, the first halo region HR1 and the second halo region HR2 are in regions adjacent to the mutually opposing portions of the pair of sources or drains, respectively, and the first access from the region immediately below the sidewall spacer SW. It is formed so as to reach a region immediately below gate AG1. The impurity concentration of the halo region HR is on the order of 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ / cm ³ , but in the semiconductor device SCD, the impurity concentration of the second halo region HR2 is the impurity concentration of the first halo region HR1. It is set higher than the concentration.

FIG. 41 shows the impurity concentration profile of the halo region HR. The horizontal axis indicates the depth (arrows F1, F2) from the surface portion of the semiconductor substrate SS at the lower end of the side surface of the first access gate AG1, and the vertical axis indicates the impurity concentration of the P-type impurity. In the first halo region HR1 and the second halo region HR2, the impurity concentration of the second halo region HR2 is the impurity concentration of the first halo region HR1 in the surface portion of the semiconductor substrate SS at the lower end of the side surface of the first access gate AG1. Higher than.

In addition, the peak (maximum value) of the impurity concentration first appears at predetermined depths f1 and f2 from the surface, respectively, and the peak of the impurity concentration of the second halo region HR2 is also higher than the peak of the impurity concentration of the first halo region HR1. high, the second halo region HR2 about 6 × 10 ¹⁸ / cm ^3, the first halo regions HR1 is about 5 × 10 ¹⁸ / cm ^3. The impurity concentration of the extension region ER of the SRAM memory cell MC1 is 5 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / cm ³ , and the impurity concentration of the source or drain is about 5 × 10 ²¹ / cm ³ .

As will be described later, in the semiconductor device SCD, the first of the pair of halo regions HR of the first access transistor NA1 and the second access transistor NA2 on the side connected to the first storage node SN1 and the second storage node SN2. The impurity concentrations of the 2 halo region HR2 and the fourth halo region HR4 are higher than the impurity concentrations of the first halo region HR1 and the third halo region HR3 on the side connected to the first bit line BL and the second bit line / BL. By setting it high, a read margin and a write margin can be secured.

Next, a method for manufacturing a semiconductor device will be described. A semiconductor device includes a logic circuit in addition to an SRAM circuit. Here, a method for forming an access transistor and a driver transistor of an SRAM memory cell will be mainly described. 42, FIG. 44 to FIG. 46, FIG. 48, FIG. 50, and FIG. 52 to FIG. 55 referred to hereinafter, each figure (A) is taken along the sectional line corresponding to the line XXXVIII-XXXVIII shown in FIG. A cross-sectional structure is shown, and each figure (B) shows a cross-sectional structure along a cross-sectional line corresponding to the XXXIX-XXXIX line shown in FIG.

First, by forming an element isolation region IR on the main surface of the semiconductor substrate SS, element formation regions FRN and FRP that are electrically isolated from each other are defined. Next, a p-well PW is formed in the element formation region FRN.

Next, referring to FIGS. 42A and 42B, a high-k film HK having a predetermined dielectric constant and a predetermined work function are provided on the surface of the semiconductor substrate SS with an interface layer SF interposed therebetween. The gate structure G to be the first access gate AG1 and the respective gate structures G to be the first driver gate DG1 and the third driver gate DG3 are formed in such a manner that the metal film ML and the polysilicon film PS are stacked. Next, for example, a silicon nitride film (not shown) is formed on the semiconductor substrate SS so as to cover the gate structure G. Next, the silicon nitride film is anisotropically etched to form offset spacers OS on both side surfaces of the gate structure G.

Next, referring to FIG. 43, by performing a predetermined photoengraving process, a resist mask RM11 serving as an implantation mask for forming each halo region HR is formed. The resist mask RM11 is patterned to expose the NMIS region RN and cover the PMIS region RP. The resist mask RM11 exposes each gate structure G to be the first access gate AG1, the first driver gate DG1, and the third driver gate DG3 through one opening, and the second access gate AG2, the second driver gate DG2, Each gate structure G to be a 4-driver gate DG4 is formed in a pattern that is exposed through one opening. That is, the individual openings of the resist mask RM11 are continuously formed so as to straddle the adjacent SRAM memory cell MC1 and SRAM memory cell MC2.

Next, referring to FIGS. 44A and 44B, using resist mask RM11 as an implantation mask, for example, boron is substantially perpendicular to the direction in which gate structure G extends from the main surface of semiconductor substrate SS. By implanting at an angle (θ = about 7 degrees) with respect to the direction perpendicular to, a p-type impurity region PIR is formed in the exposed p-well PW.

Next, with reference to FIGS. 45A and 45B, using the same resist mask RM11 as an implantation mask, for example, boron is used from one side opposite to the direction substantially perpendicular to the direction in which the gate structure G extends from the other side. By implanting obliquely (θ = about 7 degrees) with respect to the direction perpendicular to the main surface of the semiconductor substrate SS, a p-type impurity region PIR is formed in the exposed p-well PW. Note that boron is implanted with the same implantation amount and the same implantation energy in the implantation in the step shown in FIGS. 44A and 44B and the implantation in the step shown in FIGS. 45A and 45B. Further, the injection amount and the injection energy may be different injection amounts and different injection energies.

Next, referring to FIGS. 46A and 46B, using the same resist mask RM11 as an implantation mask, for example, phosphorus or arsenic is implanted into semiconductor substrate SS from a direction perpendicular to the main surface of semiconductor substrate SS. As a result, an extension region ER is formed from the exposed surface of the p-well PW to a predetermined depth (extension implantation). Thereafter, the resist mask RM11 is removed. The extension implantation step shown in FIG. 46 is performed after the mask formation step shown in FIG. 43 and before the halo implantation step shown in FIGS. 44 (A) and (B) and FIGS. 45 (A) and (B). Also good.

47, a resist mask RM12 that covers NMIS region RN and exposes PMIS region RP is formed. Next, in the same manner as the step of forming the halo region HR in the element formation region FRN, for example, phosphorus or arsenic is introduced into the semiconductor substrate SS from the direction perpendicular to the main surface of the semiconductor substrate SS using the resist mask RM12 as an implantation mask. By implantation, a halo region (not shown) is formed in the element formation region FRP. Next, using the resist mask RM12 as an implantation mask, for example, boron is implanted into the semiconductor substrate SS from a direction perpendicular to the main surface of the semiconductor substrate SS, thereby forming an extension region (not shown). Thereafter, the resist mask RM12 is removed.

Next, for example, a silicon oxide film and a silicon nitride film (not shown) are sequentially formed so as to cover the gate structure G (first access gate AG1, dummy gate DU, first driver gate DG1, third driver gate DG3, etc.). It is formed. Next, referring to FIGS. 48A and 48B, the silicon oxide film and the silicon nitride film are subjected to anisotropic etching, so that the silicon oxide film SO is formed on both side surfaces of the gate structure G. Sidewall spacers SW made of the silicon nitride film SNI are formed.

Next, referring to FIG. 49, a resist mask RM13 that exposes NMIS region RN and covers PMIS region RP is formed. The resist mask RM13 is formed using the same photomask as the resist mask RM11. Next, referring to FIGS. 50A and 50B, for example, phosphorus or arsenic is perpendicular to the main surface of semiconductor substrate SS using resist mask RM13 (FIG. 49) and sidewall spacer SW as an implantation mask. By injecting into the semiconductor substrate SS from the direction, the first source / drain SD1, the third source / drain SD3, and the fifth source / drain SD5 are formed from the exposed surface of the p-well PW to a predetermined depth. Thereafter, the resist mask RM13 is removed.

Next, referring to FIG. 51, a resist mask RM14 that covers NMIS region RN and exposes PMIS region RP is formed. Next, using the resist mask RM14, the sidewall spacer SW, etc. as an implantation mask, for example, boron is implanted into the semiconductor substrate SS from a direction perpendicular to the main surface of the semiconductor substrate SS, thereby exposing the surface of the exposed element formation region FRP. A source / drain (not shown) is formed from a predetermined depth to a predetermined depth. Thereafter, the resist mask RM14 is removed.

Next, referring to FIGS. 52A and 52B, a predetermined annealing process is performed to thermally diffuse the implanted impurities, thereby providing a first source / drain SD1 and a third source / drain SD3. , Fifth source / drain SD5, extension region ER, first halo region HR1, second halo region HR2, fifth halo region HR5, sixth halo region HR6, ninth halo region HR9, and tenth halo region HR10 are activated. Is done.

At this time, the impurities are thermally diffused, so that the first source / drain SD1, the third source / drain SD3, the fifth source / drain SD5, the extension region ER, the first halo region HR1, the second halo region HR2, the fifth halo. The region HR5, the sixth halo region HR6, the ninth halo region HR9, and the tenth halo region HR10 extend in the horizontal direction and the vertical (depth) direction.

Next, referring to FIGS. 53A and 53B, the exposed first source / drain SD1, third source / drain SD3, fifth source / drain SD5, first access gate are exposed by the salicide process. A metal silicide film SCL such as nickel silicide is formed on the surface of the polysilicon film PS of the AG1, the first driver gate DG1, and the third driver gate DG3.

Next, referring to FIGS. 54A and 54B, for example, a stress liner film SL such as a silicon nitride film so as to cover first access gate AG1, first driver gate DG1, and third driver gate DG3. Is formed. An interlayer insulating film IL1 such as a silicon oxide film (for example, a TEOS film) is formed so as to cover the stress liner film SL.

Next, referring to FIGS. 55A and 55B, the interlayer insulating film IL1 is anisotropically etched to form a contact hole CH that exposes the metal silicide film SCL. Next, a barrier metal film BA1 such as titanium nitride (TiN) is formed so as to cover the inner wall of the contact hole CH, and further, the tungsten film is filled on the barrier metal film BA1. TL1 is formed.

Next, by performing chemical mechanical polishing (CMP), the barrier metal film and the tungsten film located on the upper surface of the interlayer insulating film IL1 are removed, as shown in FIGS. 55A and 55B. Thus, the plug PG1 including the barrier metal film BA1 and the tungsten film TL1 is formed in the contact hole CH.

Next, functions and effects of the semiconductor device of this embodiment will be described.
According to the semiconductor device SCD of the present embodiment, the first access transistor NA1 is adjacent to the first halo region HR1 adjacent to the other of the first source / drain SD1 and one of the first source / drain SD1, A second halo region HR2 having an impurity concentration higher than that of the halo region HR1. The second access transistor NA2 has a third halo region HR3 adjacent to the other of the second source / drain SD2 and an impurity concentration higher than the impurity concentration of the third halo region HR3 adjacent to one of the second source / drain SD2. And a fourth halo region HR4.

As a means for ensuring both the read margin and the write margin, it is effective to use a transistor having an asymmetric property that the current characteristic varies depending on the direction of current flow as the access transistor. In the semiconductor device SCD, the impurity concentration of the second halo region HR2 in the first access transistor NA1 is set higher than the impurity concentration of the first halo region HR1, and the impurity concentration of the fourth halo region HR4 in the second access transistor NA2. Is set higher than the impurity concentration of the third halo region HR3. That is, the first access transistor NA1 and the second access transistor NA2 have the asymmetric halo region HR.

Referring to FIG. 56, the improvement of the operation margin by the asymmetric halo region HR will be described. The first access transistor NA1 will be typically described, but the same applies to the second access transistor NA2. In the first access transistor NA1, the first halo region HR1 having a relatively low impurity concentration is formed from one of the first source / drain SD1 located on the side where the second halo region HR2 having a relatively high impurity concentration is formed. The current flowing toward the other of the first source / drain SD1 located on the other side is defined as a current IF, and the current flowing in the opposite direction is defined as a current IS.

With reference to FIG. 57, the relationship between the currents IF and IS and the source-to-gate voltage Vgs at the same source-to-drain voltage will be described. That is, the threshold voltage of the first access transistor NA1 when current flows from one of the first source / drain SD1 on the second halo region HR2 side to the first source / drain SD1 on the first halo region HR1 side is: From the threshold voltage of the first access transistor NA1 when current flows from the other first source / drain SD1 on the opposite first halo region HR1 side to one of the first source / drain SD1 on the second halo region HR2 side. Also lower.

Therefore, the second halo region HR2 having a relatively high impurity concentration is formed on the first storage node SN1 side, and the first halo region HR1 having a relatively low impurity concentration is formed on the first bit line BL side. Thus, the current from the first bit line BL to the first storage node SN1 can be easily suppressed during reading, and the current from the first storage node SN1 to the first bit line BL can be easily increased during writing.

It is desirable to increase the β ratio in order to ensure the read margin of the SRAM memory cell, and it is desirable to increase the γ ratio in order to increase the write margin. The γ ratio is expressed by the current ratio of the access transistor to the load transistor (the source-to-gate voltage and the source-to-drain voltage are the same between the access transistor and the load transistor).

In the present embodiment, the γ ratio can be increased without deteriorating the β ratio, and the β ratio can be increased without deteriorating the γ ratio. Alternatively, both the β ratio and the γ ratio can be increased. As a result, the read margin and the write margin can be expanded.

In the semiconductor device SCD of the present embodiment, the first access gate AG1 and the second access gate AG2, the first driver gate DG1, the second driver gate DG2, the first load gate LG1 and the second load gate LG2 in the planar layout. Each is formed to extend in the same direction. Therefore, when forming the halo region HR, the halo implantation can be performed in two steps (two directions). Thereby, local variations due to impurity fluctuations can be reduced.

In addition, since the gates are formed in the same direction, it is possible to reduce that the halo regions HR are not sufficiently formed due to mask displacement. Therefore, local variations due to mask displacement can be reduced.

In the semiconductor device SCD of the present embodiment, each of the first driver transistor ND1, the second driver transistor ND2, the first load transistor PL1, and the second load transistor PL2 in the SRAM memory cell MC1 and the SRAM memory cell MC2 is a plane. They are arranged in line symmetry (mirror symmetry) in the layout.

Therefore, in SRAM memory cell MC1 and SRAM memory cell MC2, halo implantation is performed to form halo region HR using linear resist masks RM11 and RM12 covering first driver transistor ND1 and second driver transistor ND2. be able to. Further, halo implantation can be performed to form the halo region HR using a linear resist mask covering the first load transistor PL1 and the second load transistor PL2. For this reason, local variations due to impurity fluctuations can be reduced.

Further, the extension region ER and the halo region HR can be formed with the same resist masks RM11 and RM12. Further, the resist masks RM11 and RM12 for forming the extension region ER and the halo region HR and the resist masks RM13 and RM14 for forming the source / drain can be formed with the same Impla mask (photomask). For this reason, production cost can be reduced.

Also, in the resist masks RM11 and RM12 used for the halo implantation, an opening that is sufficiently larger than between adjacent gates is formed as an opening (a blank pattern). Thereby, even if the halo implantation is performed obliquely with respect to the main surface of the semiconductor substrate SS, the halo implantation is prevented from being blocked by the resist masks RM11 and RM12. For this reason, the halo region HR can be reliably formed.

In the semiconductor device SCD of the present embodiment, in the planar layout, the third direction D3 from one of the pair of third source / drain SD1 to the other and the one of the pair of fifth source / drain SD5 from one to the other. The fifth direction D5 is opposite, and the fourth direction D4 is directed from one of the pair of fourth source / drains SD4 to the other, and the one direction is directed from one of the pair of sixth source / drains SD6 to the other. The sixth direction D6 is opposite. In the planar layout, a fifth direction D5 extending from one of the pair of fifth source / drain SD5 to the other and a sixth direction D6 extending from one of the pair of sixth source / drain SD6 to the other are provided. The same. The fifth directions D5 of the SRAM memory cell MC1 and the SRAM memory cell MC2 are the same direction, and the sixth directions D6 are the same direction.

Although an asymmetric halo region is formed in the first driver transistor ND1 to the fourth driver transistor ND4, the first driver transistor ND1 and the third driver transistor ND3 are opposite to each other, and the second driver transistor ND2 and the fourth driver transistor The direction of the transistor ND4 is opposite to that of the transistor ND4. Therefore, the influence of the asymmetric halo region is canceled by the first driver transistor ND1 and the third driver transistor ND3. Further, the influence of the asymmetric halo region is canceled by the second driver transistor ND2 and the fourth driver transistor ND4. For this reason, the first driver transistor ND1 and the third driver transistor ND3, and the second driver transistor ND2 and the fourth driver transistor ND4 ensure a balance between the left and right inverter characteristics of the cell. Therefore, cell characteristics can be improved.

(Embodiment 5)
The semiconductor device according to the fifth embodiment of the present invention is mainly different from the semiconductor device according to the first embodiment in that the threshold voltage of the driver transistor is higher than the threshold voltage of the access transistor. Yes.

Referring to FIG. 58, first access transistor NA1 and second access transistor NA2 are formed with asymmetric halo regions, and dark halo regions DHI are formed respectively. The first driver transistor ND1 and the third driver transistor ND3 are formed to have a higher threshold voltage (Hvth) than the first access transistor NA1. The second driver transistor ND2 and the fourth driver transistor ND4 are formed to have a higher threshold voltage (Hvth) than the second access transistor NA2.

In the method of manufacturing the semiconductor device SCD of the present embodiment, halo implantation for forming the halo region HR is performed in the first and second access transistors NA1 and NA2 and the first to fourth driver transistors ND1 to ND4. Thereafter, referring to FIG. 59, a resist mask RM21 is formed so as to open first to fourth driver transistors ND1 to ND4. Bidirectional halo implantation is performed using resist mask RM21 as an implantation mask.

Thereby, the concentration of the halo region is increased in the region immediately below the driver gates DG1 to DG4 of the first driver transistor ND1 to the fourth driver transistor ND4. Therefore, the threshold voltages of the first to fourth driver transistors ND1 to ND4 are higher than the threshold voltages of the first and second access transistors NA1 and NA2.

According to the semiconductor device SCD of the present embodiment, the first driver transistor ND1 and the second driver transistor ND2 have threshold voltages higher than the threshold voltages of the first access transistor NA1 and the second access transistor NA2. Is provided. Therefore, the leakage current of the first driver transistor ND1 and the second driver transistor ND2 can be reduced. Thereby, variation in cell characteristics can be reduced. In addition, power consumption can be reduced.

(Embodiment 6)
In the semiconductor device according to the sixth embodiment of the present invention, the active region that forms the access transistor is electrically connected to the upper layer and the lower layer of the ground wiring, with the point that the active region continuously extends between the plurality of SRAM memory cells. Mainly different in that shunts are formed.

FIG. 60 is a schematic plan view showing a connection relationship between each transistor of the SRAM memory cell and the third metal wiring. FIG. 61 is a schematic plan view showing a connection structure between each transistor and the first metal wiring. FIG. 62 is a schematic cross sectional view taken along a cross sectional line LXII-LXII orthogonal to the extending direction of the first access gate AG1 so as to pass through the first access transistor NA1 of the SRAM memory cell MC1 and the dummy transistor DNM in FIG. is there. FIG. 63 is a plan view showing a connection structure between the second metal wiring and the third metal wiring. FIG. 64 is a diagram showing an equivalent circuit of the SRAM memory cell shown in conformity with the planar layout of FIG.
Referring to FIGS. 60 and 61, in the planar layout, first bit line BL and second bit line / BL extend across SRAM memory cell MC1. SRAM memory cell MC1 and SRAM memory cell MC2 (not shown) are arranged adjacent to each other in the direction in which first bit line BL and second bit line / BL extend.

The active regions AR forming the first source / drain SD1 of the first access transistor NA1 and the second source / drain SD2 of the second access transistor NA2 of the SRAM memory cell MC1 and the SRAM memory cell MC2 (not shown) are continuous. And extending across the SRAM memory cell MC1 and the SRAM memory cell MC2 (not shown).

The dummy gate DU of the dummy transistor DNM formed on the first access transistor NA1 side is electrically connected to the word line WL via the contact C3, the first metal wiring M15, the via hole V12, the second metal wiring M28, and the via hole V23. It is connected. The dummy gate DU formed on the second access transistor NA2 side is electrically connected to the word line WL via the contact C13, the first metal wiring M16, the via hole V13, the second metal wiring M29, and the via hole V24. .

Referring to FIG. 62, ground electricity is always applied to dummy gate DU of dummy transistor DNM. Therefore, the dummy transistor DNM is always off. Therefore, no current flows through the dummy transistor DNM.

Referring to FIG. 60 and FIG. 63, the SRAM memory cell MC1 will be typically described, but the same applies to the SRAM memory cell MC2. In the SRAM memory cell MC1, the ground wiring (lower layer wiring) VSS, which is the second metal wiring, is formed along the first bit line BL in the planar layout. The ground wiring (upper layer wiring) VSS, which is the third metal wiring, is disposed on the ground wiring (lower layer wiring) VSS. The ground wiring (upper layer wiring) VSS is formed to extend in a direction crossing the ground wiring (lower layer wiring) VSS in plan view.

On the third driver transistor ND3, the ground wiring (lower layer wiring) VSS and the installation wiring (upper layer wiring) VSS are electrically connected by a via hole V25 that is a shunt. On the fourth driver transistor ND4, the ground wiring (lower layer wiring) VSS and the installation wiring (upper layer wiring) VSS are electrically connected by a via hole V26 that is a shunt.

As shown in FIG. 64, the dummy transistor DNM formed on the first access transistor NA1 side is electrically connected to the first bit line BL, and the dummy transistor DNM formed on the second access transistor NA2 side is It is electrically connected to the 2-bit line / BL.

As shown in FIG. 65, the local interconnector LIC can be applied to the semiconductor device SCD of the present embodiment as in the first embodiment. In this case, the structure and manufacturing method of the local interconnector LIC are the same as those in the first embodiment.

According to the semiconductor device SCD of the present embodiment, in the planar layout, the SRAM in which the first bit line BL and the second bit line / BL are arranged adjacent to each other in the direction extending across the SRAM memory cell MC1. The active regions AR forming the first source / drain SD1 and the second source / drain SD of the first access transistor NA1 and the second access transistor NA2 of the memory cell MC1 and the SRAM memory cell MC2 extend continuously, and the SRAM memory It is provided so as to cross the cell MC1 and the SRAM memory cell MC2.

Since the active region AR is formed so as to extend continuously, it is possible to reduce variations in the finished dimensions due to mask displacement or the like for forming the active region AR. Further, since the active region AR is formed in a rectangular shape, lithography is facilitated from the viewpoint of RDR (Restrained Design Rule). Therefore, fine processing becomes easy. Thereby, global variation can be reduced.

Further, since the active region AR is formed so as to extend continuously, the on-current (Ion) is improved by the stress applied to the active region AR. Therefore, the cell current increases. As a result, the operation speed can be improved.

According to the semiconductor device SCD of the present embodiment, each of the SRAM memory cell MC1 and the SRAM memory cell MC2 is located on the ground wiring (lower layer wiring) VSS and the ground wiring (lower layer wiring) VSS and is viewed in plan view. 1 includes a ground wiring (upper layer wiring) VSS extending in a direction intersecting with the ground wiring (lower layer wiring) VSS. The ground wiring (lower layer wiring) VSS and the ground wiring (upper layer wiring) VSS are electrically connected.

Since the ground wiring (lower layer wiring) VSS and the ground wiring (upper layer wiring) VSS are electrically connected by a shunt, the ground wiring VSS is formed in a mesh shape. Therefore, IR drop can be reduced.

The above embodiments can be combined in a timely manner.
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

The present invention can be applied particularly advantageously to a semiconductor device including an SRAM.

AG1 first access gate, AG2 second access gate, AR active region, BA1 to BA5 barrier metal film, BL first bit line, / BL second bit line, C1 to C21 contact, CH contact hole, CL1 to CL3 copper film , CW1 to CW3, copper wiring D1 to D6, first direction to sixth direction, DG1 to DG4, first driver gate to fourth driver gate, DHI dark halo region, DNM dummy transistor, DU dummy gate, ER extension region, ES1 , ES2 etching stopper film, FRN, FRP element formation region, G gate structure, HK High-k film, HR halo region, HR1-HR12, 1st halo region to 12th halo region, IF, IS current, IL1-IL5 interlayer insulation Membrane, IO IO area, IR Element isolation region, LC logic circuit, LG1, LG2 load gate, LIC local interconnector, M1 to M32 metal wiring, MA SRAM cell array, MC main control circuit, MC1, MC2 SRAM memory cell, ML metal film, NA1 first access transistor , NA2 second access transistor, ND1 to ND4, first driver transistor to fourth driver transistor, OS offset spacer, PG1, PG2 plug, PIR type impurity region, PL1 first load transistor, PL2 second load transistor, PS polysilicon film , PW p well, R12 to RM21 resist mask, RN NMIS region, RP PMIS region, SD1 to SD6 1st source / drain to 6th source / drain, SA SAMP, SCL metal silicide film, SCD semiconductor device, SF interface layer, SL stress liner film, SN1, first storage node, SN2, second storage node, SNI silicon nitride film, SO silicon oxide film, SR SRAM section, SS semiconductor substrate, SW sidewall spacer, T1, T2 access transistor, T3, T4 driver transistor, T5, T6 load transistor, TL1, TL2 tungsten film, V1 to V24 via hole, VDD power supply wiring, Vgs source-to-gate voltage, VL boundary line, VSS Ground wiring (ground potential), WA1 to WA4 gate width, WD write driver, WL word line, XD X decoder, YD Y decoder.

Claims

A semiconductor device SCD having at least two static random access memory cells (MC1, MC2) arranged adjacent to each other in a planar layout,
Each of the at least two static random access memory cells (MC1, MC2)
A first driver transistor (ND1) having a first driver gate (DG1);
A first load transistor (PL1) having a first load gate (LG1) and electrically connected to the first driver transistor (ND1) at a first storage node (SN1);
A second driver transistor (ND2) having a second driver gate (DG2);
A second load transistor (PL2) having a second load gate (LG2) and electrically connected to the second driver transistor (ND2) at a second storage node (SN2);
A first bit line (BL) and a second bit line (/ BL) for inputting and outputting data;
A first access gate (AG1) and a pair of first source / drain (SD1), and one of the pair of first source / drain (SD1) is electrically connected to the first storage node (SN1); A first access transistor (NA1) connected to the first bit line (B / L) and electrically connected to the other of the pair of first source / drain (SD1);
A second access gate (AG2) and a pair of second source / drain (SD2) are provided, and one of the pair of second source / drain (SD2) is electrically connected to the second storage node (SN2). A second access transistor (NA2) connected to the second bit line (/ BL) and electrically connected to the other of the pair of second source / drain (SD2),
In the planar layout, the first and second access gates (AG1, AG2), the first and second driver gates (DG1, DG2), and the first and second load gates (LG1, LG2) are the same. Extending in the direction,
In the planar layout, a first direction (D1) from one of the pair of first source / drains (SD1) toward the other and a direction from one of the pair of second source / drain (SD2) to the other. The second direction (D2) is the same,
The first directions (D1) of the at least two static random access memory cells (MC1, MC2) are the same direction, and the second directions (D2) are the same direction. Semiconductor device (SCD).
In the planar layout, the two static random lines arranged adjacent to each other in a direction in which the first and second bit lines (BL, / BL) extend across the static random access memory cell (MC1). Each of the first and second driver transistors (ND1, ND2) of the access memory cells (MC1, MC2) and the first and second load transistors (PL1, PL2) are:
The semiconductor device (SCD) according to claim 1, wherein the semiconductor device (SCD) is arranged in line symmetry in the planar layout.
The first and second access transistors (NA1, NA2) are provided to have threshold voltages different from the threshold voltages of the first and second driver transistors (ND1, ND2). The semiconductor device (SCD) according to the first item in the range.
The first and second access transistors (NA1, NA2) are provided to have a threshold voltage higher than a threshold voltage of the first and second driver transistors (ND1, ND2). The semiconductor device (SCD) according to the first item in the range.
The first access transistor (NA1) is adjacent to the other of the first source / drain (SD1) and has a second conductivity type impurity different from the first conductivity type impurity of the first source / drain (SD1). A first halo region (HR1) having
A second halo region (HR2) having an impurity of the second conductivity type having an impurity concentration higher than the impurity concentration of the first halo region (HR1) adjacent to one of the first source / drain (SD1); Including
The second access transistor (NA2) is adjacent to the other of the second source / drain (SD2) and has a second conductivity type impurity different from the first conductivity type impurity of the second source / drain (SD2). A third halo region (HR3) having
A fourth halo region (HR4) adjacent to one of the second source / drain (SD2) and having an impurity of the second conductivity type having an impurity concentration higher than that of the third halo region (HR3); The semiconductor device (SCD) according to claim 1, further comprising:
The first driver transistor (ND1) has a pair of third source / drain (SD3),
One of the pair of third source / drain (SD3) is electrically connected to the first storage node (S / N1), and the pair of third source / drain (SD3) is connected to a ground wiring (VSS). ) Is electrically connected,
The second driver transistor (ND2) has a pair of fourth source / drain (SD4),
One of the pair of fourth source / drain (SD4) is electrically connected to the second storage node (SN2), and the pair of fourth source / drain (SD4) is connected to a ground wiring (VSS). The other is electrically connected, and
A third driver gate (ND3) and a pair of fifth source / drain (SD5) are provided, and one of the pair of fifth source / drain (SD5) is electrically connected to the first storage node (SN1). A third driver transistor (ND3) connected and grounded (VSS) with the other of the pair of fifth source / drain (SD5) electrically connected;
A fourth driver gate (DG4) and a pair of sixth source / drain (SD6) are provided, and one of the pair of sixth source / drain (SD6) is electrically connected to the second storage node (SN2). A fourth driver transistor (ND4) connected to the ground wiring (VSS) and electrically connected to the other of the pair of sixth source / drain (SD6);
In the planar layout, each of the first and second driver gates (DG1, DG2) and the third and fourth driver gates (DG3, DG4) extends in the same direction,
In the planar layout, a third direction (D3) from one of the pair of third source / drain (SD3) to the other and a first direction from one of the pair of fifth source / drain (SD5) to the other. A fourth direction (D4) that is opposite to the fifth direction (D5) and goes from one of the pair of fourth source / drains (SD4) to the other, and the pair of sixth source / drains The sixth direction (D6) from one side of (SD6) to the other is opposite,
In the planar layout, a fifth direction (D5) from one of the pair of fifth source / drains (SD5) to the other and a direction from one to the other of the pair of sixth source / drains (SD6). The sixth direction (D6) is the same,
The fifth directions (D5) of each of the at least two static random access memory cells (MC1, MC2) are the same direction, and the sixth directions (D6) are the same direction. The semiconductor device (SCD) according to claim 1.
The width of the first access gate (AG1) of the first access transistor (NA1) is equal to the width (WA1) of the first driver gate (DG1) of the first driver transistor (ND1) and the third driver transistor ( ND3) is provided to be larger than the width (WA3) of the third driver gate (DG3),
The width of the second access gate (AG2) of the second access transistor (NA2) is equal to the width WA2 of the second driver gate (DG2) of the second driver transistor (ND2) and the fourth driver transistor (ND4). 7. The semiconductor device (SCD) according to claim 6, wherein the semiconductor device (SCD) is provided to be larger than a width WA4 of the fourth driver gate (DG4).
The first driver transistor (ND1) is located in a region immediately below the first driver gate (DG1).
A fifth halo region (HR5) adjacent to the other of the third source / drain (SD3) and having a second conductivity type impurity different from the first conductivity type impurity of the third source / drain (SD3); ,
A sixth halo region (HR6) having an impurity of the second conductivity type having an impurity concentration higher than that of the fifth halo region (HR5), adjacent to one of the third source / drain (SD3). ,
The second driver transistor (ND2) has a region immediately below the second driver gate (DG2).
A seventh halo region (HR7) adjacent to the other of the fourth source / drain (SD4) and having a second conductivity type impurity different from the first conductivity type impurity of the fourth source / drain (SD4); ,
An eighth halo region (HR8) adjacent to one of the fourth source / drain (SD4) and having an impurity of the second conductivity type having an impurity concentration higher than that of the seventh halo region (HR7). ,
The third driver transistor (ND3) is in a region immediately below the third driver gate (DG3).
A ninth halo region (HR9) adjacent to one of the fifth source / drain (SD5) and having a second conductivity type impurity different from the first conductivity type impurity of the fifth source / drain (SD5); ,
A tenth halo region (HR10) having an impurity of the second conductivity type having an impurity concentration higher than that of the ninth halo region (HR9) adjacent to the other of the fifth source / drain (SD5). ,
The fourth driver transistor (ND4) is located in a region immediately below the fourth driver gate (DG4).
An eleventh halo region (HR11) adjacent to one of the sixth source / drain (SD6) and having a second conductivity type impurity different from the first conductivity type impurity of the sixth source / drain (SD6); ,
And a twelfth halo region (HR12) having an impurity of the second conductivity type having an impurity concentration higher than that of the eleventh halo region (HR11) adjacent to the other of the sixth source / drain (SD6). A semiconductor device (SCD) according to claim 6.
The first and second driver transistors (ND1, ND2) are provided to have a threshold voltage higher than that of the first and second access transistors (NA1, NA2). The semiconductor device (SCD) according to the first item in the range.
In the planar layout, the two static lines are arranged adjacent to each other in a direction in which the first and second bit lines (BL, / BL) extend across the static random access memory cell (MC1). The active regions forming the first and second source / drains (SD1, SD2) of the first and second access transistors (NA1, NA2) of the random access memory cells (MC1, MC2) extend continuously. The semiconductor device (SCD) according to claim 1, wherein the semiconductor device (SCD) is provided so as to traverse the two static random access memory cells (MC1, MC2).
Each of the at least two static random access memory cells (MC1, MC2)
Underlayer wiring (VSS),
An upper layer wiring (VSS) located on the lower layer wiring (VSS) and extending in a direction intersecting with the lower layer wiring (VSS) in plan view,
The semiconductor device (SCD) according to claim 1, wherein the lower layer wiring (VSS) and the upper layer wiring (VSS) are electrically connected.