JP2008004664A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress asymmetry failure in device characteristics of a transistor, relating to a memory cell of SRAM. <P>SOLUTION: The semiconductor device comprises an SRAM cell including a pair of inverters consisting of a driver transistor and a load transistor, being so connected that an input and output form a cross-couple, and a pair of access transistors connected to the outputs of the paired inverter. At least one paired transistor among the paired drive transistor and the paired load transistor constituting the paired inverter as well as the paired access transistor is so arranged that the directions are identical from source to drain. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a layout of a SRAM (Static Random Access Memory) memory cell and a differential amplifier in a semiconductor memory device.

  In recent years, miniaturization of SRAM memory cells has progressed, but a circuit margin in the device characteristics of a MOS (Metal Oxide Semiconductor) transistor in the memory cell is gained, and a high-performance and highly reliable SRAM cell is laid out. Is getting harder.

  Hereinafter, as a conventional technique, an SRAM memory cell layout including six transistors will be described with reference to FIGS. 6 and 7 (see, for example, Patent Document 1).

  FIG. 6 shows a basic circuit diagram of an SRAM memory cell composed of six transistors, and FIG. 7 shows a conventional layout of an SRAM memory cell composed of six transistors. .

  As shown in FIGS. 6 and 7, the conventional SRAM memory cell includes drive nMOS transistors TN1 and TN2, access nMOS transistors TN3 and TN4, load pMOS transistors TP1 and TP2, and polysilicon wirings PL1, PL2, and PL3. And PL4, wiring layers AL1 and AL2, contacts CN1, CN2, CN3 and CN4, a first inverter INV1 composed of a drive nMOS transistor TN1 and a load pMOS transistor TP1, a drive nMOS transistor TN2 and a load pMOS transistor TP2 A second inverter INV2, a node SN1 which is an output node of the first inverter INV1, an input node of the second inverter INV2, and a second inverter INV2. A node SN2 which is an input node of the power node and the first inverter INV1, a word line WL1, bit lines BL1 and BL2 running in the vertical direction, a bit line precharge signal PR, and precharge transistors TPR1 and TPR2. And a dynamic amplifier SA.

  Drive nMOS transistors TN1 and TN2 and access nMOS transistors TN3 and TN4 are formed on the p-type diffusion region, and load pMOS transistors TP1 and TP2 are formed on the n-type diffusion region.

  In addition, the gates of the drive nMOS transistor TN1 and the load pMOS transistor TP1 are connected by a polysilicon wiring PL1, and both drains are connected by a wiring layer AL1 through a contact, forming a first inverter INV1. Yes. The gates of the drive nMOS transistor TN2 and the load pMOS transistor TP2 are connected by a polysilicon wiring PL2, and both drains are connected by a wiring layer AL2 through contacts, thereby constituting a second inverter INV2.

  Further, the wiring layer AL1 serving as the output node of the first inverter INV1 is connected to the wiring PL2 functioning as the input node of the second inverter INV2, and the wiring layer AL2 serving as the output node of the second inverter INV2 is the first one. It is connected to a wiring PL1 that functions as an input node of one inverter INV1. As a result, a circuit for holding data is formed.

  The drain of the access nMOS transistor TN3 is connected to the wiring layer AL1 serving as the output node of the first inverter INV1, and the source is connected to the bit line BL1 running in the vertical direction via the contact CN1. The drain of the access nMOS transistor TN4 is connected to the wiring layer AL2 serving as the output node of the second inverter INV2, and the source is connected to the bit line BL2 running in the vertical direction via the contact CN2. Access nMOS transistors TN3 and TN4 are connected to word line WL1 running in the lateral direction via contacts CN3 and CN4.

  Here, as shown in FIG. 7, the drive nMOS transistors TN1 and TN2, the access nMOS transistors TN3 and TN4, and the load pMOS transistors TP1 and TP2 are paired symmetrically around the center of the memory cell region. The source and drain directions of each pair transistor are arranged so as to be opposite to each other.

  Next, with respect to the operation of the SRAM memory cell having the above-described conventional layout, with reference to FIG. While explaining.

  First, the precharge signal PR is in the “L” level state, and the bit lines BL1 and BL2 are precharged to the “H” level state in advance. Thereafter, when the bit line precharge signal PR becomes the “H” level state and the precharge is completed, the word line WL1 becomes the “H” level state, and the access nMOS transistors TN3 and TN4 are turned on. As a result, the bit line BL1 and the node SN1, and the bit line BL2 and the node SN2 become conductive.

  At this time, since the bit line BL1 and the node SN1 have the same potential, no current flows through the access nMOS transistor TN3, so the potential of the bit line BL1 does not change (see 8a in the figure). On the other hand, since there is a potential difference corresponding to the VDD level between the bit line BL2 and the node SN2, a current flows from the bit line BL2 to the node SN2, and the potential of the bit line BL2 gradually decreases (see 8b in the figure). At this time, the node SN2 is affected by the current (I) flowing in the order of the bit line BL2, the node SN2, and the VSS, and the potential of the node SN2 from the on-resistance RTN2 of the drive nMOS transistor TN2 and the on-resistance RTN4 of the access nMOS transistor TN4. Rises by RTN2 / (RTN2 + RTN4) × VDD (see 8c in the figure). As a result, the potential of the gate of the drive nMOS transistor TN1 similarly rises by RTN2 / (RTN2 + RTN4) × VDD, the gate of the drive nMOS transistor TN1 appears to open, and a slight current flows. Slightly lower (see 8d in the figure). As the differential amplifier SA is activated, the lowered potential of the bit line BL2 is lowered to the VSS level (see 8e in the figure). On the other hand, the potential of the bit line BL1 maintains the VDD level.

  At this time, the device characteristics of the pair transistors of the drive nMOS transistors TN1 and TN2, the access nMOS transistors TN3 and TN4, and the load pMOS transistors TP1 and TP2 in the SRAM memory cell are accurately read out from the signals of the nodes SN1 and SN2. The balance is greatly affected. The reason why this balance of device characteristics is important for accurately reading the signals of the nodes SN1 and SN2 will be described below.

  If an asymmetry defect occurs in the device characteristics of each pair transistor, an accurate signal cannot be output to the differential amplifier. For example, in the pair transistors of the drive nMOS transistors TN1 and TN2, when asymmetry occurs in the device characteristics so as to satisfy the relationship of (threshold voltage VT2 of the drive nMOS transistor TN2)> (threshold voltage VT1 of the drive nMOS transistor TN1) An example of the read operation in FIG.

  The precharge state is the same as the state from time T0 to time T1 shown in FIG. However, since the threshold voltage VT2 of the drive nMOS transistor TN2 is high, the potential of the node SN2 increases until the current flows in the order of the bit line BL2, the node SN2, and VSS in the node SN2, and conversely, the drive nMOS transistor TN1. Since the threshold voltage VT1 of the node n2 is low, the potential of the node SN1 gradually decreases as the node SN2 rises slightly and exceeds the threshold voltage VT1 of the drive nMOS transistor TN1. Therefore, the node SN1 of the SRAM memory cell in which the “H” level state is preliminarily written in the node SN1 and the “L” level state is written in the node SN2 approaches the “L” level state from the “H” level state. When the differential amplifier SA is activated from the “L” level state to the “H” level state, the lowered potential of the bit line BL1 is pulled down to the VSS level, and the potential of the bit line BL2 becomes the VDD level. This causes a malfunction that can be lifted up.

  In order to prevent the malfunction caused in this way, the device characteristics of the pair transistors of the drive nMOS transistors TN1 and TN2, the access nMOS transistors TN3 and TN4, and the load pMOS transistors TP1 and TP2 in the SRAM memory cell are secured. It is important to do.

  Although the SRAM memory cell having the conventional layout has been described above, a differential amplifier SA that amplifies a minute potential having the conventional layout, which causes the same problem, will be described below with reference to FIGS. Explained.

  FIG. 9 shows a basic circuit configuration of the differential amplifier SA, and FIG. 10 shows a conventional layout of the differential amplifier SA.

  As shown in FIGS. 9 and 10, the conventional differential amplifier SA includes nMOS transistors TN5 and TN6, pMOS transistors TP5 and TP6, nMOS transistors TNS and pMOS transistors TPS, wiring layers AL3 and AL4, and control signals. SA1 and an inverter circuit INV3 are included.

  The nMOS transistors TN5 and TN6 and the nMOS transistor TNS are formed on the p-type diffusion region, and the pMOS transistors TP5 and TP6 and the pMOS transistor TPS are formed on the n-type diffusion region.

  The gates of the nMOS transistor TN5 and the pMOS transistor TP5 are connected by a wiring layer AL4 through a contact, and the drains of the nMOS transistor TN5 and the pMOS transistor TP5 are connected by a wiring layer AL3 through a contact. The gates of the nMOS transistor TN6 and the pMOS transistor TP6 are connected by a wiring layer AL3 through a contact, and the drains of the nMOS transistor TN6 and the pMOS transistor TP6 are connected by a wiring layer AL3 through a contact.

  The drains of the nMOS transistor TN5 and the pMOS transistor TP5 and the gates of the nMOS transistor TN6 and the pMOS transistor TP6 are connected to each other through the contact by the wiring layer AL3 and to the bit line BL1. The drains of the nMOS transistor TN6 and the pMOS transistor TP6 and the gates of the nMOS transistor TN5 and the pMOS transistor TP5 are connected to each other through the contact in the wiring layer AL4 and to the bit line BL2.

  The sources of the nMOS transistor TN5 and the nMOS transistor TN6 are connected via a contact and are connected to the drain of the nMOS transistor TNS. The sources of the pMOS transistor TP5 and the pMOS transistor TP6 are connected via a contact and also connected to the drain of the pMOS transistor TPS. The gate of the nMOS transistor TSN and the gate of the pMOS transistor TPS are connected via an inverter circuit INV3. The nMOS transistor TSN and the pMOS transistor TPS are transistors controlled by the control signal SA1.

  Here, as shown in FIG. 10, the nMOS transistor TN5 and the nMOS transistor TN6 are arranged point-symmetrically, and the source-drain directions of the pair transistors are arranged in opposite directions. In addition, the pMOS transistor TP5 and the pMOS transistor TP6 are arranged point-symmetrically so that the source-drain directions of the pair transistors are opposite to each other.

  Next, the operation of the differential amplifier SA having the above-described conventional layout will be described with reference to FIG.

  First, the differential amplifier SA is on standby with the bit lines BL1 and BL2 in the “H” level state and the control signal SA1 in the “L” state. Thereafter, in a state where the potential of the bit line BL2 is slightly lowered from the VDD level by the operation of the memory cell, the control signal SA1 changes from the “L” state to the “H” state, and the gates of the nMOS transistor TSN and the pMOS transistor TPS are turned on. When the circuit is opened and turned on and current flows, the drain potential of the nMOS transistor TSN gradually decreases.

  At this time, since there is a relationship of (potential VBL1 of bit line BL1)> (potential VBL2 of bit line BL2), a relationship of (gate potential VGS of nMOS transistor TN5) <(gate potential VGS of nMOS transistor TN6) is established. The nMOS transistor TN6 is first turned on to lower the potential of the bit line BL2 (see 11a in the figure). On the other hand, regarding the bit line BL1, since there is a relationship of (the potential VBL1 of the bit line BL1)> (the potential VBL2 of the bit line BL2), the pMOS transistor TP5 is more likely to be turned on than the pMOS transistor TP6. Since the pMOS transistor TP5 is turned on and the pMOS transistor TP6 is turned off, the potential is kept at the VDD state (see 11b in the figure).

  At this time, the balance of the device characteristics of the pair transistors greatly affects the accurate reading of the signals of the bit lines BL1 and BL2. The reason why this balance of device characteristics is important for accurately reading the signals of the nodes SN1 and SN2 will be described below.

  While the differential amplifier SA is on standby, the state is the same as the state from time T0 to time T1 shown in FIG. Thereafter, in a state where the potential of the bit line BL2 is slightly lowered from the VDD level by the operation of the memory cell, the control signal SA1 changes from the “L” state to the “H” state, and the gates of the nMOS transistor TSN and the pMOS transistor TPS are turned on. When the circuit is opened and turned on and current flows, the drain potential of the nMOS transistor TSN gradually decreases.

At this time, since the relationship of (the potential VBL1 of the bit line BL1)> (the potential VBL2 of the bit line BL2) is satisfied, the relationship of (VGS of the nMOS transistor TN5) <(VGS of the nMOS transistor TN6) is satisfied, and the nMOS transistor TN6 Is turned on to lower the potential of the bit line BL2, but asymmetry occurs in the device characteristics due to implantation,
| (Threshold voltage VT6 of nMOS transistor TN6) − (Threshold voltage VT5 of nMOS transistor TN5) |
> | Potential VBL1 of bit line BL1-potential VBL2 of bit line BL2 |
Therefore, even if there is a relationship of (VGS of nMOS transistor TN5) <(VGS of nMOS transistor TN6), the nMOS transistor TN5 is likely to be turned on. As a result, the nMOS transistor TN5 is turned on first. And the potential of the bit line BL1 is lowered.

  On the other hand, the bit line BL2 has a relationship of (potential VBL1 of the bit line BL1) <(potential VBL2 of the bit line BL2), so that the pMOS transistor TP6 is more likely to be turned on than the pMOS transistor TP5. Since the pMOS transistor TP6 is turned on and the pMOS transistor TP5 is turned off, the potential is raised to the VDD level.

  In order to prevent the malfunction caused in this way, it is important to balance the device characteristics of the nMOS transistors TN5 and TN6 and the pMOS transistors TP5 and TP6 in the differential amplifier.

  As described above, the balance of the device characteristics of the MOS transistor has a great influence on the occurrence of malfunction in the SRAM memory cell having the conventional layout and the differential amplifier having the conventional layout.

  By the way, extension injection (also referred to as LDD (lightly doped drain) injection) and halo injection (or pocket injection) are known as having a great influence on the balance of device characteristics of MOS transistors.

  First, extension implantation for forming a source region and a drain region of a MOS transistor will be described with reference to FIG.

  FIG. 12 is a schematic diagram showing the spread of an ion beam in an implanter, and shows an ion beam E1 with a high energy beam and an ion beam E2 with a low energy beam.

  As shown in FIG. 12, since the spread of the ion beam spreads due to repulsion between ions, it has a feature of spreading in a trumpet shape. For this reason, the ion beam has a feature that the distribution of angles varies depending on the travel distance. Comparing the trumpet-shaped spread of the ion beam E1 with a high energy beam and the trumpet-shaped spread of the ion beam E2 with a low energy beam, the lower the energy, the larger the trumpet-shaped spread. However, a difference in energy to be injected easily occurs depending on the position in the plane. Particularly recently, extension implantation in MOS transistors is performed at 1 KeV or less, and the trumpet spread of the ion beam has become very large.

  In a batch type ion implantation apparatus in which a plurality of wafers are mounted on a rotating disk used for extension implantation and implanted, a pad angle is provided to attach the wafer by centrifugal force. For this reason, in the ion implantation at a tilt of 0 degree, an angle deviation of 1 degree or more appears on the left and right sides of the wafer, and as a result, asymmetry appears in the device characteristics of the MOS transistor, which is the result of 2002 IWJT (International workshop Junction Technology). Have been reported. Therefore, it can be seen that even if the channel direction is the same, if the source position and the drain position of the MOS transistor are switched, an asymmetry occurs in the threshold voltage (VT) of the MOS transistor.

Many of the problems in the asymmetry of the device characteristics can be obtained by canceling the distortion of the ion beam or the asymmetry in the ion beam by implanting from four directions with a rotation of 90 degrees called four-step implantation.
JP 2004-71118 A Japanese Patent No. 3539705

  However, for the halo implantation (or pocket implantation) for suppressing the short channel characteristics in the medium current ion implantation apparatus, it is essential to use the above four-step implantation as in the extension implantation. Therefore, there is a problem that even if four-step implantation is used, distortion of the ion beam or asymmetry in the ion beam cannot be canceled.

  This phenomenon is caused by the structure of the ion implantation apparatus. In general, the medium-current ion implantation apparatus has a configuration in which an ion beam is scanned electrostatically or magnetically in the horizontal direction, and in the surface is uniformly implanted by two-dimensional scanning by mechanical scanning in the vertical direction. It has become. There are two types of mechanical scanning in the vertical direction. One of them is a high tilt angle implantation, and the ion beam irradiation point moves depending on the implantation position in the wafer. An injection with a different beam spread will be made.

  FIG. 13 shows a wafer W1, ion beams E4, E5, E6, and E7, and MOS transistors T1, T2, T3, and T4.

  As shown in FIG. 13, in halo implantation (or pocket implantation) at two locations above and below the 4-step implantation (for example, the location where the transistor T1 exists and the location where the transistor T4 exists), the implantation points of the ion beams E4 and E7 Therefore, the ion beams E4 and E7 are implanted with different ion beam spreads. Therefore, as shown in FIG. 14, according to halo implantation (or pocket implantation) at two locations above and below the four-step implantation, impurity distributions 14a and 14b are formed on the left and right (or top and bottom) of the gate electrode G1 of the MOS transistor. Are formed as a source region and a drain region which are not intended for each other. Similarly, in the case of halo implantation (or pocket implantation) at the two left and right locations (two locations in the horizontal direction) of the four-step implantation, when the distances to the left and right implantation points are different, the ion beams E5 and E6 are similarly used. Therefore, the implantation of the ion beam in the wafer W1 is narrowed and the implantation is widened, and the impurity distributions at the sources and drains of the MOS transistors T2 and T3 show asymmetry. End up.

  In other words, even if the channel directions of the MOS transistors are the same, if the positions of the source and drain of the MOS transistors are reversed, the distance between the MOS transistors is close. Asymmetry of the impurity distribution also occurs.

  For this reason, as shown in FIG. 15, depending on the channel direction of the MOS transistor, transistors having different threshold voltage (VT) characteristics are formed, and the source and drain directions are arranged opposite to each other even if the channel direction is the same. In this case, an asymmetry of the device characteristics of the MOS transistor occurs.

  Therefore, for the purpose of preventing defects due to the non-target property of the device characteristics, as described above, in the conventional SRAM memory cell, each pair transistor is arranged to be point-symmetric, and the source-drain of each pair transistor is In the conventional differential amplifier, the pair transistors are arranged so as to be symmetric with respect to each other so that the source-drain directions of the pair transistors are opposite to each other. However, there is still a problem that asymmetry of the device characteristics of the MOS transistor occurs.

  Further, in the SRAM memory cell, in order to achieve high integration, further miniaturization of the size of the MOS transistor in the memory cell is required. However, in order to provide a high-yield and highly reliable SRAM memory cell, it is necessary to gain a circuit margin due to variations in device characteristics of the MOS transistor. As a result, the size of the MOS transistor can be easily reduced. There is a problem that it is difficult. This problem also applies to a differential amplifier that amplifies a minute potential.

  In view of the above, an object of the present invention is to suppress an asymmetry defect in the device characteristics of a MOS transistor in an SRAM memory cell or a differential amplifier, and to obtain a circuit margin. It is an object to provide a semiconductor device that achieves high reliability.

  In order to achieve the above object, a semiconductor device according to the first aspect of the present invention is connected so that input and output are cross-coupled, and each of an inverter pair including a driver transistor and a load transistor, and an inverter pair A semiconductor device comprising an SRAM cell including an access transistor pair connected to an output, wherein at least one of a drive transistor pair and a load transistor pair and an access transistor pair constituting an inverter pair The two transistor pairs are arranged so that the directions from the source to the drain are the same.

  In the semiconductor device according to the first aspect of the present invention, the source-drain directions are all the same in all of the pair of drive transistors, the pair of load transistors, and the pair of access transistors. It is preferable that they are arranged as described above.

  A semiconductor device according to a second aspect of the present invention includes a differential amplifier including a first inverter and a second inverter which are connected so that input and output are cross-coupled and each of which includes a pMOS transistor and an nMOS transistor. In the first inverter and the second inverter, at least one transistor pair of the first transistor pair including the pMOS transistors and the second transistor pair including the nMOS transistors is from the source. They are arranged so that the directions to the drain (which may be paraphrased as the direction from the drain to the source. The same applies hereinafter) are the same.

  In the semiconductor device according to the second aspect of the present invention, all of the pMOS transistor pair and the nMOS transistor pair are arranged so that the directions from the source to the drain are the same. It is preferable that

A semiconductor device according to a third aspect of the present invention is a semiconductor device including a differential amplifier including a first inverter and a second inverter which are connected so that input and output are cross-coupled and each of which includes a pMOS transistor and an nMOS transistor. The pMOS transistors constituting the first inverter are composed of first and second pMOS transistors connected in parallel to each other.
The nMOS transistor constituting the first inverter is composed of first and second nMOS transistors connected in parallel to each other, and the pMOS transistor constituting the second inverter is composed of third and fourth pMOSs connected in parallel to each other. The nMOS transistors that are transistors and constitute the second inverter are third and fourth nMOS transistors that are connected in parallel to each other, and are a pair of transistors including the first and second pMOS transistors, the first and second transistors. Each of the pair of transistors consisting of nMOS transistors, the pair of transistors consisting of third and fourth pMOS transistors, and the pair of transistors consisting of third and fourth nMOS transistors are opposite in direction from the source to the drain. Arranged to face the first And a pair of transistors consisting of the first and third nMOS transistors, a pair of transistors consisting of the second and fourth pMOS transistors, and a pair of transistors consisting of the second and fourth nMOS transistors. Each pair of transistors is arranged so that the direction from the source to the drain is the same.

  According to the semiconductor device of the present invention, it is possible to suppress the asymmetry defect in the device characteristics of the MOS transistor caused by the asymmetry of the impurity distribution of the source and drain during the implantation, and to increase the circuit margin. And high reliability can be realized.

(First embodiment)
A semiconductor device (semiconductor memory device) according to a first embodiment of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a layout of an SRAM memory cell composed of six transistors according to the first embodiment of the present invention. Since the circuit diagram of the SRAM memory cell is the same as the circuit diagram of FIG. 6 described above, description thereof will not be repeated here.

  As shown in FIG. 1, the SRAM memory cell in this embodiment includes drive nMOS transistors TN1 and TN2, access nMOS transistors TN3 and TN4, load pMOS transistors TP1 and TP2, polysilicon wirings PL1, PL2, PL3, and PL4, wiring layers AL1 and AL2, and contacts CN1, CN2, CN3, and CN4 are provided.

  Drive nMOS transistors TN1 and TN2 and access nMOS transistors TN3 and TN4 are formed on the p-type diffusion region, and load pMOS transistors TP1 and TP2 are formed on the n-type diffusion region.

  In addition, the gates of the drive nMOS transistor TN1 and the load pMOS transistor TP1 are connected by a polysilicon wiring PL1, and both drains are connected by a wiring layer AL1 through a contact, forming a first inverter INV. Yes. The gates of the drive nMOS transistor TN2 and the load pMOS transistor TP2 are connected by a polysilicon wiring PL2, and both drains are connected by a wiring layer AL2 through contacts, thereby constituting a second inverter INV2.

  The wiring layer AL1 that is the output node of the first inverter INV1 is connected to the wiring PL2 that is the input node of the second inverter INV2, and the wiring layer AL2 that is the output node of the second inverter INV2 is the first inverter. It is connected to a wiring PL1 that becomes an input node of INV1. As a result, a circuit for holding data is formed.

  The drain of the access nMOS transistor TN3 is connected to the wiring layer AL1 serving as the output node of the first inverter INV1, and the source is connected to the bit line BL1 running in the vertical direction via the contact CN1. The drain of the access nMOS transistor TN4 is connected to the wiring layer AL2 serving as the output node of the second inverter INV2, and the source is connected to the bit line BL2 running in the vertical direction via the contact CN2. Access nMOS transistors TN3 and TN4 are connected to word line WL1 running in the lateral direction via contacts CN3 and CN4.

  Here, as shown in FIG. 1, the pair transistors of the drive nMOS transistors TN1 and TN2 and the access nMOS transistors TN3 and TN4 are arranged symmetrically with respect to the vertical line segment passing through the center of the memory cell region. The direction from the source to the drain of each pair transistor is arranged to be the same. Further, the load pMOS transistors TP1 and TP2 are arranged point-symmetrically around the center of the memory cell region, and the pair transistors are arranged so that the directions from the source to the drain are opposite to each other.

  As a result, the direction from the source to the drain of each pair transistor of the drive nMOS transistor and the access nMOS transistor is the same, and the asymmetry defect in the device characteristics of the MOS transistor caused by the asymmetry of the impurity distribution of the source and drain in the implantation is eliminated. Therefore, the accuracy of the transistor characteristics required for the load pMOS transistor is relaxed, and as a result, the cost of the implantation mask and the implantation machine can be reduced.

  According to the semiconductor device according to the present embodiment, when the SRAM dedicated implantation mask exists, the direction from the source to the drain of each pair transistor of the drive transistor and the pair transistor of the access transistor in the SRAM memory cell is the same. Since it is arranged so as to be oriented, it becomes possible to suppress the asymmetry defect in the device characteristics of the MOS transistor resulting from the asymmetry of the impurity distribution of the source and drain during implantation, and the device characteristic accuracy of the load transistor is relaxed. The As a result, the accuracy required of the injector used for the implantation for forming the load transistor is relaxed, so that the cost of the injector can be reduced and the wafer cost can be reduced.

  In the present embodiment, the case where the drive transistor pair and the access transistor pair are arranged so that the directions from the source to the drain are the same is described, but the present invention is not limited to this, and at least the drive transistor pair, In any one of the load transistor pair and the access transistor pair, the source-to-drain direction is the same, so that the MOS transistor caused by the asymmetry of the source and drain impurity distribution in the implantation The effect of suppressing the asymmetry defect in the device characteristics can be obtained.

-Modification-
FIG. 2 shows a layout of an SRAM memory cell composed of six transistors according to a modification of the first embodiment of the present invention. In FIG. 2, elements having the same functions as those of the elements constituting FIG. 1 described above are denoted by the same reference numerals, and description thereof will not be repeated. The circuit diagram of the SRAM memory cell of this modification is the same as that of FIG.

  In the modification of the first embodiment of the present invention, as shown in FIG. 2, the pair transistors of the drive nMOS transistors TN1 and TN2, the access nMOS transistors TN3 and TN4, and the load pMOS transistors TP1 and TP2 are all in the memory cell region. Are arranged symmetrically with respect to a line segment in the vertical direction passing through the center of each pair, and the direction from the source to the drain of each pair transistor is arranged in the same direction.

  In this way, since the direction from the source to the drain of the pair transistor is the same, the asymmetry defect in the device characteristics of the MOS transistor caused by the asymmetry of the impurity distribution of the source and drain during implantation is suppressed, and a circuit margin is gained. It becomes possible.

  Further, the drive transistor pair transistor, the load transistor pair transistor, and the access transistor pair transistor in the SRAM memory cell are arranged in the same direction from the source to the drain in the pair transistors of the access transistor. Therefore, the asymmetry defect in the device characteristics of the MOS transistor caused by the asymmetry of the impurity distribution of the source and drain during the implantation can be further suppressed, and as a result, the circuit margin can be further increased, and the SRAM memory with higher accuracy can be obtained. A cell is realized.

(Second Embodiment)
Hereinafter, a semiconductor device (differential amplifier) according to a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 3 shows a layout of the differential amplifier according to the second embodiment of the present invention. Since the circuit diagram of the differential amplifier is the same as the circuit diagram of FIG. 9 described above, description thereof will not be repeated here.

  As shown in FIG. 3, the differential amplifier in this embodiment includes nMOS transistors TN5 and TN6, pMOS transistors TP5 and TP6, nMOS transistors TNS and pMOS transistors TPS, wiring layers AL3, AL4, AL5 and AL6, Bit lines BL1 and BL2 are provided.

  The nMOS transistors TN5 and TN6 and the nMOS transistor TNS are formed on the p-type diffusion region, and the pMOS transistors TP5 and TP6 and the pMOS transistor TPS are formed on the n-type diffusion region. The gates of the nMOS transistor TN5 and the pMOS transistor TP5 are connected by a wiring layer AL4 through a contact, and the drains of the nMOS transistor TN5 and the pMOS transistor TP5 are connected by a wiring layer AL3 through a contact. The gates of the nMOS transistor TN6 and the pMOS transistor TP6 are connected by a wiring layer AL3 through a contact, and the drains of the nMOS transistor TN6 and the pMOS transistor TP6 are connected by a wiring layer AL4 through a contact.

  The drains of the nMOS transistor TN5 and the pMOS transistor TP5 and the gates of the nMOS transistor TN6 and the pMOS transistor TP6 are connected to each other through the contact by the wiring layer AL3 and to the bit line BL1. The drains of the nMOS transistor TN6 and the pMOS transistor TP6 and the gates of the nMOS transistor TN5 and the pMOS transistor TP5 are connected to each other through the contact in the wiring layer AL4 and to the bit line BL2. The sources of the nMOS transistor TN5 and the nMOS transistor TN6 and the drain of the nMOS transistor TNS are connected by the wiring layer AL5. The sources of the pMOS transistor TP5 and the pMOS transistor TP6 and the drain of the pMOS transistor TPS are connected by the wiring layer AL6. The gate of the nMOS transistor TSN and the gate of the pMOS transistor TPS are connected via an inverter circuit. The nMOS transistor TSN and the pMOS transistor TPS are controlled by a control signal.

  Here, the pair transistors of the nMOS transistor TN5 and the nMOS transistor TN6 are arranged so that the directions from the source to the drain are the same. Similarly, the pMOS transistors TP5 and TP6 are arranged so that the directions from the source to the drain of the pair transistors are the same. In this way, the direction from the source to the drain becomes the same direction, and it is possible to suppress the asymmetry defect in the device characteristics of the MOS transistor caused by the asymmetry of the impurity distribution of the source and the drain in the implantation, and to obtain a circuit margin. Become.

  Similarly, according to the differential amplifier according to the second embodiment of the present invention, the direction from the source to the drain of the pair transistors of the nMOS transistor and the pair transistors of the pMOS transistor is the same. As a result, the device characteristics of the MOS transistor due to the asymmetry of the impurity distribution of the source and drain during the implantation are further suppressed, and as a result, the circuit margin can be further increased, resulting in higher accuracy. A differential amplifier can be realized.

  In the present embodiment, the case where the paired transistors of the nMOS transistor and all the paired transistors of the pMOS transistor are arranged in the same direction from the source to the drain has been described. However, the present invention is not limited to this. Instead, at least one of the pair transistor of the nMOS transistor and the pair transistor of the pMOS transistor is arranged so that the direction from the source to the drain is the same, so that The effect of suppressing the asymmetry defect in the device characteristics of the MOS transistor caused by the asymmetry of the impurity distribution of the drain can be obtained.

-Modification-
Hereinafter, a semiconductor device (differential amplifier) according to a modification of the second embodiment of the present invention will be described with reference to the drawings.

  FIG. 4 shows a circuit diagram of a differential amplifier according to a modification of the second embodiment of the present invention. FIG. 5 shows a layout of the differential amplifier shown in FIG. 4 and 5, elements having the same functions as those of the elements constituting FIG. 3 described above are denoted by the same reference numerals, and description thereof will not be repeated here.

  4 and 5, the differential amplifier according to the modification of the second embodiment of the present invention includes nMOS transistors TN7A, TN7B, TN8A and TN8B, pMOS transistors TP7A, TP7B, TP8A and TP8B, It has an nMOS transistor TNS, a pMOS transistor TPS, wiring layers AL7, AL8, AL9 and AL10, a control signal SA1, an inverter circuit INV3, and bit lines BL1 and BL2.

  The nMOS transistors TN7A, TN7B, TN8A, and TN8B are formed on the p-type diffusion region, and the pMOS transistors TP7A, TP7B, TP8A, and TP8B are formed on the n-type diffusion region.

  In the modification of the second embodiment of the present invention, in the two nMOS transistors TN5 and TN6 constituting the basic circuit diagram of the differential amplifier shown in FIG. 9, the nMOS transistor TN5 is replaced with two nMOS transistors TN7A and TN7B. The nMOS transistor TN6 is composed of two nMOS transistors TN8A and TN8B. The nMOS transistors TN7A and TN7B and the nMOS transistors TN8A and TN8B are arranged so that the directions from the source to the drain are opposite to each other. On the other hand, the nMOS transistors TN7A and TN8A and the nMOS transistors TN7B and TN8B are arranged in the same direction from the source to the drain.

  Further, for the two pMOS transistors TP5 and TP6 in FIG. 9, the pMOS transistor TP5 is composed of two pMOS transistors TP7A and TP7B, and the pMOS transistor TP6 is composed of pMOS transistors TP8A and TP8B. The pMOS transistors TP7A and TP7B and the pMOS transistors TP8A and TP8B are arranged so that the directions from the source to the drain are opposite to each other. On the other hand, the pMOS transistors TP7A and TP8A and the pMOS transistors TP7B and TP8B are arranged in the same direction from the source to the drain.

  The gates of the nMOS transistor TN7A, the nMOS transistor TN7B, the pMOS transistor TP7A, and the pMOS transistor TP7B are connected to each other through the contact by the wiring layer AL7. Are connected to the wiring layer AL7 through contacts, and are connected to the bit line BL2.

  The gates of the nMOS transistor TN8A, the nMOS transistor TN8B, the pMOS transistor TP8A, and the pMOS transistor TP8B are connected to each other through the contact by the wiring layer AL8. Are connected by the wiring layer AL8 through contacts, and are connected to the bit line BL1.

  The sources of the nMOS transistors TN7A, TN7B, TN8A, and TN8B and the drain of the nMOS transistor TNS are connected by a wiring layer AL9 through a contact. The sources of the pMOS transistors TP7A, TP7B, TP8A, and TP8B and the drain of the pMOS transistor TPS are connected by the wiring layer AL10 through a contact. The gate of the nMOS transistor TSN and the gate of the pMOS transistor TPS are connected via an inverter circuit INV3. The nMOS transistor TSN and the pMOS transistor TPS are transistors controlled by the control signal SA1.

  Thus, each nMOS transistor constituting the conventional differential amplifier is composed of two nMOS transistors, and the two nMOS transistors are arranged so that the directions from the source to the drain are opposite to each other. As a result, the two nMOS transistors cancel out the asymmetry in the device characteristics of the MOS transistor caused by the asymmetry of the impurity distribution of the source and drain caused by the difference in the ion beam spread in the wafer surface during implantation. It is possible to suppress variations in the wafer surface of the dynamic amplifier and to obtain a circuit margin.

  Further, in the two nMOS transistors constituting the conventional differential amplifier, each nMOS transistor is composed of two nMOS transistors so that the directions from the source to the drain of the two nMOS transistors are opposite to each other. Similarly, in the two pMOS transistors constituting the differential amplifier, each pMOS transistor is composed of two pMOS transistors, and the directions from the source to the drain of the two pMOS transistors are mutually different. By arranging them in the opposite direction, the variation in the wafer surface of the differential amplifier due to the asymmetry of the impurity distribution caused by the difference in the spread of the ion beam in the wafer surface during implantation is suppressed, and the circuit margin is increased. It is possible to earn and a high-precision differential amplifier It can be current.

  As described above, the semiconductor device according to the present invention eliminates the asymmetry defect in the device characteristics of the MOS transistor caused by the asymmetry of the impurity distribution of the source and drain in the implantation of each pair transistor in the SRAM memory cell or the differential amplifier. This makes it possible to suppress and increase a circuit margin, and is particularly useful for the layout design of an SRAM memory cell or a differential amplifier.

1 is a layout diagram of an SRAM memory cell according to a first embodiment of the present invention. FIG. 10 is a layout diagram of an SRAM memory cell according to a modification of the first embodiment of the present invention. FIG. 6 is a layout diagram of a differential amplifier according to a second embodiment of the present invention. It is a circuit diagram of the differential amplifier which concerns on the modification of the 2nd Embodiment of this invention. FIG. 10 is a layout diagram of a differential amplifier according to a modification of the second embodiment of the present invention. 1 is a basic circuit diagram of an SRAM memory cell. It is a conventional layout diagram of an SRAM memory cell. 10 is a timing chart of a read operation in the conventional layout of the SRAM memory cell. It is a basic circuit diagram of a differential amplifier. It is the conventional layout figure of a differential amplifier. It is a timing chart of the read-out operation in the conventional layout of a differential amplifier. It is a schematic diagram which shows the breadth of the ion beam in an implanter. It is a schematic diagram which shows the difference of the breadth of the ion beam in a wafer surface. It is a schematic diagram which shows the asymmetry of the ion beam in high inclination angle implantation. It is a figure which shows the asymmetry of the threshold voltage by the direction of a transistor.

Explanation of symbols

TN1, TN2 Drive nMOS transistors TN3, TN4 in the SRAM memory cell Access nMOS transistors TP1, TP2 in the SRAM memory cell Load pMOS transistors PL1, PL2, PL3, PL4 in the SRAM memory cell Polysilicon wiring AL1, AL2 In the SRAM memory cell Wiring layers CN1, CN2, CN3, CN4 contacts INV1, INV2 Inverter SN1 in SRAM memory cell Output node of first inverter INV1 and input node SN2 of second inverter INV2 Output node of first inverter INV2 and first Inverter INV1 input node WL1 Word line BL1, BL2 Bit line
PR bit line precharge signal TPR1, TPR2 precharge transistor SA differential amplifier SA1 control signals TN5, TN6, TN7A, TN7B, TN8A, TN8B nMOS transistors TP5, TP6, TP7A, TP7B, TP8A, TP8B in the differential amplifier PMOS transistor INV3 in amplifier Inverter TNS connected to differential amplifier nMOS transistor TPS controlled by control signal pMOS transistors AL3, AL4, AL5, AL6, AL7, AL8, AL9, AL10 controlled by control signal In differential amplifier Wiring layer E1 Ion beam with high energy beam in implanter E2 Ion beam with low energy beam in implanter W1 Wafers E4, E5, E6, E7 Ion in implanter Beam T1, T2, T3, T4 MOS transistor G1 gate electrode

Claims (5)

A semiconductor device including an SRAM cell including input / output cross-coupled inverter pairs including a driver transistor and a load transistor, and an access transistor pair connected to each output of the inverter pair. And
At least one transistor pair of the drive transistor pair and the load transistor pair and the access transistor pair constituting the inverter pair has the same direction from the source to the drain. A semiconductor device characterized in that the semiconductor device is disposed.   All of the pairs of transistors constituting each of the pair of drive transistors, the pair of load transistors, and the pair of access transistors are arranged so that the directions from the source to the drain are the same as each other. The semiconductor device according to claim 1. A semiconductor device including a differential amplifier including a first inverter and a second inverter, each of which is connected so that input / output is cross-coupled and includes a pMOS transistor and an nMOS transistor,
In the first inverter and the second inverter, at least one of the pair of first transistors composed of the pMOS transistors and the pair of second transistors composed of the nMOS transistors is from the source to the drain. The semiconductor devices are arranged so that their directions are the same as each other.   4. The transistor pair constituting each of the pair of pMOS transistors and the pair of nMOS transistors is arranged so that directions from a source to a drain are the same as each other. A semiconductor device according to 1. A semiconductor device including a differential amplifier including a first inverter and a second inverter, each of which is connected so that input / output is cross-coupled and includes a pMOS transistor and an nMOS transistor,
The pMOS transistor constituting the first inverter is composed of first and second pMOS transistors connected in parallel to each other,
The nMOS transistors constituting the first inverter are composed of first and second nMOS transistors connected in parallel to each other,
The pMOS transistors constituting the second inverter are composed of third and fourth pMOS transistors connected in parallel to each other,
The nMOS transistors constituting the second inverter are composed of third and fourth nMOS transistors connected in parallel to each other,
A pair of transistors consisting of the first and second pMOS transistors, a pair of transistors consisting of the first and second nMOS transistors, a pair of transistors consisting of the third and fourth pMOS transistors, and the third and Each of the pair of transistors composed of the fourth nMOS transistors is arranged so that the directions from the source to the drain are opposite to each other,
A pair of transistors consisting of the first and third pMOS transistors, a pair of transistors consisting of the first and third nMOS transistors, a pair of transistors consisting of the second and fourth pMOS transistors, and the second and second pairs of transistors. 4. A semiconductor device, wherein each of a pair of four nMOS transistors is arranged so that directions from a source to a drain are the same.

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