WO2012013977A1 - Compensation de variation de résistance induites par une contrainte - Google Patents

Compensation de variation de résistance induites par une contrainte Download PDF

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Publication number
WO2012013977A1
WO2012013977A1 PCT/GB2011/051434 GB2011051434W WO2012013977A1 WO 2012013977 A1 WO2012013977 A1 WO 2012013977A1 GB 2011051434 W GB2011051434 W GB 2011051434W WO 2012013977 A1 WO2012013977 A1 WO 2012013977A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
resistor
reference resistor
metallic
compensation parameter
Prior art date
Application number
PCT/GB2011/051434
Other languages
English (en)
Inventor
Stephen John Harrold
Adrian Harvey Bratt
Jonathan Lasselet Goldfinch
Original Assignee
Eosemi Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eosemi Limited filed Critical Eosemi Limited
Priority to EP11754462.7A priority Critical patent/EP2599119A1/fr
Priority to JP2013521220A priority patent/JP2013535832A/ja
Priority to CN201180046664.6A priority patent/CN103125021A/zh
Publication of WO2012013977A1 publication Critical patent/WO2012013977A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D3/00—Indicating or recording apparatus with provision for the special purposes referred to in the subgroups
    • G01D3/028—Indicating or recording apparatus with provision for the special purposes referred to in the subgroups mitigating undesired influences, e.g. temperature, pressure
    • G01D3/036—Indicating or recording apparatus with provision for the special purposes referred to in the subgroups mitigating undesired influences, e.g. temperature, pressure on measuring arrangements themselves
    • G01D3/0365—Indicating or recording apparatus with provision for the special purposes referred to in the subgroups mitigating undesired influences, e.g. temperature, pressure on measuring arrangements themselves the undesired influence being measured using a separate sensor, which produces an influence related signal
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/26—Auxiliary measures taken, or devices used, in connection with the measurement of force, e.g. for preventing influence of transverse components of force, for preventing overload
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

Definitions

  • This invention relates to an apparatus for compensating for stress induced variations in the resistance of a semiconductor resistor element, and to associated methods of compensating for stress induced variations in the resistance of said semiconductor resistor element, with particular, but by no means exclusive, reference to RC oscillators.
  • Semiconductor devices such as silicon chips can be placed under stress during use or as a consequence of the manufacturing process.
  • packaging of a silicon chip can create stress therein in a manner which is hard to predict in terms of both its magnitude and direction.
  • the stress is determined by the nature of the package, lead frames, curing materials, curing temperatures, and many other factors. This stress produces strain of the silicon die, and changes in the stress can cause resistors to change value in comparison to their values before the change in stress was applied. Changes in the stress and associated strain can also be caused by other means, such as temperature changes, mechanical means such as mounting the silicon chip on a printed circuit board, or by slow changes in the nature of the packaging materials.
  • a particular example of a semiconductor device which may be realised on an integrated circuit is an electronic oscillator such as an RC oscillator.
  • an electronic oscillator such as an RC oscillator.
  • a packaged RC oscillator will shift in frequency when the silicon chip is stressed, irrespective of whether it was precisely calibrated prior to stressing of the silicon chip.
  • this calibration process may be performed during or shortly after the manufacturing process, for example at wafer probe.
  • a temperature sweep at this time in order to calibrate the response of the device with respect to temperature so that subsequent temperature dependent variations can be removed.
  • these known calibration procedures do not account for subsequent changes in the RC product caused by changes in the stress induced by the packaging of the silicon chip.
  • Package-induced stress is not easy to fully predict, and the present invention is predicated upon the basis that compensation of package stress requires a system for monitoring the package stress or its effects prior to making an appropriate compensation.
  • strain gauges for mechanical measurement of stress induced strains, but typically these devices rely on an unstrained, reference component which is compared to one or more components which are strained.
  • a known reference quantity such as voltage or current may be used to measure the strain gauge properties. This represents a major obstacle to implementation on a silicon die, because all of the components on the die are stressed to some degree, and there is no ideal reference component or quantity.
  • the present invention in at least some of its embodiments, addresses the above described problems and needs.
  • the present invention provides methods and apparatus for compensating for stress induced variations in an RC oscillator.
  • the invention can be applied more generally to the compensation of stress induced variations in the resistance of semiconductor resistor elements which are used for other purposes.
  • the present invention can be used in connection with band gap reference systems, piezo- resistive devices, sensors, or other semiconductor devices requiring a fine control of resistance.
  • a method of compensating for stress induced variations in the resistance of a semiconductor resistor element including the steps of:
  • the semiconductor resistor element includes the semiconductor resistor element and a reference arrangement, in which the reference arrangement includes a metallic reference resistor and a semiconductor reference resistor;
  • the invention exploits the different sensitivities to stress exhibited by metallic and semiconductor materials to determine and quantify resistance changes which are induced by stress.
  • the semiconductor resistor element and the semiconductor reference resistor are formed from the same semiconductor material.
  • at least the semiconductor reference resistor and, optionally, the metallic reference resistor are located close to the location of the semiconductor resistor element.
  • the compensation parameter is generated by measuring a first ratio of the resistances of the metallic reference resistor and the semiconductor reference resistor.
  • the compensation parameter is generated by comparing the first ratio to a second, reference ratio of the resistances of the metallic reference resistor and the semiconductor reference resistor which is determined under reference conditions.
  • the second, reference ratio is determined at or shortly after the time of manufacture, such as at the time of wafer probe. This may be performed as part of a larger calibration process which may include a temperature dependence calibration.
  • the compensation parameter is generated by obtaining a ratio of the first ratio to the second ratio, or a quantity functionally related thereto.
  • the step of generating a compensation parameter includes a temperature compensation step for compensating for temperature induced variations in the measured resistances of the metallic reference resistor and the semiconductor reference resistor.
  • the temperature compensation step is performed with reference to a database or a mathematical model of metallic resistor and semiconductor reference resistor resistances as a function of temperature.
  • a temperature calibration procedure is performed, and the temperature dependence of the ratio of the resistances of the metallic reference resistor and the semiconductor reference resistor (or at least one quantity functionally related thereto) is determined by curve-fitting.
  • the step of generating the compensation parameter may include correcting for a ratio of the gauge factors of the metallic reference resistor and the semiconductor reference resistor.
  • the correction factor is derived from the relationship
  • RR AS is the first ratio
  • RR is the second ratio
  • G S is the gauge factor of the semiconductor material in the semiconductor reference resistor
  • G M is the gauge factor of the metallic material in the metallic reference resistor
  • AS S is the change in strain experienced by the semiconductor reference resistor
  • AS M is the change in strain experienced by the metallic reference resistor
  • G M /Gs and ASM ASS can be ignored.
  • GM/G s may be accounted for.
  • the correction factor may derived from the relationship
  • the metallic reference resistor and the semiconductor reference resistor are connected in series. This arrangement permits convenient measurement of the ratio of the resistances of these elements. However, other arrangements and associated measurement methodologies may be implemented.
  • the semiconductor resistor element forms part of an RC oscillator
  • the step of using the compensation parameter includes using the compensation parameter as an indication of the stress induced variation in the resistance of the semiconductor resistance element, and adjusting the RC oscillator to achieve a desired output frequency, taking account of said indication of the stress induced variation.
  • the compensation parameter may be used in any suitable manner to compensate for stress induced variations in the resistance of one or more semiconductor resistor elements used in many other applications.
  • an apparatus for compensating for stress induced variations in the resistance of a semiconductor resistor element including:
  • a semiconductor device which includes the semiconductor resistor element and a reference arrangement, in which the reference arrangement includes a metallic reference resistor and a semiconductor reference resistor; a compensation parameter generator including a measurement arrangement for measuring stress induced changes in the resistance of the metallic reference resistor and the semiconductor reference resistor, or at least one quantity functionally related thereto, in which the compensation parameter generator generates a compensation parameter from the stress induced changes measured by the measurement arrangement; and
  • a compensator which uses the compensation parameter to compensate for stress induced variations in the resistance of the semiconductor resistor element.
  • the semiconductor device is an integrated circuit.
  • the metallic reference resistor may be formed by connecting a plurality of vias on the integrated circuit.
  • the vias may be connected in series, although other arrangements might be utilised.
  • the metallic reference resistor may be formed from tungsten or an alloy of tungsten.
  • Tungsten has the advantages of possessing a low gauge factor, and also a lower modulus of elasticity than many semiconductor materials such as polysilicon, so that the strain induced by stress is lower than such semiconductor materials, and therefore the second term inside the brackets of equation (1) is smaller.
  • the metallic reference resistor is formed from a plurality of connected tungsten vias on an integrated circuit.
  • the semiconductor reference resistor may be formed from any suitable semiconductor material, such as polysilicon or doped silicon. Typically, the semiconductor reference resistor and the semiconductor resistor element are formed from the same semiconductor material.
  • the semiconductor device includes an RC oscillator, and a semiconductor resistor element forms part of said RC oscillator.
  • the compensator may use the compensation parameter as an indication of the stress induced variation in the resistance of the semiconductor resistor elements, and adjust the RC oscillator to achieve a desired output frequency taking account of said indication of the stress induced variation.
  • the compensation parameter generator may include a temperature compensator for compensating for temperature induced variations in the measured resistances of the metallic reference sensor and the semiconductor reference resistor.
  • the temperature compensator may include a database of metallic reference resistor and semiconductor reference resistor resistances as a function of temperature, or be configured to utilise a mathematical model of metallic reference resistor and semiconductor reference resistor resistances as a function of temperature, and may further include a temperature measurement device for measuring a temperature and a comparator for comparing resistances measured by the measurement arrangement with the database or mathematical model using the temperature measured by the temperature measurement device as a reference datum for the database or mathematical model.
  • Figure 1 is a schematic diagram of an integrated circuit of the invention
  • Figure 2 shows a three dimensional element (a) without an applied axial stress and (b) with an applied axial stress;
  • FIG. 3 shows a reference arrangement of the invention
  • Figure 4 is a cross sectional view of a portion of an integrated circuit of the invention, showing a via.
  • FIG 1 is a schematic diagram of an integrated circuit 10 of the invention comprising a programmable RC oscillator 12, a control arrangement 14 for the RC oscillator 12, a compensation parameter generator 16 and a temperature sensor 18.
  • the compensator parameter generator 16 comprises a measurement arrangement 16a and a compensation parameter calculator 16b.
  • the measurement arrangement 16a includes a metallic reference resistor and a semiconductor reference resistor (not shown in Figure 1).
  • the programmable RC oscillator 12 comprises a plurality of capacitors and resistors which can be interconnected so as to provide an output signal of a desired frequency which is determined essentially by the RC product. The arrangement of the capacitors and the resistors in the RC oscillator is controlled by the control arrangement 12.
  • the resistors in the programmable RC oscillator 12, and the metallic reference resistor and the semiconductor reference resistor in the measurement arrangement 16a are all located on the integrated circuit 10, and therefore are subjected to substantially identical stresses.
  • at least the semiconductor reference resistor is physically located on the integrated circuit close to the location of the resistors in the RC oscillator 12.
  • the compensation parameter calculator 16b utilises measurements of the ratio of the metallic reference resistor and the semiconductor reference resistor in the measurement arrangement 16a to derive a compensation parameter which is indicative of changes in resistance which are induced by a stress that the integrated circuit is subjected to.
  • the present invention exploits the different sensitivities to stress exhibited by metallic and semiconductor materials. This can be understood and quantified in terms of the gauge factor of a material.
  • the gauge factor arises from the geometric deformation of three dimensional solids when they are subjected to a stress. A change in the applied stress leads to a strain of AL/L which in turns leads to a change in the sectional area of a physical solid which is defined by Poisson's ratio v where,
  • the stretch of the material can be expressed volumetrically as,
  • the strain causes the geometries of resistor elements to change.
  • a solid with a Poisson's ratio 0.5 will maintain a constant volume under varying stress conditions, but will show a change in shape.
  • Figure 2a shows an element 20 in perspective and cross sectional view before a change in the axial stress
  • Figure 2b shows the element 20 in perspective and cross sectional view after the change in axial stress leading to an axial strain.
  • the axial strain causes the element to increase in length, but to decrease in cross sectional area.
  • a metal resistor which is strained to be 1% longer also has a 1% smaller sectional area, and hence shows approximately a 2% resistance change for a 1 % strain.
  • Most metals have a gauge factor close to 2, because these materials retain a fairly constant volume under strain but show no other significant resistance altering effects under relatively small stresses.
  • semiconductor materials such as polysilicon have a higher gauge factor. This is because, in addition to causing changes in length and cross sectional area, strain of these materials also causes changes in the number of minority carriers and carrier mobility within the semiconductor material.
  • the gauge factor of polysilicon is approximately 20.
  • the invention exploits the different gauge factors of metals and semiconductor materials by comparing the behaviour of a semiconductor reference resistor with the behaviour of a metal reference resistor. Because the resistance of the metal resistor is less affected by strain in comparison to the semiconductor resistor, it is possible from a differential analysis of the resistances of the metallic reference resistor and the semiconductor reference resistor to obtain a variation in resistance which can be ascribed to the influence of strain. In an ideal system, one of the reference resistors would have a gauge factor of zero, and therefore would act as a strain insensitive reference. The present invention recognises that this ideal reference resistor does not exist, but also recognises that excellent compensation can be achieved using the differential resistor arrangement.
  • FIG 3 shows a possible arrangement of the metallic reference resistor 30 and the semiconductor reference resistor 32 in the measurement arrangement 16a of Figure 1.
  • the metallic reference resistor 30 and the semiconductor reference resistor 32 are placed in series. If a suitable supply current is fed to the resistors 30, 32, then the voltage ratio V1/V2 can be readily measured, where Vi is the voltage across the semiconductor reference resistor 32 and V 2 is the voltage across the metallic reference resistor 30.
  • This voltage ratio represents the ratio of the resistances of the resistors 32, 30, and is independent of the supply current.
  • This method of interrogating the reference resistors is convenient, but the skilled reader will appreciate that many other comparison methods exist using techniques which are well known in the art. For example, the resistors might be connected in parallel, being fed identical currents provided by a current-mirror circuit.
  • the voltage ratio might be measured by using one voltage as the reference level and the other the input level for an analogue-to-digital converter. Other suitable techniques will be apparent to those skilled in the art.
  • fi(T) and f 2 (T) describe the temperature dependence of the individual resistances
  • RR(T) describes the temperature dependency of the resistor ratio.
  • the temperature dependence of the resistor ratio can be determined in a number of ways. For example, the temperature dependent behaviour of the resistors or a direct measurement of the resistor ratio can be determined prior to packaging of the integrated circuits. Typically, the RC oscillator is calibrated prior to packaging of the integrated circuit, and conveniently the temperature dependence of the resistor ratio can be determined at or around this time. Curve fitting may be performed in order to establish the relationship.
  • the temperature coefficient of the metal is greater than the semiconductor material, and accordingly it may be desirable to ensure that the value of R sem i is much greater than the value of R me tai, so that the temperature induced changes in resistance are of similar magnitude and the stress-induced change in R se mi is not swamped by the temperature induced change in Rmetai-
  • Equation (2) can be used to derive a compensation parameter for stress induced resistance changes with varying degrees of approximation.
  • the first term in the denominator of equation 2 might be ignored completely, since it is known that the change in metal resistance will be much less than the change in semiconductor resistance, and hence k will be very small.
  • higher accuracy can be obtained if the ratio of the gauge factors of the metal and semiconductor materials are known, or may be determined. For example, as stated above, the ratio G M /G S for a metal/polysilicon combination is known to be about 0.1. If it is assumed that the applied stress produces similar levels of strain in the metal and semiconductor reference resistors (i.e, AS S ⁇ ASM), then k can be approximated by 0.1 .
  • the value may be transmitted from the compensation parameter calculator 16b to the control arrangement 14 for the programmable RC oscillator.
  • the control arrangement 14 receives the value 5R S , and uses the value in order to ensure that the RC oscillator produces a desired frequency output.
  • the control arrangement 14 can control the operation of the programmable RC oscillator 2 in response to the received value in a number of ways which would readily occur to one skilled in the art. For example, the control arrangement 14 may ensure that a different combination of resistors and capacitors and/or a different interconnection scheme is used in comparison to a situation where no stress induced variation in the resistance is detected. Additionally, or alternatively, a dithering scheme might be implemented in order to fine tune the frequency of the signal outputted by the programmable oscillator 12.
  • Various metals may be used to produce the metallic reference resistor.
  • the resistance of the metal chosen exhibits a low sensitivity to stress, and has a temperature dependence which is close to that of the semiconductor material used in the semiconductor reference resistor.
  • a metal which might be used is tungsten, particularly, but not exclusively, when the semiconductor reference resistor is formed from polysilicon.
  • Advantages include a low gauge factor and a lower modulus of elasticity than polysilicon (the modulus of elasticity is approximately one third that of polysilicon), so that the strain induced by a common stress is lower. This has the effect that the term k in the denominator of equation 2 is smaller, and consequently errors in the value of this term will have less impact on the calculated change in semiconductor resistance.
  • the metallic reference resistor may be formed in a variety of ways. Many standard silicon wafers offer metal resistors with a typical sheet resistance of the order of 100 ⁇ per square. Metallic reference resistors may be fabricated using these standard metal resistors, although the resistances associated with such structures are likely to be less than preferable for many applications. Silicon wafers having metal resistors with a larger sheet resistance might be advantageously employed. In an alternative approach, a novel use of via structures is proposed. Many standard silicon wafers have via structures, which are small posts of conductive material filled into a hole between insulating layers, such that conductive layers above and below the via are electrically connected.
  • Figure 4 shows a cross sectional view of a portion of an integrated circuit which depicts a first insulating layer 40 having a second insulating layer 42 formed thereon. Adjacent to the first insulating layer 40 is a conductive layer 44, and a further conductive layer 46 is formed on top of the second insulating layer 42.
  • Figure 4 shows a via structure 48 which is positioned in an aperture formed in the second insulating layer 42. It can be seen that the via 48, which is formed from a metallic material, electrically connects the conductive layers 44, 46. Various materials can be used to form the via 48, but it is commonly formed with tungsten.
  • the present inventors have realised that a plurality of vias can be connected together to form the metallic reference resistor in a convenient manner which can be easily integrated into the design as standard silicon wafers.
  • the reference metallic resistor can be conveniently formed by an arrangement of a plurality of vias in series. It is particularly preferred that an arrangement of tungsten vias is used for this purpose, owing to the advantageous properties of tungsten discussed above, and also because each tungsten via resistance is typically about 5 ⁇ , and therefore a metallic reference resistor having a usable resistance (for example, about a few ⁇ ) is readily manufactured using standard silicon wafers.
  • a metallic reference resistor having a usable resistance for example, about a few ⁇

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

L'invention concerne un procédé de compensation de variations, induites par une contrainte, dans la valeur de résistance d'un élément résistant semi-conducteur, le procédé comprenant les étapes suivantes : fournir un dispositif semi-conducteur qui comprend l'élément résistant semi-conducteur et un agencement de référence, l'agencement de référence comprenant une résistance métallique de référence (30) et une résistance semi-conductrice de référence (32); produire un paramètre de compensation par mesure de changements, induits par la contrainte, dans les valeurs de résistance de la résistance métallique de référence et de la résistance semi-conductrice de référence, ou au moins une quantité qui y est liée fonctionnellement; et utiliser le paramètre de compensation pour compenser des variations, induites par la contrainte, dans la valeur de résistance de l'élément résistant semi-conducteur.
PCT/GB2011/051434 2010-07-28 2011-07-27 Compensation de variation de résistance induites par une contrainte WO2012013977A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP11754462.7A EP2599119A1 (fr) 2010-07-28 2011-07-27 Compensation de variation de résistance induites par une contrainte
JP2013521220A JP2013535832A (ja) 2010-07-28 2011-07-27 応力起因抵抗値変動に対する補償
CN201180046664.6A CN103125021A (zh) 2010-07-28 2011-07-27 应力诱导电阻变化的补偿

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB201012656A GB201012656D0 (en) 2010-07-28 2010-07-28 Compensation for stress induced resistance variations
GB1012656.3 2010-07-28

Publications (1)

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WO2012013977A1 true WO2012013977A1 (fr) 2012-02-02

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PCT/GB2011/051434 WO2012013977A1 (fr) 2010-07-28 2011-07-27 Compensation de variation de résistance induites par une contrainte

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EP (1) EP2599119A1 (fr)
JP (1) JP2013535832A (fr)
CN (1) CN103125021A (fr)
GB (1) GB201012656D0 (fr)
WO (1) WO2012013977A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2993983A1 (fr) * 2012-07-30 2014-01-31 St Microelectronics Rousset Procede de compensation d'effets de contraintes mecaniques dans un microcircuit
US20160241186A1 (en) * 2015-02-13 2016-08-18 Infineon Technologies Ag Stress compensated oscillator circuitry and integrated circuit using the same
WO2016135071A1 (fr) 2015-02-23 2016-09-01 Universität Wien Composé pour la préparation de polypeptides
US20170261567A1 (en) * 2016-03-10 2017-09-14 Allegro Microsystems, Llc Electronic circuit for compensating a sensitivity drift of a hall effect element due to stress
IT201600077188A1 (it) * 2016-07-22 2018-01-22 St Microelectronics Srl Procedimento per compensare effetti di stress di substrato in dispositivi a semiconduttore e corrispondente dispositivo
US10162017B2 (en) 2016-07-12 2018-12-25 Allegro Microsystems, Llc Systems and methods for reducing high order hall plate sensitivity temperature coefficients
US10520559B2 (en) 2017-08-14 2019-12-31 Allegro Microsystems, Llc Arrangements for Hall effect elements and vertical epi resistors upon a substrate

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JP6080497B2 (ja) * 2012-10-31 2017-02-15 ルネサスエレクトロニクス株式会社 抵抗補正回路、抵抗補正方法、及び半導体装置
CN106960067B (zh) * 2016-01-08 2021-11-12 中兴通讯股份有限公司 一种电子装置、应力敏感参数的补偿方法和系统
CN112838023B (zh) * 2019-11-25 2022-12-16 中芯国际集成电路制造（天津）有限公司 一种半导体制造设备的补偿调节方法、装置及系统
CN114141461B (zh) * 2021-10-25 2022-08-05 深圳技术大学 基于飞秒激光的柔性电子器件制备方法及柔性应变传感器
CN114114091B (zh) * 2021-11-24 2023-08-08 苏州纳芯微电子股份有限公司 应力补偿电路及磁场感测系统

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US20040036545A1 (en) * 2002-08-20 2004-02-26 Samsung Electronics Co., Ltd. Power supply voltage and temperature-independent RC oscillator using controllable schmitt trigger
US20050162160A1 (en) * 2004-01-26 2005-07-28 Infineon Technologies Ag Concept of compensating for piezo influences on integrated circuitry
US20070018655A1 (en) * 2005-06-24 2007-01-25 Udo Ausserlechner Concept for Compensating Piezo-Influences on an Integrated Semiconductor Circuit

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JPS5477082A (en) * 1977-12-02 1979-06-20 Hitachi Ltd Semiconductor displacement transducer
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US20040036545A1 (en) * 2002-08-20 2004-02-26 Samsung Electronics Co., Ltd. Power supply voltage and temperature-independent RC oscillator using controllable schmitt trigger
US20050162160A1 (en) * 2004-01-26 2005-07-28 Infineon Technologies Ag Concept of compensating for piezo influences on integrated circuitry
US20070018655A1 (en) * 2005-06-24 2007-01-25 Udo Ausserlechner Concept for Compensating Piezo-Influences on an Integrated Semiconductor Circuit

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2993983A1 (fr) * 2012-07-30 2014-01-31 St Microelectronics Rousset Procede de compensation d'effets de contraintes mecaniques dans un microcircuit
US9127994B2 (en) 2012-07-30 2015-09-08 Stmicroelectronics (Rousset) Sas Method of compensating for effects of mechanical stresses in a microcircuit
US20160241186A1 (en) * 2015-02-13 2016-08-18 Infineon Technologies Ag Stress compensated oscillator circuitry and integrated circuit using the same
US10333463B2 (en) * 2015-02-13 2019-06-25 Infineon Technologies Ag Stress compensated oscillator circuitry and integrated circuit using the same
WO2016135071A1 (fr) 2015-02-23 2016-09-01 Universität Wien Composé pour la préparation de polypeptides
US10107873B2 (en) * 2016-03-10 2018-10-23 Allegro Microsystems, Llc Electronic circuit for compensating a sensitivity drift of a hall effect element due to stress
US10254354B2 (en) 2016-03-10 2019-04-09 Allegro Microsystems, Llc Electronic circuit for compensating a sensitivity drift of a hall effect element due to stress
US20170261567A1 (en) * 2016-03-10 2017-09-14 Allegro Microsystems, Llc Electronic circuit for compensating a sensitivity drift of a hall effect element due to stress
US10162017B2 (en) 2016-07-12 2018-12-25 Allegro Microsystems, Llc Systems and methods for reducing high order hall plate sensitivity temperature coefficients
US10746818B2 (en) 2016-07-12 2020-08-18 Allegro Microsystems, Llc Systems and methods for reducing high order hall plate sensitivity temperature coefficients
IT201600077188A1 (it) * 2016-07-22 2018-01-22 St Microelectronics Srl Procedimento per compensare effetti di stress di substrato in dispositivi a semiconduttore e corrispondente dispositivo
US10250233B2 (en) 2016-07-22 2019-04-02 Stmicroelectronics S.R.L. Method for compensating effects of substrate stresses in semiconductor devices, and corresponding device
US10520559B2 (en) 2017-08-14 2019-12-31 Allegro Microsystems, Llc Arrangements for Hall effect elements and vertical epi resistors upon a substrate

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JP2013535832A (ja) 2013-09-12
GB201012656D0 (en) 2010-09-15
CN103125021A (zh) 2013-05-29
EP2599119A1 (fr) 2013-06-05

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