WO2012009998A1

WO2012009998A1 - Llc series resonant converter and driving method thereof

Info

Publication number: WO2012009998A1
Application number: PCT/CN2011/073148
Authority: WO
Inventors: 范杰; 王静
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-07-23
Filing date: 2011-04-21
Publication date: 2012-01-26
Also published as: CN101895201A; CN101895201B

Abstract

An LLC series resonant converter includes: a bridge circuit which is coupled to an input voltage (Vin) and consists of at least two first switches (S1, S2), a resonant circuit which is coupled to the bridge circuit and driven by the first switches (S1, S2), a transformer (Tx) coupled to the resonant circuit, and a rectification circuit (60) which comprises two sub-driving circuits (601, 602). The two sub-driving circuits (601, 602) respectively include: a second switch (Q1, Q2) which is coupled to the two terminals of the secondary winding of the transformer (Tx) and provides the voltage output (Vo) of the LLC series resonant converter, a turn-off circuit which provides the second switch (Q1, Q2) with a turn-off signal (V_COM1, V_COM2) and comprises a current transformer (CT1, CT2), and a pulse width processor (610) for generating a turn-on signal (V_pulse1, V_pulse2) and providing the turn-on signal for the second switch (Q1, Q2) after reducing the duty ratio of the transformer primary power switch driving signal (V_g,s1, V_g,s2) of the control terminal of the first switch (S1, S2). The current transformer (CT1, CT2) is serially connected between the secondary winding of the transformer (Tx) and the second switch (Q1, Q2) and measures the current flowing through the source-drain electrode branch of the second switch (Q1, Q2) to generate the turn-off signal (V_COM1, V_COM2).

Description

TECHNICAL FIELD The present invention relates to the field of communications, and in particular to an LLC series resonant converter and a driving method thereof. BACKGROUND OF THE INVENTION FIG. 1 is a circuit diagram of a related art LLC series resonant converter composed of a synchronous rectification transistor, as shown in FIG. 1, wherein an inductor-inductor-capacitor (LLC) series resonant converter (Series-Parallel Resonance) The circuit, abbreviated as SPRC, 100 is mainly composed of a bridge circuit 110, a resonance circuit 120, and a rectifier circuit 130. The bridge circuit 110 uses a symmetrical half-bridge control method, and the upper and lower tubes are complementarily turned on, and the duty ratio is 50%; the resonant circuit 120 is composed of a resonant capacitor Cr, a resonant inductor Lr, and a magnetizing inductance Lm to form a resonant body, and Lr can be used as a leakage of the transformer. The sense circuit is composed of a pair of synchronous rectification transistors Q1 and Q2 connected to the output capacitor Co. The converter 100 is a converter having a double resonance point. When Lr, Cr participates in resonance only, the high-frequency resonance point fr is generated, and Lm does not participate in resonance. When the secondary current drops to zero, Lm and Lr, Cr participate in resonance in series, and the resonant current frequency is fin. The two resonance points are calculated as follows:

Since the bridge circuit 110 of the LLC series resonant converter is configured to control the output voltage by means of frequency modulation, the frequency modulation controller 140 is also required. According to the DC gain characteristics of the converter, the LLC series resonant converter can work not only in the frequency range of fs>fr and fs=fr, but also in the frequency range of fin<fs<fr, and fs is the LLC series resonance. The operating frequency of the converter, fin is the low frequency resonance point of the LLC series resonant converter, and fr is the high frequency resonance point of the LLC series resonant converter. 2 is a schematic diagram showing the voltage and current waveforms of the main components of the prior art LLC series resonant converter operating in the fin<fs<fr region. Where _&81 and _§ , ₈₂ are the gate drive signals of the two FETs S1 and S2 in the bridge circuit 110, respectively, i _r , respectively the resonant inductor Lr and the magnetizing inductance The current of Lm, i _Q1 , i _Q2 and Vg, _SR1 , Vg, _S R2 are the current waveform and the driving voltage waveform of the two synchronous rectifying transistors Q1 and Q2 in the rectifying circuit 130, respectively. At time to, the resonant current i _r increases inversely from zero, the field effect transistor S 1 begins to conduct forward, the primary side of the transformer is clamped, and the field current changes linearly. The resonant current i _r flows through S 1 and gradually rises in a sinusoidal form. i _r flows through Lm and the primary side of the transformer, transfers energy to the secondary side of the transformer, and outputs Vo. When the resonant current i _r and the exciting current i _m are equal, the current at the output is zero, that is, at time 11, the phase ends. At time t1, the resonant current i _r and the exciting current i _m are equal, and at this time, the two synchronous rectifying transistors Q1 and Q2 on the secondary side are both in an off state, and the output voltage Vo is supplied from the output capacitor Co. At the same time, the output voltage is no longer clamped to the primary side of the transformer, and the magnetizing inductance Lm begins to participate in resonance, forming a series resonance with Lr and Cr. The period of this resonance is much larger than the period of resonance of Lr and Cr, and the slope of the resonant current is much smaller, so the primary current can be approximately constant during this process. Since the resonant current i _r has dropped to equal the exciting current i _m before the synchronous rectifying transistor Q1 is turned off, the synchronous rectifying transistor Q1 should be turned off at time t1. At time t2, FETs S1 and S2 are turned off and enter dead time. The resonant current i _r charges the parasitic capacitance of S1 and the parasitic capacitance of S2 discharges. At this time, the output voltage clamps the primary side of the transformer, and the magnetizing inductance Lm is discharged at a constant voltage. After the parasitic capacitance of S2 is discharged, the diode of S2 is turned on, and the field effect transistor S2 is turned on under the condition of Zero Voltage Switching (ZVS). The same working process can be analyzed in the time interval of t3 < t < t4 and t4 < t < t5. The same operating state and current waveform i _Q2 as the synchronous rectification transistor Q1 also occurs on the synchronous rectification transistor Q2, and current 1 ₍₂₁ and i _Q2 constitute the output rectified current i _rec . Because at t1 to t2 and t4 to t5, synchronization rectification transistor Q1 or Q2 the current decreases to zero, and all occurred in the FETs S1 or pre-S2 is turned off, so that their wave guide width TONGMAI Vg, _Q1, Vg, Q ₂ than the small FET S1 and S2. It can be seen from the above analysis that when the LLC series resonant converter 100 operates below the resonant frequency, the drive pulse of the synchronous rectification FET must be turned off when its reverse current from the source to the drain drops to zero. That is, i _ree must be zero during the dead time. Otherwise, the converter operates in the dead time, and there may be a phenomenon that the secondary side energy is recharged to the primary side, causing the circuit to malfunction. Therefore, in order to avoid synchronous rectification If the FET is malfunctioning, the synchronous rectification drive signals V _g , _Q1 , Vg , Q ₂ must refer to the corresponding half bridge FET control signals V _{& S1} , Vg , _S2 , and Vg , _sl , Vg , _S2 behind or Cut in advance This ensures that the circuit can block the secondary side energy back to the primary side during the dead time by using the body diode inside the synchronous rectification transistor. 3 is a waveform timing diagram of a prior art LLC series resonant converter in a state where a switching frequency is greater than or equal to a resonant frequency, as shown in FIG. 3, when operating at a resonance frequency fs, the original of the LLC series resonant converter The side switch tube can realize zero voltage switch (ZVS) under any load, but the transformer magnetizing inductance Lm is clamped by the output voltage and does not participate in the whole resonance process. Therefore, the current on the secondary side synchronous rectifier of the transformer is continuous. At this time, the output rectified current i _rec is a quasi-sinusoidal absolute value waveform which is synchronized with the driving permanent waves of the synchronous rectifying transistors Q1 and Q2. At the same time, when the LLC series resonant converter operates above the resonant frequency, there is no dead zone in the above i _rec , and the driving signals of the synchronous rectifying transistors Q1 and Q2 can be simply obtained by using the driving signals of the primary side FETs S1 and S2. Please refer to FIG. 4 , which is a circuit diagram of a synchronous rectification driving method of a prior art LLC series resonant converter. Compared with FIG. 1 , the LLC series resonant converter 400 is provided with two reference voltages and two comparators. And 2 with the door. In FIG. 4, when the synchronous rectification transistor Q2 flows a current from the source to the drain, a channel resistance voltage drop is generated in its channel resistance. Therefore, when the operating frequency of the resonant converter 400 is less than the resonant frequency, the channel resistance voltage drop V _ds ( _.n ) is compared by the comparator 410 and the reference voltage V _ref to generate the pulse wave signal _Ve . _m . V _e . _{The m} signal and the drive signal V _g , _{s2 of the} FET S2 are processed by the AND gate 420 to obtain a drive signal of the synchronous rectification transistor Q2. When the operating frequency of the resonant converter 400 is greater than the resonant frequency, the synchronous rectifying transistors Q1 and Q2 of the rectifying circuit are driven by the same signals for driving the FETs S1, S2, respectively. The scheme of Fig. 4 can adaptively obtain the driving pulse wave of the synchronous rectification transistor. However, since the voltage amplitude of ^(.„) is 4艮, in order to achieve the best synchronous rectification drive effect, the reference voltage value V _ref must be very low, which is easily affected by the disturbance. Especially when the LLC circuit works below When the resonant frequency is connected to a light load, if V _ds (. _n ) oscillates or is disturbed, the output pulse signal V _c . _{m of the} comparator 410 will cause an error signal. If the error signal is bad, it will cause The phenomenon that the synchronous rectification transistor is commonly short-circuited. Therefore, the scheme has poor anti-interference capability. Referring to FIG. 5, it is a circuit diagram of another synchronous rectification driving method of the prior art LLC series resonant converter, compared with FIG. The LLC series resonant converter 500 is equipped with two synchronous circuits (Syn) 510, two constant pulse width generators (ie, Forced Oscillation Technique, referred to as FOT) 520, and two OR gates 530. In 5, when the synchronous rectification transistor Q2 flows through the current from the source to the drain, a voltage drop is generated in its channel resistance, and the voltage drop V _ds (. _n ) passes through the comparator and the reference voltage V _ref . 410 Comparing the generated pulse signal V _c. _M. When the operating frequency of the resonant converter 500 is less than the resonant frequency and the resonant converter 500 is connected to a light load, since the voltage drop V _ds ( _.n ) is small and the comparison signal is not easily obtained, the synchronous circuit 510 and the fixed pulse width are generated. The 520 generates a constant pulse width signal V _FOT , which is determined by the resonance parameters Lr, Cr, and the rising edge of the pulse wave is synchronized with the signal V _SYN through the synchronization circuit 510. Constant pulse width signal V _FOT and pulse wave signal V _e . 530 _m through the OR gate after treatment, then the FET driving signal S2 V _g, _s2 After treatment with the gate drive signal 420 synchronous rectification transistor Q2 is obtained. When the operating frequency of the resonant converter 500 is less than the resonant frequency and the resonant converter 500 is connected to the heavy load, the channel resistance voltage V _ds (. _n ) for the synchronous rectifying transistors Q1 and Q2 is compared with the reference voltage V _ref . The pulse wave signal V _e generated after comparison is performed on the device 410. _{m is} used to drive the synchronous rectification transistors Q1 and Q2 of the rectifier circuit. Finally, when the operating frequency of the resonant converter 500 is greater than the resonant frequency, the synchronous rectifying transistors Q1 and Q2 of the rectifying circuit are driven by the same signals for driving the FETs S1, S2, respectively. The scheme of FIG. 5 is based on the scheme of FIG. 4, and the synchronous rectification driving device of the LLC series resonant converter at the time of light load is added, that is, when the operating frequency is less than the resonant frequency and the converter is connected to the light load, the resonance of the resonant circuit is utilized. The parameter drives the synchronous rectification transistor to determine a constant pulse width signal. However, the output rectification current of the resonant converter is intermittent at light load. When the period of the synchronous rectification transistor flowing through the current is shorter than the resonance period, since the driving pulse of the synchronous rectification transistor is determined by the resonance period, the current is decreased. When the drive pulse reaches zero, the drive pulse is still not turned off. At this time, the inverter will have current backflow, that is, the secondary energy is returned to the primary side. Therefore, the reliability of the scheme at light loads is slim. SUMMARY OF THE INVENTION A primary object of the present invention is to provide an LLC series resonant converter and a driving method thereof to solve at least the above-mentioned problem of low reliability. According to an aspect of the present invention, an LLC series resonant converter is provided, comprising: a bridge circuit connected to an input voltage and composed of at least two first switches; and a resonant circuit coupled to the bridge circuit, The first switch is driven; a transformer is coupled to the resonant circuit; and a rectifier circuit includes two sub-driving circuits, each of which includes: a second switch coupled to both ends of the secondary side of the transformer, configured to provide LLC series resonance a voltage output of the converter; a shutdown circuit configured to provide a shutdown signal to the second switch, comprising a current transformer connected in series between the secondary side of the transformer and the two second switches, configured to measure the flow through a current of the source-drain branch of the second switch to generate a turn-off signal; a pulse width processor configured to reduce a duty cycle of a power switch drive signal of the transformer primary side of the control terminal of the first switch to obtain an open signal Provided to the second switch. According to another aspect of the present invention, a driving method of an LLC series resonant converter is provided. The LLC series resonant converter includes: a bridge circuit coupled to an input voltage and composed of at least two first switches; The circuit is coupled to the bridge circuit and is driven by the first switch; a transformer coupled to the resonant circuit; and a rectifier circuit including two sub-drive circuits, each comprising: a second switch coupled to the secondary side of the transformer Both ends are arranged to provide a voltage output of the LLC series resonant converter; a shutdown circuit is provided to provide a shutdown signal to the second switch, which includes a current transformer connected in series with the secondary side of the transformer and two Between the two switches, the current flowing through the source-drain branch of the second switch is measured to generate a turn-off signal; a pulse width processor is provided to reduce the primary power switch of the transformer at the control end of the first switch After the duty cycle of the signal, the turn-on signal is supplied to the second switch; the driving method includes: when the LLC series resonant converter operates in the entire work Within the frequency range to provide a second shutdown circuit switching off signal, processor provides pulse on signal to the second switch. The LLC series resonant converter of the present invention and the driving method thereof, because the current transformer is used to measure the current flowing through the source-drain branch of the second switch, so that the related art LLC series resonant converter achieves reliable current backflow. The problem of lower sex improves the reliability at light loads. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, In the drawings: FIG. 1 is a circuit diagram of a related art LLC series resonant converter composed of a synchronous rectification transistor; FIG. 2 is a prior art LLC series resonant converter operating in a fin<fs<fr region. FIG. 3 is a waveform timing diagram of a prior art LLC series resonant converter in a state where a switching frequency is greater than or equal to a resonant frequency; FIG. 4 is a prior art LLC series resonant converter FIG. 5 is a circuit diagram of a synchronous rectification driving scheme of another prior art LLC series resonant converter; 6 is a circuit diagram of a synchronous rectification driving scheme of an LLC series resonant converter according to an embodiment of the present invention; and FIG. 7 is a main waveform timing diagram of an embodiment of the LLC series resonant converter proposed by the present invention. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. 6 is a circuit diagram of a synchronous rectification driving scheme of the LLC series resonant converter 600 according to the present invention, comprising: a bridge circuit 110 coupled to an input voltage Vin, which is composed of two first switches SI, S2; The oscillating circuit 120 is connected to the bridge circuit 110 and is driven by the first switches S1, S2; a transformer TX is coupled to the resonant circuit 120; and a rectifying circuit 60 includes two sub-driving circuits 601, 602, respectively: A second switch Q1, or Q2, coupled to both ends of the secondary side of the transformer Tx, is configured to provide a voltage output Vo of the LLC series resonant converter; a shutdown circuit configured to provide a switch to the second switch Q1 or Q2 Break signal V _e . _m , comprising a current transformer CT1 , CT2 , connected in series between the secondary side of the transformer Tx and the two second switches Q1 or Q2 , configured to measure the source-drain branch flowing through the second switch Q1 or Q2 Current to generate a turn-off signal V _c . _m; a pulse processor 610, to provide a reduced set transformer primary side power switch signal v driving the control terminal of the first switch S1 or S2, _{_g,} _sl, v _g, the duty ratio _s2 to obtain _Pulse ON signal v Give the second switch Q1 or Q2. Method of driving the LLC series resonant converter comprising: when the LLC series resonant converter operation over the entire operating frequency range, the shutdown circuit to provide off signal V _c to the second switch Q1 or Q2. _m (for example, V _c . _ml and V _c . _{m2 in} FIG. 6), the pulse width processor 610 supplies an on signal V _pulse to the second switch Q1 or Q2 (eg, V _pulsel and V _{pulse2 in} FIG. 6 ). Preferably, the rising edge of the output signal of the pulse width processor is synchronized with the rising edge of the corresponding driving signals of the power switches S1, S2. Referring to the operating waveforms of the LLC series resonant converters in Figures 2 and 3, it can be seen that when the output rectified current i _rec has a dead zone, the on-time of each synchronous rectification transistor Q1 or Q2 is half of the LLC series resonant frequency. The period 1/( 2fs ) is only determined by the parameter values of Ls and Cs. When the input voltage or output voltage range changes, as long as fin<fs<fr, the on-time of each synchronous rectification transistor Q1 or Q2 does not change. What is changed is only the size of the dead zone in the output rectified current i _ree , that is, the width of the time interval t1 to t2 or t4 to t5. When fs ≥ fr, the output rectified current i _rec does not have a dead zone, so the on-time of the synchronous rectification transistor Q1 or Q2 corresponds to the on-time of the FETs S1 and S2, respectively. The LLC series resonant converter uses the current transformers CT1 and CT2 to measure the current flowing through the source-drain branches of the second switches Q1, Q2, so that the related art LLC series resonant converter current inrush is reliable. The problem of lower sex improves the reliability at light loads. Preferably, the bridge circuit 110 is a half bridge circuit or a full bridge circuit. Preferably, the resonant circuit 120 is composed of a resonant capacitor Cr, a resonant inductor Lr, and a magnetizing inductance Lm in series. Preferably, the resonant inductor is an independent external inductor Lr or a leakage inductance of the transformer Tx. These circuits are simple in structure and easy to implement. Preferably, as shown in FIG. 6, each of the shutdown circuits includes: a reference voltage source Vref, a current transformer CT1, CT2, a magnetic reset resistor R1, R3, a sample resistor R2, R4, and a diode D1. D2, a comparator 410, an OR gate 530, the primary input of the current transformers CT1, CT2 is connected to the input of the second switch Q1 or Q2, and the primary output is connected to the secondary side of the transformer Tx, the current transformer CT1, CT2 are connected with magnetic reset resistor R1 or R3 at both ends; magnetic reset resistors Rl, R3 are connected to the anode of diode D1 or D2 at one end, and the other end is grounded; parallel resistor R2 is connected between the cathode of diodes D1 and D2 and ground. Or R4; a reference voltage source Vref is connected in series between the first input terminal of the comparator 410 and the output terminal of the second switch Q1 or Q2, the second input terminal of the comparator 410 is connected to the negative electrode of the diode D1 or D2, and the comparator 410 is set to Comparing the voltage V _c outputted by the diode D1 or D2 with the voltage Vref output by the reference voltage source Vref generates a turn-off signal

Vcom, the pulse width processor 610 makes the duty ratio of the turn-on signal V _pulse equal to or smaller than the turn-off signal V _c . The duty cycle of _m ; the pulse between the first input of the OR gate 530 and the control terminal of the first switch S1 or S2 The wide processor 610, the second input of the OR gate 530 is coupled to the output of the comparator 410, and the output of the OR gate 530 is coupled to the control terminal of the second switch Q1 or Q2. Preferably, in the above LLC series resonant converter, the driving mode of the second switch Q1 (or Q2) is: when the LLC series resonant converter operates over the entire frequency range, the current transformer CT1 (or CT2) is The current signal is converted to a voltage signal by a sample resistor R2 (or R4), and is output as a voltage V _e via a diode D1 (or D2), and is compared with a voltage Vref of the reference voltage source Vref by a comparator 410 to generate a turn-off signal V _e . _m , turn off the signal V _e . _m and another turn-on signal V _pu i _{se are} processed by OR gate 530 to obtain a complete drive signal to drive second switch Q1 (or Q2). Although the present embodiment uses two OR logic gates 530 to implement adaptive control of the synchronous rectification drive signals, the implementation of the specific circuit is not limited to such logic gate structures, and any logic function that can implement this OR logic function. Circuit architecture is within the scope of the present invention. The rectifier circuit has a simple structure and is easy to implement. 7 and 8 are main waveform timing diagrams of an embodiment of the LLC series resonant converter proposed by the present invention. As shown in FIG. 7 and FIG. 8, the synchronous rectification driving timing operation diagram of the LLC series resonant converter of the present embodiment is between the frequency of fin and fr and the operating frequency is higher than fr. Wherein, the output signal V _{pulse of the} monthly Yongkuan processor and the output signal V _{c of the} comparator. _{The m-} phase or after obtains the synchronous rectification drive signals V _g , _Q1 , V _g , _Q1 . The turn-on of the drive signal is determined by the drive signal of the primary power switch, and the turn-off is determined by the output signal of the comparator. Preferably, the first switch S1 or S2 is a field effect transistor, and the second switch Q1 or Q2 is a field effect transistor. The input, output and control terminals of the first switch S1 (or S2) and the second switch Q1 (or Q2) are the drain, the source and the gate of the FET, respectively. FETs are low cost and easy to implement. From the above description, it can be seen that the LLC series resonant converter of the present invention and the driving method thereof have the advantages that the driving signal of the synchronous rectifier is completely synchronized with the current signal, the duty ratio is lost less, and the efficiency of the converter is improved. . At the same time, the transformer amplifies the current signal into a large voltage signal, which is not easily disturbed by the ground voltage peak, thereby effectively avoiding the pulse converter V _c at the light load. An error occurs in _m , which causes the switches in the synchronous rectification circuit to be driven incorrectly. Therefore, the scheme is more resistant to interference. In addition, the synchronous rectification driving method uses the output current of the converter to realize the driving control of the synchronous rectification transistor, which not only simplifies the design of the conventional driving circuit, but also effectively prevents the synchronous rectifier from passing through or output voltage backflow. Further improved reliability. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claims A LLC series resonant converter, including:

a bridge circuit (110) connected to the input voltage ( Vin ), consisting of at least two first switches (SI, S2);

a resonant circuit (120) coupled to the bridge circuit (110) and subjected to the first switch (SI, S2);

a transformer (TX) coupled to the resonant circuit (120);

A rectifier circuit (60) comprising two sub-drive circuits (601, 602), respectively comprising:

a second switch (Q1, Q2) coupled to both ends of the secondary side of the transformer (Tx), configured to provide a voltage output ( Vo ) of the LLC series resonant converter;

a shutdown circuit configured to provide a turn-off signal (V _com ) to the second switch (Q1, Q2), comprising a current transformer (CT1, CT2) coupled in series with the transformer (Tx) Between the edge and the two second switches (Q1, Q2), a current flowing through the source-drain branch of the second switch (Q1, Q2) is set to generate the turn-off signal (V) _e . _m ); a pulse width processor (610) arranged to reduce the primary power switch drive signal (V _g , _sl , V _g , _s2 ) of the transformer of the control terminal of the first switch (SI, S2) After the duty ratio, an open signal (V _pulse ) is supplied to the second switch (Q1, Q2). The LLC series resonant converter according to claim 1, wherein said bridge circuit (110) is a half bridge circuit or a full bridge circuit. The LLC series resonant converter according to claim 1, wherein said resonant circuit (120) is composed of a resonant capacitor (Cr), a resonant inductor (Lr), and a magnetizing inductance (Lm) connected in series. The LLC series resonant converter according to claim 3, wherein the resonant inductor is an independent external inductor (Lr) or a leakage inductance of the transformer (Tx). The LLC series resonant converter according to claim 1, wherein each of said shutdown circuits comprises: a reference voltage source (Vref), one of said current transformers (CT1, CT2), and a magnetic reset resistor (R1) , R3), a sample resistor (R2, R4), a diode (D1, D2), a comparator (410), an OR gate (530),

a primary side input end of the current transformer (CT1, CT2) is connected to an input end of the second switch (Q1, Q2), and a primary side output end is connected to a secondary side of the transformer (Tx), the current The magnetic reset resistors (R1, R3) are connected in parallel at both ends of the secondary side of the transformer (CT1, CT2);

One end of the magnetic reset resistor (R1, R3) is connected to the positive pole of the diode (D1, D2), and the other end is grounded;

The sample resistor (R2,) is connected in parallel between the cathode of the diode (D1, D2) and the ground.

R4);

The reference voltage source (Vref) is connected in series between the first input end of the comparator (410) and the output end of the second switch (Q1, Q2), and the second input end of the comparator (410) Connecting a cathode of the diode (D1, D2), the comparator (410) is configured to compare a voltage V _e output by the diode ( D1, D2 ) with a voltage Vref output by the reference voltage source (Vref) The turn-off signal (V _e . _m ), the pulse width processor ( 610 ) makes the duty ratio of the turn-on signal (V _pulse ) equal to or smaller than the turn-off signal (V _e . _m ) Air ratio

The first input end of the OR gate (530) and the control end of the first switch (SI, S2) are connected in series with the ^i wide processor (610), and the second of the OR gate (530) The input is connected to the output of the comparator (410), and the output of the OR gate (530) is connected to the control end of the second switch (Q1, Q2). The LLC series resonant converter according to claim 5, wherein said first switch (S1, S2) is a field effect transistor, and said second switch (Q1, Q2) is a field effect transistor. The LLC series resonant converter according to claim 6, wherein

The input end, the output end and the control end of the first switch (SI, S2) and the second switch (Q1, Q2) are respectively a drain, a source and a gate of the FET. A driving method of an LLC series resonant converter, the LLC series resonant converter comprising: a bridge circuit (110) connected to an input voltage (Vin), composed of at least two first switches (SI, S2); a resonant circuit (120) coupled to the bridge circuit (110), driven by the first switch (SI, S2); a transformer (TX) coupled to the resonant circuit (120); a rectifying circuit (60) comprising two sub-driving circuits (601, 602), respectively comprising: a second switch (Q1, Q2) coupled to both ends of the secondary side of the transformer (Tx), configured to Providing a voltage output ( Vo) of the LLC series resonant converter; a shutdown circuit configured to provide a turn-off signal (V _e . _m ) to the second switch (Q1, Q2), which includes a current transformer (CT1, CT2), connected in series between the secondary side of the transformer (Tx) and the two second switches (Q1, Q2), configured to measure the flow through the second switch (Ql, Q2) source - drain current branch to generate the shutdown signal (V _e _m.); - a pulse width processor (610) arranged to reduce the After the duty cycle of a switch (S1, S2) the control terminal of the transformer primary side power switch drive signal _{_{_{(V g, sl, V g}}} , s2) to obtain turn-on signal (V _pulse) is supplied to the second switch (Ql, , Q2); the driving method includes:

When the LLC series resonant converter operates over the entire operating frequency range, the shutdown circuit provides the turn-off signal (V _e . _m ) to the second switch (Q1, Q2), the pulse width processing The device (610) supplies the turn-on signal (V _pulse ) to the second switch (Q1, Q2). The driving method according to claim 8, wherein each of said shutdown circuits comprises: a reference voltage source (Vref), one of said current transformers (CT1, CT2), and one magnetic reset resistor (R1, R3) a sample resistor (R2, R4), a diode (D1, D2), a comparator (410), an OR gate (530), the primary input of the current transformer (CT1, CT2) is connected to The input end of the second switch (Q1, Q2) is connected to the secondary side of the transformer (Tx), and the magnetic transformer is connected in parallel with the secondary side of the current transformer (CT1, CT2) a resistor (R1, R3); one end of the magnetic reset resistor (R1, R3) is connected to the anode of the diode (D1, D2), and the other end is grounded; the cathode of the diode (D1, D2) is connected in parallel with the ground Said reference resistor (R2, R4); said reference voltage source (Vref) is connected in series between the first input of said comparator (410) and the output of said second switch (Q1, Q2) A second input of the comparator (410) is coupled to a cathode of the diode (D1, D2), and the comparator (410) is configured to Compared with the diode to generate the OFF signal (V _e. _M), the pulse width processor (610 after (Dl, D2) the output voltage (V _c) and the voltage of the reference voltage source (Vref) output a duty ratio of the turn-on signal (V _pulse ) equal to or less than a duty ratio of the turn-off signal (V _c . _m ); the OR gate ( 530 ) a pulse width processor (610) is connected in series between the first input terminal and the control terminal of the first switch (SI, S2), and the second input terminal of the OR gate (530) is connected to the comparator ( An output end of the OR gate (530) is connected to a control end of the second switch (Q1, Q2);

The driving mode of the second switch (Q1, Q2) is: when the LLC series resonant converter operates over the entire operating frequency range, the current signal of the current transformer (CT1, CT2) passes through the 釆The sample resistor (R2, R4) is converted into a voltage signal, which is output as a voltage (V _e ) via the diode (D1, D2), and the voltage of the reference voltage source (Vref) through the comparator (410) (Vref) Performing a comparison to generate the turn-off signal (V _e . _m ), the turn-off signal (V _c . _m ) and another of the turn-on signals (V _pulse ) passing through the OR gate

(530) After the processing, a complete driving signal is obtained to drive the second switch (Q1, Q2). The driving method according to claim 8, wherein the method further includes:

The second switch (Q1, Q2) is driven by the turn-on signal (V _pulse ) when the LLC series resonant converter operates over the entire operating frequency range.