WO2012001785A1 - 表示装置と表示装置の制御方法 - Google Patents
表示装置と表示装置の制御方法 Download PDFInfo
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- WO2012001785A1 WO2012001785A1 PCT/JP2010/061183 JP2010061183W WO2012001785A1 WO 2012001785 A1 WO2012001785 A1 WO 2012001785A1 JP 2010061183 W JP2010061183 W JP 2010061183W WO 2012001785 A1 WO2012001785 A1 WO 2012001785A1
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- booster circuit
- display
- driver
- control signal
- display device
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
- G06F1/3218—Monitoring of peripheral devices of display devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3265—Power saving in display device
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0469—Details of the physics of pixel operation
- G09G2300/0478—Details of the physics of pixel operation related to liquid crystal pixels
- G09G2300/0482—Use of memory effects in nematic liquid crystals
- G09G2300/0486—Cholesteric liquid crystals, including chiral-nematic liquid crystals, with transitions between focal conic, planar, and homeotropic states
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3622—Control of matrices with row and column drivers using a passive matrix
- G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3651—Control of matrices with row and column drivers using an active matrix using multistable liquid crystals, e.g. ferroelectric liquid crystals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to a display device using a memory type liquid crystal and a control method of the display device.
- the memory liquid crystal panel examples include a panel using cholesteric liquid crystal.
- Cholesteric liquid crystal has the characteristics of semi-permanent display retention, vivid color display, high contrast, and high resolution.
- the panel using the memory-type liquid crystal can maintain the drawn content without supplying power, except for the panel reset period for resetting the panel and the drawing period for drawing on the panel. There is no need to supply power. Therefore, a display device using a panel using a memory-type liquid crystal can keep power consumption low compared to a liquid crystal that always requires power during display.
- the panel reset period is a period for resetting a region to be rewritten in the display portion.
- the drawing period is a period for erasing previously drawn contents during operation of the display device and drawing new contents.
- a high voltage must be continuously applied to a driver that drives the panel during a panel reset period and a drawing period using a high-power booster circuit.
- a driver for driving the panel must ensure the maximum amount of current required by the panel during the panel reset period and the drawing period. Therefore, the conventional booster circuit must always supply the driver with the maximum amount of current required by the panel at high power during the panel reset period and the drawing period.
- a technique is known in which the battery voltage is precharged to a predetermined level before charging the boosting capacitor, thereby shortening the boosting time.
- a technique is known in which necessary and sufficient power is generated by varying the boosting operation according to the display state of a display device using a memory-type liquid crystal, thereby reducing the power consumption of the display device.
- the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a display device and a control method for the display device that suppress power for driving a memory liquid crystal.
- a display device including a display unit using a memory liquid crystal, which is one aspect of the present invention, a row driver that drives a scanning line of the display unit, and a column driver that drives a data line of the display unit, 1 booster circuit, a second booster circuit, and a control unit.
- the first booster circuit is a high-power booster circuit that outputs a current for driving the display unit, the row driver, and the column driver.
- the second booster circuit is a low power consumption booster circuit that outputs a voltage for holding the display of the display unit.
- the control unit refers to the timing at which each of the display data latch signal for determining the display data and the pulse polarity control signal for preventing deterioration of the liquid crystal, which controls the row driver and the column driver, change. Then, control is performed to switch to the first booster circuit at a preset timing before the timing at which the display data latch signal and the pulse polarity control signal change, and to switch to the second booster circuit after a preset period. .
- the power consumption of the display device can be suppressed.
- two boosting circuits of high power and low power are provided in a period in which high power is required and a period in which the power is low, based on a control signal input to a driver that drives a panel using memory liquid crystal.
- the switching of the two booster circuits is controlled so that the high output booster circuit is activated during periods when high power is required and the voltage is held by the low power booster circuit with low power consumption during other periods.
- FIG. 1 is a block diagram showing an embodiment of a display device.
- the display device 1 includes a charge control unit 2, a battery 3, a power supply unit 4, a peripheral circuit 5, a control unit 6, a recording unit 7, a driver control unit 8, a display unit 9, a row driver 10, a column driver 11, and a multi-voltage generation unit. 12, a capacitor 13 and the like. Further, the display device 1 includes a first booster circuit 14, a second booster circuit 15, rectifying elements 16 and 17, and an inverting element 20.
- the charging control unit 2 supplies power supplied from an external power source such as an alternating current source to the battery 3. Further, the charging control unit 2 supplies power to the power supply unit 4, the first booster circuit 14, and the second booster circuit 15. When power is not supplied from the external power source, the charging control unit 2 performs control to switch the power supply path in order to switch power from the external power source to the battery 3. Note that the charging control unit 2 may convert the power supplied from the external power source into a direct current if the power is an alternating current.
- the battery 3 supplies the charged power to the power supply unit 4, the first booster circuit 14, and the second booster circuit 15 via the charge control unit 2 when power is not supplied from the external power supply.
- the power supply unit 4 converts the power supplied via the charging control unit 2 into a voltage used in the peripheral circuit 5 and supplies the converted voltage.
- the power supply unit 4 is, for example, a three-terminal regulator, an AC-DC converter (AC-DC converter), a DC-DC converter (DC-DC converter), or the like.
- the peripheral circuit 5 includes a clock source that supplies a clock signal to each unit included in the display device 1, a control unit 6, a recording unit 7, and the like.
- the peripheral circuit 5 acquires data from an input device such as a keyboard or a touch panel connected to the display device 1, an image input device such as a camera or a scanner, and a network.
- the peripheral circuit 5 records the data acquired via the control unit 6 in the recording unit 7.
- the control unit 6 controls each unit of the display device 1.
- the control unit 6 outputs the display data acquired by the peripheral circuit 5 to the driver control unit 8.
- the driver control unit 8 is separated from the control unit 6, but the control unit 6 may have the function of the driver control unit 8.
- the control unit 6 includes a central processing unit (CPU) and a programmable device (Field Programmable Gate).
- An array (FPGA), a programmable logic device (PLD), or the like may be used.
- the recording unit 7 a program and data for controlling the driver control unit 8, the multi-voltage generation unit 12, the first booster circuit 14, and the second booster circuit 15 are recorded.
- the recording unit 7 records programs, data, and the like for controlling each unit of the display device 1.
- the recording unit 7 is a memory such as a Read Only Memory (ROM) or a Random Access Memory (RAM).
- the recording unit 7 may record data such as parameter values and variable values, or may be used as a work area.
- the driver control unit 8 outputs a plurality of types of control signals to the row driver 10 and the column driver 11 via the bus in accordance with instructions from the control unit 6.
- Examples of the plurality of control signals include a display data latch signal LP, a pulse polarity control signal FR, display data DATA, a display data capturing clock signal CLK, and the like.
- the display data latch signal LP is input to the row driver 10 and the column driver 11. In the case of the column driver 11, it is a pulse for latching display data. In the case of the row driver 10, this is a pulse for latching scan data.
- the pulse polarity control signal FR reverses the polarity of the voltage applied from the first booster circuit 14 and the second booster circuit 15 to the row driver 10 and the column driver 11, and recovers the deterioration over time peculiar to the liquid crystal.
- This is a polarity inversion control signal.
- the display data DATA is data output from the driver control unit 8 to the column driver 11. Further, the data is for one line that drives the data line connecting the column driver 11 and the display unit 9.
- the data fetch clock CLK is a clock used when fetching display data output from the driver control unit 8 to the column driver 11.
- six control signals have been described for the sake of convenience, but actually there are control signals in addition to the six control signals. Note that the number of control signals varies depending on the types of the display unit 9, the row driver 10, and the column driver 11 used in the display device 1 and the connection method between the display unit 9, the row driver 10, and the column driver 11.
- the driver control unit 8 outputs a boost switching control signal 18 for switching the first booster circuit 14 and the second booster circuit 15 to the first booster circuit 14 and the second booster circuit 15.
- the timing at which the boost switching control signal 18 is output is obtained in advance based on the change timing of the display data latch signal LP and the pulse polarity control signal FR recorded in the recording unit 7.
- the display unit 9 is a liquid crystal panel using a memory display material such as cholesteric liquid crystal.
- a memory display material such as cholesteric liquid crystal.
- it has 1024 ⁇ 768 pixels.
- the number of pixels of the liquid crystal panel is not limited to the number of pixels.
- the row driver 10 drives a scanning line connected to the display unit 9.
- the row driver 10 drives 768 scanning lines in the A4 size XGA specification.
- the number of pixels of the liquid crystal panel is not limited.
- the column driver 11 drives the data line connected to the display unit 9.
- the column driver 11 drives 1024 data lines in the A4 size XGA specification.
- the number of pixels of the liquid crystal panel is not limited.
- the multi-voltage generation unit 12 receives the voltage control signal 19 from the driver control unit 8 and uses the voltage VDDH output from the first booster circuit 14 and the second booster circuit 15 in accordance with the instruction of the voltage control signal 19. Various voltages to be supplied to the column driver 11 and the row driver 10 are generated.
- the voltage control signal 19 is a signal output from the driver control unit 8, and is a signal for notifying the multi-voltage generation unit 12 of a voltage value determined by how the column driver 11 and the row driver 10 are driven.
- the capacitor 13 is provided between a line connecting the first booster circuit 14, the second booster circuit 15, and the multi-voltage generator 12 and the ground, and smoothes and stabilizes the voltage VDDH.
- the first booster circuit 14 is a circuit that boosts the input voltage from the charging control unit 2 using a DC-DC converter (DC-DC converter) or the like.
- the first booster circuit 14 is a high output type booster circuit and is used in a period in which the column driver 11 and the row driver 10 require high power, and is shut down in other periods. For example, it is desirable to use a device having a boost control terminal for shutting down the first booster circuit 14. That is, the first booster circuit 14 can be easily shut down by the boost switching control signal 18 at the boost control terminal.
- the boosting of the first booster circuit 14 boosts up to the maximum voltage required for panel reset and drawing.
- the input voltage 4.2V is boosted to a voltage 38V necessary for panel reset, and at the time of drawing, the input voltage 4.2V is boosted to a voltage 24V necessary for drawing.
- boosting is not limited to the above.
- the second booster circuit 15 is a circuit that boosts the input voltage from the charging control unit 2 by a DC-DC converter (DC-DC converter) or the like.
- the second booster circuit 15 is a low power type booster circuit, and is used in a period in which the column driver 11 and the row driver 10 are driven with low power consumption, and is shut down in other periods.
- the inversion signal is generated using, for example, the inversion element 20.
- the boosting operation of the second booster circuit 15 boosts the voltage up to the maximum voltage required for panel reset and drawing. For example, the input voltage 4.2V is boosted to a voltage 38V necessary for panel reset, and at the time of drawing, the input voltage 4.2V is boosted to a voltage 24V necessary for drawing.
- boosting is not limited to the above.
- the rectifying element 16 is disposed between the output terminal of the first booster circuit 14 and a connection point where the input terminal of the multi-voltage generator 12 and the terminal on the voltage VDDH side of the capacitor 13 are connected.
- the anode terminal of the rectifying element 16 is connected to the output terminal of the first booster circuit 14, and the cathode terminal is connected to the connection point.
- the rectifying element 17 is disposed between the output terminal of the second booster circuit 15 and the connection point.
- the anode terminal of the rectifying element 17 is connected to the output terminal of the second booster circuit 15, and the cathode terminal is connected to the connection point. That is, the connection between the rectifying element 16 and the rectifying element 17 is a diode OR, which prevents a reverse current flow.
- FIG. 2 is a flowchart showing an embodiment of switching processing between a high power booster circuit and a low power booster circuit.
- the booster circuit 15 is switched.
- step S ⁇ b> 1 the control unit 6 receives a request notification for rewriting the display image of the display unit 9 from an input device or the like, and supplies power to the power source that supplies power to the display unit 9 and each unit that drives the display unit 9. Instruct.
- the charging control unit 2 supplies power, an inrush current that flows into each bypass capacitor or the capacitor 13 of the display device 1 is generated.
- step S2 the first booster circuit 14 is selected.
- the driver control unit 8 receives a notification indicating that the boost switching control signal 18 and the voltage control signal 19 should be output from the control unit 6, the driver control unit 8 outputs the boost switching control signal 18 and the voltage control signal 19. .
- the step-up switching control signal 18 has information for selecting the first step-up circuit 14.
- the voltage control signal 19 includes setting information for the voltage value to be output by the multi-voltage generation unit 12 when the panel is reset.
- the timing to output the boost switching control signal 18 is before the data latch timing of the display data latch signal LP or the inversion timing of the pulse polarity control signal FR related to the latch. Further, the boost switching control signal 18 is output in consideration of the time required for the first booster circuit 14 to be stably operable.
- the inversion timing of the pulse polarity control signal FR, the data latch timing of the display data latch signal LP, and the output timing of the boost switching control signal 18 are recorded in advance in the recording unit 7 as timing information.
- the timing included in this timing information is measured using, for example, a counter or a device having a clock function.
- the first booster circuit 14 that has received the boost switching control signal 18 releases the shutdown and starts up, and the second booster circuit 15 that has received the inverted signal of the boost switching control signal 18 shuts down. That is, the first booster circuit 14 is selected.
- the multi-voltage generator 12 uses the voltage output from the first booster circuit 14 to output a voltage necessary at the time of panel reset.
- control unit 6 instructs the driver control unit 8, but when the control unit 6 has the function of the driver control unit 8, the control unit 6 includes the first booster circuit 14, The booster circuit 15 and the multi-voltage generator 12 may be instructed.
- step S3 the control unit 6 instructs the driver control unit 8 to apply a panel reset voltage.
- the driver control unit 8 that has received the instruction from the control unit 6 outputs an instruction to apply a voltage to the column driver 11 and the row driver 10 corresponding to the region in order to reset the region to be rewritten to the display image. To do. Then, the column driver 11 and the row driver 10 reset the display image rewriting target.
- step S4 the second booster circuit 15 is selected.
- the controller 6 outputs an instruction to switch from the first booster circuit 14 to the second booster circuit 15 to the driver controller 8.
- the driver control unit 8 receives the instruction and outputs a boost switching control signal 18.
- the step-up switching control signal 18 has information for selecting the second step-up circuit 15.
- the driver control unit 8 outputs the boost switching control signal 18 at least after the reset of the display image rewriting target is completed. Timing for switching from the first booster circuit 14 to the second booster circuit 15 is recorded in the recording unit 7 in advance as timing information.
- the second booster circuit 15 that has received the inverted signal of the booster switching control signal 18 releases the shutdown and starts up, and the first booster circuit 14 that has received the booster switching control signal 18 shuts down. That is, the second booster circuit 15 is selected.
- step S5 the first booster circuit 14 is selected.
- the driver control unit 8 receives a notification indicating that the boost switching control signal 18 should be output from the control unit 6, the driver control unit 8 outputs the boost switching control signal 18.
- the step-up switching control signal 18 has information for selecting the first step-up circuit 14.
- the timing at which the driver control unit 8 outputs the boost switching control signal 18 is before the timing at which the pulse polarity control signal FR is inverted, and is necessary until at least the first booster circuit 14 can be stably operated.
- the boost switching control signal 18 is output in consideration of a long time.
- the inversion timing of the pulse polarity control signal FR and the timing of outputting the boost switching control signal 18 are recorded in the recording unit 7 as timing information in advance.
- the timing included in the timing information is measured using a device having a counter or a clock function.
- the first booster circuit 14 that has received the boost switching control signal 18 releases the shutdown and starts up, and the second booster circuit 15 that has received the inverted signal of the boost switching control signal 18 shuts down. That is, the first booster circuit 14 is selected.
- control unit 6 instructs the driver control unit 8, but when the control unit 6 has the function of the driver control unit 8, the control unit 6 includes the first booster circuit 14 and the second booster circuit 14. The booster circuit 15 and the multi-voltage generator 12 may be instructed.
- step S6 the driver control unit 8 receives an instruction to reverse the polarity of the applied voltage output from the control unit 6 to recover the aging deterioration peculiar to the memory liquid crystal, and reverses the polarity of the applied voltage to the liquid crystal. Recovers characteristic aging degradation.
- step S7 the second booster circuit 15 is selected.
- the controller 6 outputs an instruction to switch from the first booster circuit 14 to the second booster circuit 15 to the driver controller 8.
- the driver control unit 8 receives the switching instruction and outputs a boost switching control signal 18.
- the step-up switching control signal 18 has information for selecting the second step-up circuit 15.
- the driver control unit 8 outputs the boost switching control signal 18 at least after the inversion of the pulse polarity control signal FR is completed.
- the output timing for switching from the first booster circuit 14 to the second booster circuit 15 is recorded in the recording unit 7 as timing information in advance.
- the second booster circuit 15 that has received the inverted signal of the booster switching control signal 18 releases the shutdown and starts up, and the first booster circuit 14 that has received the booster switching control signal 18 shuts down. That is, the second booster circuit 15 is selected.
- step S8 the panel reset ends.
- step S9 drawing processing is started.
- An example of the drawing process will be described with reference to FIG.
- FIG. 3 shows waveforms of various signals on the vertical axis and the time axis on the horizontal axis.
- the signal waveform on the vertical axis indicates the display data latch signal LP, the pulse polarity control signal FR, the display data DATA, the display data fetch clock signal CLK, the output voltage OUT, the input current to the first booster circuit 14, and the boost switching control signal 18.
- the inversion signal of the boost switching control signal 18 is shown.
- step 9 in accordance with an instruction from the control unit 6, the driver control unit 8 transfers display data for one line to the column driver 11 using the display data capturing clock signal CLK.
- the periods are indicated by t4-t5, t12-t13, and t20-t21.
- step S10 the first booster circuit 14 is selected.
- the driver control unit 8 receives a notification indicating that the boost switching control signal 18 and the voltage control signal 19 should be output from the control unit 6, the driver control unit 8 outputs the boost switching control signal 18 and the voltage control signal 19. .
- the timings are t5, t13, and t21.
- the step-up switching control signal 18 has information for selecting the first step-up circuit 14.
- the voltage control signal 19 has voltage value setting information output from the multi-voltage generation unit 12 during drawing.
- the timing for outputting the boost switching control signal 18 is before the data latch timing of the display data latch signal LP and the inversion timing of the pulse polarity control signal FR related to the latch. Further, the boost switching control signal 18 is output in consideration of the time required for the first booster circuit 14 to be stably operable.
- the inversion timing of the pulse polarity control signal FR, the data latch timing of the display data latch signal LP, and the timing to output the boost switching control signal 18 at the time of drawing are recorded in the recording unit 7 in advance as timing information.
- the timing included in this timing information is measured using, for example, a counter or a device having a clock function.
- the first booster circuit 14 that has received the boost switching control signal 18 releases the shutdown and starts up, and the second booster circuit 15 that has received the inverted signal of the boost switching control signal 18 shuts down. That is, the first booster circuit 14 is selected.
- the multi-voltage generation unit 12 outputs a voltage necessary for drawing using the voltage output from the first booster circuit 14.
- control unit 6 instructs the driver control unit 8, but when the control unit 6 has the function of the driver control unit 8, the control unit 6 includes the first booster circuit 14, The booster circuit 15 and the multi-voltage generator 12 may be instructed.
- step S11 the control unit 6 instructs the driver control unit 8 to apply a drawing voltage.
- the driver control unit 8 Upon receiving the instruction from the control unit 6, the driver control unit 8 applies a voltage to the column driver 11 and the row driver 10 for drawing on the display unit 9.
- the timings are t6-t7, t14-t15, and t22-t23.
- step S12 the second booster circuit 15 is selected.
- the controller 6 outputs an instruction to switch from the first booster circuit 14 to the second booster circuit 15 to the driver controller 8.
- the driver control unit 8 receives the instruction and outputs a boost switching control signal 18.
- the timings are t8, t16, and t24.
- the boost switching control signal 18 has information for selecting the second booster circuit 15.
- the timing at which the driver control unit 8 outputs the boost switching control signal 18 is at least after completion of the reset of the display image rewriting target. Timing for switching from the first booster circuit 14 to the second booster circuit 15 is recorded in the recording unit 7 in advance as timing information.
- the second booster circuit 15 that has received the inverted signal of the booster switching control signal 18 releases the shutdown and starts up, and the first booster circuit 14 that has received the booster switching control signal 18 shuts down. That is, the second booster circuit 15 is selected.
- step S13 the first booster circuit 14 is selected. After receiving a notification indicating that the driver control unit 8 outputs the boost switching control signal 18 from the control unit 6, the driver control unit 8 outputs the boost switching control signal 18.
- the timings are t1, t9, and t17.
- the step-up switching control signal 18 has information for selecting the first step-up circuit 14.
- the timing at which the driver control unit 8 outputs the boost switching control signal 18 is before the timing at which the pulse polarity control signal FR is inverted, and is necessary until at least the first booster circuit 14 can be stably operated.
- the boost switching control signal 18 is output in consideration of a long time.
- the inversion timing of the pulse polarity control signal FR and the timing to output the boost switching control signal 18 are recorded in the recording unit 7 as timing information in advance.
- the timing included in the timing information is measured using a device having a counter or a clock function.
- the first booster circuit 14 that has received the boost switching control signal 18 releases the shutdown and starts up, and the second booster circuit 15 that has received the inverted signal of the boost switching control signal 18 shuts down. That is, the first booster circuit 14 is selected.
- control unit 6 instructs the driver control unit 8, but when the control unit 6 has the function of the driver control unit 8, the control unit 6 includes the first booster circuit 14 and the second booster circuit 14. The booster circuit 15 and the multi-voltage generator 12 may be instructed.
- step S14 the driver control unit 8 receives an instruction from the control unit 6 to recover the deterioration over time peculiar to the memory liquid crystal, and reverses the polarity of the applied voltage to recover the deterioration over time peculiar to the liquid crystal.
- the timing is t2-t3, t10-t11, t18-t19.
- step S15 the second booster circuit 15 is selected.
- the control unit 6 outputs an instruction to switch from the first booster circuit 14 to the second booster circuit 15 to the driver controller 8.
- the driver control unit 8 receives the instruction and outputs a boost switching control signal 18.
- the timing is t4, t12, and t20.
- the boost switching control signal 18 has information for selecting the second booster circuit 15.
- the driver control unit 8 outputs the boost switching control signal 18 at least after the inversion of the pulse polarity control signal FR is completed.
- the output timing for switching from the first booster circuit 14 to the second booster circuit 15 is recorded in the recording unit 7 as timing information in advance.
- the second booster circuit 15 that has received the inverted signal of the booster switching control signal 18 releases the shutdown and starts up, and the first booster circuit 14 that has received the booster switching control signal 18 shuts down. That is, the second booster circuit 15 is selected.
- step S16 it is determined whether or not the control unit 6 or the driver control unit 8 is the final line. If it is the final line, the process proceeds to step S17. If it is not the final line, the process proceeds to step S9. Transition. For example, in the case of A4 size XGA specification, it is determined whether or not the number is 768 lines.
- step S ⁇ b> 17 the control unit 6 detects that the rewriting of the display image on the display unit 9 has been completed, and outputs an instruction to stop to the power supply that supplies power to the display unit 9 and each unit that drives the display unit 9. To do.
- the supply current fluctuates depending on the load of the display unit 9 and the content to be displayed.
- the booster circuit that can output high power during the period requiring high power in each of the panel reset period and the drawing period.
- a booster circuit with low power consumption is used. As a result, power consumption during the panel reset period and the drawing period can be reduced.
Abstract
Description
第2の昇圧回路は、上記表示部の表示を保持する電圧を出力する低消費電力の昇圧回路である。
図1は、表示装置の一実施例を示すブロック図である。
表示装置1は、充電制御部2、バッテリ3、電源部4、周辺回路5、制御部6、記録部7、ドライバ制御部8、表示部9、ロウドライバ10、カラムドライバ11、多電圧生成部12、コンデンサ13などを備えている。また、表示装置1は第1の昇圧回路14、第2の昇圧回路15、整流素子16、17、反転素子20を備えている。
電源部4は、充電制御部2を介して供給された電力を周辺回路5で用いる電圧に変換して供給する。電源部4は、例えば、三端子レギュータ、交流-直流変換器(AC-DCコンバータ)、直流-直流変換器(DC-DCコンバータ)などである。
Array(FPGA)、Programmable Logic Device(PLD)など)を用いて実現してもよい。
第1の昇圧回路14は、直流-直流変換器(DC-DCコンバータ)などにより、充電制御部2からの入力電圧を昇圧する回路である。第1の昇圧回路14は、高出力タイプの昇圧回路で、カラムドライバ11とロウドライバ10が高電力を必要とする期間に用いられ、それ以外の期間はシャットダウンされる。例えば、第1の昇圧回路14をシャットダウンさせるための昇圧制御端子を備えるデバイスを用いることが望ましい。つまり、昇圧制御端子に昇圧切替制御信号18により、第1の昇圧回路14を容易にシャットダウンさせられる。なお、第1の昇圧回路14の昇圧は、パネルリセット、描画時に必要な最大の電圧まで昇圧するものである。例えば、入力電圧4.2Vをパネルリセットに必要な電圧38Vまで昇圧し、描画時は入力電圧4.2Vを描画に必要な電圧24Vまで昇圧する。ただし、昇圧は上記に限定されるものではない。
図2は、高電力の昇圧回路と低電力の昇圧回路の切り替え処理の一実施例を示すフロー図である。本実施形態の表示装置1では、表示部9の書き換えの対象となる領域をリセットするパネルリセット期間と描画を実行する描画期間内において、高電力の第1の昇圧回路14と低電力の第2の昇圧回路15の切り替えを行う。
ドライバ制御部8が制御部6から昇圧切替制御信号18と電圧制御信号19を出力すべきことを示す通知を受信したのち、ドライバ制御部8は昇圧切替制御信号18と電圧制御信号19を出力する。昇圧切替制御信号18は、第1の昇圧回路14を選択する情報を有している。電圧制御信号19は、パネルリセット時に多電圧生成部12が出力すべき電圧値の設定情報を有する。昇圧切替制御信号18を出力するタイミングは、表示データラッチ信号LPのデータラッチのタイミングまたはそのラッチに係るパルス極性制御信号FRの反転タイミングより前である。また、第1の昇圧回路14が安定して動作可能な状態になるまでに必要な時間を考慮して、昇圧切替制御信号18を出力する。パルス極性制御信号FRの反転タイミング、表示データラッチ信号LPのデータラッチのタイミングおよび昇圧切替制御信号18を出力するタイミングは、予め記録部7にタイミング情報として記録されている。このタイミング情報に含まれるタイミングは、例えば、カウンタまたは時計機能を備えるデバイスなどを用いて計測する。
制御部6が第1の昇圧回路14から第2の昇圧回路15に切り替える指示をドライバ制御部8に出力する。ドライバ制御部8は指示を受信して、昇圧切替制御信号18を出力する。昇圧切替制御信号18は、第2の昇圧回路15を選択する情報を有している。ドライバ制御部8が該昇圧切替制御信号18を出力するタイミングは、少なくとも表示画像の書き換え対象のリセットを完了した後である。第1の昇圧回路14から第2の昇圧回路15に切り替えるタイミングは、予め記録部7にタイミング情報として記録されている。また、昇圧切替制御信号18の反転信号を受信した第2の昇圧回路15はシャットダウンを解除して起動し、昇圧切替制御信号18を受信した第1の昇圧回路14はシャットダウンする。すなわち、第2の昇圧回路15が選択される。
ドライバ制御部8が制御部6から昇圧切替制御信号18を出力すべきことを示す通知を受信したのち、ドライバ制御部8が昇圧切替制御信号18を出力する。昇圧切替制御信号18は、第1の昇圧回路14を選択する情報を有している。ドライバ制御部8が昇圧切替制御信号18を出力するタイミングは、パルス極性制御信号FRを反転するタイミングより前であり、少なくとも第1の昇圧回路14が安定して動作可能な状態になるまでに必要な時間を考慮して、昇圧切替制御信号18を出力する。パルス極性制御信号FRの反転タイミングおよび昇圧切替制御信号18を出力するタイミングは、予め記録部7にタイミング情報として記録されている。タイミング情報に含まれるタイミングは、カウンタまたは時計機能を備えるデバイスなどを用いて計測する。
制御部6が第1の昇圧回路14から第2の昇圧回路15に切り替える指示をドライバ制御部8に出力する。ドライバ制御部8は切り替える指示を受信して、昇圧切替制御信号18を出力する。昇圧切替制御信号18は、第2の昇圧回路15を選択する情報を有している。ドライバ制御部8が該昇圧切替制御信号18を出力するタイミングは、少なくともパルス極性制御信号FRの反転が完了した後のタイミングである。なお、第1の昇圧回路14から第2の昇圧回路15に切り替える出力タイミングは、予め記録部7にタイミング情報として記録されている。また、昇圧切替制御信号18の反転信号を受信した第2の昇圧回路15はシャットダウンを解除して起動し、昇圧切替制御信号18を受信した第1の昇圧回路14はシャットダウンする。すなわち、第2の昇圧回路15が選択される。
ステップS9では描画処理を開始する。
図3を用いて、描画処理の一実施例について説明をする。図3は、縦軸に各種信号の波形を示し、横軸に時間軸を示している。縦軸の信号波形は、表示データラッチ信号LP、パルス極性制御信号FR、表示データDATA、表示データ取り込みクロック信号CLK、出力電圧OUT、第1の昇圧回路14への入力電流、昇圧切替制御信号18、昇圧切替制御信号18の反転信号を示している。
ドライバ制御部8が制御部6から昇圧切替制御信号18と電圧制御信号19を出力すべきことを示す通知を受信したのち、ドライバ制御部8は昇圧切替制御信号18と電圧制御信号19を出力する。図3の例ではt5、t13、t21のタイミングである。
制御部6が第1の昇圧回路14から第2の昇圧回路15に切り替える指示をドライバ制御部8に出力する。ドライバ制御部8は指示を受信して、昇圧切替制御信号18を出力する。図3の例では、t8、t16、t24のタイミングである。
ドライバ制御部8が制御部6から昇圧切替制御信号18を出力することを示す通知を受信したのち、ドライバ制御部8が昇圧切替制御信号18を出力する。図3の例では、t1、t9、t17のタイミングである。
制御部6が、第1の昇圧回路14から第2の昇圧回路15に切り替える指示をドライバ制御部8に出力する。ドライバ制御部8は指示を受信して、昇圧切替制御信号18を出力する。図3の例では、t4、t12、t20のタイミングである。
なお、本発明は、上記実施の形態に限定されるものでなく、本発明の要旨を逸脱しない範囲内で種々の改良、変更が可能である。
2 充電制御部
3 バッテリ
4 電源部
5 周辺回路
6 制御部
7 記録部
8 ドライバ制御部
9 表示部
10 ロウドライバ
11 カラムドライバ
12 多電圧生成部
13 コンデンサ
14 第1の昇圧回路
15 第2の昇圧回路
16、17 整流素子
18 昇圧切替制御信号
19 電圧制御信号
20 反転素子
Claims (6)
- メモリ性液晶を用いた表示部と、前記表示部の走査ラインを駆動するロウドライバと、前記表示部のデータラインを駆動するカラムドライバとを備える表示装置であって、
前記表示部と、前記ロウドライバと、前記カラムドライバを駆動する電流を出力する第1の昇圧回路と、
前記表示部の表示を保持する電圧を出力する第2の昇圧回路と、
前記ロウドライバと前記カラムドライバを制御する、表示データを確定する表示データラッチ信号と液晶の劣化を防止するためのパルス極性制御信号のそれぞれが変化するタイミングを参照し、表示データラッチ信号とパルス極性制御信号が変化するタイミングより前の予め設定したタイミングで前記第1の昇圧回路に切り替え、予め設定した期間経過したのち前記第2の昇圧回路に切り替える制御をする制御部と、
を備えることを特徴とする表示装置。 - 前記制御部は、前記表示部をパネルリセットする期間内と描画する期間内に、前記第1の昇圧回路と前記第2の昇圧回路を切り替えることを特徴とする請求項1に記載の表示装置。
- 前記制御部は、前記第1の昇圧回路又は前記第2の昇圧回路のいずれか一方のみを選択して切り替える制御を行うことを特徴とする請求項1または2に記載の表示装置。
- メモリ性液晶を用いた表示部と、前記表示部の走査ラインを駆動するロウドライバと、前記表示部のデータラインを駆動するカラムドライバとを備える表示装置の制御方法であって、
コンピュータが、
記録部に記録されている、前記ロウドライバと前記カラムドライバを制御する、表示データを確定する表示データラッチ信号と液晶の劣化を防止するためのパルス極性制御信号のそれぞれが変化するタイミングを参照し、
前記表示データラッチ信号と前記パルス極性制御信号が変化するタイミングより前の予め設定したタイミングで、前記表示部と、前記ロウドライバと、前記カラムドライバを駆動する電流を出力する第1の昇圧回路に切り替え、
予め設定した期間経過したのち、前記表示部の表示を保持する電圧を出力する第2の昇圧回路に切り替える、
ことを実行する表示装置の制御方法。 - コンピュータが
前記表示部をパネルリセットする期間内と描画する期間内に、前記第1の昇圧回路と前記第2の昇圧回路を切り替えることを実行する請求項4に記載の表示装置の制御方法。 - コンピュータが、
前記第1の昇圧回路又は前記第2の昇圧回路のいずれか一方のみを選択して切り替えることを実行する請求項4または5に記載の表示装置の制御方法。
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KR1020127033355A KR20130023277A (ko) | 2010-06-30 | 2010-06-30 | 표시 장치와 표시 장치의 제어 방법 |
CN2010800675257A CN102959612A (zh) | 2010-06-30 | 2010-06-30 | 显示装置和显示装置的控制方法 |
JP2012522390A JPWO2012001785A1 (ja) | 2010-06-30 | 2010-06-30 | 表示装置と表示装置の制御方法 |
PCT/JP2010/061183 WO2012001785A1 (ja) | 2010-06-30 | 2010-06-30 | 表示装置と表示装置の制御方法 |
TW099134019A TW201201173A (en) | 2010-06-30 | 2010-10-06 | Display device and display device control method |
US13/719,915 US20130106822A1 (en) | 2010-06-30 | 2012-12-19 | Display device and method for controlling display device |
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US10755622B2 (en) * | 2016-08-19 | 2020-08-25 | Samsung Electronics Co., Ltd. | Display driver integrated circuit for supporting low power mode of display panel |
KR102606476B1 (ko) * | 2016-08-19 | 2023-11-29 | 삼성전자주식회사 | 디스플레이 장치의 저전력 모드를 지원하는 디스플레이 구동 회로 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005151634A (ja) * | 2003-11-12 | 2005-06-09 | Toshiba Matsushita Display Technology Co Ltd | Dc−dc変換回路 |
WO2009050771A1 (ja) * | 2007-10-15 | 2009-04-23 | Fujitsu Limited | コレステリック液晶表示装置 |
JP2010026019A (ja) * | 2008-07-16 | 2010-02-04 | Renesas Technology Corp | 電子ペーパーディスプレイおよびそれに使用される半導体集積回路とその動作方法 |
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JP4212791B2 (ja) * | 2000-08-09 | 2009-01-21 | シャープ株式会社 | 液晶表示装置ならびに携帯電子機器 |
JP4794756B2 (ja) * | 2001-06-13 | 2011-10-19 | ローム株式会社 | 表示駆動装置 |
JP5374913B2 (ja) * | 2008-04-21 | 2013-12-25 | カシオ計算機株式会社 | 表示装置及び電源装置 |
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- 2010-06-30 CN CN2010800675257A patent/CN102959612A/zh active Pending
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- 2010-06-30 JP JP2012522390A patent/JPWO2012001785A1/ja not_active Ceased
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---|---|---|---|---|
JP2005151634A (ja) * | 2003-11-12 | 2005-06-09 | Toshiba Matsushita Display Technology Co Ltd | Dc−dc変換回路 |
WO2009050771A1 (ja) * | 2007-10-15 | 2009-04-23 | Fujitsu Limited | コレステリック液晶表示装置 |
JP2010026019A (ja) * | 2008-07-16 | 2010-02-04 | Renesas Technology Corp | 電子ペーパーディスプレイおよびそれに使用される半導体集積回路とその動作方法 |
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US20130106822A1 (en) | 2013-05-02 |
JPWO2012001785A1 (ja) | 2013-08-22 |
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