WO2012000163A1

WO2012000163A1 - Nonvolatile semiconductor memory unit

Info

Publication number: WO2012000163A1
Application number: PCT/CN2010/074613
Authority: WO
Inventors: 唐粕人; 黄如; 蔡一茂; 许晓燕
Original assignee: 北京大学
Priority date: 2010-06-28
Filing date: 2010-06-28
Publication date: 2012-01-05

Abstract

A nonvolatile semiconductor memory unit is provided, belonging to the technical field of the semiconductor memory. A silicon substrate (101) is provided and a source and a drain region (102, 102') is formed in the both side of the carrier channel in the upper surface of the silicon substrate (101). A tunneling oxide layer (103) is formed on the carrier channel region of the silicon substrate (101). A floating gate charge storage layer (104) is formed on the tunneling oxide layer (103). A block dielectric layer (105) is formed on the floating gate charge storage layer (104). A polysilicon control gate (106) is formed on the block dielectric layer (105). The coupling between flash units and the generation and the density of the defect in the block dielectric layer of the flash are reduced by the memory unit, and the signal window of the flash is increased and the retention performance and the reliability of the flash unit are improved. The memory unit has a wide application prospect in the high density and the high reliability storage application.

Description

Non-volatile semiconductor memory unit

TECHNICAL FIELD The present invention relates to the field of semiconductor memory technology, and more particularly to a non-volatile semiconductor memory unit capable of improving device performance and reliability.

BACKGROUND OF THE INVENTION Semiconductor memories are an indispensable and important component in various electronic devices, and nonvolatile semiconductor memories have the characteristics of being able to retain data even in the event of power failure, and thus are widely used in various mobile portable devices, such as Mobile phones, laptops, PDAs, etc. Due to the rapid development of mobile portable electronic devices in recent years, the demand for non-volatile flash memory (also known as flash memory) is also increasing. Advances in technology have made the cost of flash memory increasingly low, which in turn has further spurred purchases and new market applications. Flash memory has become the fastest growing semiconductor memory and has occupied most of the market share of non-volatile semiconductor memory.

Now the most widely used on the market is based on flash-doped (such as boron, phosphorus) polysilicon gate as the floating gate (floating gate) and the control gate (control gate) of floating gate flash (Floating Gate Flash Memory) ₀ When flash During programming, the appropriate voltage is applied to the source, drain, control gate, and substrate electrodes. The electrons will pass through the channel and source and drain regions through the tunneling oxide under the floating gate and be evenly distributed. Among the floating gates. Electrons entering the floating gate can be divided into two cases, one is thermal electron injection and the other is quantum tunneling. Due to its compatibility with traditional CMOS processes and its simple structure, floating gate flash memory has been rapidly developed. However, as the size of flash memory cells shrinks sharply, the scale reduction of floating gate flash memory faces great challenges. Especially after entering the 45nm technology node, the distance between floating gate flash memory cells is reduced, the interference between cells is aggravated, and the memory is reliable. Sex has a serious impact. In addition, the stored charge of the floating gate flash memory is continuously distributed in the polysilicon floating gate. When there is a leakage channel in the tunneling oxide layer (ie, silicon dioxide), all stored electrons on the floating gate may be lost from this channel, resulting in information loss. Device reliability is degraded.

Discrete Trap flash technology has recently received great attention and research, using a separate trap in silicon nitride as a charge storage layer to store charge. The energy level of the trap is separated and limited in the charge storage layer, and the stored charge cannot move freely, so that the storage charge is less affected by oxide defects and leakage channels. However, the technology for separating trap flash memory is still under development, and the device is also faced with a series of reliability problems such as erasing saturation and maintaining insufficient characteristics. So the current mainstream solution is to continue to optimize and develop traditional floating-gate flash technology.

For floating gate flash memory, in order to reduce the coupling crosstalk between cells, it is necessary to reduce the thickness of the floating polysilicon gate, or increase the distance between the flash memory cells, and increase the distance between the flash memory cells. This reduces memory density, which is contrary to the development of flash memory technology, so crosstalk can only be reduced by reducing the thickness of the floating polysilicon gate.

However, if the thickness of the floating gate used is too small, it will also cause reliability problems. As shown in FIG. 1 , when a flash memory cell is programmed or erased, electrons are generally injected into the floating gate through thermal implantation or tunneling, and electrons injected into the floating gate have high energy, and these electrons pass through the thin floating gate and have low energy loss, so When it reaches the barrier dielectric layer, it still has higher energy. The high-energy electrons can cause the dielectric layer to form a dielectric layer defect, which causes the sub-threshold slope of the cell to deteriorate, eventually leading to degradation of the flash memory performance, resulting in a flash memory as shown in FIG. 2. The problem of poor threshold characteristics, charge leakage and signal window reduction. The dotted line in Fig. 2 refers to the slope of the sub-threshold of the device after the dielectric layer defect is generated. It can be found that the slope of the flash sub-threshold is deteriorated, and the leakage of the charge through the defect causes the signal window (AV _TH ) to shrink. These defects will further affect the quality of the blocking dielectric layer on the floating gate, increasing the probability of flash charge leaking from the blocking dielectric layer, directly affecting the charge retention characteristics of the flash memory cell.

Therefore, how to further reduce the damage and defects of the floating polysilicon gate blocking dielectric layer in the device and improve the reliability of the device is a problem that needs to be solved urgently.

Summary of the invention

(1) Technical problems to be solved

In view of this, the main object of the present invention is to provide a non-volatile semiconductor memory cell to reduce damage and defects to the floating polysilicon gate and dielectric layer in the device, and to reduce the lack of The trapped leakage current reduces the shrinkage of the signal window and enhances the holding characteristics of the device, improving the reliability of the device.

(ii) Technical solutions

To achieve the above object, the present invention provides a non-volatile semiconductor memory unit, including:

Silicon substrate

Forming a source and a drain on both sides of the surface carrier channel on the upper surface of the silicon substrate;

a tunneling oxide layer formed over the surface carrier channel of the silicon substrate;

a floating gate charge storage layer formed over the tunneling oxide layer;

a blocking dielectric layer formed over the floating gate charge storage layer;

A polysilicon control gate formed over the blocking dielectric layer.

In the above solution, the tunneling oxide layer serves to enhance the adsorption force between the floating gate charge storage layer and the silicon substrate and form an interface with a small defect density of the silicon substrate.

In the above solution, the floating gate charge storage layer is formed by stacking floating gates of mixed materials, and includes:

a first polysilicon floating gate;

A first metal floating gate is stacked over the first polysilicon floating gate.

In the above solution, the floating gate charge storage layer further includes a second polysilicon floating gate formed on the first metal floating gate.

In the above solution, the floating gate charge storage layer further includes a second metal floating gate formed under the first polysilicon floating gate.

In the above solution, the blocking dielectric layer is made of a dielectric material having a high dielectric constant for preventing leakage of charges stored in the floating gate charge storage layer. The high dielectric constant dielectric material is made of any one of aluminum oxide, antimony pentoxide, antimony oxide, antimony silicon oxide and titanium dioxide, or is oxidized by using aluminum oxide, antimony pentoxide, antimony oxide or antimony. At least two materials of silicon and titanium dioxide.

In the above solution, the blocking dielectric layer is made of silicon dioxide/silicon nitride/silicon dioxide.

(ONO) three-layer structure, the floating gate charge storage layer uses polysilicon floating gate/metal floating gate/multiple Three-layer structure of crystalline silicon floating gate.

a third metal floating gate;

A third polysilicon floating gate is stacked on top of the third metal floating gate.

In the above solution, the floating gate charge storage layer further includes a fourth metal floating gate formed on the third polysilicon floating gate.

In the above solution, the floating gate charge storage layer further includes a fourth polysilicon floating gate formed under the third metal floating gate.

In the above solution, the metal floating gate adopts any one of tungsten W, tantalum Ta, vanadium, chromium Cr, nickel Ni, cobalt Co, titanium Ti, tantalum nitride HfN, tantalum nitride TaN, and titanium nitride TiN. .

In the above solution, the polysilicon floating gate or the metal floating gate adopts an ultra-thin structure, and each of the thicknesses thereof is 3 nm to 40 nm.

(3) Beneficial effects

As can be seen from the above technical solutions, the present invention has the following beneficial effects:

1. The non-volatile semiconductor memory unit provided by the present invention is a thin-body hybrid floating gate structure flash memory, which reduces coupling between flash memory cells and the generation and density of barrier dielectric layer defects in the flash memory, and Increasing the signal window of the flash memory improves the retention characteristics and reliability of the flash memory, and has obvious advantages and broad application prospects in future high-density, high-reliability storage applications.

2. The non-volatile semiconductor memory unit provided by the present invention can reduce the coupling between the floating gates of the flash memory cells by using a thin floating gate structure and a high dielectric constant barrier dielectric material. The coupling produces a misreading, while a higher coupling voltage is coupled to the floating gate, which improves the programming/erasing speed of the flash memory.

3. The non-volatile semiconductor memory unit provided by the present invention reduces the damage of the high-energy electron to the flash-blocking dielectric layer due to the use of the mixed thin-body floating gate, so that the stored charge does not block the dielectric layer. The defects in the leak are leaked, which improves the retention characteristics and reliability of the device. Degree.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of the energy band structure of high energy thermal injection or tunneling electrons causing degradation of flash memory performance;

2 is a schematic diagram of a flash memory signal window caused by a defect in a flash dielectric layer;

Figure 3 is a block diagram showing the structure of a nonvolatile semiconductor memory unit in accordance with a first embodiment of the present invention;

Figure 4 is a block diagram showing the structure of a nonvolatile semiconductor memory unit in accordance with a second embodiment of the present invention;

Figure 5 is a block diagram showing the configuration of a nonvolatile semiconductor memory unit in accordance with a third embodiment of the present invention;

Figure 6 is a process flow diagram of fabricating a non-volatile semiconductor memory cell in accordance with an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION In order to make the objects, technical solutions and advantages of the present invention more comprehensible, the present invention will be described in detail below with reference to the accompanying drawings.

For the problem of poor reliability of ultra-thin floating gates, the use of metal floating gates is a better solution because the electron free path of the metal floating gate is short, and the energy of the tunneled electrons passes through the metal gate and is scattered. Thus, no high-energy electrons re-enter the blocking dielectric layer of the flash memory, reducing the damage to the flash-blocking dielectric layer. The non-volatile semiconductor memory unit provided by the invention, that is, the structure of the flash memory cell, is a metal floating gate embedded in the charge storage layer, and the metal floating gate is used to reduce scattering, so that the electron energy is reduced, thereby improving the reliability of the unit. .

As shown in FIG. 3, FIG. 3 is a schematic structural view of a nonvolatile semiconductor memory unit in accordance with a first embodiment of the present invention. The reference numerals are as follows: 101 silicon substrate, 102 source, 102' drain, 103 tunnel oxide layer, 104 floating gate charge storage layer, 105 blocking dielectric layer, more than 106 Crystal silicon control gate, 111 polysilicon floating gate, 112 metal floating gate. The non-volatile semiconductor memory cell structure shown in FIG. 3 includes a silicon substrate 101, a source 102 and a drain 102', a tunnel oxide layer 103, a floating gate charge storage layer 104, a blocking dielectric layer 105, and a polysilicon control gate. Pole 106. The tunnel oxide layer 103, the floating gate charge storage layer 104, the blocking dielectric layer 105, and the polysilicon control gate 106 are sequentially on the surface carrier channel on the upper surface of the silicon substrate 101. The source 102 And the drain electrode 102' are respectively formed on both sides of the upper surface carrier channel of the silicon substrate 101, and the tunnel oxide layer 103 is formed on the carrier channel of the upper surface of the silicon substrate 101, and the floating gate charge A memory layer 104 is formed over the tunnel oxide layer 103, and a blocking dielectric layer 105 is formed over the floating gate charge storage layer 104. The polysilicon control gate 106 is formed over the blocking dielectric layer 105.

Referring to FIG. 3 again, the floating gate charge storage layer 104 is formed by stacking floating gates of mixed materials, and comprises an ultra-thin polysilicon floating gate 111 and an ultra-thin metal stacked on the polysilicon floating gate 111. Floating gate 112. The floating gate charge storage layer 104 uses a polysilicon floating gate to form a lower floating gate, that is, a polysilicon floating gate 111. The lower floating gate has good process compatibility, and has good adhesion between the underlying oxide oxide layer 103 and Interface characteristics, and can well control the effects of edge effects. At the same time, the floating gate charge storage layer 104 is made of a high temperature resistant metal material to form an upper floating gate, that is, a metal floating gate 112, which can absorb the energy of high energy electrons entering the lower polysilicon floating gate, thereby reducing the blocking power to the flash memory. Layer damage, reducing interface state density and leakage current, and improving the reliability of the flash memory unit.

The tunneling oxide layer 103 under the floating gate charge storage layer 104 serves to enhance the adsorption between the floating gate charge storage layer 104 and the silicon substrate 101, and can form a good tunnel between the oxide layer and the silicon substrate. Interface, the defect density is extremely small.

A blocking dielectric layer 105 over the floating gate charge storage layer 104 serves to prevent charge stored by the floating gate charge storage layer 104 from leaking to the gate or elsewhere. In order to increase the coupling coefficient of the control gate to the floating gate, the blocking dielectric layer 105 can be formed of a dielectric material having a high dielectric constant, and the current metal gate-high dielectric constant dielectric layer process can be used in the metal floating gate The high dielectric constant blocks a good interface between the dielectric layers.

Of course, the blocking dielectric layer 105 can also be a bottom-up silicon dioxide/silicon nitride/silicon dioxide dielectric layer (ONO) structure commonly used in general flash memory, but due to the metal floating gate. The high-quality ONO dielectric layer structure is grown, the growth process is complicated, and a large number of structural defects and interface states are easily generated at the interface, resulting in deterioration of device reliability, particularly information retention performance, so if the dielectric layer 105 is blocked. With the bottom-up silicon dioxide/silicon nitride/silicon dioxide dielectric layer structure, the above flash memory structure can be modified to the structure shown in FIG.

As shown in Fig. 4, Fig. 4 is a schematic structural view of a nonvolatile semiconductor memory unit in accordance with a second embodiment of the present invention. The reference numerals are as follows: 101 silicon substrate, 102 source, 102' drain, 103 tunnel oxide layer, 104 floating gate charge storage layer, 105 blocking dielectric layer, 106 polysilicon control gate, 211 polysilicon floating gate, 212 metal floating gate, 213 polysilicon floating gate. Referring to the structure shown in FIG. 3, the structure of FIG. 4 is to deposit a polysilicon floating gate layer 213 over the metal floating gate 212. At this time, the floating gate charge storage layer 104 is composed of a polysilicon floating gate/metal floating gate/polysilicon floating gate. Three layers of material. Compared with the structure shown in FIG. 3, since the top layer of the floating gate charge storage layer 104 is composed of a polysilicon floating gate material, the growth of the ONO blocking dielectric layer on the floating gate charge storage layer 104 is the same as that of the conventional flash memory, and the process is easy. The interface density between the floating gate layer and the ONO blocking dielectric layer is low, and the defects are small, which is favorable for long-term retention during charge power-off, and reduces the risk of reliability reduction due to the increase of defects.

As flash memory devices continue to scale down toward high density and high reliability, the performance degradation of flash devices in short trench lengths has increasingly become a serious obstacle to the continued shrinking of devices. The tunneling oxide layer 103 uses silicon dioxide having a low dielectric constant, which seriously affects the short-channel characteristics of the flash memory device, so that the sub-threshold slope of the flash memory device is too large, and the sub-threshold leakage current is large. Therefore, in order to further reduce the sub-threshold slope of the device and improve the device performance, it is necessary to introduce a dielectric material having a high dielectric constant to form a tunneling oxide layer. In this case, a dielectric material having a high dielectric constant is used. The tunneling oxide layer is generally referred to as a tunneling dielectric layer.

For a flash memory using a high dielectric constant tunneling dielectric layer, the structure shown in FIG. 3 is to grow a polysilicon floating gate in a high-k dielectric layer, based on the memory cell structure shown in FIG. Further reducing the complexity of the process, reducing the occurrence of interface defects and avoiding the leakage of stored information, the present invention also proposes a flash structure for a mixed polycrystalline and metal floating gate of a high dielectric constant tunneling oxide layer, as shown in FIG. 5 is a schematic structural view of a nonvolatile semiconductor memory unit in accordance with a third embodiment of the present invention. The reference numerals are as follows: 101 silicon substrate, 102 source, 102' drain, 103' tunneling dielectric layer, 104 floating gate charge storage layer, 105 blocking Dielectric layer, 106 polysilicon control gate, 311 metal floating gate, 312 polysilicon floating gate.

5 is a thin metal floating gate 311 formed under the polysilicon floating gate 312 before forming the polysilicon floating gate 312, which together form the floating gate charge storage layer 104. This structure first grows a metal floating gate on a high dielectric constant (high K) tunneling dielectric layer 103', which is similar to the high-k gate dielectric, metal gate process, and is easy to implement, and is advantageous for reducing high K tunneling. The interface defect between the dielectric layer 103' and the charge storage layer 104 reduces the interface state density, and the metal floating gate can also effectively reduce the energy of the high-energy electrons and prevent the damage of the high-energy electrons to the blocking dielectric layer.

Preferably, in order to better improve the interface characteristics between the floating gate charge storage layer 104 and the blocking dielectric layer 105, a metal floating gate material may be deposited on the polysilicon floating gate 312 of the structure shown in FIG. The floating gate charge storage layer 104 is composed of a metal floating gate/polysilicon floating gate/metal floating gate material. The advantage of this structure is that the top metal gate can further reduce the energy of the high-energy electrons, and can reduce the defect density of the interface between the floating gate charge storage layer and the blocking dielectric layer, and improve the reliability of the flash memory unit.

The above high dielectric constant material refers to a dielectric material having a higher dielectric constant than silicon dioxide/silicon nitride (Si0 ₂ /Si ₃ N ₄ ), and these high dielectric constant materials may be aluminum oxide (A1 ₂ 0 _3). ), a material such as tantalum pentoxide (Ta ₂ 0 ₅ ), yttrium oxide (Hf0 ₂ ), silicon germanium oxide (HfSi _x O _y ), titanium dioxide (Ti0 ₂ ), or a mixture thereof. Considering process compatibility, the above metal floating gate can be made of high temperature resistant metal materials such as tungsten (W), tantalum (Ta), vanadium (V), chromium (Cr), nickel (Ni), cobalt (Co). , titanium (Ti), tantalum nitride (HfN), tantalum nitride (TaN) and titanium nitride (TiN).

In addition, the metal can chemically react with the polysilicon floating gate during the process realization to form a stable metal silicide floating gate such as titanium silicide (TiSi), nickel silicide (Ni _x Si _y ) or the like as a charge storage layer. In order to reduce the coupling between the cells, the polysilicon floating gate and the metal floating gate are both made of an ultra-thin structure, each of which has a thickness of 3 nm to 40 nm.

In order to more clearly describe the non-volatile semiconductor memory unit provided by the present invention, the fabrication process of the non-volatile semiconductor memory unit provided by the present invention will be described in detail below with reference to the non-volatile semiconductor memory cell structure shown in FIG. 3 to FIG. .

As shown in FIG. 6, FIG. 6 is a process flow diagram of fabricating a non-volatile semiconductor memory cell in accordance with an embodiment of the present invention. Referring to FIG. 3, the process first selects a substrate 101 in which the silicon A tunneling oxide layer 103 of a SiO ₂ material is formed on the substrate 101 by oxidative growth, chemical vapor deposition (CVD) or atomic layer deposition (ALD); then, CVD is performed on the tunnel oxide layer 103. Forming a floating gate charge storage layer 104 by a method such as ALD or sputtering; then forming a blocking dielectric layer 105 on the floating gate charge storage layer 104 by CVD, ALD or sputtering; and then, blocking the dielectric On the layer 105, a polysilicon control gate 106 is formed by CVD, ALD or sputtering; finally, the etch 106, 105, 104 forms a gate stack line, and ion implantation is performed on both sides of the gate line, and the implant is heavily doped. The ions form a source 102 and a drain 102' on both sides of the channel below the gate line.

In the step of forming the floating gate charge storage layer 104, an ultrathin polysilicon floating gate 111 is formed on the tunnel oxide layer 103 by CVD, ALD or sputtering, and then floating on the polysilicon. On top of the gate 111, an ultra-thin metal floating gate 112 is formed by electron beam evaporation, ALD or sputtering. Among them, the polysilicon floating gate 111 has good process compatibility, has good adhesion and interface characteristics with the tunneling oxide layer 103 under it, and can well control the influence of edge effects. The metal floating gate 112 can absorb the energy of the high-energy electrons entering the lower polysilicon floating gate, thereby reducing the damage to the flash-blocking dielectric layer, reducing the interface state density and leakage current, and improving the reliability of the flash memory unit.

Preferably, in conjunction with FIG. 4, in order to have a good interface between the floating gate charge storage layer 104 and the blocking dielectric layer 105, the risk of reliability reduction due to the increase in defects is reduced, and the present invention is in a polysilicon floating gate. After forming an ultra-thin metal floating gate thereon, a polysilicon floating gate layer 213 is deposited over the metal floating gate 212. At this time, the floating gate charge storage layer 104 is covered by a polysilicon floating gate/metal floating gate/polysilicon floating. The grid is made of three layers of material. Since the top layer of the floating gate charge storage layer 104 is composed of a polysilicon floating gate material, the interface between the floating gate charge storage layer 104 and the blocking dielectric layer 105 is the same as that of the conventional flash memory, and the process is more controllable, and The good interface between the floating gate charge storage layer 104 and the blocking dielectric layer 105 reduces the risk of reliability degradation due to increased defects.

Preferably, in conjunction with FIG. 5, in order to reduce the interface defect density between the floating gate charge storage layer 104 and the tunnel dielectric layer 103', and further reduce the energy of the high energy electrons to prevent damage of the barrier dielectric layer by the high energy electrons, The interface between the floating gate charge storage layer 104 and the tunnel dielectric layer 103' is composed of a high dielectric constant (high K) dielectric layer and a metal floating gate. At this time, in the above In the step of forming the floating gate charge storage layer 104, a thin metal floating gate 311 is formed on the tunnel dielectric layer 103' by electron beam evaporation, CVD, ALD or sputtering, and then A thin polysilicon floating gate 312 is formed on the thin metal floating gate 311 by CVD, ALD or sputtering. The thin metal floating gate 311 and the polysilicon floating gate 312 together form a floating gate charge storage layer 104.

Preferably, on the basis of the structure shown in FIG. 5, in order to better improve the interface characteristics between the floating gate charge storage layer 104 and the blocking dielectric layer 105, a metal may be deposited on the polysilicon floating gate 312. The floating gate material, at this time, the floating gate charge storage layer 104 is composed of a metal floating gate/polysilicon floating gate/metal floating gate material. The advantage of this structure is that the top metal gate can further reduce the energy of the high energy electrons, and can reduce the defect density of the interface between the floating gate charge storage layer and the blocking dielectric layer, and improve the reliability of the flash memory unit.

Therefore, the thin-body hybrid floating gate structure flash memory proposed by the invention reduces the coupling between the flash memory cells, and the generation and density of blocking dielectric layer defects in the flash memory, and increases the signal window of the flash memory, thereby improving the flash memory unit. The retention characteristics and reliability have obvious advantages and broad application prospects in future high-density and high-reliability storage applications.

The specific embodiments described above describe the structure of the flash memory provided by the present invention in detail, and those skilled in the art should understand that the above description is only for the specific embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claim

A non-volatile semiconductor memory unit, comprising:

Silicon substrate

a floating gate charge storage layer formed over the tunneling oxide layer;

a blocking dielectric layer formed over the floating gate charge storage layer;

A polysilicon control gate formed over the blocking dielectric layer.

2. The non-volatile semiconductor memory cell according to claim 1, wherein the tunneling oxide layer is used to enhance an adsorption force between the floating gate charge storage layer and the silicon substrate, and The silicon substrate forms an interface of small defect density.

The non-volatile semiconductor memory cell according to claim 1, wherein the floating gate charge storage layer is formed by stacking floating gates of mixed materials, and includes:

a first polysilicon floating gate;

4. The non-volatile semiconductor memory cell of claim 3, wherein the floating gate charge storage layer further comprises a second polysilicon floating gate formed on the first metal floating

5. The non-volatile semiconductor memory cell of claim 3, wherein the floating gate charge storage layer further comprises a second metal floating gate formed under the first polysilicon floating gate.

6. The non-volatile semiconductor memory cell according to claim 1, wherein the blocking dielectric layer is formed of a dielectric material having a high dielectric constant for preventing a charge stored in the floating gate charge storage layer. The leak.

7. The non-volatile semiconductor memory cell according to claim 6, wherein the high dielectric constant dielectric material is any of alumina, tantalum pentoxide, cerium oxide, cerium oxide, and titanium dioxide. A material or at least two materials selected from the group consisting of alumina, tantalum pentoxide, cerium oxide, cerium oxide, and titanium oxide.

8. The non-volatile semiconductor memory cell of claim 1, wherein the blocking dielectric layer is a silicon/silicon nitride/silicon dioxide (ONO) three-layer structure, the floating gate charge The storage layer adopts a three-layer structure of a polysilicon floating gate/metal floating gate/polysilicon floating gate.

The non-volatile semiconductor memory cell of claim 1 , wherein the floating gate charge storage layer is formed by stacking floating gates of mixed materials, including:

a third metal floating gate;

10. The non-volatile semiconductor memory cell of claim 9, wherein the floating gate charge storage layer further comprises a fourth metal floating gate formed over the third polysilicon floating gate.

11. The non-volatile semiconductor memory cell of claim 9, wherein the floating gate charge storage layer further comprises a fourth polysilicon floating gate formed under the third metal floating gate.

The non-volatile semiconductor memory cell according to any one of claims 3, 4, 5, 8, 9, 10 or 11, wherein the metal floating gate is made of tungsten W, tantalum Ta, vanadium Any of V, chromium Cr, nickel 3⁄4, cobalt Co, titanium Ti, tantalum nitride HfN, tantalum nitride TaN, and titanium nitride TiN.

The non-volatile semiconductor memory cell according to any one of claims 3, 4, 5, 8, 9, 10 or 11, wherein the polysilicon floating gate or the metal floating gate are both ultra-thin structures , each of which has a thickness of 3 nm to 40 nm.