WO2011157138A2 - 多核路由器 - Google Patents

多核路由器 Download PDF

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Publication number
WO2011157138A2
WO2011157138A2 PCT/CN2011/075031 CN2011075031W WO2011157138A2 WO 2011157138 A2 WO2011157138 A2 WO 2011157138A2 CN 2011075031 W CN2011075031 W CN 2011075031W WO 2011157138 A2 WO2011157138 A2 WO 2011157138A2
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WO
WIPO (PCT)
Prior art keywords
board
core
interface board
pcie
interface
Prior art date
Application number
PCT/CN2011/075031
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English (en)
French (fr)
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WO2011157138A3 (zh
Inventor
王江
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2011/075031 priority Critical patent/WO2011157138A2/zh
Priority to CN201180000569.2A priority patent/CN102204185B/zh
Publication of WO2011157138A2 publication Critical patent/WO2011157138A2/zh
Publication of WO2011157138A3 publication Critical patent/WO2011157138A3/zh

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/60—Router architectures

Definitions

  • Embodiments of the present invention relate to the field of communications, and in particular, to a multi-core router.
  • the existing distributed router includes a main control board, a backboard, an interface board, and a network board.
  • the main control board is a collection of multiple functional modules.
  • the management of the entire router is performed through an Ethernet switch chip on the main control board. Realize communication with the interface board and the network board.
  • each interface board and network board has a separate central processing unit (CPU, Central Processing Unit), and the CPU is also connected to the bootrom chip and the flash chip, wherein the bootrom chip is used for CPU startup, flash The chip is used to save related configuration data.
  • CPU Central Processing Unit
  • the interface board will initialize the Ethernet communication controller, send the text to the main control board through the backplane, complete the registration of the interface board on the main control board, and realize the main control board. The download of communication and related configuration data.
  • the embodiment of the invention provides a multi-core router, which manages the network board and the interface board inside the router by using a multi-core CPU on the router, and uses the PCIE bus to transmit data, thereby effectively reducing hardware resources required by the router and reducing the router. Power consumption.
  • the multi-core router in the embodiment of the present invention includes: a multi-core router internal bus is a PCIE-based bus, and the PCIE bus connects the main control board inside the multi-core router with the backplane; the multi-core router further includes a network board and at least one interface board.
  • the stencil and the interface board are respectively connected to the backplane by using a PCIE connection mode to implement data transmission.
  • the main control board includes a multi-core CPU, and the multi-core CPU controls the stencil and the interface board respectively.
  • the embodiments of the present invention have the following advantages:
  • the multi-core CPU is used on the main control board, and the main control board is connected to the backplane by using the PCIE bus, so that the multi-core CPU on the main control board can separately control the network board and the interface board, and the CPU is not required to be set on the network board and the interface board.
  • the Ethernet communication controller saves hardware resources and reduces the power consumption of the router.
  • 1 is a schematic diagram of a multi-core router according to an embodiment of the present invention
  • 2 is a schematic diagram of a multi-core CPU configuration access deployment according to an embodiment of the present invention.
  • the embodiment of the present invention provides a multi-core router.
  • the main control board on the multi-core router is connected to the backplane by using a PCIE (Peripheral Component Interconnect Express) bus, and the multi-core CPU on the main control board controls the stencil and the interface board respectively, so that the stencil And the interface board does not need to set the CPU, boootroom chip and flash chip, and Ethernet communication controller, which reduces the hardware resources required by the router and reduces the power consumption of the router.
  • PCIE Peripheral Component Interconnect Express
  • an embodiment of a multi-core router includes:
  • the multi-core router internal bus is connected to the PCIE bus.
  • the PCIE bus connects the main control board 101 inside the multi-core router with the backplane 102.
  • the PCIE is a bus and interface standard.
  • the main control board 101 is integrated with a PCIE chip 106.
  • the PCIE chip 106 includes a PCIE interface, and the main control board 101 is connected to the backplane 102 through a PCIE interface.
  • the network board 103 and the at least one interface board 104 are also included in the multi-core router, and the network board 103 and the interface board 104 are respectively connected to the back board 102 by using a PCIE connection manner to implement data transmission.
  • the stencil 103 and the interface board 104 are respectively connected to the backplane 102 by using a PCIE bus, or the stencil 103 and the interface board 104 are respectively connected to the PCIE slot on the backplane 102 by using a plug-in connection.
  • the stencil 103 and the interface board 104 are inserted into the PCIE interface slot of the backplane 102 to implement the connection.
  • the Ethernet communication controller is not required to be set on the stencil 103 and the interface board 104, thereby saving hardware resources.
  • a multi-core CPU 105 is included on the main control board 101.
  • the multi-core CPU 105 controls the network board 103 and the interface board 104 respectively.
  • the multi-core CPU on the main control board 101 can directly access the hardware resources on the interface board 104 and the network board 103.
  • the multi-core CPU 105 internally manages and controls the network board 103 and the interface board 104, so that the CPU 103 and the interface board 104 do not need to be provided with a CPU, a bootroom chip for CPU startup, and a flash for CPU related configuration data saving. Chip, effectively saving hardware resources.
  • the backplane 102 is connected to the main control board 101, the network board 103, and the interface board 104, and the back board can transmit data transmitted by the interface board 104 or the network board 103 to the interface board 104 or the network board.
  • 103 processes the corresponding arithmetic core on the multi-core CPU 105.
  • the division of the memory of the multi-core CPU 105 is performed according to the requirements of the main control board 101, the network board 103, and the interface board 104, to implement physical isolation of the memory.
  • FIG. 2 an access deployment diagram of a multi-core CPU is configured in an embodiment of the present invention.
  • an inter-core communication mechanism is adopted between the main control board 101, the interface board 104, and the network board 103, so that the inter-core packet forwarding can be implemented inside the multi-core CPU 105.
  • the loading of the image file of the interface board 104 is completed by the corresponding computing core on the main control board 101, and when the interface board 104 is reset, the corresponding computing core of the multi-core CPU 105 of the interface board on the main control board 101 will complete the interface board. Reloading the code.
  • the multi-core CPU is used on the main control board of the multi-core router, and the internals of the multi-core router are communicated based on the PCIE bus, so that the multi-core CPU can separately control the network board and the interface board, and on the network board and the interface board.
  • the Ethernet communication controller saves hardware resources and reduces the power consumption of the router.
  • the medium can be a read only memory, a magnetic disk or a compact disk or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Sources (AREA)
  • Bus Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Description

多核路由器 技术领域
本发明实施例涉及通信领域， 尤其涉及多核路由器。
背景技术
现有的分布式路由器包括主控板、 背板、接口板及网板， 主控板是多个功 能模块的集合体， 对整个路由器的管理， 通过主控板上的以太网交换芯片， 可 实现和接口板以及网板之间的互相通信。在现有技术中，每个接口板和网板都 有单独的中央处理器（CPU, Central Processing Unit ), 且 CPU还与 bootrom 芯片及 flash芯片连接， 其中， bootrom芯片用于 CPU的启动， flash芯片用于 相关配置数据的保存， 接口板在启动时， 会初始化以太网通讯控制器， 通过背 板发送 文到主控板， 完成本接口板在主控板的注册，从而实现和主控板的通 信及相关配置数据的下载。
发明人在研究中发现，路由器中的接口板的数目越来越多，每个接口板上 都需要设置 CPU, 需要大量的硬件资源及功耗。
发明内容
本发明实施例提供了多核路由器， 通过在路由器上使用多核 CPU对路由 器内部的网板及接口板进行管理， 且采用 PCIE总线进行数据的传输， 能够有 效减少路由器所需的硬件资源， 降低了路由器的功耗。
本发明实施例中的多核路由器包括： 多核路由器内部总线是基于 PCIE的 总线， 所述 PCIE总线将多核路由器内部的主控板与背板连接； 多核路由器内 部还包含网板与至少一个接口板， 网板及接口板分别采用 PCIE连接方式与背 板连接， 实现数据的传输； 主控板上包含多核中央处理器 CPU, 多核 CPU分 别控制所述网板及接口板。
从以上技术方案可以看出， 本发明实施例具有以下优点：
在主控板上使用多核 CPU, 且主控板采用 PCIE总线与背板连接， 使得主 控板上的多核 CPU能够分别控制网板与接口板， 不需要在网板及接口板上设 置 CPU, 及以太网通讯控制器， 节约了硬件资源， 降低了路由器的功耗。 附图说明
图 1为本发明实施例多核路由器的一个示意图； 图 2为本发明实施例多核 CPU配置访问部署的示意图。
具体实施方式
本发明实施例提供了多核路由器， 该多核路由器上的主控板采用 PCIE ( Peripheral Component Interconnect Express )总线与背板连接, 且主控板上的 多核 CPU 分别控制网板和接口板， 使得网板及接口板上不需要设置 CPU, boootroom芯片及 flash芯片，及以太网通讯控制器，减少了路由器所需的硬件 资源， 降低了路由器的功耗。
请参阅图 1 , 为本发明实施例中多核路由器的实施例， 包括：
该多核路由器内部总线 ^^于 PCIE的总线， PCIE总线将多核路由器内部 的主控板 101与背板 102连接， 其中， PCIE是总线和接口标准。
在本发明实施例中， 主控板 101上集成 PCIE芯片 106, 该 PCIE芯片 106 包含 PCIE接口， 主控板 101通过 PCIE接口与背板 102连接。
在多核路由器的内部还包含网板 103及至少一个接口板 104, 且网板 103 与接口板 104分别采用 PCIE连接方式与背板 102连接， 以实现数据的传输。
在本发明实施例中， 网板 103及接口板 104可采用 PCIE总线分别与背板 102连接， 或者网板 103及接口板 104分别采用插拔式连接方式与背板 102上 的 PCIE插槽连接， 即将网板 103及接口板 104插入背板 102的 PCIE接口槽 位中实现连接， 使用 PCIE的方式连接时， 不需要在网板 103及接口板 104设 置以太网通信控制器， 节约硬件资源。
在主控板 101上包含多核 CPU105, 该多核 CPU105分别控制网板 103及 接口板 104, 通过主控板 101上的多核 CPU能够直接访问接口板 104及网板 103上的硬件资源， 由于在路由器内部使用多核 CPU105对网板 103及接口板 104进行管理和控制， 使得网板 103及接口板 104上不需要设置 CPU, 及用于 CPU启动的 bootroom芯片， 及用于 CPU相关配置数据保存的 flash芯片， 有 效的节约硬件资源。
在本发明实施例中， 背板 102与主控板 101、 网板 103、 接口板 104分别 连接，且背板可将接口板 104或网板 103传输的数据传输给该接口板 104或网 板 103在多核 CPU105上对应的运算内核进行处理。
在本发明实施例中， 多核 CPU105的内存的划分是根据主控板 101 , 网板 103及接口板 104的需要进行物理地址区间的划分， 以实现内存的物理隔离， 请参看图 2, 为本发明实施例中多核 CPU配置访问部署图。
在本发明实施例中， 主控板 101、 接口板 104及网板 103之间采用核间通 信机制， 使得多核 CPU105内部可以实现核间报文转发。接口板 104的映像文 件的加载由主控板 101上对应的运算内核完成，且当接口板 104复位时， 该接 口板在主控板 101上的多核 CPU105中对应的运算内核将完成该接口板代码的 重新加载。
在本发明实施例中， 通过在多核路由器的主控板上使用多核 CPU, 且多 核路由器的内部基于 PCIE总线进行通信，使得多核 CPU能够分别控制网板及 接口板， 在网板及接口板上则不需要设置 CPU、 bootroom芯片及 flash芯片， 及以太网通信控制器节约了硬件资源， 减少了路由器的功耗。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分步骤 是可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可 读存储介质中， 上述提到的存储介质可以是只读存储器， 磁盘或光盘等。
以上对本发明所提供的多核路由器，进行了详细介绍，对于本领域的一般 技术人员，依据本发明实施例的思想，在具体实施方式及应用范围上均会有改 变之处， 综上所述， 本说明书内容不应理解为对本发明的限制。

Claims

权 利 要 求
1、 一种多核路由器， 其特征在于， 所述多核路由器内部总线^ ^于 PCIE 的总线， 所述 PCIE总线将所述多核路由器内部的主控板与背板连接；
所述多核路由器内部还包含网板与至少一个接口板，所述网板及接口板分 别采用 PCIE连接方式与背板连接， 实现数据的传输；
所述主控板上包含多核中央处理器 CPU, 所述多核 CPU分别控制所述网 板及接口板。
2、 根据权利要求 1所述的多核路由器， 其特征在于， 所述主控板上集成 PCIE芯片， 所述 PCIE芯片包含 PCIE接口。
3、 根据权利要求 1所述的多核路由器， 其特征在于， 所述网板及接口板 分别采用 PCIE连接方式与背板连接包括：
所述网板及接口板分别采用 PCIE总线与所述背板连接。
4、 根据权利要求 1所述的多核路由器， 其特征在于， 所述网板及各接口 板分别采用 PCIE连接方式与背板连接包括：
所述网板及接口板分别采用插拔式连接方法与所述背板上的 PCIE接口插 槽连接。
5、 根据权利要求 1至 4任一项所述的多核路由器， 其特征在于， 所述背 板将所述接口板或所述网板传输的数据传输给所述接口板或所述网板在多核 CPU上对应的运算内核进行处理。
6、 根据权利要求 5所述的多核路由器， 其特征在于， 所述多核路由器中 的所述主控板、 接口板及网板采用核间通信机制。
7、 根据权利要求 6所述的多核路由器， 其特征在于， 所述接口板的映像 文件的加载由所述主控板上对应的运算内核完成。
8、 根据权利要求 7所述的多核路由器， 其特征在于， 所述接口板复位时， 所述接口板在所述主控板上对应的运算内核将完成所述接口板代码的重新加 载。
PCT/CN2011/075031 2011-05-31 2011-05-31 多核路由器 WO2011157138A2 (zh)

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CN103188157B (zh) * 2011-12-28 2016-06-08 迈普通信技术股份有限公司 一种路由器设备
CN102571443B (zh) * 2012-01-20 2015-04-08 华为技术有限公司 一种异常处理的方法和装置
CN103401773B (zh) * 2013-06-26 2017-04-19 杭州华三通信技术有限公司 一种实现板间通信的方法及网络设备
CN105119849B (zh) * 2015-07-21 2018-07-31 浪潮(北京)电子信息产业有限公司 一种交换机架构及应用于交换机架构的数据管理方法
CN105959090A (zh) * 2016-06-16 2016-09-21 国网信息通信产业集团有限公司 电力无线专网的业务处理方法及装置
CN106445865A (zh) * 2016-10-14 2017-02-22 上海泓戟信息科技有限公司 一种冗余计算机背板总线连接方法
CN109753460A (zh) * 2017-11-06 2019-05-14 中兴通讯股份有限公司 一种存储设备及存储系统
CN109831326B (zh) * 2019-01-25 2021-08-06 新华三技术有限公司 网络设备控制方法及网络设备
CN109600270B (zh) * 2019-01-25 2021-08-06 新华三技术有限公司 网络设备控制方法及网络设备
CN115001963B (zh) * 2022-05-05 2024-01-05 武汉光迅信息技术有限公司 基于多元配置存储通信设备的信息配置方法及装置

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CN102204185A (zh) 2011-09-28
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