WO2011149427A1

WO2011149427A1 - A circuit arrangement and a modulator

Info

Publication number: WO2011149427A1
Application number: PCT/SG2011/000193
Authority: WO
Inventors: Yong Zhong Xiong; Lei Wang; Bo Zhang; Xiaojun Yuan
Original assignee: Agency For Science, Technology And Research (A*Star)
Priority date: 2010-05-25
Filing date: 2011-05-25
Publication date: 2011-12-01
Also published as: WO2011149427A8

Abstract

Embodiment provide a circuit arrangement. The circuit arrangement includes a plurality of parallel switch elements. The switch elements are configured to switch between a first state and a second state in response to a control signal. The plurality of switch elements act as capacitive elements when they are in the first state, configuring the circuit arrangement as a band pass filter. The plurality of switch elements act as resistive elements when they are in the second state, configuring the circuit arrangement as a band stop filter.

Description

A CIRCUIT ARRANGEMENT AND A MODULATOR

[0001] The present application claims the benefit of the Singapore patent application 201003640-8 (filed on 25 May 2010), the entire contents of which are incorporated herein by reference for all purposes.

Technical Field

[0002] Embodiments relate generally to a circuit arrangement and a modulator.

Background

[0003] With the rapidly increasing of multimedia application, the communication system have developed into gigabits per second or even tenths of gigabits per second to meet the requirement of data transfer. In order to fulfill the desired speed and bandwidth, the integrated circuits are needed to operate at millimeter-wave frequency range. Silicon based technologies has aggressively extend the applications from a few gigahertz to millimeter wave, even terahertz range (>100 GHz). In these systems, a preliminary problem is how to modulate the carrier signal with very high speed data rate.

[0004] In order to modulate the carrier signal with very high speed data rate, currently, there are generally two groups of common methods. One is to directly control an oscillator in high speed (>10 Gbps data rate) millimeter wave communication system using an Amplitude-Shift-Keying (ASK) modulation method. However, this ASK modulation method is generally not suitable due to signal source isolation and stability issues. Another modulation method is to add a modulator between an oscillators and a power amplifier as shown in FIG 1. This method is intuitively more suitable for high speed (>10 Gbps) modulation system. [0005] As one of key components in communication system, an ASK modulator with high speed is required. In traditional communication system design, a switch is commonly used as an ASK modulator with different statuses: switch-on and switch-off.

[0006] Recently, some millimeter wave and sub-millimeter wave switches have been reported (cf. [1]-[12]). However, most of these switches have been implemented in III-V semiconductor process which are incompatible with silicon-based baseband circuit design for integration. On the other hand, with the downscaling of device size, the available CMOS device operation frequency becomes higher and higher. Thus, with considerations of cost and capability of integration in a whole, CMOS technology becomes a favorable candidate for millimeter wave and sub-millimeter wave system design. CMOS switch design for high speed (>10 Gbps) modulation generally faces two challenges: lossy substrate and transistor speed.

[0007] Recently, in order to overcome these challenges, many researchers reported various millimeter wave switches which developed at different frequency in silicon-based technologies from 20 GHz to 1 10 GHz (cf. [5]-[8]). In those switch designs, the shunt- series configuration is the most common topology which utilizes the series transistor and shunt transistor as signal transmission path and connection to ground, respectively. This configuration shows good performance even in gigahertz frequency range (cf. [1] and [5]). However, the signal is controlled by on/off state of the transistors, and the parasitic components of the transistors will not only affect the operation frequency of the carrier signal, the bandwidth of the carrier signal, the insertion loss, but also heavily impact on the switching speed. In this context, insertion loss refers to the loss of signal power resulting from the insertion of a device in a signal transmission line. [0008] The traveling- wave concept is commonly used for high frequency switch design to compensate the parasitic capacitance and enhance the bandwidth (cf. [6]). However, due to more distribution of parasitic components in such high frequency switch design, switch speed is limited.

[0009] In cf. [7], the on-chip impedance transformer network (ΓΓΝ) is used in 0.13- μπι CMOS switch design to extend the operation frequency up to 15 GHz and improve the power handling capacity. However, the ΓΓΝ technique was based on the high-Q on- chip components which limits the bandwidth. Moreover, for the reported CMOS switch using artificial transmission-line concept, its operating frequency is still limited within 20 GHz application range due to large slow wave loss in CMOS technology (cf. [1]). In this context, power handing capacity may be referred to as the maximum power a device may transmit.

[0010] The transmission-line integrated switches were realized in 90 nm CMOS technology (cf. [8]). Though the operating frequency is achieved up to 10 GHz, the operating speed is still a big concern.

Summary of the Invention

[0011] Various embodiments provide a circuit arrangement and a modulator which solve at least partially the above mentioned problems.

[0012] In one embodiment, a circuit arrangement is provided. The circuit arrangement may include a plurality of parallel switch elements. The switch elements may be configured to switch between a first state and a second state in response to a control signal. The plurality of switch elements may act as capacitive elements when they are in the first state, configuring the circuit arrangement as a band pass filter. The plurality of switch elements may act as resistive elements when they are in the second state, configuring the circuit arrangement as a band stop filter.

[0013] In one embodiment, a modulator is provided. The modulator may include a circuit arrangement as described herein.

[0014] It should be noted that the embodiments described in the dependent claims of the independent circuit arrangement claim are analogously valid for the corresponding modulator claim where applicable, and vice versa.

Brief Description of the Drawings

[0015] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

FIG. 1 shows a wireless communication transmitter;

FIG. 2 illustrates a circuit arrangement in one embodiment;

FIG. 3 shows a modulator in one embodiment;

FIG. 4 (a) shows a circuit arrangement according to one exemplary embodiment;

FIG. 4 (b) shows an equivalent circuit of the circuit arrangement as shown in FIG. 4 (a) when the transistors included in the circuit arrangement shown in FIG. 4 (a) are in an off state;

FIG. 4 (c) shows the equivalent function diagram of the circuit arrangement as shown in FIG. 4 (a) when the transistors included in the circuit arrangement shown in FIG. 4 (a) are in an off state; FIG. 4 (d) shows an equivalent circuit of the circuit arrangement as shown in FIG. 4 (a) when the transistors included in the circuit arrangement shown in FIG. 4 (a) are in an on state;

FIG. 4 (e) shows the equivalent function diagram of the circuit arrangement as shown in FIG. 4 (a) when the transistors included in the circuit arrangement shown in FIG. 4 (a) are in an on state;

FIG. 5 (a) illustrates an equivalent circuit of a transistor when the transistor is in an on state;

FIG. 5 (b) illustrates an equivalent circuit of a transistor when the transistor is in an off state;

FIG. 6 (a) illustrates a simplified equivalent circuit of the circuit as shown in FIG.

4 (b);

FIG. 6 (b) illustrates a simplified equivalent circuit of the circuit as shown in FIG.

4 (d);

FIG. 7 illustrates a chip microphotography 700 of the fabricated switch according to one exemplary embodiment;

FIG. 8 illustrates a diagram of the measurement result of insertion loss and isolation;

FIG. 9 (a) illustrates the time domain modulation wave-form of 135 GHz sine wave with 10 Gb/s modulation signal;

FIG. 9 (b) illustrates the frequency domain modulation wave-form of 135 GHz sine wave with 12.5 GHz modulation signal; FIG. 9 (c) illustrates the frequency domain modulation wave-form of 135 GHz sine wave with 8 GHz modulation signal;

FIG. 9 (d) illustrates the frequency domain modulation wave- form of 135 GHz sine wave with 11.3 Gbps data rate;

FIG. 10 (a) illustrates the simulation results of isolation for the circuit arrangement shown in FIG. 4 (a) when the carrier signal has a frequency of 135 GHz;

FIG. 10 (b) illustrates the simulation results of insertion loss for the circuit arrangement shown in FIG. 4 (a) when the carrier signal has a frequency of 135 GHz; and

FIG. 11 illustrates the output PldB for the circuit arrangement shown in FIG. 4 (a) when the carrier signal has a frequency of 135 GHz.

Description

[0016] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. In this regard, directional terminology, such as "top", "bottom", "front", "back", "leading", "trailing", etc, is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The following detailed description therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0017] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0018] In an embodiment, a "circuit" may be understood as any kind of a logic implementing entity, which may be special purpose circuitry or a processor executing software stored in a memory, firmware, or any combination thereof. Thus, in an embodiment, a "circuit" may be a hard-wired logic circuit or a programmable logic circuit such as a programmable processor, e.g. a microprocessor (e.g. a Complex Instruction Set Computer (CISC) processor or a Reduced Instruction Set Computer (RISC) processor). A "circuit" may also be a processor executing software, e.g. any kind of computer program, e.g. a computer program using a virtual machine code such as e.g. Java. Any other kind of implementation of the respective functions which will be described in more detail below may also be understood as a "circuit" in accordance with an alternative embodiment.

[0019] As mentioned earlier, one modulation method for modulating a carrier signal with high speed data rate is to add a modulator between oscillators and power amplifier in FIG. 1.

[0020] FIG. 1 illustrates a wireless communication transmitter 100 which may be used to modulate a carrier signal with very high speed data rate. The transmitter 100 may include a signal source 101, a modulator 102, an amplifier 103 and an antenna 104. [0021] The signal source 101 may be an oscillator configured to generate a carrier signal. The output of the signal source 101 may be input into the modulator 102 such that the carrier signal is modulated by a modulator 102. The output of the modulator 102 may be connected to the amplifier 103 which is configured to amplify the modulated signal output from the modulator 102. The output of the amplifier 103 may be connected to the antenna 104 for the transmission of the amplified modulated signal.

[0022] The modulator 102 may be an amplitude-shift-keying (ASK) modulator with high speed. In traditional communication system design, switch is commonly used as an ASK modulator while with different statuses: switch-on and switch-off.

[0023] It is commonly known that ASK is a form of modulation that represents digital data as variations in the amplitude of a carrier signal. According to ASK modulation, the amplitude of a carrier signal may vary in accordance with the bit stream, e.g. modulating signal, while keeping frequency and phase constant. The level of the amplitude may be used to represent binary logic 0s and Is. In the modulated signal, for example, logic 0 may be represented by the absent of a carrier signal, and logic 1 may be represented by the presence of the carrier signal. In this sense, ASK operates as a switch, using the presence of a carrier signal to indicate a binary logic one and the absence of the carrier signal to indicate a binary logic zero. In this context, an ASK modulator may be also referred to as a switch or a switch based modulator.

[0024] In mm-wave high speed Amplitude-Shift-Keying (ASK) modulation communication system, high speed modulator is a key component. In 0.13 μπι BiC OS technology, though its SiGe heterojunction bipolar transistor (HBT) operating cutoff frequency can reach up to 180 GHz, the data modulation circuitry is quite complicated due to the current mode of the HBT transistor, and hence the HBT is not suitable to be a candidate for switch based modulator design. In order to simplify modulation data driver circuitry, a metal-oxide-semiconductor field effect transistor (MOSFET) may be a choice. Preferably, millimeter wave carrier may be modulated with very high speed data using MOSFET transistors the cutoff operating frequency of which is limited to less 70 GHz in silicon based lossy substrate. Generally, the input return loss of a modulator is a key specification since the input return loss may heavily impact on stability of a signal source or an oscillator. Preferably, the switch has good input return loss while the switch works both in on and off states. However, in conventional switch designs such as a

transmitter/receiver (T/R) switch, only input return loss while the switch works in on- state is a design consideration, while the input return loss while the switch works in off- state is not in a design consideration. In this context, the return loss of a line may be referred to as the ratio of the power reflected back from the line to the power transmitted into the line. The return loss at the input may be called input return loss, and the return loss at output may be called output return loss.

[0025] In addition, while designers use transistor to design switch or ASK modulator for millimeter wave applications, a problem is that the transistor isolation is generally not enough for a switch which requires high isolation and low insertion loss when the operating frequency of a carrier signal is close to the cutoff frequency of transistors. Thus, transistor isolation may not be suitable to be directly used for the circuit isolation. One solution is to provide a circuit in matching and mismatching to meet the isolation requirement. However, impedance mismatching may result in poor input output return loss, which may result in source stability issue. So it is a challenge to provide a switch with high isolation as well as good input and output return loss for millimeter wave applications. In this context, switch isolation refers to an input-to-output isolation of a switch which is determined by measuring the amount of power that bleeds from the input port into the output port when the transistor connecting the two ports is off. The isolation characteristic measures how well the switch turns off (i.e. how well the switch blocks the input signal from the output signal).

[0026] Various embodiments provide a circuit arrangement which may be included in a modulator (e.g. the modulator 102 as shown in FIG. 1) and which may enable the modulator to modulate a carrier signal with high speed data rate. The circuit arrangement as described herein may provide the switch with high isolation as well as good return loss for millimeter wave applications.

[0027] FIG. 2 illustrates a circuit arrangement 200 according to one embodiment. The circuit arrangement 200 may include a plurality of parallel switch elements 201. It is noted that FIG. 2 shows the two parallel switch elements 201 only for illustration purpose, and there may be any number of parallel switch elements 201. The plurality of circuit arrangement 201 may be configured to switch between a first state and a second state in response to a control signal. The plurality of switch elements 201 may act as capacitive elements when they are in the first state, configuring the circuit arrangement 200 as a band pass filter. The plurality of switch elements 201 may act as resistive elements when they are in the second state, configuring the circuit arrangement as a band stop filter.

[0028] In this context, a band pass filter may refer to a device that passes frequencies within a certain range and rejects or attenuates frequencies outside that range. A band stop filter may refer to a filter that passes most frequencies unaltered, but attenuates those in a specific range to very low levels.

[0029] In one embodiment, in other words, for example, the circuit arrangement 200 may be included in a modulator (e.g. the modulator 102 as shown in FIG. 1) such that a carrier signal may be modulated by a modulating signal in the modulator. The modulator may be configured, for example, to perform a Amplitude-Shift-Keying (ASK) modulation of the carrier signal. For example, the ASK may operate as a switch, using the presence of the carrier signal to indicate a binary logic one and the absence of the carrier signal to indicate a binary logic zero. In one embodiment, the circuit arrangement 200 may include a plurality of switch elements 201 which are connected to each other in a parallel manner in the circuit arrangement 200. Each switch element 201 may be configured to switch between a first state and a second state in response of a control signal. For example, such a control signal may be a modulating signal. Each switch element 201 may act as a capacitive element when the switch element is in the first state, and each switch element 201 may act as a resistive element when the switch element is in the second state. When the plurality of switch elements 201 are switched to the first state upon the receiving of the control signal, the circuit arrangement 200 may function as a band pass filter. When the plurality of switch elements 201 are switched to the second state upon the receiving of the control signal, the circuit arrangement 200 may function as a band stop filter. For example, when the circuit arrangement 200 functions as a band pass filter, the circuit arrangement 200 may allow the carrier signal to pass through the circuit arrangement 200; while when the circuit arrangement 200 functions as a band stop filter, the circuit arrangement 200 may stop or attenuate the carrier signal to pass through the circuit arrangement 200. That is, the circuit arrangement 200 may operate as a switch which is configured to either allow or disallow the carrier signal to pass, thereby modulating the carrier signal. The circuit arrangement 200 may be included in a modulator which receives the carrier signal, and the control signal may control the plurality of switching elements 201 in such a way that, in the output of the modulator, the presence of the carrier signal may represent the logic 1 or 0, and the absence of the carrier signal may represent the logic 0 or 1, for example.

[0030] In one embodiment, each switch element 201 may include a transistor. For example, each switch element 201 may be or may include a metal-oxide-semiconductor field effect transistor (MOSFET), e.g. a bipolar complementary metal-oxide- semiconductor (BiCMOS) MOSFET. In an alternative embodiment, each switch element may include or may be a bipolar junction transistor (BJT). For example, it is commonly known that for a MOSFET, the current between a drain terminal and a source terminal may be turned on or off by the voltage applied at the gate of the MOSFET. When the current is turned off, the transistor may be referred to be in a first state; when the current is turned on, the transistor may be referred to be in a second state. For example, when each transistor is in a first state, the transistor may be off such that the transistor may act as a capacitive element. When each transistor is in a second state, the transistor may be on such that the transistor may act as a resistive element. The control signal may for example be connected to the gate of each transistor so as to control the on or off of each transistor.

[0031] In one embodiment, the circuit arrangement 200 may further include at least one parallel arrangement of an inductive element and a capacitive element coupled between two adjacent switch elements. The at least one parallel arrangement may increase power handing capacity and matching bandwidth. For example, the inductive element may include an inductor. The capacitive element may include a capacitor. In a further embodiment, each switch element 201 may include a transistor and the at least one parallel arrangement may be coupled between drain terminals of two adjacent transistors. This embodiment if further illustrated with reference to FIG. 4 (a).

[0032] In a further embodiment wherein each switch element 201 may include a transistor, in one embodiment, a source terminal of each transistor may be connected to a ground reference point, and a gate terminal of each transistor may be configured to receive the control signal. In this embodiment, accordingly, when a drain terminal of a transistor is connected to a signal transmission path of a carrier signal, the carrier signal may be shunted to the ground reference point when the transistor is in the second state, i.e. when the transistor is on. In such a case, there may be no presence of the carrier signal at the output of the circuit arrangement 200, and the absence of the carrier signal may represent a logic 0, for example. Similarly, when a drain terminal of a transistor is connected to a signal transmission path of a carrier signal, and when all the transistors are in an off state, the carrier signal may pass through the transmission path without being shunted to the ground reference point.

[0033] In one embodiment, the circuit arrangement 200 may further include a plurality of inductive elements, wherein each inductive element may be connected in parallel with a corresponding switch element 201. The plurality of inductive elements may increase power handing capacity and matching bandwidth. In the embodiment wherein each switch element 201 may include a transistor, in one embodiment, one end of each inductive element of the plurality of inductive elements may be connected to the drain terminal of the corresponding transistor and the other end of each inductive element of the plurality of inductive elements may be connected to the ground reference point.

[0034] In one embodiment, each inductive element may include an inductor.

[0035] In one embodiment, each capacitive element may include a capacitor.

[0036] FIG. 3 illustrates a modulator 310 in one embodiment.

[0037] The modulator 310 may include a circuit arrangement 200 as described herein used as a high frequency switch. That is, the circuit arrangement 200 may be used as a switch which is configured to switch between a first state and a second state at high frequencies. Accordingly, a high speed modulation (e.g. > 10 Gbps) may be achieved. In the first state, the circuit arrangement 200 may function as a band pass filter. In the second state, the circuit arrangement 200 may function as a band stop filter. The modulator 300 may for example include an input 301 which is configured to receive a carrier signal. The modulator 300 may further include an output 302 which is configured to output a modulated signal. The modulation of the carrier signal may be achieved by the circuit 200, which may be configured to switch between the first state and the second state. When the circuit arrangement 200 functions as a band pass filter, the carrier signal may pass through the circuit arrangement 200 and be output from the output 302. The presence of the carrier signal at the output 302 may represent a logic 1, for example. When the circuit arrangement functions as a band stop filter, the carrier signal may not be able to pass through the circuit arrangement 200, and there may be absence of the carrier signal a the output 302. The absence of the carrier signal at the output 302 may represent a logic 0. [0038] In one embodiment, the control signal may be a modulating signal.

[0039] In one embodiment, the circuit arrangement 300 may include at least one parallel arrangement of an inductive element and a capacitive element disposed along a signal transmission path. The signal transmission path may carry a signal to be modulated with the modulating signal. The signal to be modulated may be referred to as a carrier signal, for example.

[0040] In one embodiment, each switch element 201 may include a transistor, and the drain terminal of each transistor may be connected to the signal transmission path.

[0041] FIG. 4 (a) illustrates a circuit diagram of a circuit arrangement 400 according to one exemplary embodiment. The circuit arrangement 400 may for example be included in a modulator for modulating a carrier signal. For illustration purpose, the carrier signal may have a frequency of 135 GHz. The circuit arrangement 400 may include a signal transmission path which carries the carrier signal with a modulating signal. The circuit arrangement 400 may include an input 421 for receiving the carrier signal, and an output 422 for outputting the modulated carrier signal.

[0042] The circuit arrangement 400 includes three parallel transistors (switch elements) Tl, T2 and T3. The transistors Tl, T2 and T3 may for example be MOSFET. Each transistor of transistors Tl, T2 and T3 may be configured to switch between a first state and a second state in response to a control signal. For example, the control signal may be a modulating signal, and may be received at the gate gl of transistor Tl, the gate g2 of transistor T2, the gate g3 of transistor T3, respectively. The first state of a transistor may be the state when a transistor is off, and the second state may be the state when a transistor is on. When a transistor is off, the transistor acts as a capacitive element; while when the transistor is on, the transistor acts as an inductive element. This is further illustrated with reference to FIG. 5 (a) and FIG. 5 (b). A source terminal si of transistor Tl, a source terminal s2 of transistor T2, and a source tenninal s3 of transistor T3 may each be connected to a ground reference point 450. A drain terminal dl of transistor Tl, a drain terminal d2 of transistor T2, and a drain terminal of transistor T3 may each be connected to the signal transmission path. The circuit arrangement 400 may function as a switch, i.e. when the transistors Tl, T2 and T3 are off, the circuit arrangement 400 may function as a band pass filter, and when the transistors Tl, T2 and T3 are on, the circuit arrangement 400 may function as a band stop filter. The transistors Tl, T2 and T3 may serve to increase the input-to-output isolation of the switch. When the transistors Tl, T2, and T3 are in an off state, the circuit arrangement 400 may be referred to as in a first state and function as a band pass filter, and when the transistors Tl, T2 and T3 are in an on state, the circuit arrangement 400 may be referred to as in a second state and function as a band stop filter. When the circuit arrangement 400 are changing from the second state to the first state, the circuit isolation may change from high (~20 dB) to low (~2 dB which is caused by insertion loss). When the circuit arrangement 400 changes the state between the first state and the second state with high speed, then circuit arrangement 400 may function as a high speed switch.

[0043] The circuit arrangement 400 further includes a parallel arrangement 411 of an inductor LI (inductive element) and a capacitor CI (capacitive element) coupled between two adjacent transistors Tl and T2. The parallel arrangement 411 is coupled between the drain terminal dl of transistor Tl and the drain tenninal d2 of transistor T2. [0044] The circuit arrangement 400 further includes a parallel arrangement 412 of an inductor L2 (inductive element) and a capacitor C2 (capacitive element) coupled between two adjacent transistors T2 and T3. The parallel arrangement 412 is coupled between the drain terminal d2 of transistor T2 and the drain terminal T3 of transistor T3.

[0045] Each of parallel arrangements 411 and 412 may be disposed along the signal transmission path.

[0046] The circuit arrangement 400 further includes three inductors L3, L4 and L5 (inductive elements) wherein each inductor of inductors L3, L4 and L5 is connected in parallel with a corresponding transistor (switch element). That is, the inductor L3 is connected in parallel with a corresponding transistor Tl ; the inductor L4 is connected in parallel with a corresponding transistor T2; and the inductor L5 is connected in parallel with a corresponding transistor T3. One end of each inductor of inductors L3, L4 and L5 is connected to the drain terminal of the corresponding transistor and the other end of each inductor of inductors L3, L4 and L5 is connected to the ground reference 450.

[0047] FIG. 4 (b) illustrates the equivalent circuit of circuit arrangement 400 when the modulating signal controls each transistor of transistors Tl, T2 and T3 to be in an off state. As can be seen, when each transistor of transistors Tl, T2 and T3 is off, each transistor of transistors Tl, T2 and T3 acts as a capacitive element (e.g. a capacitor). On is the equivalent capacitance of the transistor Tl when the transistor Tl is in an off state; CT2 is the equivalent capacitance of the transistor T2 when the transistor T2 is in an off state; and On is the equivalent capacitance of the transistor T3 when the transistor T3 is in an off state. The circuit arrangement 400 in FIG. 4 (b) functions as a band pass filter. That is, the carrier signal of 135 GHz passes through the transmission path and is output from the output 422.

[0048] FIG. 4 (c) illustrates the function of the circuit arrangement 400 when each transistor of transistors Tl, T2 and T3 are in an off state, i.e. the circuit arrangement 400 functions as a band pass filter which allows the carrier signal received at the input 421 to pass through the circuit arrangement 400.

[0049] FIG. 4 (d) illustrates the equivalent circuit of circuit arrangement 400 when the modulating signal controls each transistor of transistors Tl, T2 and T3 to be in an on state. As can be seen, when each transistor of transistors Tl, T2 and T3 is on, each transistor of transistors Tl, T2 and T3 acts as a resistive element (e.g. a resistor). Rn is the equivalent resistance of transistor Tl when the transistor Tl is in an on state; is the equivalent resistance of transistor T2 when the transistor T2 is in an on state; and RT₃ is the equivalent resistance of transistor T3 when the transistor T3 is in an on state. The circuit arrangement 400 in FIG. 4 (d) functions as a band stop filter. That is, the carrier signal of 135 GHz is shunted to the ground reference point 450 when the transistors Tl, T2 and T3 are controlled to be in an on state, and there is an absence of carrier signal at the output 422, i.e. the carrier signal can not pass through from input 421 to output 422.

[0050] FIG. 4 (e) illustrates the function of the circuit arrangement 400 when each transistor of transistors Tl, T2 and T3 are in an on state, i.e. the circuit arrangement 400 functions as a band stop filter which does not allow the carrier signal received at the input 421 to pass through the circuit arrangement 400. [0051] In order to illustrate the working mechanism of the circuit arrangement, e.g. circuit 400, as described herein, the MOSFETs small-signal equivalent circuits in both the on and off states as shown in FIG. 5 (a) and FIG. 5 (b).

[0052] FIG. 5 (a) illustrates an equivalent circuit 501 of a transistor when the transistor is in an on state.

[0053] As shown in FIG. 5 (a), when a transistor is in an on state, the equivalent circuit 501 includes, in parallel configuration, an on-resistance RON, a drain-source resistance RD_S in series with on-state bulk capacitance C_bui_k-ON, and parasitic capacitance of gate-drain CD_G and gate-source CS_G- It is noted that the on state resistance (R_ON) dominates the behavior of on state transistor when the transistor is in an on state.

[0054] FIG. 5 (b) illustrates an equivalent circuit of a transistor when the transistor is in an off state.

[0055] As shown in FIG. 5 (b), the off-state transistor equivalent circuit 502 is consisted of, in parallel configuration, an off state drain-source capacitance CDS-OFF, drain-source resistance RD_S in series with off-state bulk capacitance C_bui_k-_OFF, and parasitic capacitance of gate-drain CD_G and gate-source CSG- The equivalent circuit 502 shows the off state capacitance which includes CDS-OFF, CDG, CSG and Cbuik-OFF dominates the behavior of off state transistor, and thus may have effects on input return loss and isolation, especially at very high operating frequency.

[0056] In one embodiment, the capacitances as shown in the equivalent circuit of a transistor in FIG. 5 (a) and FIG. 5 (b) may be used to form switches which may switch between a band pass state and a band stop state according to the operating state of the transistor, and the input return loss may be hold in a required range, e.g. an input return loss of > 10 dB.

[0057] In an off state of a transistor, the transistor works as an equivalent capacitor, which consists of CDS-OFF, CDG, CSG, RDS and Cbuik-oFF as shown in FIG. 5 (b). So when the transistors Tl, T2 and T3 are in an off state, the function of whole circuit 400 shown in FIG. 4 (a) is approximate to a band pass filter at the operating frequency (e.g. FIG. 4 (b))-

[0058] FIG. 6 (a) shows a simplified equivalent circuit 601 of the circuit 400 shown in FIG. 4 (b) wherein all the transistors Tl to T3 in the circuit 400 are in an off state.

[0059] The circuit arrangement 601 may include a signal transmission path which carries the carrier signal with a modulating signal. The circuit arrangement 601 may include an input 421 for receiving the carrier signal, and an output 422 for outputting the modulated carrier signal.

[0060] The circuit arrangement 601 includes two parallel transistors T4 and T5. When the transistors T4 and T5 are off, the transistor T4 acts as a capacitive element C_T4, and the transistor T5 acts as a capacitive element CT_S. The capacitive elements Cj₄ and Cj5 may be seen to correspond to transistors Tl, T2 and T3 in the circuit 400 shown in FIG. 4 (b).

[0061] The circuit arrangement 601 further includes a parallel arrangement 611 of an inductor L6 (inductive element) and a capacitor C3 (capacitive element) coupled between two adjacent transistors T4 and T5. The parallel arrangements 611 may be disposed along the signal transmission path. The parallel arrangement 611 may be seen to correspond to the parallel arrangements 411 and 412 in the circuit 400 shown in FIG. 4 (b). [0062] The circuit arrangement 601 further includes two inductors L7 and L8 (inductive elements) wherein each inductor of inductors L7 and L8 is connected in parallel with a corresponding transistor (switch element). That is, the inductor L7 is connected in parallel with a corresponding transistor T4; and the inductor L8 is connected in parallel with a corresponding transistor T5. One end of each inductor of inductors L7 and L8 is connected to the drain terminal of the corresponding transistor and the other end of each inductor of inductors L7 and L8 is connected to the ground reference 450. The inductors L7 and L8 may be seen to correspond to the inductors L3, L4 and L5 in the circuit 400 shown in FIG. 4 (b).

[0063] The transmission matrix of the circuit 400 shown in FIG. 4 (b) may be calculated as follows:

-3

"2 , (4)

C₃(l+S²Z₁C_n)

where s = y^'<y , Cji and Cnare circuit elements as mentioned in Fig. 4(b), respectively; Li, L₂, and L₃ are inductance of the inductors LI, L2, and L3, respectively; and when the transistors Tl, T2 and T3 are in an off state, C3=C₁=C2 wherein Ci is capacitance of the capacitor CI, and C₂ is capacitance of the capacitor C2 as shown in FIG. 4 (b). [0064] FIG. 6 (b) shows a simplified equivalent circuit 602 of the circuit 400 shown in FIG. 4 (d) wherein all the transistors in the circuit 400 are in an on state.

[0065] The circuit arrangement 602 may include a signal transmission path which carries the carrier signal with a modulating signal. The circuit arrangement 602 may include an input 421 for receiving the carrier signal, and an output 422 for outputting the modulated carrier signal.

[0066] The circuit arrangement 602 includes two parallel transistors T4 and T5. When the transistors T4 and T5 are on, the transistor T4 acts as an inductive element RT₄, and the transistor T5 acts as an inductive element R s- The inductive elements RT₄ and RT5 may be seen to correspond to transistors Tl, T2 and T3 in the circuit 400 shown in FIG. 4 (d).

[0067] The circuit arrangement 602 further includes a parallel arrangement 611 of an inductor L6 (inductive element) and a capacitor C3 (capacitive element) coupled between two adjacent transistors T4 and T5. The parallel arrangements 611 may be disposed along the signal transmission path. The parallel arrangement 611 may be seen to correspond to the parallel arrangements 41 1 and 412 in the circuit 400 shown in FIG. 4 (d).

[0068] The circuit arrangement 602 further includes two inductors L7 and L8 (inductive elements) wherein each inductor of inductors L7 and L8 is connected in parallel with a corresponding transistor (switch element). That is, the inductor L7 is connected in parallel with a corresponding transistor T4; and the inductor L8 is connected in parallel with a corresponding transistor T5. One end of each inductor of inductors L7 and L8 is connected to the drain terminal of the corresponding transistor and the other end of each inductor of inductors L7 and L8 is connected to the ground reference 450. The inductors L7 and L8 may be seen to correspond to the inductors L3, L4, and L5 in the circuit 400 shown in FIG. 4 (d).

[0069] The transmission matrix of the circuit 400 as shown in FIG. 4 (d) may be calculated as follows:

_B ^+S'^ (6,

1 + SC₃ (R_ri + R_T2 ) + S²C₃ m+ L₂ + L₃)

SC₃(R_n + + SL₂)

(7)

S (R_n +5Z,)

where s = )ω , RTI and RT2 are circuit elements as mentioned in Fig. 4(d), respectively; Li, L₂, and L₃ are inductance of the inductors LI, L2, and L3, respectively; and C₃=Ci=C₂ wherein Ci is capacitance of the capacitor CI, and C₂ is capacitance of the capacitor C2 as shown in FIG. 4 (d).

(0070] Based on the above equations (1) to (8), a person skilled in the art would be able to implement a switch for high frequency and high speed modulation, and the switch may be controlled by controlling the on or off state of the transistors, respectively.

[0071] In an exemplary embodiment, the circuit arrangement 400 as shown in FIG. 4 (a) may be used as a switch for 135 GHz 10 Gbps signal modulation. The circuit arrangement 400 may be included in a switch based modulator. From the isolation point of view, three shunt stages (e.g. three parallel transistors) may be employed for broadband matching and higher power handling capacity. Due to the fact that there is no active device (e.g. a transistor) in the series signal transmission path, the power handling capability may be improved. There is also no transistor channel resistance loss in the signal transmission path, and hence the insertion loss may be improved too. In one embodiment, for the accuracy of inductor value in D-band circuit design (D-band is the range of radio frequencies from 110 GHz to 170 GHz in the electromagnetic spectrum, which is equal to wave lengths between 1.8 mm and 2.7 mm), all inductors in the circuit arrangement as described herein (e.g. in the circuit arrangement 200 and 400) may be implemented by thin-film micro-strip lines. The width may be chosen to be 2 μπι and the top thickest metal may be used to minimize insertion loss (thickness is 3 μιη). The size of shunt transistors (e.g. transistors Tl, T2 and T3 as shown in FIG. 4 (a)) is important for whole circuit performance. As a trade-off between insertion losses, isolation, input return loss and power handling capability, the transistor Tl, T2 and T3 may be set to 7 μπι x 0.13 μπι x 7 fingers, 42 μπι x 0.13 μπι x 42 fingers and 7 μπι x 0.13 μπι x 42 fingers, respectively. In addition, the circuit arrangement as described herein may not only be used for modulation, but may also be used for transmitter/receiver (T/R) switch, e.g. at 135 GHz.

[0072] Performance of the switch based modulator as described herein has been tested. The switch based modulator as tested includes a circuit arrangement as illustrated in FIG. 4 (a). The capacitance of a transistor is depended on the size of the transistor. The size of transistor Tl, T2 and T3 used in the test are set to 7 μηι 0.13 μπι ^χ 7 fingers, 2 μηι x 0.13 μπι ^χ 42 fingers and 7 μπι 0.13 μπι ^χ 7 fingers, respectively. The inductors are with transmission lines, 330um , 220um and 330um for L3, L4 and L5 respectively. The LI and L2 are with the transmission line of 150 μπι.

[0073] The switch based modulator was designed and fabricated in commercial foundry with 0.13 μιη SiGe BiCMOS process. The on-wafer measurements were performed using a set of high performance network analyzers and spectrum analyzers up to 170 GHz with a ground-signal-ground (G-S-G) probe. The measurement equipments were calibrated by using line-reflect-reflect-match (LR M) calibration with a ceramic standard substrate.

[0074] FIG. 7 shows the chip microphotography 700 of the fabricated switch that is used for the test. The active area of whole switch modulator including the test pads occupied area is 500 μπι x 420 μηι.

[0075] The control voltage is chosen to be 0V/2V. The measurement was performed from 110 GHz to 170 GHz.

[0076] FIG. 8 shows a diagram 800 of the measurement result after de-embedding of input output pads [13] of insertion loss and isolation. The solid lines shows the results when the transistors are in an off state, and the dotted lines show the results when the transistors are in an on state. Line 801 shows the insertion loss when the transistors are in an off state. Line 802 shows the insertion loss when the transistors are in an on state. Line 803 and line 804 show the input and output return loss respectively when the transistors are in an on state. Line 805 and 806 show the input and output return loss respectively when the transistors are in an off state. The lines in the circled area 810 indicated that the switch may transmit the carrier signal. The lines in the circled area 820 indicated that the carrier signal is blocked. The measured insertion loss and isolation are within ~5.0 dB and better than 12 dB over 120 GHz to 140 GHz, respectively. Both input/output return losses in on/off states were mostly below -12 dB over 120 GHz to 140 GHz. At 135 GHz, the input/output return loss is -16.3 dB and -17dB in on/off state, respectively. The power handling capability was measured, and no obvious compression was observed up the limited maximum input power of measurement equipment of +2 dBm for both on/off and results indicated the PidB is about 6 dBm which is generally enough for modulation purpose. In this context, in a linear range, with each increment of 1 db of input power, the insertion loss is with certain number. If there is compression, the insertion loss is increased when the input power is increased. PldB refers to the 1 dB compression point wherein the 1 dB more insertion loss increases when input power increases. Input PldB refers to the input power in dBm at the 1 dB compression point, and output PldB refers to the output power in dBm at the 1 dB compression point. Input PldB and output PldB may be used as an indicator of the network linearity. A relatively larger value of the input PldB or output PldB indicates a relatively better network linearity.

[0077] FIG. 9 (a) shows the results for high speed modulated signal in time domain, i.e. the time domain modulation wave-form of 135 GHz sine wave with 10 Gb/s modulation signal. The modulation index is 20 dB.

[0078] FIG. 9 (b) shows the results for high speed modulated signal in frequency domain, i.e. frequency domain modulation wave-form of 135 GHz sine wave with 9 GHz modulation sine wave signal.

[0079] FIG. 9 (c) shows the results for high speed modulated signal in frequency domain, i.e. frequency domain modulation wave-form of 135 GHz sine wave with 8 GHz modulation sine wave signal. [0080] FIG. 9 (d) shows the results for high speed modulated signal in frequency domain, i.e. frequency domain modulation wave-form of 135 GHz sine wave with 11.3 Gbps data rate.

[0081] FIG. 10 (a) illustrates the simulation results 1010 of isolation for the circuit arrangement 400 shown in FIG. 4 (a) when the carrier signal has a frequency of 135 GHz. The horizontal axis represents the tested frequency range between 100 GHz and 200 GHz, and the vertical axis represents the return loss in dB. Line 1011 shows the return loss when the transistors are in an off state, and line 1012 shows the return loss when the transistors are in an on state.

[0082] FIG. 10 (b) illustrates the simulation results 1020 of insertion loss for the circuit arrangement 400 shown in FIG. 4 (a) when the carrier signal has a frequency of 135 GHz. The horizontal axis represents the frequency range between 100 to 200 GHz, and the vertical axis represents the insertion loss in dB. Line 1021 is the result when the transistors in the circuit arrangement 400 are in an off state, and line 1022 is the result when the transistors in the circuit arrangement 400 are in an on state. It can be seen from FIG. 10 (b) that for a carrier signal with 135 GHz, the isolation is larger than 20 dB, and the insertion loss is lower than 1.8 dB when the transistors are off.

[0083] FIG. 11 illustrates the output PldB for the circuit arrangement 400 as shown in FIG. 4 (a) when the transistors Tl to T3 are in an off state, i.e. when the switch functions as a band pass filter. The horizontal axis is the input power in dBm, and the vertical axis represents the output power in dBm. The carrier signal is set to be 135 GHz.

[0084] In various embodiments, a circuit arrangement which may be used in a modulator and which may reduce insertion loss and to increase modulation index using CMOS or bipolar junction transistor (BJT) is provided. A switch based modulator has been provided which may switch between the working function of a band pass filter and a band stop filter at e.g. 135 GHz band. Higher isolation and low loss may be achieved compared to conventional switch.

[0085] In various embodiments, the impedance changes caused by change of state of a transistor (e.g. from on state to off state) may be used to design a modulator. That is, while transistors are in on state, transistors may be simplified to a resistance, and the modulator as described herein may function as a band stop filter. While transistors are in off state, transistors may be simplified to a capacitance, and the modulator as described herein may function as a band pass filter. The modulator in various embodiments may work on two states with good return loss and high isolation with low loss.

[0086] In various embodiments, a switch-based modulator has been provided which may work for above 10 Gbps D-band communication system and may be implemented with 0.13 μπι MOSFET. With MOSFET working status changing between off-state to on-state, the modulation equivalent circuit is correspondingly converted between a band pass filter to a band stop filter. The modulation circuit may maintain high isolation as well as a constant input return loss which minimizes its input impedance variation, and furthermore keeps signal source output with higher stability. The switch-based modulator as described herein may exhibit a measured insertion loss of less than about 4.7 dB and isolation of more than about 13 dB over 125 GHz to 145 GHz. The measured input Ρ_1(¾ is at about 6 dBm at 135 GHz.

[0087] In various embodiments, a millimeter wave switch is provided for high speed (e.g. above 10 Gbps) modulation. In order to maintain constant impedance for signal source output, while modulating on or off states of the transistors, the modulator input impedance (input return loss) may be with no changes while the transistors are in on or off states. The switch may employ the synthetic filter technique which converts the switch between band-pass and band-stop filter states at operating frequency range with stable return loss at both on and off states, and 0.13μηι BiCMOS MOSFET transistors may be implemented. The circuit arrangement may be applied for high speed

transistor/receiver (T/R) switch as well as a high speed modulator.

[0088] In various embodiments, a circuit arrangement which may function as a switch structure for high frequency and high speed modulation system is provided. The high frequency switch may be commonly used as a modulator, since the switch has two states which may be used for signal controlling. In conventional switch design, the input return loss which may badly impact the stability of oscillator is generally not carefully considered. This problem has been solved by an artificial filter technique as described herein. In various embodiments, a D-band switch for 135 GHz 10 Gbps signal modulation may be designed and fabricated in low cost 0.13 μπι CMOS process. The fabricated switch with insertion loss of less than 5 dB over 110 GHz to 140 GHz, isolation of larger than 12 dB from 110 GHz to 140 GHz, and input PldB of +6 dBm demonstrate the D- band switch in CMOS technology with competitive performance. Meanwhile, the modulation wave-form demonstrate the capability of this switch for 135 GHz lOGbps signal modulation. Moreover, the comparison with previous switches, this switch may also be used for high frequency T/R switch application. So the circuit arrangement may pave the way for design of high frequency switch and modulator with competitive performance in low cost CMOS technology. [0089] In various embodiment, the impedance of the circuit arrangement and the modulator as described herein may be changed upon the change of the state of the transistors included in the circuit arrangement or the modulator, thereby enabling the circuit arrangement or modulator switch between a band pass filter and a band stop filter. Accordingly, high isolation of 20 dB (or modulation index) with low loss of 1.8 dB (due to passive path at above 100 GHz) at 135 GHz, and good input and output return loss (<- 20 dB) may be achieved. The circuit arrangement as described herein may be used for high speed modulation up to 10 Gbps. In addition, the circuit arrangement as described herein has high power handing capability. The circuit involved in the circuit arrangement as described herein is also relatively simple.

[0090] The circuit arrangement and modulator as described herein may be used in high data rate wireless applications and switching, for example.

[0091] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

[0092] The following references have been cited in the description.

[1] Y. Jin and C. Nguyen, "Ultra-compact high-linearity high-powerfully integrated DC- 20-GHz 0.18^mCMOS T/R switch," IEEE Trans. Microw. Theory Tech., vol.55, no.l, pp.30-36, Jan.2007. [2] K. Y. Lin, W. H. Tu, P. Y. Chen, H. Chen, H. Wang, and R. B. Wu, "Millimeter- wave MMIC passive HEMT switches using traveling-wave concept," IEEE Trans. Microw. Theory Tech., vol.52, no. 8, pp. 1798-1808, Aug. 2004.

[3] P. Park, D. H. Shin, C. P. Yue, "High-Linearity CMOS T/R Switch Design Above 20 GHz Using Asymmetrical Topology and AC-Floating Bias " IEEE Trans. Microw. Theory Tech., vol.57, no.4, pp.948-956, Apr.2009.

[4] Q. Li, Y. P. Zhang, K. S. Yeo, W. M. Lim, "16.6- and 28-GHz Fully Integrated CMOS RF Switches With Improved Body Floating " IEEE Trans. Microw. Theory Tech., vol.56, no.2, pp.339-345, Feb.2008.

[5] A. Tomkins, P. Garcia, S. P. Voinigescu, "A 94 GHz SPST switch in 65nm bulk CMOS," in Proc. IEEE CSIC Symp. , Oct.2008, pp. 1-4.

[6] S. F. Chao, H. Wang, C. -Y. Su, J. G. J. Chern, "A 50 to 94-GHz CMOS SPDT switch using traveling- wave concept," IEEE Microw. Wireless Compon. Lett. , vol. 17, no. 2, pp. 130-132, Feb.2007.

[7] Z. Li and K. K. O, "15-GHz fully integrated nMOS switches in a 0.13-μιη CMOS process," IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2323-2328, Nov. 2005.

[8] R. -B. Lai, J. -J. Kuo, H. Wang, "A 60-110 GHz Transmission-Line Integrated SPDT Switch in 90 nm CMOS Technology" IEEE Microw. Wireless Compon. Lett. , vol. 20, no. 2, pp. 85-87, Feb.2010.

[9] C. M. Ta, E. Skafidas, R. J. Evans, "A 60-GHz CMOS transmit/receive switch," in IEEE RFIC Symp. Dig. , Jun.2007, pp. 725-728.

[10] Y. A. Atesal, B. Cetinoneri, G. M. Rebeiz, "Low-loss 0.13-μιη CMOS 50-70 GHz SPDT and SP4T Switches" in IEEE RFIC Symp. Dig. , Jun.2009, pp. 43-46. [11] B. -W. Min, G. M. Rebeiz, "Ka-Band Low-Loss and High-Isolation Switch Design in 0.13-μιη CMOS" IEEE Trans. Microw. Theory Tech., vol.56, no.6, pp.l364- 1371, Jun.2008.

[12] I. Kallfass, S. Diebold, H. Massler, S. Koch, M. Seelmann-Eggebert A. Leuther, "Multiple-throw millimeter- wave FET switches for frequencies from 60 up to 120 GHz " in Proc. 38^th European Microwave Conference, Amsterdam, pp. 1453—1456, Oct.2008.

[13] A.Issaoun, Y. -Z. Xiong, J. Shi, J. BrinkhofF, F. Lin, "On the Deembedding Issue of CMOS Multigigahertz Measurements," IEEE Trans. Microw. Theory Tech., vol. 55, no. 9, pp. 1813-1823, Sep. 2007

Claims

Claims What is claimed is:

1. A circuit arrangement, comprising:

a plurality of parallel switch elements, the switch elements configured to switch between a first state and a second state in response to a control signal;

wherein the plurality of switch elements act as capacitive elements when they are in the first state, configuring the circuit arrangement as a band pass filter, and wherein the plurality of switch elements act as resistive elements when they are in the second state, configuring the circuit arrangement as a band stop filter.

2. The circuit arrangement of claim 1,

wherein each switch element comprises a transistor.

3. The circuit arrangement of claims 1 or 2,

further comprising at least one parallel arrangement of an inductive element and a capacitive element coupled between two adjacent switch elements.

4. The circuit arrangement of claim 3,

wherein the at least one parallel arrangement is coupled between drain terminals of two adjacent transistors.

5. The circuit arrangement of any one of claims 2 to 4, wherein a source terminal of each transistor is connected to a ground reference point, and a gate terminal of each transistor is configured to receive the control signal.

6. The circuit arrangement of any one of claims 1 to 5,

further comprising a plurality of inductive elements, each inductive element being connected in parallel with a corresponding switch element.

7. The circuit arrangement of claim 6,

wherein each switch element comprises a transistor, and

wherein one end of each inductive element of the plurality of inductive elements is connected to the drain terminal of the corresponding transistor and the other end of each inductive element of the plurality of inductive elements is connected to the ground reference.

8. The circuit arrangement of any one of claims 3, 4, 6 and 7,

wherein each inductive element comprises an inductor.

9. The circuit arrangement of any one of claims 1 to 8,

wherein each capacitive element comprises a capacitor.

10. A modulator comprising a circuit arrangement as claimed in any one of claims 1 to 9 used as a high frequency switch.

11. The modulator of claim 10,

wherein the control signal is a modulating signal.

12. The modulator of claims 10 or 11,

wherein the circuit arrangement comprises at least one parallel arrangement of an inductive element and a capacitive element disposed along a signal transmission path.

13. The modulator of claim 12,

wherein each switch element comprises a transistor, and wherein the drain terminal of each transistor is connected to the signal transmission path.

14. The modulator of claims 12 or 13,

wherein the signal transmission path carries a signal to be modulated with the modulating signal.