WO2011148440A1

WO2011148440A1 - Solid-state image pickup device, semiconductor integrated circuit device, camera, and signal processing method

Info

Publication number: WO2011148440A1
Application number: PCT/JP2010/006842
Authority: WO
Inventors: 繁孝春日; 基範石井; 剛久加藤; 三蔵鵜川; 雄介岡田
Original assignee: パナソニック株式会社
Priority date: 2010-05-25
Filing date: 2010-11-24
Publication date: 2011-12-01
Also published as: JP2011250039A

Abstract

Provided are a solid-state image pickup device provided with an A/D conversion unit capable of reducing a linearity error and a differential linearity error in AD conversion and maintaining data continuity, and the like. The solid-state image pickup device is provided with an image pickup unit (10), an A/D conversion unit (70) for converting a pixel signal from the image pickup unit (10) into a digital signal, and a calibration unit (100) for performing calibration on the A/D conversion unit (70). The A/D conversion unit (70) comprises a reference voltage generation unit (40) for generating a plurality of reference voltages, a high-order bit conversion unit (20) for specifying a voltage section in which the pixel signal is included from among a plurality of voltage sections with the respective plurality of reference voltages as the basic points thereof, and a low-order bit conversion unit (30) for converting the difference voltage between the reference voltage that is the basic point of the specified voltage section and the pixel signal into the digital signal. The calibration unit (100) calibrates the plurality of reference voltages in the plurality of voltage sections with the respective reference voltages as the basic points thereof in a plurality of horizontal scanning periods in the beginning of a frame.

Description

Solid-state imaging device, semiconductor integrated circuit device, camera, and signal processing method

The present invention relates to a solid-state imaging device, a semiconductor integrated circuit device, a camera, and a signal processing method, and particularly to a solid-state imaging device including an AD converter that converts an analog signal obtained by photoelectric conversion into a digital signal.

In recent years, with a dramatic increase in the number of pixels in a solid-state imaging device, there is an increasing demand for reading signals from the solid-state imaging device at high speed.

In the initial configuration in which an analog signal obtained as a result of photoelectric conversion in the pixel circuit is read out from the solid-state imaging device and a digital signal is obtained by an external AD (analog-digital) converter, the internal stray capacitance of the solid-state imaging device is For this reason, there is a limit to the improvement in reading speed.

As a countermeasure against this, a technique for achieving high-speed signal output by converting an analog signal output from a pixel circuit into a digital signal in a solid-state imaging device and suppressing the influence of stray capacitance or the like is well known ( For example, see Patent Document 1).

FIG. 14 is a schematic diagram showing the configuration of the main part of the solid-state imaging device disclosed in Patent Document 1. In this solid-state imaging device, a signal voltage output from the pixel circuit 92 is converted into a digital signal by a single slope AD converter 90. A rough operation of the solid-state imaging device will be described.

The pixel circuit 92 in the imaging unit 91 applies a signal voltage obtained by photoelectric conversion to one of the input terminals of the voltage comparison unit 93. The reference signal generation unit 95 generates a ramp wave RAMP that rises in synchronization with the clock signal CK supplied from the control unit 94 by using, for example, a DA (digital analog) converter, and the other input terminal of the voltage comparison unit 93. Apply to.

The counter unit 96 starts to count the clock signal CK simultaneously with the start of rising of the ramp wave RAMP. When the voltage comparison unit 93 receives a signal indicating that the level of the ramp wave RAMP and the signal voltage from the pixel circuit 92 coincide with each other, the counter unit 96 calculates the count value at that time from the pixel circuit 92. Output as a digital signal representing the signal voltage.

However, according to this technique, in order to obtain a digital signal at a high speed, it is required to determine in a short time when the level of the ramp wave RAMP matches the signal voltage from the pixel circuit 92. Therefore, it is necessary to sweep the ramp wave RAMP at high speed using a high-speed (that is, high frequency) clock signal CK.

For example, in order to output a 12-bit digital output of a full high-definition moving image at 60 fps, the period for comparing the level of the ramp wave RAMP and the signal voltage from the pixel circuit 92 is about 15 μs or less, and the frequency of the clock signal CK is about 300 MHz. Cost. Furthermore, in order to obtain a 14-bit digital output, the frequency reaches 1 GHz or more.

Since the technical difficulty is high for stable AD conversion under such a high-speed clock signal CK, it has been difficult to achieve both the multi-bit digital output and the high-speed frame number.

Therefore, an improved circuit configuration as shown in FIG. 15 is proposed as a solid-state imaging device capable of outputting a digital signal at a multi-bit high frame rate without using such a high-speed (that is, high-frequency) clock signal CK. (For example, see Patent Document 2). The operation principle of this circuit configuration will be described with reference to FIG. In this improved circuit configuration, the AD converter 70 generates a plurality of reference voltages VREF that are different from each other within a voltage range that can be taken by the reference voltage generator 40, and each reference voltage is generated by the upper bit converter 20. The result of specifying the voltage section including the signal voltage from among the plurality of voltage sections with the base point as the base bit is converted as the value of the upper bit of the digital signal, and is specified by the upper bit conversion unit 20 by the lower bit conversion unit 30 The difference voltage between the reference voltage, which is the base point of the voltage section, and the signal voltage is converted into the lower bits of the digital signal. In this way, unnecessary lower bit conversion processing in the voltage section not including the signal voltage is omitted.

JP 2005-323331 A JP 2009-200931 A

However, problems still remain in the improved circuit configuration as shown in FIG. That is, when generating a plurality of reference voltages different from each other within a voltage range that can be taken by the signal voltage, it is ideal that the reference voltages are set equally, but this is not the case. Referring to FIGS. 17A to 17C, although depending on the chip layout method of the solid-state imaging device, in general, the wiring resistance at the center of the chip compared to the positions where the reference voltage is input at both left and right ends of the chip. In many cases, the input reference voltage has a low value due to the influence of the parasitic capacitance or the like (see FIG. 17B). Therefore, a plurality of voltage sections do not have the same voltage difference. Further, if AD conversion is performed in a single slope type using a ramp wave RAMP having the same supply source in this section, it is difficult to input the same signal to the ramp wave RAMP depending on the position of the chip layout (FIG. 17). (See (c)). If these are combined, a large error may occur in the AD conversion result. Note that the “fine counter value” in FIG. 17C is a conversion result in the low-order bit conversion unit 30.

Especially noticeable is the conversion result near the boundary between adjacent voltage sections. As a phenomenon, it is conceivable that the digital conversion result causes a bit skip or the same value is repeated, and linearity error (integral linearity) and differential linearity error in AD conversion become very large. This is shown in FIGS. 18 (a) and 18 (b). FIG. 18A shows the conversion characteristics at the left and right ends of the chip, and FIG. 18B shows the conversion characteristics near the center of the chip. In FIG. 18 (a), the linearity error and the differential linearity error are only recognized, but in FIG. 18 (b), not only the linearity error and the differential linearity error but also the drop in the reference voltage and the ramp wave RAMP. Due to the dullness, duplication of data and lack of data occur and the continuity is lost.

The present invention has been made in view of such circumstances, and provides a solid-state imaging device including an AD conversion unit that can reduce linearity errors and differential linearity errors in AD conversion and maintain data continuity. The purpose is to provide.

In order to achieve the above object, one embodiment of a solid-state imaging device according to the present invention is a solid-state imaging device that repeats imaging in units of frames, and is arranged in a matrix and a plurality of pixel circuits that photoelectrically convert received light An imaging unit including: an AD conversion unit that converts pixel signals from the plurality of pixel circuits into digital signals for each column of the pixel circuits; and a calibration unit that performs calibration on the AD conversion unit, The AD conversion unit includes a reference voltage generation unit that generates a plurality of reference voltages that are different from each other within a voltage range that the pixel signal can take, and a plurality of voltage sections that are based on each of the plurality of reference voltages for each column. An upper bit conversion unit that specifies a voltage section including the pixel signal from among the above and outputs a specification result as a value of an upper bit of the digital signal, and for each column A low-order bit conversion unit that converts a difference voltage between a reference voltage that is a base point of the specified voltage section and the pixel signal into a low-order bit of the digital signal, and the calibration unit includes a plurality of start bits of a frame. The plurality of reference voltages are calibrated in a plurality of voltage sections with the reference voltages as base points using the horizontal scanning period.

According to this configuration, calibration is performed for a plurality of reference voltages used in AD conversion using the AD conversion unit in the solid-state imaging device, so that the upper bit, the lower bit, and the digital value converted by the synthesis thereof are accurate. Can be corrected well.

Here, the calibration unit may perform the calibration every frame or every other frame. According to this configuration, when there is a significant change in the use environment, the calibration is performed every frame to perform an accurate correction. On the other hand, when the use in the steady state is continued, one or more By performing calibration every frame, unnecessary processing can be omitted, so that current consumption can be reduced.

The calibration unit corrects the digital signal obtained by the AD conversion unit by causing the AD conversion unit to input the maximum value and the minimum value of the voltage interval for each of the plurality of voltage intervals. The correction data may be created. As a result, calibration is performed on the reference voltages corresponding to the maximum value and the minimum value of each voltage section, so that accurate calibration can be performed.

At this time, it is preferable that the calibration unit creates the correction data by causing the AD conversion unit to input the same reference voltage as the maximum value and the minimum value of each of the plurality of adjacent voltage sections. As a result, calibration is performed with respect to the same reference voltage in the plurality of adjacent voltage sections, so that duplication of data and missing data in AD conversion do not occur, and continuity of AD conversion can be maintained.

Further, the calibration unit uses the first arithmetic unit that creates the correction data, a storage device that stores the generated correction data, and the correction data stored in the storage device, to A second computing unit that creates calibrated data from the digital signal obtained by the AD conversion unit, and outputs the calibrated data as an AD conversion result. Thereby, the correction data can be obtained by a simple arithmetic expression, so that it can be generated for each frame, and calibration corresponding to the high-speed frame rate can be performed.

The higher-order bit conversion unit is a flash AD converter that specifies a voltage section in which the pixel signal is included by comparing the pixel signal and the plurality of reference signals all at once. The reference voltage, which is the base point of the voltage section, is output as an offset voltage to the lower bit conversion unit, and the lower bit conversion unit is a single slope AD converter, and is between the pixel signal and the offset voltage. Comparing the differential voltage with a ramp wave that fluctuates at a constant slope, when the comparison result is inverted, the value of a built-in counter that operates in conjunction with the ramp wave is read, and the value of the counter is read with the lower bit You may output as a conversion result of a conversion part. As a result, the upper bit conversion unit and the lower bit conversion unit can be configured relatively easily, which is suitable for an ADC circuit built in a solid-state imaging device that is becoming increasingly finer.

At this time, the calibration unit supplies, to the lower bit conversion unit, a reference voltage that is a minimum value and a reference voltage that is a maximum value of the plurality of voltage intervals for a plurality of voltage intervals based on the reference voltages. Correction data for correcting the digital signal obtained by the AD conversion unit may be created from the count values obtained by the lower-order bit conversion unit obtained for each input. Thereby, it is possible to know a deviation from the ideal value in the AD conversion values of the maximum value and the minimum value, and it is possible to accurately and easily create correction data for the plurality of voltage sections.

Here, in the calibration, the low-order bit conversion unit is configured to increase the ramp wave to a value that exceeds a predetermined maximum conversion value of the low-order bit conversion unit in a plurality of voltage sections based on the reference voltages. It is preferable to convert the maximum value of the plurality of voltage sections as a digital value by performing overscan. As a result, in calibration, the lower bit conversion result can be obtained and the correction coefficient can be calculated in a range up to a value exceeding the maximum conversion value of the lower bit conversion unit, so that the correction data of the plurality of voltage sections can be reliably obtained. Can be created.

Further, it is more preferable that the AD converter further includes an interphase double sampling circuit. Thereby, the offset voltage difference which is different for each column can be made inconspicuous by the interphase double sampling, and the fixed pattern noise can be suppressed with high accuracy.

The present invention can be realized not only as the above-described solid-state imaging device but also as a semiconductor integrated circuit device in which the solid-state imaging device is mounted on a semiconductor substrate of one chip or a plurality of chips, a camera including the solid-state imaging device, and It can also be realized as a signal processing method in the solid-state imaging device.

The solid-state imaging device according to the present invention can eliminate unnecessary lower-bit conversion processing in a voltage section that does not include a signal voltage, and can realize high-speed AD conversion. Reduces the linearity error and differential linearity error in AD conversion that occur, and suppresses the phenomenon such as bit skipping of the digital conversion result that occurs remarkably near the boundary of adjacent voltage sections and the same value being repeated. There is an effect to keep.

Therefore, according to the present invention, a solid-state imaging device having an AD conversion function with high accuracy and a camera including such a solid-state imaging device are realized, and the practical value of the present invention in which digital cameras have become widespread is extremely high.

FIG. 1 is a circuit block diagram showing the configuration of the solid-state imaging device according to the first embodiment of the present invention. FIG. 2A is a diagram illustrating an input range of an AD conversion unit included in the solid-state imaging device, and FIG. 2B is a timing diagram of calibration. 3A to 3C are diagrams showing the basic operation of the calibration unit included in the solid-state imaging device. 4A to 4E are diagrams for explaining a correction coefficient calculation method by the solid-state imaging device. FIG. 5 is a diagram illustrating a normal operation (AD conversion for a pixel signal) of the solid-state imaging device. FIGS. 6A and 6B are diagrams illustrating a first step in a series of operations of calibration by the solid-state imaging device. FIGS. 7A and 7B are diagrams illustrating a second step in a series of calibration operations performed by the solid-state imaging device. FIGS. 8A and 8B are diagrams illustrating a third step in a series of calibration operations by the solid-state imaging device. FIGS. 9A and 9B are diagrams illustrating a fourth step in a series of operations of calibration by the solid-state imaging device. FIGS. 10A and 10B are diagrams for explaining an overscan operation of a ramp wave in the solid-state imaging device. FIG. 11 is a circuit block diagram showing the configuration of the solid-state imaging device according to the second embodiment of the present invention. FIG. 12 is a block diagram showing a configuration of a camera according to the third embodiment of the present invention. FIG. 13 is an external view of the camera. FIG. 14 is a circuit block diagram showing a configuration of a conventional solid-state imaging device. FIG. 15 is a circuit block diagram showing a configuration of a conventional improved solid-state imaging device. FIG. 16 is a diagram illustrating an operation principle of the improved solid-state imaging device. FIG. 17 is a diagram for explaining the problem of the improved solid-state imaging device. FIG. 18 is a diagram for explaining the problem of the improved solid-state imaging device.

A solid-state imaging device according to an embodiment of the present invention is a device that repeats imaging in frame units, and outputs a digital signal by performing AD conversion on a signal voltage obtained as a result of photoelectric conversion by a pixel circuit It is.

The solid-state imaging device of the present invention generates a plurality of reference voltages that are different from each other within a voltage range that the signal voltage can take, and includes a voltage section that includes the signal voltage from among a plurality of voltage sections based on each reference voltage. The identification result is used as the value of the upper bit (MSB) of the digital signal, and the difference voltage between the reference voltage and the signal voltage, which is the base point of the identified voltage section, is used as the lower bit (LSB) of the digital signal. Further, it is characterized in that calibration is performed in a plurality of voltage sections using the respective reference voltages as base points using a plurality of horizontal scanning periods at the beginning of the frame.

Hereinafter, a solid-state imaging device, a semiconductor integrated circuit device, a camera, and a signal processing method according to the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit block diagram showing a configuration of a solid-state imaging device (here, MOS type image sensor 1) according to the first embodiment of the present invention. This MOS image sensor 1 is a single chip in which a calibration unit 100 is added to the configuration shown in FIG. 15 (the imaging unit 10, AD conversion unit 70, timing control unit 80, row scanning circuit 81, column scanning circuit 82). Or it is comprised with the semiconductor integrated circuit which consists of a some chip | tip.

The imaging unit 10 is a collection of a plurality of pixel circuits 11 that are arranged in a matrix and photoelectrically convert received light. A pixel signal from the pixel circuit 11 is received for each row by a drive signal from the row scanning circuit 81. The data is output to the AD conversion unit 70.

The row scanning circuit 81 outputs a driving signal for scanning each row in the column direction to output a pixel signal to the pixel circuit 11 constituting the imaging unit 10.

The AD conversion unit 70 converts a plurality of AD converters (for each column of the pixel circuits 11) that convert pixel signals output from the plurality of pixel circuits 11 constituting one row in the imaging unit 10 into digital signals for each column of the pixel circuits 11. A reference voltage generator 40, upper bit converter 20, reference signal generator 95, and lower bit converter 30.

The reference voltage generation unit 40 is a circuit that generates a plurality of reference voltages VREF that are different from each other within a voltage range that the pixel signal can take. Here, “a plurality of reference voltages” means boundary voltages (Vref1 and Vref2 from the low voltage side) that divide the voltage between the minimum value VL and the maximum value VH of the input range of the AD converter 70 into four voltage sections. , Vref3).

For each column of the pixel circuits 11, the upper bit conversion unit 20 includes a plurality of voltage sections (here, a minimum value VL of the input range and a plurality of reference voltages generated by the reference voltage generation unit 40). VL to Vref1, Vref1 to Vref2, Vref2 to Vref3, and Vref3 to VH (four voltage intervals) are specified, and the specified voltage interval including the pixel signal is output, and the specified result is output as the value of the upper bits of the digital signal This is a collection of AD converters (upper bit AD converters provided for each column of the pixel circuit 11). More specifically, each of the AD converters constituting the higher-order bit conversion unit 20 is a flash AD converter, and a voltage including a pixel signal by comparing the pixel signal and a plurality of reference signals all at once. The section is specified, and the reference voltage that is the base point of the specified voltage section is output to the lower bit conversion unit 30 as an offset voltage.

The reference signal generation unit 95 is a circuit that generates a reference signal that is a ramp wave RAMP having a voltage waveform having a constant slope.

The lower bit conversion unit 30 converts, for each column of the pixel circuits 11, a difference voltage between the reference voltage, which is the base point of the voltage section specified by the upper bit conversion unit 20, and the pixel signal into lower bits of the digital signal. (A lower-bit AD converter provided for each column of the pixel circuit 11). More specifically, each of the AD converters constituting the lower bit conversion unit 30 is a single slope type AD converter, and the difference voltage between the pixel signal and the offset voltage output from the upper bit conversion unit 20 Are compared with the ramp wave generated by the reference signal generation unit 95, and when the comparison result is inverted, the value of the built-in counter that operates in conjunction with the ramp wave is read, and the value of the counter is read from the digital signal. Output as lower bits.

The timing control unit 80 controls the reference signal generation unit 95 to start and stop the generation of the ramp wave RAMP, and controls the column scanning circuit 82 to obtain the results of the upper bit conversion unit 20 and the lower bit conversion unit 30. Is output for each column of the pixel circuit 11.

The column scanning circuit 82 outputs a drive signal for scanning each column in the column direction in order to sequentially output the AD conversion results to the individual AD converters constituting the upper bit conversion unit 20 and the lower bit conversion unit 30. Output.

The calibration unit 100 uses a plurality of horizontal scanning periods at the beginning of a frame every frame or every one or more frames to calculate the minimum value VL of the input range and a plurality of reference voltages generated by the reference voltage generation unit 40. This is a circuit that calibrates a plurality of reference voltages in a plurality of voltage sections each having a base point, and includes a level determination unit 105, a first computing unit 110, a memory 130, and a second computing unit 120. As for the frequency of calibration, the calibration unit 100 detects, for example, a temperature or usage frequency in the usage environment with a sensor or the like, so that a significant change in the usage environment is detected. By performing calibration every frame, priority is given to correct correction, while when it is detected that the use in a steady state is continued, by performing calibration every other frame, Reduce current consumption without degrading AD conversion accuracy.

The first arithmetic unit 110 eliminates the difference between the data obtained by AD conversion in the lower bit conversion unit 30 and the ideal data that should be originally for each of the plurality of reference voltages generated by the reference voltage generation unit 40. Correction data (hereinafter, also referred to as “correction coefficient”) for each column, and a first temporary memory and a second temporary memory that temporarily store the data, and a first that executes the calculation 1 arithmetic processing unit 113. The “correction coefficient” is a coefficient for correcting the digital signal obtained by the AD conversion unit 70 (that is, creating calibrated data from the digital signal).

The memory 130 is a storage device that stores the correction coefficient created by the first computing unit 110, and corresponds to each of a plurality of voltage intervals (here, four voltage intervals) specified by the upper bit conversion unit 20. It has a first memory 131, a second memory 132, a third memory 133, and a fourth memory 134, which are storage areas.

The level determination unit 105 selects a memory area (the first memory 131, the second memory 132, the third memory 133, or the fourth memory 134) in the memory 130 corresponding to the voltage section specified by the upper bit conversion unit 20. It is.

The second arithmetic unit 120 performs correction stored in the memory 130 on the conversion result of the AD conversion unit 70 (here, the lower bit conversion unit 30) for the pixel signal in normal operation (AD conversion for the pixel signal). A second arithmetic processing unit that creates a calibrated data by using a coefficient (here, divided by a correction coefficient) and outputs the calibrated data as an AD conversion result. 121.

Next, the operation of the calibration unit 100, which is a characteristic component of the MOS image sensor 1 according to the present embodiment configured as described above, will be described in detail.

2A and 2B are conceptual diagrams for explaining the operation of the calibration unit 100. FIG.

In general, the imaging unit 10 outputs a plurality of rows of optical black signals and dummy signals before and after the normal pixel signal is output. The calibration unit 100 performs calibration using this timing.

FIG. 2A is a diagram illustrating an input range of the AD conversion unit 70. As shown in the figure, in the present embodiment, there are four voltage intervals (VL to Vref1, Vref1 to Vref2, Vref2 to Vref3, Vref3 to VH) between the minimum value VL and the maximum value VH of the AD input range. It is divided into This boundary voltage is supplied as a reference voltage from the reference voltage generation unit 40 as Vref1, Vref2, and Vref3 from the low voltage side. The conversion of the upper bits in the upper bit converter 20 can be obtained as HIGH or LOW, which is the result of comparing the pixel signal with these reference voltages. The upper bit conversion unit 20 selects one section from the four voltage sections based on the conversion result of the upper bits, and notifies the lower bit conversion section 30 of the voltage section. If data is output to the outside as it is, as described in the problem of the conventional circuit configuration, linearity error and differential linearity error in AD conversion occur in each divided voltage section, and duplication of data and lack of data occur. There is a risk of generating non-continuous data.

Therefore, in the present embodiment, the AD converter 70 is calibrated at the timing shown in FIG. In the circuit block diagram shown in FIG. 2B, only the circuit excluding the calibration unit 100 is shown in the MOS image sensor 1 according to the present embodiment. As shown in FIG. 2B, the calibration unit 100 sets, for each frame, a period corresponding to any eight rows at the beginning of the frame before the normal pixel signal is output as a calibration data period. During this period, the correction coefficient is calculated by the first computing unit 110 from the obtained data, and the correction coefficient is stored in the memory 130.

Specifically, since the AD input range is divided into four voltage sections, the calibration unit 100 controls the AD conversion unit 70 to first Vref3 on the first line of the frame and VH on the second line. Vref2 in the 3rd row, Vref3 in the 4th row, Vref1 in the 5th row, Vref2 in the 6th row, VL in the 7th row, Vref1 in the 8th row, the AD conversion unit 70 (here, the lower bit conversion unit 30) ). The reason for performing this order will be described later.

3A to 3C are diagrams showing a basic operation (signal processing method) by the calibration unit 100. FIG. Here, only the main part of the calibration unit 100 is shown. First, the calibration unit 100 uses, as a calibration step, a correction coefficient that eliminates the difference between the above-described data for eight rows (conversion result D _cal in the lower bit conversion unit 30) and ideal data that should be originally, as a pixel circuit 11. Is calculated by the first computing unit 110 (FIG. 2 (a)), and the calculation result is stored in the memory 130 (for each of all AD converters constituting the AD conversion unit 70) (see FIG. 2A). FIG. 2 (b)). Thereafter, when the normal pixel signal is output, the calibration unit 100 performs the second calculation using the correction coefficient stored in the memory 130 on the AD conversion result (D _IS ) for the pixel signal when the normal pixel signal is output. The digital conversion result (D _out ) corrected by the device 120 and suppressing the linearity error and the differential linearity error in AD conversion is output to the outside (FIG. 2C).

FIGS. 4A to 4E are diagrams for explaining a correction coefficient calculation method. The simple calculation method for calculating the correction coefficient described above and the reason why the reference voltage is selected as the calibration voltage and the input order is determined will be described with reference to FIG.

In this example, as shown in FIGS. 4A to 4D, correction coefficients are calculated for each of the four voltage sections, and four memories (first memory 131 to fourth memory 134) are calculated. ). In other words, the calibration unit 100 sets the difference in the first memory 131 when the storage location of the selected memory 130 is the first memory 131 when the pixel signal voltage is the highest voltage section, that is, the reference voltage Vref3 or more. The first correction coefficient obtained by performing calibration by inputting VH as the HIGH side for calculation and Vref3 as the LOW side to the AD conversion unit 70 (here, the lower bit conversion unit 30) is stored (see FIG. FIG. 4 (a)). Similarly, the calibration unit 100 stores the second correction coefficient in the second memory 132 when the pixel signal voltage is lower than the reference voltage Vref3 and equal to or higher than Vref2 (FIG. 4B), and the pixel signal voltage Is lower than the reference voltage Vref2 and greater than or equal to Vref1, the third correction coefficient is stored in the third memory 133 (FIG. 4C), and the pixel signal voltage is lower than the reference voltage Vref1 and greater than or equal to VL. The fourth correction coefficient is stored in the 4 memory 134 (FIG. 4D).

In order to obtain the correction coefficient, as shown in FIG. 4 (e), the first arithmetic unit 110 includes an AD conversion unit 70 (here, a high-side reference voltage is input in each voltage range). The difference between the digital conversion value in the lower bit conversion unit 30) and the digital conversion value in the AD conversion unit 70 (here, the lower bit conversion unit 30) obtained when the LOW side reference voltage is input. The digital conversion value per bit is obtained by calculating and dividing the difference data by the number of lower bits (maximum value of the conversion result in the lower bit conversion unit 30) ((i) and ( ii)). The first computing unit 110 calculates the digital conversion value per bit as a correction coefficient (“hosei-data” in FIG. 4E) corresponding to each of all the columns of the imaging unit 10. And stored in the memory 130.

In the normal operation, the second computing unit 120 converts the conversion result of the AD conversion unit 70 (here, the lower bit conversion unit 30) for the pixel signal ("digital value before correction" in FIG. 4E). On the other hand, the data corrected by dividing by the correction coefficient stored in the memory 130 (“hosei-data” in FIG. 4E) (the “digital value after correction” in FIG. 4E)) And calibrated data is output as an AD conversion result. In the specific example shown in FIG. 4E, the digital value is 10110 before correction, but it is reduced to 10101 after correction. This is a calibration value obtained by dividing the digital value before correction by the digital conversion value (correction coefficient) per bit.

FIG. 5 is a diagram showing a normal operation (AD conversion for a pixel signal) in the MOS image sensor 1 according to the present embodiment.

In this figure, Vsig is a pixel signal, the minimum value of the AD input range is VL, the maximum value is VH, and Vref1, Vref2, and Vref3 are shown from the low voltage side as reference voltages to be divided into four voltage sections. The digital conversion value of the upper bits by the upper bit converter 20 can be obtained as HIGH or LOW, which is the result of comparing the pixel signal with these reference voltages.

Thereafter, the lower bit conversion unit 30 selects one of the four voltage intervals based on the conversion result of the upper bits, and sets the ramp wave Vramp, which is the reference signal, to the reference voltage that is the minimum value of the voltage interval. Is superimposed, and the signal after superposition (Vref3 + Vramp in the example of this figure) is compared with the pixel signal Vsig, and the counter value of the built-in counter at the time when the signal level matches is output as the digital conversion value of the lower bits. . Here, it is assumed that the ramp wave Vramp is interlocked with the counter value.

6 (a) and 6 (b) to 9 (a) and 9 (b) are diagrams showing the details of the calibration operation (a series of operations consisting of four steps) in the MOS image sensor 1. FIG.

FIGS. 6A and 6B are diagrams showing a first step in a series of calibration operations by the MOS image sensor 1. The calibration unit 100 calculates the first correction coefficient corresponding to each of all the columns of the imaging unit 10 by performing calibration for the first of the four voltage sections in the following procedure.

That is, the calibration unit 100 controls the AD conversion unit 70 to input the reference voltage Vref3 to the lower bit conversion unit 30 in the first row of calibration (the first row of the frame), and the lower bit conversion at this time The lower bit digital conversion value Vref3-Data1 which is a conversion result in the unit 30 is input to the first arithmetic unit 110 and temporarily stored in the first temporary memory 111 of the first arithmetic unit 110 (FIG. 6A). Subsequently, the calibration unit 100 controls the AD conversion unit 70 to input the reference voltage VH to the lower bit conversion unit 30 in the second row of the frame, and the conversion result in the lower bit conversion unit 30 at this time A certain lower-order bit digital conversion value VH-Data is inputted to the first computing unit 110 and temporarily stored in the second temporary memory 112 of the first computing unit 110 (FIG. 6B). Then, the calibration unit 100 uses the first computing unit 110 to calculate the number of lower bits (with respect to the difference between VH-Data stored in the second temporary memory 112 and Vref3-Data1 stored in the first temporary memory 111 ( A value divided by the maximum value of the conversion result in the lower bit conversion unit 30 is calculated, and the obtained value is stored in the first memory 131 as 1 bit-digital-Data1 (first correction coefficient).

FIGS. 7A and 7B are diagrams showing a second step in a series of calibration operations by the MOS type image sensor 1. The calibration unit 100 calculates a second correction coefficient corresponding to each of all the columns of the imaging unit 10 by performing calibration for the second of the four voltage sections in the following procedure.

In other words, the calibration unit 100 controls the AD conversion unit 70 to input the reference voltage Vref2 to the lower bit conversion unit 30 in the third row of calibration (the third row of the frame), and the lower bit conversion unit at this time The lower bit digital conversion value Vref2-Data1 which is the conversion result at 30 is input to the first computing unit 110 and temporarily stored in the first temporary memory 111 of the first computing unit 110 (FIG. 7A). The calibration unit 100 controls the AD conversion unit 70 to input the reference voltage Vref3 to the lower bit conversion unit 30 in the fourth line of the frame, and the lower order bit conversion unit 30 at this time is the lower order. The bit-digital converted value Vref3-Data2 is input to the first arithmetic unit 110, and the second temporary memory 112 of the first arithmetic unit 110 is input. Then, the calibration unit 100 stores the Vref3-Data2 stored in the second temporary memory 112 and the Vref2- stored in the first temporary memory 111 by the first computing unit 110. A value obtained by dividing the difference from Data1 by the number of lower bits (the maximum value of the conversion result in the lower bit conversion unit 30) is calculated, and the obtained value is defined as 1 bit-digital-Data2 (second correction coefficient). Save in the second memory 132.

FIGS. 8A and 8B are diagrams showing a third step in a series of calibration operations by the MOS type image sensor 1. The calibration unit 100 calculates a third correction coefficient corresponding to each of all the columns of the imaging unit 10 by performing calibration for the third of the four voltage sections in the following procedure.

That is, the calibration unit 100 controls the AD conversion unit 70 to input the reference voltage Vref1 to the lower bit conversion unit 30 in the fifth row of calibration (the fifth row of the frame), and the lower bit conversion unit at this time The lower bit digital conversion value Vref1-Data1 which is the conversion result at 30 is input to the first computing unit 110 and temporarily stored in the first temporary memory 111 of the first computing unit 110 (FIG. 8A). The calibration unit 100 controls the AD conversion unit 70 to input the reference voltage Vref2 to the lower bit conversion unit 30 on the sixth line of the frame, and the lower order bit conversion unit 30 at this time is the lower order. The bit-digital converted value Vref2-Data2 is input to the first computing unit 110, and the second temporary memory 112 of the first computing unit 110 is input. The calibration unit 100 stores the Vref2-Data2 stored in the second temporary memory 112 and the Vref1- stored in the first temporary memory 111 by the first computing unit 110. A value obtained by dividing the difference from Data1 by the number of lower bits (the maximum value of the conversion result in the lower bit conversion unit 30) is calculated, and the obtained value is defined as 1 bit-digital-Data3 (third correction coefficient). Save in the third memory 133.

FIGS. 9A and 9B are diagrams showing a fourth step in a series of calibration operations by the MOS image sensor 1. The calibration unit 100 calculates a fourth correction coefficient corresponding to each of all the columns of the imaging unit 10 by performing calibration for the fourth of the four voltage sections in the following procedure.

That is, the calibration unit 100 controls the AD conversion unit 70 to input the reference voltage VL to the lower bit conversion unit 30 in the seventh row of calibration (the seventh row of the frame), and the lower bit conversion unit at this time The low-order bit digital conversion value VL-Data that is the conversion result at 30 is input to the first arithmetic unit 110 and temporarily stored in the first temporary memory 111 of the first arithmetic unit 110 (FIG. 9A). The calibration unit 100 controls the AD conversion unit 70 to input the reference voltage Vref1 to the lower bit conversion unit 30 in the eighth row of the frame, and the lower order bit that is the conversion result of the lower bit conversion unit 30 at this time. The bit digital conversion value Vref1-Data2 is input to the first arithmetic unit and temporarily stored in the second temporary memory 112 of the first arithmetic unit (FIG. 9B). Then, the calibration unit 100 uses the first calculator 110 to calculate the number of lower bits for the difference between Vref1-Data2 stored in the second temporary memory 112 and VL-Data stored in the first temporary memory 111. A value divided by (the maximum value of the conversion result in the lower bit conversion unit 30) is calculated, and the obtained value is stored in the fourth memory 134 as 1 bit-digital-Data4 (fourth correction coefficient).

The first to fourth correction coefficients stored in the memory 130 as described above are used as corrections in normal AD conversion of pixel signals. That is, in the calibration unit 100, when the pixel signal is converted by the AD conversion unit 70, the second arithmetic unit 120 corresponds to the conversion result in the upper bit conversion unit 20 for each of all the columns of the imaging unit 10. The correction coefficient corresponding to the column is read from the area of the memory 130 (the first memory 131 to the fourth memory 134), the conversion result in the lower bit conversion unit 30 is divided by the read correction coefficient, and the value after the division A value obtained by combining the conversion result in the upper bit conversion unit 20 is output as a calibrated digital signal.

In order to perform the above-described calibration, a digital conversion value cannot be obtained and a correction coefficient cannot be obtained unless the reference voltage and the ramp wave Vramp always match in the divided voltage section. For this reason, it is desirable to overscan the ramp wave Vramp to a value exceeding the maximum conversion value of the lower-order bit conversion unit 30. This is shown in FIGS. 10A and 10B. If the number of lower conversion bits by the lower bit conversion unit 30 is 10 bits, the maximum conversion value of the lower bit conversion unit 30 is 1024, but the counter value is always digitally converted by overscanning the attenuated ramp wave Vramp. Therefore, a counter value exceeding 1024 is returned, such as 1024 + a in FIG. 10A. If this value is corrected by an arithmetic unit and rounded to 1024, there will be no missing bits as shown in FIG.

In addition, the AD conversion unit 70 according to the present embodiment may include a CDS (correlated double sampling) circuit. By providing this circuit, by calculating a digital value corresponding to the difference between the signal in the reset period of the pixel circuit 11 and the signal in the signal period, the difference in offset voltage for each column of the pixel circuit 11 is made inconspicuous. It is possible to suppress fixed pattern noise with high accuracy.

Further, the solid-state imaging device of the present invention may be used for a camera or the like. In recent years, with a dramatic increase in the number of pixels in a solid-state imaging device used for a camera or the like, there has been an increasing demand for reading a signal from the solid-state imaging device at high speed. Therefore, it is suitable for applications such as cameras.

(Second Embodiment)
Next, a solid-state imaging device according to the second embodiment of the present invention will be described.

FIG. 11 is a circuit block diagram showing a configuration of a solid-state imaging device (here, MOS type image sensor 2) according to the second embodiment of the present invention. This MOS type image sensor 2 has a configuration in which a digital double sampling (DDS) circuit 200 is added to the MOS type image sensor 1 in the first embodiment.

The digital double sampling circuit 200 is an example of a CDS circuit, and includes a third arithmetic unit 210, a dark image memory 220, and a bright image memory 230.

The digital double sampling circuit 200 is an example of a CDS circuit that performs digital double sampling and calculates a difference between a pixel signal component and a pixel reset component for each column of the pixel circuit 11, and includes a third arithmetic unit 210, a dark image, and the like. A memory 220 and a bright image memory 230 are included. With this configuration, an offset difference between different pixel signals for each column of the pixel circuit 11 is taken to make the vertical fixed pattern noise inconspicuous. The digital double sampling circuit 200 stores the pixel signal component corrected by the calibration in the light image memory 230 and the pixel reset component corrected by the calibration in the dark image memory 220, and performs the third arithmetic unit 210. Thus, the vertical fixed pattern noise is made inconspicuous by calculating and outputting the difference in the final stage.

(Third embodiment)
Next, a camera according to a third embodiment of the present invention will be described.

FIG. 12 is a diagram illustrating a configuration of the camera 3 including the solid-state imaging device according to the present invention. The camera 3 is a digital still camera shown in FIG. 13 (a), a video camera shown in FIG. 13 (b), etc., and includes a lens 300, a solid-state imaging device 301 according to the present invention, a drive circuit 302, A signal processing unit 303 and an external interface unit 304 are provided. In this figure, the drive circuit 302 corresponds to the row scanning circuit 81 and the column scanning circuit 82 in the first and second embodiments, and the solid-state imaging device 301 is the first and second embodiments. This corresponds to a circuit excluding the row scanning circuit 81 and the column scanning circuit 82 among the MOS image sensors in the embodiment.

The light that has passed through the lens 300 enters the solid-state imaging device 301. The signal processing unit 303 drives the solid-state imaging device 301 via the drive circuit 302 and takes in an output signal from the solid-state imaging device 301. The output signal is subjected to various signal processing such as white balance in the signal processing unit 303 and is output to the outside via the external interface unit 304.

According to the camera 3 configured as described above, the solid-state imaging device 301 has a function of calibrating the reference voltage in the built-in AD conversion unit, so that linearity errors and differential linearity errors in AD conversion are suppressed. .

As described above, the solid-state imaging device, the semiconductor integrated circuit device, the camera, and the signal processing method according to the present invention have been described based on the first to third embodiments. However, the present invention is limited to these embodiments. It is not something. Without departing from the spirit of the present invention, forms obtained by subjecting these embodiments to various modifications conceived by those skilled in the art, and forms obtained by arbitrarily combining the components in each embodiment are also included in this embodiment. Included in the invention.

For example, not only the first embodiment but also the MOS image sensor 2 in the second embodiment may be realized by a semiconductor integrated circuit including one chip or a plurality of chips.

Further, the calibration unit 100 in the first and second embodiments may be realized by being incorporated in the signal processing unit 303 shown in FIG. 12, or by a combination of a processor such as a CPU or DSP and a program. It may be realized by software.

The solid-state imaging device and the semiconductor integrated circuit device according to the present invention can cope with accurate AD conversion by having a correction circuit even if the accuracy of the reference voltage and the linearity of the ramp wave are somewhat rough. In order to realize this, a high-speed and high-resolution digital output MOS image sensor can be provided by using a relatively simple ADC circuit, a small-scale arithmetic processing circuit, and a small-capacity memory device. Each frame can be corrected and is not easily affected by changes in the usage environment, and can be used in a wide variety of applications such as digital still cameras, digital video cameras, mobile terminal cameras, in-vehicle cameras, street cameras, security cameras, and medical cameras. It is.

DESCRIPTION OF

SYMBOLS

1, 2 MOS type image sensor 3 Camera 10 Imaging part 11 Pixel circuit 20 Upper bit conversion part 30 Lower bit conversion part 40 Reference voltage generation part 70 AD conversion part 80 Timing control part 81 Row scanning circuit 82 Column scanning circuit 95 Reference signal generation Unit 100 calibration unit 105 level determination unit 110 first arithmetic unit 111 first temporary memory 112 second temporary memory 113 first arithmetic processing unit 120 second arithmetic unit 121 second arithmetic processing unit 130 memory 131 first memory 132 second Memory 133 Third memory 134 Fourth memory 200 Digital double sampling circuit 210 Third computing unit 220 Dark image memory 230 Bright image memory 300 Lens 301 Solid-state imaging device 302 Drive times 303 signal processing section 304 External interface section

Claims

A solid-state imaging device that repeats imaging in frame units,
An imaging unit having a plurality of pixel circuits arranged in a matrix and photoelectrically converting received light;
An AD converter that converts pixel signals from the plurality of pixel circuits into digital signals for each column of the pixel circuits;
A calibration unit that performs calibration on the AD conversion unit,
The AD converter is
A reference voltage generator that generates a plurality of different reference voltages within a voltage range that the pixel signal can take;
For each of the columns, a voltage section including the pixel signal is identified from a plurality of voltage sections based on each of the plurality of reference voltages, and the identification result is output as the value of the high-order bit of the digital signal A bit conversion unit;
A low-order bit conversion unit that converts a difference voltage between a reference voltage that is a base point of the specified voltage section and the pixel signal into a low-order bit of the digital signal for each column;
The solid-state imaging device, wherein the calibration unit calibrates the plurality of reference voltages in a plurality of voltage sections based on the respective reference voltages using a plurality of horizontal scanning periods at the beginning of a frame.
The solid-state imaging device according to claim 1, wherein the calibration unit performs the calibration every frame or every other frame.
The calibration unit corrects the digital signal obtained by the AD conversion unit by causing the AD conversion unit to input a maximum value and a minimum value of the voltage interval for each of the plurality of voltage intervals. The solid-state imaging device according to claim 1, wherein the data is created.
4. The solid according to claim 3, wherein the calibration unit creates the correction data by causing the AD conversion unit to input the same reference voltage as the maximum value and the minimum value of each of the adjacent voltage sections. 5. Imaging device.
The calibration unit uses the first arithmetic unit that generates the correction data, a storage device that stores the generated correction data, and the AD conversion using the correction data stored in the storage device. The solid-state imaging device according to claim 3, further comprising: a second arithmetic unit that creates calibrated data from the digital signal obtained by the unit, and outputs the calibrated data as an AD conversion result.
The higher-order bit conversion unit is a flash type AD converter, specifies a voltage interval in which the pixel signal is included by comparing the pixel signal and the plurality of reference signals all at once, and the specified voltage The reference voltage that is the base point of the section is output as an offset voltage to the lower bit conversion unit,
The low-order bit conversion unit is a single slope type AD converter, which compares a difference voltage between the pixel signal and the offset voltage with a ramp wave that fluctuates with a constant slope, and the comparison result is inverted. 2. The solid-state imaging device according to claim 1, wherein a value of a built-in counter that operates in conjunction with the ramp wave is read and the value of the counter is output as a conversion result of the lower bit conversion unit.
The calibration unit, for a plurality of voltage sections based on each reference voltage, the reference voltage that is the minimum value of the plurality of voltage sections and the reference voltage that is the maximum value are input to the lower bit conversion unit, The solid-state imaging device according to claim 6, wherein correction data for correcting a digital signal obtained by the AD conversion unit is created from a count value obtained by the lower bit conversion unit obtained for each input. .
In the calibration, the low-order bit conversion unit overscans the ramp wave to a value exceeding a predetermined maximum conversion value of the low-order bit conversion unit in a plurality of voltage sections based on the reference voltages. The solid-state imaging device according to claim 6, wherein the maximum value of the plurality of voltage sections is converted as a digital value by performing.
The solid-state imaging device according to claim 1, wherein the AD conversion unit further includes an interphase double sampling circuit.
A semiconductor integrated circuit device including a plurality of pixel circuits, an AD conversion unit, and a calibration unit included in the solid-state imaging device according to claim 1.
A camera comprising the solid-state imaging device according to claim 1.
A signal processing method in a solid-state imaging device that repeats imaging in frame units,
The solid-state imaging device
An imaging unit having a plurality of pixel circuits arranged in a matrix and photoelectrically converting received light;
An AD converter that converts pixel signals from the plurality of pixel circuits into digital signals for each column of the pixel circuits;
The AD converter is
A reference voltage generator that generates a plurality of different reference voltages within a voltage range that the pixel signal can take;
For each of the columns, a voltage section including the pixel signal is identified from a plurality of voltage sections based on each of the plurality of reference voltages, and the identification result is output as the value of the high-order bit of the digital signal A bit conversion unit;
A low-order bit conversion unit that converts a difference voltage between a reference voltage that is a base point of the specified voltage section and the pixel signal into a low-order bit of the digital signal for each column;
The signal processing method includes:
A calibration step for calculating a correction coefficient by performing calibration of the plurality of reference voltages in a plurality of voltage sections based on the respective reference voltages using a plurality of horizontal scanning periods at the beginning of a frame;
And a correction step of performing correction on lower bits obtained by conversion of the pixel signal by the lower bit conversion unit using the calculated correction coefficient.