WO2011126578A1 - Mise en œuvre de planification de décodage sélectif ldpc - Google Patents

Mise en œuvre de planification de décodage sélectif ldpc Download PDF

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Publication number
WO2011126578A1
WO2011126578A1 PCT/US2011/000646 US2011000646W WO2011126578A1 WO 2011126578 A1 WO2011126578 A1 WO 2011126578A1 US 2011000646 W US2011000646 W US 2011000646W WO 2011126578 A1 WO2011126578 A1 WO 2011126578A1
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Prior art keywords
group
check node
check
groups
cost function
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PCT/US2011/000646
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English (en)
Inventor
Kin Man Ng
Kwok W. Yeung
Lingqi Zeng
Yu Kou
Aditi R. Ganesan
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Link_A_Media Devices Corporation
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Priority to CN201180017954.8A priority Critical patent/CN102859885B/zh
Priority to KR1020127029196A priority patent/KR101610727B1/ko
Publication of WO2011126578A1 publication Critical patent/WO2011126578A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices

Definitions

  • Low-density parity-check (LDPC) codes are a type of error correcting code.
  • LDPC codes are becoming increasingly popular for encoding data that is written to storage media, such as hard disk drives or flash drives.
  • LDPC layered decoding When compared to other message-passing scheduling methods, e.g., flooding scheduling, LDPC layered decoding has better convergence speed in terms of the number of iterations and better decoding performance. Therefore, it would be desirable to develop techniques for LDPC layered decoding.
  • Figure 1 is a flowchart illustrating an embodiment of a process for decoding data.
  • Figure 2 is a diagram showing some embodiments of groups of check nodes.
  • Figure 3 is a flowchart illustrating an embodiment of a process for subsequent processing of distorted LDPC encoded data.
  • Figures 4 and 5 show an embodiment of a group of check nodes that are processed in a selective order based on a cost function.
  • Figures 6A and 6B show an embodiment that uses a cost function that takes as input information associated with a check node.
  • Figure 7 is a diagram showing an embodiment of reliability values associated with variable nodes.
  • Figure 8 is a diagram showing an embodiment of a disk drive system that includes an error correction decoder configured to use a cost function to select a group of check nodes.
  • Figure 9 is a diagram showing an embodiment of a system configured to select a group of check nodes based on a cost function.
  • Figure 10 is a diagram showing an embodiment of a cost function evaluator configured to evaluate a cost function and select a group of check nodes based on the
  • Figure 1 1 is a diagram showing an embodiment of a system 1 100 that includes a check node memory block 1 102, a selective layered decoding scheduler 1 104, and an LDPC layered decoder 1 106 for processing groups of check nodes in a selective order based on a cost function.
  • Figure 12 is a diagram showing an embodiment of an LDPC matrix 1200 partitioned into a plurality of groups of check node layers.
  • Figure 13 is a diagram showing an exemplary embodiment of selective layered decoding scheduling.
  • Figure 14 is a diagram showing a second exemplary embodiment of selective layered decoding scheduling.
  • the invention can be implemented in numerous ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer readable storage medium; and/or a processor, such as a processor configured to execute instructions stored on and/or provided by a memory coupled to the processor.
  • these, implementations, or any other form that the invention may take, may be referred to as techniques.
  • the order of the steps of disclosed processes may be altered within the scope of the invention.
  • a component such as a processor or a memory described as being configured to perform a task may be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task.
  • the term 'processor' refers to one or more devices, circuits, and/or processing cores configured to process data, such as computer program instructions.
  • the techniques described herein are implemented in a variety of systems or forms.
  • the techniques are implemented in hardware as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA).
  • ASIC application-specific integrated circuit
  • FPGA field-programmable gate array
  • a processor e.g., an embedded one such as an ARM core
  • the technique is implemented as a computer program product which is embodied in a computer readable storage medium and comprises computer instructions.
  • Figure 1 is a flowchart illustrating an embodiment of a process for decoding data.
  • LDPC codes are a class of error correction codes.
  • An LDPC code is defined as the null space of a sparse parity-check matrix H .
  • An LDPC codeword ⁇ ⁇ °' ' is a vector in the null space which can satisfy all the check nodes of H.
  • An LDPC code can achieve relatively good error performance by using a message passing algorithm (such as SPA (sum-product algorithm), min-sum, etc.).
  • the parity-check matrix H of an LDPC code is related to a bipartite graph, also referred to as a Tanner Graph.
  • the nodes of the Tanner Graph G are divided into two sets of nodes, V and C .
  • V contains n variable nodes v . (or left nodes), corresponding to the columns of H , and m check nodes c, (or right nodes), corresponding to the rows of H .
  • a variable node v . is connected to a check node if and only if the corresponding entry A ( of the parity-check matrix H is non-zero.
  • the degree of a node in G is defined as the number of edges connected to it.
  • the degree of a variable node is simply equal to the weight of its corresponding column of H
  • the degree of a check node is simply equal to the weight of its corresponding row of H .
  • a cost function is obtained.
  • a cost function receives as an input information associated with variable nodes, such as the distorted reliability value associated with each variable node and the updated message from the connected check nodes.
  • / is a function of check nodes information, such as the number of unsatisfied check nodes within each group of check nodes.
  • a cost function is a function of both check nodes and variable nodes information.
  • a cost function will also include some special constraints (e.g., the same group of check nodes is never processed twice in the same iteration and/or the same group of check nodes is never processed consecutively even in the different iterations.).
  • a cost function is evaluated for each of a plurality of groups of check nodes using information associated with variable nodes and/or information associated with check nodes at 102. Some examples of specific cost functions are described in further detail below.
  • One of the groups of check nodes is selected based at least in part on the evaluated cost functions at 104. For example, in some embodiments the group minimizing/maximizing the evaluated cost function is selected. If there is more than one group that minimizes the cost function, another cost function can be used to conduct the further selection. If there are still multiple groups remaining after evaluating all the cost functions, one of the groups is chosen arbitrarily in some embodiments.
  • processing related to error correction decoding is performed on data associated with the selected group of check nodes.
  • this includes performing a check node update (e.g., by computing - for each check node in the selected group - an outgoing message to each connected variable node v . based on the incoming messages from all the other connected variable nodes v ..(_ ' ⁇ j) ) and a variable node update (e.g., by computing— for each variable node v . connected to any check node in the selected group— its outgoing message to each connected check node c, based on the incoming messages from all the other connected check nodes c r (V ⁇ i) ).
  • a check node update e.g., by computing - for each check node in the selected group - an outgoing message to each connected variable node v . based on the incoming messages from all the other connected variable nodes v ..(_ ' ⁇ j)
  • a variable node update e
  • One benefit to using the technique described herein is that error correction decoding (at least in some cases) is completed in a shorter amount of time than some other techniques. For example, suppose there are m groups of check nodes, each group including a single check node. Compared to an HSS processing technique that always processes the groups of check nodes in the order Group 1, Group 2, ..., Group m , the technique described herein may finish sooner. For example, if some error or noise remains in Group m (i.e., the last group to be processed by the HSS technique in an iteration) then the technique described herein will likely select and process data associated with Group m before the HSS technique does.
  • Figure 2 is a diagram showing some embodiments of groups of check nodes.
  • the example process shown in Figure 1 is used to select a group of check nodes using a cost function.
  • the first example shown (diagram 210)
  • Each of the 4 check nodes is in turn connected to 3 of the 6 total variable nodes.
  • the connections control the propagation of information during error correction decoding of the distorted LDPC encoded data.
  • the first group of check nodes (Group 1) includes 3 check nodes:
  • the second group of check nodes (Group 2) includes a single check node: 200d.
  • a cost function is evaluated.
  • the evaluated cost function has a value of 3.
  • the evaluated cost function has a value of 5.
  • the group with the lowest evaluated cost function is selected (that is, Group 1), and error correction processing is performed on equations or functions associated with the selected group (i.e., Group 1 in this example).
  • Diagram 220 shows the same variable nodes, check nodes, and connections as in diagram 210 with different groups of check nodes.
  • a cost function is evaluated.
  • the values of the evaluated cost function are 7, 4, 1 , and 4, respectively.
  • the group with the highest evaluated cost function is selected, and error correction decoding is performed on function(s)/equation(s) associated with Group A.
  • check node updating (used in some embodiments at 106 in Figure 1) is shown below.
  • the selected group includes check nodes 200a - 200c.
  • check node updating for each check node in the selected group, an outgoing message is determined to each connected variable node based on the incoming messages from all other connected variable nodes. Note that check node 200d is not included in the table below because it is not in the selected group.
  • node 20 le variable nodes 201a
  • Table 1 Check node update using diagram 210 as an example
  • variable node updating (used in some embodiments at 106 in Figure 1) is shown below.
  • check node updating is performed first, and then variable node updating is performed.
  • variable node updating for each variable node connected to a check node in the selected group (in this example, all of the variable nodes are connected to a check node in the selected group), an outgoing message is determined to be sent to a connected check node based on the incoming messages from all other connected check nodes.
  • a group of check nodes can include one or more check nodes.
  • each group has the same number of check nodes (see, e.g., diagram 220); in other embodiments, the groups have different numbers of check nodes in them (see, e.g., diagram 210).
  • FIG. 3 is a flowchart illustrating an embodiment of a process for subsequent processing of distorted LDPC encoded data.
  • the process shown in Figure 1 continues. Some of the processing shown in this figure is/are similar to processing shown in Figure 1.
  • steps 102 and 308 evaluate a cost function
  • steps 104 and 310 select a group of check nodes based on an evaluated cost function
  • steps 106 and 312 perform processing related to error correction decoding.
  • a (e.g., single) hardware component or other processor is used to perform similar steps in Figures 1 and 3.
  • it is determined if error correction decoding is completed. In some embodiments, this includes checking if all the parity checks are satisfied.
  • a full or complete iteration includes 2 selections (one for Group 1 and one for Group 2), and in diagram 220 a complete or full iteration includes 4 instances of selecting/processing (one each for Groups A - D).
  • step 308 is skipped and the single remaining group is selected without evaluating a cost function.
  • one of the remaining groups is selected based at least in part on the evaluated cost functions. Processing related to error correction decoding is performed on data associated with selected group of check nodes at 312.
  • Figures 4 and 5 show an embodiment of a group of check nodes that are processed in a selective order based on a cost function.
  • the example process of Figure 1 is used to select group of check nodes 401a based on the evaluation of a cost function for groups 401a - 40 Id.
  • the evaluated cost functions for Groups A - D are (respectively) 7, 4, 1 , and 4, and (at least in this example) the group with the highest evaluated cost function is selected (i.e., Group A).
  • the cost function is evaluated for a second time, and at least in this example the evaluated cost functions for each group are different in diagrams 400 and 402.
  • the evaluated cost functions for Groups B - D are 3, 0, and 6, respectively.
  • Group D is selected since it has the highest evaluated cost function.
  • Error correction processing is not done (e.g., one or more parity checks are still not satisfied), and in diagram 404 the cost function is evaluated again in Figure 5.
  • Group B is selected because it has a higher evaluated cost function (3) compared to Group C (2).
  • diagram 406 only Group C remains since all other groups (i.e., Groups A, B, and D) have been selected.
  • the cost function is not evaluated when only one group of check nodes remains or is otherwise eligible.
  • Figures 6A and 6B show an embodiment that uses a cost function that takes as input information associated with a check node.
  • the group of check nodes with the least number of unsatisfied check nodes is selected.
  • this technique is used in applications or environments where there is a relatively low signal-to-noise ratio (SNR).
  • Diagram 600 shows a first selection of the i th iteration .
  • unsatisfied check nodes e.g., a parity check associated with that check node is not passing
  • Groups 601c and 60 Id have the least number of unsatisfied check nodes (i.e., 0 unsatisfied check nodes), and there is a tie between them.
  • Group 601c is selected in this example.
  • the second selection of the iteration (e.g., after processing of data associated with selected group 601c is completed) is shown in diagram 602.
  • group 60 Id has the least number of unsatisfied check nodes and is selected.
  • the third selection of the i th iteration is shown in diagram 604. During that selection, groups 601a and 601b have not been selected yet in the i th iteration, and group 601a is selected since the check node in group 601b is an unsatisfied check node.
  • Figure 6B includes diagram 606 which shows the fourth selection of the i th iteration.
  • Group 601b is the only group remaining and is selected.
  • a new iteration starts in diagram 608.
  • groups 601b and 601d are tied (based strictly on number of unsatisfied check nodes) since both have the least number of unsatisfied check nodes. So group 60 Id is selected arbitrarily, at least in this example. In some embodiments, group 60 Id is the only eligible selection because of the constraint (e.g., in the cost function) that no consecutive processing is performed on the same group of check nodes.
  • groups 601a - 601c have not been selected yet in the (i+l) th iteration, and group 601b is selected because it has the least number of unsatisfied check nodes.
  • Figure 7 is a diagram showing an embodiment of reliability values associated with variable nodes.
  • information associated with a variable node such as a reliability value
  • a reliability value can be a positive value or a negative value
  • the example processes below use the absolute value (e.g., magnitude or amplitude) of the reliability values.
  • an average of the reliability values is determined first for all groups, and then the group with the largest average is selected. Using the reliability values shown in Figure 7, an example of this is shown below.
  • any tiebreaker can be employed including (for example) randomly selecting one of the groups, selecting a default group (e.g., first/last group), selecting the group that has gone the longest since it was last selected, etc.
  • Reliability values for associated Average of reliability values variable nodes absolute value
  • Table 3 An example of selecting a group wit l the largest average reliability
  • Group C (801c) is selected using this technique and with the example reliability values.
  • Table 4 An example of selecting a group with the least number of reliabilities below a threshold
  • the group with the largest of the smallest reliabilities is selected. That is, first, the smallest reliability value for each group is selected and then the group with largest of those values is selected.
  • the table below shows an example using the reliability values from Figure 7.
  • Group C (801c) is selected using this technique and with the example reliability values.
  • Table 5 An example of selecting a group with the largest of smallest reliability values
  • the three techniques shown above in Tables 3 - 5 are used in applications or cases where a SNR is relatively low. In some such low SNR environments, many small errors exist, and the techniques described above are directed towards spreading more reliable data or information earlier than "bad" data or information.
  • the examples above can be modified.
  • the group with the smallest average reliability values is selected.
  • the group having the most number of variable nodes with a reliability value below a present threshold is selected.
  • the group having the smallest reliability value is selected for each group the smallest reliability value is selected, then the group having the smallest of those reliability values is selected (i.e., smallest of smallest reliability values).
  • the group having the most number of unsatisfied check nodes is selected.
  • the examples described above are used when SNR is relatively high such that only a very small number of errors exist. Therefore, there is a higher chance to select a group of check nodes which the error variable nodes are associated with and can be corrected.
  • Figure 8 is a diagram showing an embodiment of a disk drive system that includes an error correction decoder configured to use a cost function to select a group of check nodes. For clarity, some components may not necessarily be shown.
  • encoded data e.g., encoded using an LDPC code
  • ADC analog to digital converter
  • filter 802. The filtered data is passed to soft output detector 804 which in turn is coupled to error correction decoder 806.
  • Error correction decoder 806 is configured to select a group of check nodes based on a cost function and process data associated with the selected group.
  • an error correction decoder configured to select a group of check nodes using a cost function is included in some other system or is used in some other application or environment besides storage.
  • Figure 9 is a diagram showing an embodiment of a system configured to select a group of check nodes based on a cost function.
  • error correction decoder 806 from Figure 8 includes the system shown.
  • the system shown in this figure is configured using any appropriate components.
  • a general purpose processor is configured to perform the functions described herein.
  • cost function evaluator 902 obtains the pertinent variable and/or check node information from Tanner Graph matrix 904; this information is used to evaluate a cost function.
  • cost function evaluator 902 specifies a group to Tanner Graph matrix 904, and related variable node and/or check node information is passed from Tanner Graph matrix 904.
  • Tanner Graph matrix 904 stores the connections between variable nodes and check nodes; the particular connections will depend upon the particular LDPC code used. Tanner Graph matrix 904 also stores information related to the variable nodes and check nodes, for example, related to which check nodes are unsatisfied (e.g., based on a parity check) and/or reliability values associated with the variable nodes.
  • cost function evaluator 902 is configurable. For example, it may include an interface configured to receive or otherwise obtain a cost function. In some embodiments, the particular information obtained from Tanner Graph matrix 904 will vary depending upon the particular cost function programmed into or otherwise provided to cost function evaluator 902.
  • cost function evaluator 902 After evaluating the cost function for all the groups (if appropriate), one of the groups is selected and is output by cost function evaluator 902 as the selected group.
  • cost function evaluator 902 is configured to not evaluate the cost function if there is only a single remaining group. For example, if there is one group and it is the first selection of an iteration, that group is selected without evaluating the cost function. That is, flooding schedule is a special case.
  • the selected group is passed from cost function evaluator 902 to message updater
  • Message updater 906 performs processing related to error correction decoding on data associated with the selected group. For example, message updater 906 may perform check node updates and/or variable node updates on data stored in Tanner Graph matrix 904 related to the selected group.
  • parity checker 908 determines if error correction decoding is completed by checking if all parity checks are satisfied using information stored in Tanner Graph matrix 904. If error correction is not completed, parity checker 908 sends a "continue decoding" signal to cost functions evaluator 902 and the next group is selected.
  • Figure 10 is a diagram showing an embodiment of a cost function evaluator configured to evaluate a cost function and select a group of check nodes based on the
  • cost function evaluator 902 in Figure 9 is implemented as shown.
  • the cost function takes as an input reliability values for associated variable nodes.
  • functions performed by and/or information input to a corresponding cost function evaluator are different than the example shown.
  • the reliability values of variable nodes that are connected to that check node are obtained.
  • An average of the reliability values is determined for each check node in the given group by averager 1000.
  • the average along with its corresponding group is passed from averager 1000 to storage 1002 where the information is stored.
  • selector 1004 accesses the stored averages and selects the group with the largest stored average; that group is output as the selected group.
  • there is a tie and selector 1004 is configured to perform tie breaking. For example, a random group can be selected from the tied groups, the tied group that has not been selected for the longest period of time, or a default group (e.g., first/last tied group in some order) is selected.
  • processing groups of check nodes in a selective order based on a cost function can be applied to LDPC layered decoding.
  • This is referred to herein as selective layered decoding scheduling.
  • a parity-check matrix H includes a plurality of horizontal layers.
  • LDPC layered decoding is performed by applying the decoding algorithm layer by layer.
  • LDPC layered decoding has better convergence speed in terms of the number of iterations and better decoding performance.
  • LDPC layered decoding check node updates and variable node updates are performed layer by layer.
  • an LDPC code can be defined by a sparse parity- check matrix H.
  • the variable nodes representing the information bits correspond to the columns of H, and the check nodes implementing the parity-check for the matrix H correspond to the rows of H.
  • messages are passed between the variable nodes and the check nodes.
  • an outgoing message from the check node to each connected variable node is determined based on the incoming messages to the check node from all other connected variable nodes.
  • variable node update for each variable node connected to a check node in the layer, an outgoing message from the variable node to each connected check node is determined based on the incoming messages to the variable node from all other connected check nodes.
  • a check node update is performed first, and then a variable node update is performed. In this manner, check node updates and variable node updates are performed, layer by layer, until a termination condition is reached.
  • a check node update (indicated by a "C” in the following table) is performed on the i th layer and a variable node update (indicated by a "V” in the following table) is performed on the (i-l) th layer as shown in the table below.
  • a check node update is performed on the (i+l) th layer and a variable node update is performed on the i th layer. Note that a check node update is first performed on a particular layer, and then a variable node update is performed on the same layer during the next layer iteration.
  • check node layers are partitioned into a plurality of groups.
  • a check node update may be performed on a layer other than the (i+l) th layer, for example, the (k) th layer.
  • a variable node update is still performed on the i th layer during the 2 nd layer iteration.
  • Figure 1 1 is a diagram showing an embodiment of a system 1 100 that includes a check node memory block 1102, a selective layered decoding scheduler 1 104, and an LDPC layered decoder 1 106 for processing groups of check nodes in a selective order based on a cost function.
  • Check node memory block 1 102 stores the results of check node updates (e.g., messages sent from a check node to a variable node) for different check node layers.
  • Selective layered decoding scheduler 1 104 obtains one or more cost functions, evaluates the cost function(s), selects a group to be decoded next, and sends the selected group to LDPC layered decoder 1 106 to be decoded.
  • LDPC layered decoder 1 106 implements LDPC layered decoding.
  • System 1 100 may be used for selective layered decoding and switching check node updates from one layer to another as will be described in greater detail below.
  • Check node memory block 1 102 stores the results of check node updates for different check node layers. For example, the results include messages sent from a check node to a variable node during a check node update.
  • Check node memory block 1 102 is partitioned into a plurality of groups of layers such that selective layered decoding scheduler 1 104 may select which group to send to LDPC layered decoder 1 106 for decoding.
  • FIG. 12 is a diagram showing an embodiment of an LDPC matrix 1200 partitioned into a plurality of groups of check node layers.
  • LDPC matrix L200 includes five groups, each group has four layers, and thus LDPC matrix 1200 has a total of twenty check node layers.
  • LDPC matrix 1200 in Figure 12 may be a parity-check matrix H for a quasi-cyclic LDPC code (QC-LDPC code).
  • Each square 1202 is a circulant matrix, which is a square matrix.
  • an empty square 1202 is a zero matrix
  • a square 1202 denoted by "1" is a square matrix with a column weight of one as shown below:
  • the column weight is one in the above example because each column of the circulant matrix has only a single coefficient with a value of one.
  • Parity-check matrix H may be viewed as containing "columns" of circulant matrices, each such "column” referred to as a circulant matrix column.
  • Group 1 has two circulant matrices with column weights of one in each circulant matrix column. Hence, Group 1 has a column weight of two for each of its
  • Group 1 has a group column weight of two.
  • Groups 2 through 5 also have column weights equal to two for their respective circulant matrix columns, and thus LDPC matrix 1200 has an overall column weight of ten for its circulant matrix columns.
  • the size of the square matrix shown above is a 3 by 3 matrix; however, other square matrices of different sizes may be used as well.
  • Partitioning LDPC matrix 1200 into a plurality of groups, each group having many zero matrices and a low group column weight (e.g., one or two), has a number of advantages. For example, when the group column weight for each group is only one, then only one non-zero layer (active layer) within each group needs to be processed at a time. Therefore, selective layered decoding scheduler 1 104 may select the only non-zero layer within each group and send the non-zero layer to LDPC layered decoder 1 106 for decoding at a time. In some embodiments, a multiplexer (MUX) structure may be used, which simplifies the overall hardware design and reduces the amount of hardware required for system 1 100.
  • MUX multiplexer
  • LDPC layered decoder 1 106 is also simplified because the decoder only needs to process a single layer at a time.
  • an LDPC matrix may be constructed in such a way that the group number is reduced. With fewer groups, the decoding latency can be reduced, thus improving the decoding performance of the system.
  • selective layered decoding scheduler 1 104 is coupled with check node memory block 1 102 and LDPC layered decoder 1 106.
  • Selective layered decoding scheduler 1 104 obtains one or more cost functions, evaluates the cost function(s), selects a group to be decoded next based on the cost function(s), and sends the selected group to LDPC layered decoder 1 106 to be decoded.
  • the cost function evaluated by selective layered decoding scheduler 1 104 can be any of the cost functions described in the present application.
  • the group with the least number of unsatisfied check nodes is selected.
  • an average of the reliability values associated with variable nodes is determined first for all groups, and then the group with the largest average is selected.
  • the group with the least number of reliability values below a threshold is selected.
  • the group with the largest of the smallest reliabilities is selected.
  • Figure 13 is a diagram showing an exemplary embodiment of selective layered decoding scheduling. It shows a schedule for LDPC layered decoding when an LDPC matrix is partitioned into four groups of check node layers.
  • a variable node update is indicated by a "V”
  • a check node update is indicated by a "C”
  • a group prefetch is indicated by a "P.”
  • a group prefetch P is performed first. P selects the next group for which a check node update is performed. It prepares for a check node update to be performed on the selected group during the next layer iteration.
  • a P is performed on a particular group during the n th layer iteration, a C is performed on the same group during the (n+l) th iteration, and a V is performed on the same group during the (n+2) th iteration.
  • a P is performed on Group 3 during the 1 st layer iteration
  • a C is performed on Group 3 during the 2 nd layer iteration
  • a V is performed on Group 3 during the 3 rd layer iteration.
  • P, C, and V are performed one after the other for Group 4 during the 2 nd to 4 th layer iterations.
  • V, C, and P can be performed simultaneously during a particular layer iteration.
  • V, C, and P are each performed on a different group during that layer iteration. For example, during the 1 st layer iteration, a V is performed on Group 1 , a C is performed on Group 2, and a P is performed on Group 3.
  • P selects the next group for which a check node update is performed. It prepares for a check node update to be performed on the selected group during the next layer iteration. In some embodiments, P selects the next group based on a cost function only once in every few layer iterations. In some embodiments, P selects the next group based on a cost function at each layer iteration.
  • P selects the next group based on a cost function only once in every few layer iterations.
  • P selects the next group based on a cost function after all of the groups have a variable node update at least once.
  • each of the groups has a variable node update at least once after the 4 th iteration;
  • P selects Group 4 based on a cost function during the 5 th iteration, and Group 3 is skipped.
  • each of the groups has a variable node update at least once from the 5 th to the 10 th layer iteration. Accordingly, P selects Group 2 based on a cost function during the 1 1 th layer iteration.
  • P may be limited to only selecting Group 3 or Group 4 because Group 1 has a variable node update and Group 2 has a check node update performed at that time.
  • Figure 14 is a diagram showing a second exemplary embodiment of selective layered decoding scheduling.
  • P selects the next group based on a cost function at each layer iteration.
  • a subset of the groups may not be eligible for P to select from based on a cost function. For example, during the 1 st layer iteration, a variable node update is performed on Group 1, and a check node update is performed on Group 2; therefore, the groups available for prefetching are Group 3 and Group 4 only, and P selects Group 3 based on a cost function.
  • the groups available for prefetching is reduced to Group 4 only because prefetching a Group twice within the iterations between resetting the groups for prefetch selection to all groups is not preferred in this embodiment.
  • the groups available are reset back to all four groups.
  • the groups available for prefetching are reduced to Group 3 only because prefetching Group 2 twice within the iterations between resetting the groups for prefetch selection to all groups is not preferred in this embodiment.
  • the groups available for prefetching are reset back to all four groups.

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  • Physics & Mathematics (AREA)
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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
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Abstract

L'invention porte sur un procédé de décodage de données. Le procédé comprend le partitionnement d'une matrice de contrôle de parité à faible densité (LDPC) en une pluralité de groupes, comportant chacun une ou plusieurs couches de nœud de contrôle. Le procédé comprend en outre la sélection de l'un des groupes sur la base au moins en partie d'une fonction de coût, la fonction de coût étant obtenue au moins en partie sur la base des informations associées à un nœud variable, ou des informations associées à un nœud de contrôle, ou sur la base des deux types d'informations. Le procédé comprend en outre l'exécution d'un décodage en couches LDPC sur le groupe sélectionné.
PCT/US2011/000646 2010-04-09 2011-04-11 Mise en œuvre de planification de décodage sélectif ldpc WO2011126578A1 (fr)

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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8751912B1 (en) * 2010-01-12 2014-06-10 Marvell International Ltd. Layered low density parity check decoder
US8756478B2 (en) * 2011-09-07 2014-06-17 Lsi Corporation Multi-level LDPC layer decoder
US8656249B2 (en) * 2011-09-07 2014-02-18 Lsi Corporation Multi-level LDPC layer decoder
US8954816B2 (en) * 2011-11-28 2015-02-10 Sandisk Technologies Inc. Error correction coding (ECC) decode operation scheduling
US8819515B2 (en) * 2011-12-30 2014-08-26 Lsi Corporation Mixed domain FFT-based non-binary LDPC decoder
US9015547B2 (en) * 2012-08-17 2015-04-21 Lsi Corporation Multi-level LDPC layered decoder with out-of-order processing
US8972826B2 (en) 2012-10-24 2015-03-03 Western Digital Technologies, Inc. Adaptive error correction codes for data storage systems
US9021339B2 (en) 2012-11-29 2015-04-28 Western Digital Technologies, Inc. Data reliability schemes for data storage systems
US9059736B2 (en) 2012-12-03 2015-06-16 Western Digital Technologies, Inc. Methods, solid state drive controllers and data storage devices having a runtime variable raid protection scheme
US9191256B2 (en) 2012-12-03 2015-11-17 Digital PowerRadio, LLC Systems and methods for advanced iterative decoding and channel estimation of concatenated coding systems
US9122625B1 (en) 2012-12-18 2015-09-01 Western Digital Technologies, Inc. Error correcting code encoder supporting multiple code rates and throughput speeds for data storage systems
US9619317B1 (en) 2012-12-18 2017-04-11 Western Digital Technologies, Inc. Decoder having early decoding termination detection
US8966339B1 (en) 2012-12-18 2015-02-24 Western Digital Technologies, Inc. Decoder supporting multiple code rates and code lengths for data storage systems
US9214963B1 (en) 2012-12-21 2015-12-15 Western Digital Technologies, Inc. Method and system for monitoring data channel to enable use of dynamically adjustable LDPC coding parameters in a data storage system
US9231619B2 (en) * 2013-02-04 2016-01-05 SK Hynix Inc. LDPC decoder with a variable node updater which uses a scaling constant
US9325347B1 (en) * 2014-02-21 2016-04-26 Microsemi Storage Solutions (U.S.), Inc. Forward error correction decoder and method therefor
US9344116B2 (en) * 2014-05-29 2016-05-17 Yuan Ze University Method for determining layer stoppage in LDPC decoding
US20160091951A1 (en) * 2014-09-29 2016-03-31 Lsi Corporation Systems and Methods for Power Reduced Data Decoder Scheduling
US10075190B2 (en) * 2015-10-27 2018-09-11 Sandisk Technologies Llc Adaptive scheduler for decoding
TWI583141B (zh) * 2016-05-12 2017-05-11 國立清華大學 低密度奇偶檢查碼的解碼方法與解碼器
US10425104B2 (en) 2016-11-11 2019-09-24 Electronics And Telecommunications Research Institute Scheduling method of a parity check matrix and an LDPC decoder for performing scheduling of a parity check matrix
US10637503B2 (en) * 2018-08-03 2020-04-28 Innogrit Technologies Co., Ltd. Systems and methods for decoding low density parity check encoded codewords
US11177830B2 (en) 2019-09-10 2021-11-16 Samsung Electronics Co., Ltd. Method and apparatus for data decoding in communication or broadcasting system
FR3108221B1 (fr) * 2020-03-11 2022-03-11 Commissariat Energie Atomique Méthode de décodage de codes ldpc à inversion de bits et effet inertiel
KR20210115961A (ko) 2020-03-17 2021-09-27 에스케이하이닉스 주식회사 Ldpc 디코더 및 그것의 동작 방법
US11863201B2 (en) * 2022-04-01 2024-01-02 Qualcomm Incorporated Correlation-based hardware sequence for layered decoding

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050091565A1 (en) * 2003-10-27 2005-04-28 Mustafa Eroz Method and apparatus for providing reduced memory low density parity check (LDPC) codes
US20080028274A1 (en) * 2006-07-25 2008-01-31 Communications Coding Corporation Universal error control coding scheme for digital communication and data storage systems
US20090013237A1 (en) * 2007-07-02 2009-01-08 Broadcom Corporation Distributed processing ldpc (low density parity check) decoder
US20090327847A1 (en) * 2005-01-10 2009-12-31 Broadcom Corporation LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7139959B2 (en) * 2003-03-24 2006-11-21 Texas Instruments Incorporated Layered low density parity check decoding for digital communications
JP2008515342A (ja) * 2004-10-01 2008-05-08 トムソン ライセンシング 低密度パリティ検査（ｌｄｐｃ）復号器
KR100913876B1 (ko) * 2004-12-01 2009-08-26 삼성전자주식회사 저밀도 패리티 검사 부호의 생성 방법 및 장치
CN100490334C (zh) * 2005-01-10 2009-05-20 美国博通公司 构建和选择基于grs不规则ldpc码的方法
US7536629B2 (en) 2005-01-10 2009-05-19 Broadcom Corporation Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code
US7660368B2 (en) * 2005-01-11 2010-02-09 Qualcomm Incorporated Bit log likelihood ratio evaluation
KR100941680B1 (ko) * 2005-07-01 2010-02-12 삼성전자주식회사 준순환 저밀도 패리티 검사 부호의 생성 방법 및 장치
US20070245217A1 (en) 2006-03-28 2007-10-18 Stmicroelectronics S.R.L. Low-density parity check decoding
FR2904499B1 (fr) * 2006-07-27 2009-01-09 Commissariat Energie Atomique Procede de decodage a passage de messages avec ordonnancement selon une fiabilite de voisinage.
KR100981501B1 (ko) 2006-11-06 2010-09-10 연세대학교 산학협력단 통신 시스템에서 신호 송신 장치 및 방법
US8418023B2 (en) 2007-05-01 2013-04-09 The Texas A&M University System Low density parity check decoder for irregular LDPC codes
WO2009004601A2 (fr) * 2007-07-02 2009-01-08 Technology From Ideas Limited Génération d'une matrice de contrôle de parité
US8156409B2 (en) 2008-02-29 2012-04-10 Seagate Technology Llc Selectively applied hybrid min-sum approximation for constraint node updates of LDPC decoders
US20100037121A1 (en) * 2008-08-05 2010-02-11 The Hong Kong University Of Science And Technology Low power layered decoding for low density parity check decoders
US8464129B2 (en) * 2008-08-15 2013-06-11 Lsi Corporation ROM list-decoding of near codewords
US8291285B1 (en) * 2008-09-18 2012-10-16 Marvell International Ltd. Circulant processing scheduler for layered LDPC decoder
US8219873B1 (en) * 2008-10-20 2012-07-10 Link—A—Media Devices Corporation LDPC selective decoding scheduling using a cost function
US8407555B2 (en) * 2009-03-30 2013-03-26 Broadcom Corporation LDPC codes robust to non-stationary narrowband ingress noise

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050091565A1 (en) * 2003-10-27 2005-04-28 Mustafa Eroz Method and apparatus for providing reduced memory low density parity check (LDPC) codes
US20090327847A1 (en) * 2005-01-10 2009-12-31 Broadcom Corporation LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices
US20080028274A1 (en) * 2006-07-25 2008-01-31 Communications Coding Corporation Universal error control coding scheme for digital communication and data storage systems
US20090013237A1 (en) * 2007-07-02 2009-01-08 Broadcom Corporation Distributed processing ldpc (low density parity check) decoder

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US20110252294A1 (en) 2011-10-13
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