WO2011123985A1 - 制作多层发光二极管阵列的方法 - Google Patents

制作多层发光二极管阵列的方法 Download PDF

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Publication number
WO2011123985A1
WO2011123985A1 PCT/CN2010/000462 CN2010000462W WO2011123985A1 WO 2011123985 A1 WO2011123985 A1 WO 2011123985A1 CN 2010000462 W CN2010000462 W CN 2010000462W WO 2011123985 A1 WO2011123985 A1 WO 2011123985A1
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WO
WIPO (PCT)
Prior art keywords
emitting diode
light emitting
fabricating
array type
diode according
Prior art date
Application number
PCT/CN2010/000462
Other languages
English (en)
French (fr)
Inventor
胡仲孚
吴永富
Original Assignee
盈胜科技股份有限公司
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Filing date
Publication date
Application filed by 盈胜科技股份有限公司 filed Critical 盈胜科技股份有限公司
Priority to PCT/CN2010/000462 priority Critical patent/WO2011123985A1/zh
Publication of WO2011123985A1 publication Critical patent/WO2011123985A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements

Definitions

  • the present invention relates to a method of fabricating a multilayer array type light emitting diode, and more particularly to a method of packaging a light emitting diode which can simplify the manufacturing process and thereby reduce manufacturing cost and time.
  • LED illumination According to the principle of LED illumination, it is based on the inherent characteristics of semiconductors. It is different from the discharge and heat-emitting principle of incandescent lamps. Instead, it flows light when it flows into the PN junction of the semiconductor. Therefore, the LED is called Cold light. LEDs are widely used in the lighting industry because of their high durability, long life, light weight, low power consumption, and no harmful substances such as mercury. They are usually applied to electronic advertising in LED array packaging. Cards, traffic signs and other fields.
  • the existing LED package array comprises a plurality of LEDs, and each LED structure has a chip mounted on a lead frame, and the chip and the partial lead frame are covered by a package colloid, so that the metal lead of the lead frame Exposed as an external contact outside the encapsulant; when assembled into an LED array, it is mounted on the metal connection of a plurality of LEDs to a printed circuit board, thereby electrically connecting the LEDs to each other.
  • a package array is limited by the package size of the LED structure itself, resulting in a volume that cannot be limited; and because the heat dissipation path of each LED can only pass through the metal pins and the insulating circuit board, the heat dissipation effect is limited.
  • Another LED package array is to directly package a plurality of LED chips on a printed circuit board for packaging.
  • a metal interconnection layer corresponding to each LED chip is disposed on the printed circuit board, and the LED chips are directly mounted on the printed circuit board and electrically connected with the metal interconnection layer;
  • An LED package array can be completed by encapsulating the components on the printed circuit board.
  • the disadvantage of the prior art is that the use of a printed circuit board as an LED is not suitable in terms of cost. It is well known that printed circuit boards must be formed by line patterning, pressing, drilling, and through-hole copper plating. It can be made by a multi-program, but in fact, the LED can be illuminated by connecting an electrical circuit and being driven by a voltage, and then the heat sink can ensure its luminous efficiency and service life. Therefore, the industry needs an LED package. The method, through this packaging method, can greatly reduce manufacturing cost and manufacturing time, and enhance LED luminous efficiency.
  • a main object of the present invention is to provide a method for fabricating a multilayer array type light emitting diode, and a method for fabricating a multilayer array type light emitting diode, comprising: forming a substrate by using a manufacturing method, wherein the substrate has at least one light output The area and the two lead frame receiving slots, the light exiting area is an intermediate block of the substrate, the two lead frame receiving slots are connected to the front and rear side blocks of the light exiting area, adjacent to the left and right of the light exiting area
  • the side block is provided with at least one first fixing hole and at least one through hole, and two outer grooves are formed at intervals on the outer bottom edge of the lower body of the two receiving grooves; two wires are positioned on the substrate In the accommodating space of the lead frame accommodating groove, wherein the two lead frames are not in contact with the 355, the portion of the lead frame closest to the side of the light exiting region is an inner connecting region, and the lead frame is farthest from the light exiting
  • the packaged portion is formed in the light-emitting region and the portion of the substrate provided with the through-hole.
  • the embedded portion of the package module includes the two grooves from the bottom to the top, and the lead frame receiving slot is not
  • the lead frame fills the space and the upper side of the lead frame but does not enclose the inner connecting area and the outer connecting area, and the package module is embedded in the peripheral portion of the light exiting area and fills the first fixing hole
  • the portion of the package module above the surface of the light exiting area is defined as an upper package module, and the inner wall surface of the upper package module is formed with a lens fitting groove;
  • the light emitting diode die is attached to the surface of the light exiting area of the substrate; Connecting wires to electrically connect the LED dies to the lead frame; allowing a protective layer to encapsulate the LED dies; forming a phosphor layer around the protective layer; and directly projecting a lens cover On the package module, the bottom of the lens cover fills the entire interior of the lens fitting
  • the first figure is a flow chart showing a method of fabricating a multilayer array type light emitting diode of the present invention.
  • the second drawing is a perspective view showing a substrate of a method of fabricating a multilayer array type light emitting diode of the present invention.
  • the third figure is a plan sectional view of the ⁇ - ⁇ ⁇ cutting line along the second figure.
  • the fourth figure is a schematic view showing a lead frame of the method for fabricating a multilayer array type light emitting diode of the present invention.
  • Fig. 5 is a schematic view showing a package module of the method of fabricating a multilayer array type light emitting diode of the present invention.
  • Fig. 6 is a view showing a light-emitting diode crystal grain of the method for producing a multilayer array type light-emitting diode of the present invention.
  • Figure 7 is a schematic view showing a connecting wire of the method of fabricating a multilayer array type light emitting diode of the present invention.
  • the eighth figure is a schematic view showing a protective layer of the method for fabricating a multilayer array type light emitting diode of the present invention.
  • the ninth drawing is a schematic view showing a fluorescent layer of the method of producing a multilayer array type light emitting diode of the present invention.
  • Figure 11 is a schematic view showing a lens cover of the method of fabricating a multilayer array type light emitting diode of the present invention.
  • Figure 11 is a schematic view showing a metal mirror cup of the method of fabricating a multilayer array type light emitting diode of the present invention.
  • Fig. 12 is a view showing an embodiment of a lens fitting groove of the package module of the present invention.
  • Fig. 13 is a schematic view showing a lens cover formed corresponding to the lens fitting groove of Fig. 12.
  • a substrate 1 is first prepared.
  • the substrate 1 is prepared by a stamping method, a chemical etching method or a high voltage wire cutting method or other suitable method.
  • a metal material the metal material may be a copper, aluminum, copper alloy, aluminum alloy or other suitable metal material
  • the upper surface of the substrate 1 may further comprise a reflective layer (not shown) that is plated, the reflective
  • the material of the layer may be a palladium, nickel, a silver, a platinum alloy or other suitable material, and the reflective layer has excellent thermal conductivity and excellent light reflectivity.
  • the substrate 1 after the preparation has at least one light exiting area 11 and two lead frame receiving grooves 13 , and the twill portion in the third figure is a solid portion after the cutting, wherein the light exiting area 11 is located at the The intermediate block, the two lead frame receiving slots 13 are located on the front and rear side blocks of the substrate 1, and at least two grooves corresponding to each lead frame receiving groove of the two lead frame receiving grooves,
  • the circumference of the light exiting area 11 is provided with a first "joint groove 19" having a V-shaped, concave, -U-shaped or other suitable shape woven satin.
  • the first engaging groove 19 The substrate 1 is disposed in a rear package.
  • the bottom surface of the substrate 1 is provided with two mutually spaced apart grooves 131.
  • the two grooves 131 are substantially elongated.
  • the substrate 1 further includes a substrate 1 At least one first fixing hole 15 and at least one through hole 17 on each side of the left side and the right side, the inner wall surface of the first fixing hole 15 is formed with a flange 151, or may be as shown in the embodiment,
  • the blocks on the left and right sides are each provided with a first fixing hole 15 and two perforations. 17.
  • the two perforations 17 may be disposed on either side of the first fixing hole 15 or at the end corner of the shame 1.
  • step S20 a schematic diagram of a lead frame of the method for fabricating a multilayer array type light emitting diode of the present invention. Then, the process proceeds to step S20, where the two lead frames 3 are respectively positioned in the accommodating spaces defined by the two lead frame accommodating grooves 13, wherein the two lead frames 3 do not contact the upper surface of the substrate 1, and the upper portion of the lead frame 3
  • the surface is at least not lower than the surface of the light exiting region 11, wherein each lead frame 3 includes an inner connecting region adjacent to the light exiting region 11, and one outer side relatively distant from the light exiting region 11 a connecting area, the outer connecting area must be at least beyond the circumference of the one, the outer connecting area is provided with a plurality of welding holes 33, and the inner connecting area of each lead frame 3 and the outer connecting area have at least a second
  • the fixing hole 31 and the at least one second engaging slit 31a may be provided with three second fixing holes 31 and two welding holes 33, wherein the cross section of the second engaging groove 31a may be It is
  • a package module diagram of a method of fabricating a multilayer array type light emitting diode of the present invention In the step S30, a package module 5 is formed on the substrate 1 in an injection molding manner, wherein the package module 5 surrounds the light exit region 11 , and the package module 5 is located between the light exit region 11 and the through hole 17 .
  • the module 5 is made of an epoxy resin (Epoxy) or other suitable material, wherein the package module 5 successively covers the groove 131, fills the lead frame receiving groove 13 and embeds the lead frame 3, and the package module 5, the upper surface of the inner connecting portion and the outer connecting portion are not embedded, that is, the inner space of the second fixing hole 31 and the second engaging slit 31a of the lead frame 3 are filled, and The package module 5 is embedded in the peripheral portion of the light exiting region 11 and fills the first fixing hole 15 and the inner space of the first bonding groove 19, so that the package module 5 and the substrate 1 and the lead frame 3 Tightly packed into one.
  • Epoxy epoxy resin
  • the upper part of the surface of the light-emitting area 11 is defined as an upper package module 51.
  • the upper package module 5 includes an inner side wall 51 on which a reflective surface 96 and a fluorescent wall 98 are disposed.
  • the upper package module 5 further A lens fitting groove 511 is disposed on a top portion of the reflective surface 96 of the upper package module 5.
  • the lens fitting groove 511 has a V-shaped, I- concave or a U-shaped or other suitable shape.
  • 98 is located under the inner side wall of the upper package module 5.
  • the fluorescent wall 98 is disposed around the light exit area 11 at an oblique angle between the range of 30 degrees and 60 degrees with respect to the upper surface of the light exit area 11. To limit the phosphorus compound in it.
  • the reflecting surface 96 is disposed at an oblique angle between 30 degrees and 60 degrees with respect to the upper surface of the light exiting region 11.
  • the reflective surface 96 is preferably a light reflecting surface on the inner sidewall of the upper package module 51.
  • the light reflecting surface is sputtered to deposit nickel or chromium onto the inner sidewall of the upper package module 51. Configuration.
  • a schematic diagram of a light-emitting diode die of the method of fabricating a multilayer array type light-emitting diode of the present invention referring to the seventh figure, a connecting wire of the method for fabricating a multilayer array type light-emitting diode of the present invention is shown.
  • a plurality of LED dies 6 are disposed on an upper surface of the light-emitting region 11 in an array arrangement and other arrangement manners.
  • the plurality of connection wires W are used to crystallize the LEDs.
  • the pellets 6 are electrically connected to the leadframe 3 such that the LED dies 6 form an electrical circuit with the leadframe 3.
  • a schematic diagram of a protective layer of a method for fabricating a multilayer array type light emitting diode of the present invention and a ninth drawing, a schematic diagram of a fluorescent layer of a method for fabricating a multilayer array type light emitting diode of the present invention.
  • step S60 the LEDs 6 and the connecting wires W form a protective layer 7, and the protective layer 7 is coated on the LED chips 6.
  • the protective layer 7 is wrapped in an adhesive manner.
  • the protective layer 7 is made of a non-conductive material, preferably the protective layer 7 can be made of a silicon type
  • the transparent epoxide is formed, and then proceeds to step S70, a fluorescent layer 8 is formed on the protective layer 7, wherein the fluorescent layer 8 is formed by providing a phosphorus compound in a region defined by a fluorescent wall 98.
  • the phosphorus compound is coated or poured on the upper surface of the protective layer 7, and is limited to the area defined by the fluorescent wall 98 and the periphery of the light exiting region 11.
  • a lens cover 9 is formed on the package module 5 by an injection molding method, wherein the lens The bottom of the cover 9 fills the entire interior of the lens fitting groove 511, so that the lens cover 5 can be firmly combined with the package module 5 while protecting important components inside the cover, wherein the lens cover 9 is made of a silicone or Made of a silicon type material.
  • FIG. 11 a schematic view of a mirrored mirror cup of the method of fabricating a multilayer array type light emitting diode of the present invention.
  • an eleventh figure shows a metal mirror cup 99 disposed on the reflective surface 96 and the reflective wall 98.
  • the inner sidewall is 30 degrees with respect to the upper surface of the light exiting region 11.
  • the metal mirror cup 99 is mounted on the reflective surface 96 of the upper package module 51 and the fluorescent wall 98.
  • the metal mirror cup 99 is opposite to the range of 60 degrees.
  • the upper surface of the light exiting area 11 is mounted at an oblique angle between a range of 30 degrees and 60 degrees.
  • the lens fitting groove 511 may be a U-shaped cross section and disposed at a top periphery of the reflective surface 96 of the upper package module 51, and the lens fitting groove The 511 is disposed at an oblique angle between the range of 0 degrees and 80 degrees with respect to the upper surface of the light exiting region 11, and then a lens cover 9 is formed on the package module 5 by an injection molding method, wherein the lens cover The bottom of the lens 9 corresponds to the lens fitting groove 511 to completely fill the inside of the lens fitting groove 511, so that the lens cover 5 can be firmly combined with the package module 5 to protect important components inside the cover.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Description

制作多层发光二极管阵列的方法 技术领域
本发明是有关一种制作多层式阵列型发光二极管的方法，尤其是一种可简化制 造过程， 进而降低制造成本及时间的一种发光二极管的封装方法。 背景技术
按， LED 的发光原理是利用半导体固有特性， 它不同于以往的白炽灯管的放 电、 发热发光原理， 而是将电流顺向流入半导体的 PN接面时便会发出光线， 所以 LED被称为冷光源 (cold light)。 由于 LED是具有高耐久性、 寿命长、 轻巧、 耗电量 低且不含水银等有害物质等的优点， 故可广泛应用于照明设备产业中， 且其通常以 LED阵列封装方式应用在电子广告牌、 交通号志等领域。
现有的 LED封装阵列是包括多个 LED,且每一个 LED结构是具有一芯片安装 于一导线架上， 并藉由一封装胶体包覆芯片及部份导线架， 使导线架的金属引脚露 出封胶体之外而作为对外接点； 在组装成 LED阵列时， 其是将多个 LED的金属引 脚安装至一印刷电路板的金属联机上， 以藉此使该等 LED相互电性连接。 但此种 LED封装阵列受限于该 LED结构本身的封装尺寸， 导致体积无法限缩； 且因每一 LED的散热途径仅能透过金属引脚和绝缘电路板而已， 散热效果有限。
现有另有一种 LED封装阵列是将多个 LED芯片直接配置于印刷电路板上进行 封装。 详言之， 在印刷电路板上设有与各个 LED芯片相互对应的金属联机层， 将 该等 LED芯片直接安装于印刷电路板上， 并与该金属联机层形成电性连接； 最后 再利用一封装胶体包覆印刷电路板上的各组件， 即可完成一 LED封装阵列。
然而现有技术的缺点为把印刷电路板当作 LED的_¾^ 使用就成本而言并不适 合， 众所周知， 印刷电路板的制作须藉线路图案成型、 压合、 钻孔及通孔镀铜等多 道程序才能制成， 但是实际上 LED只要经由连接一电性回路并受一电压驱动即可 发光，再搭配散热装置即能确保其发光效能及使用寿命， 因此业界极需要一种 LED 封装方法， 透过此封装方法， 以大幅降低制造成本及制造时间， 并增强 LED发光 效能。 发明内容 本发明的主要目的在于提供一种制作多层式阵列型发光二极管的方法，一种制 作多层式阵列型发光二极管的方法， 是包含： 利用一制作方法形成一基板， 其中该 至少具有一出光区及两导线架容置槽， 该出光区是为该基板的中间区块， 该两 导线架容置槽是相连于该出光区的前后侧区块， 相邻于该出光区的左、 右侧边区块 设置有至少一第一固定孔及至少一穿孔， 又该两容置槽下方板体的外侧底缘处形成 有呈间隔设置的两凹槽； 将两导线架定位于该基板的两导线架容置槽的容置空间 中， 其中该两导线架不接触于该 ί^， 该导线架最靠近该出光区一侧的部份为一内 连接区， 该导线架最远离于该出光区一侧的部份为一外连接区， 该外连接区至少须 超出该基板的周缘，该内连接区及该外连接区之间设有至少一第二固定孔及至少一 第二卡合缝； 以射出成型方式在 的该出光区以及该基板设有该穿孔的以外部份 形成有一封装模块， 该封装模块的包埋区域由下往上包含有该两凹槽、 该导线架容 置槽中未被该导线架所填满空间以及该导线架的上方但不包埋该内连接区上方及 该外连接区周围， 又该封装模块包埋于该出光区的周边部分并填满该第一固定孔， 该封装模块在出光区表面以上的部分定义成一上封装模块，该上封装模块的内壁面 形成有一透镜嵌合槽； 将发光二极管晶粒贴附在该基板的该出光区表面上； 利用多 个连接导线使该等发光二极管晶粒与该导线架形成电性连接；令一保护层将该等发 光二极管晶粒包援住； 该保护层周围形成有一荧光层； 以及直接射出成型一透镜罩 于该封装模块上， 该透镜罩的底部会将该透镜嵌合槽内部整个填满。 附图说明
第一图为显示本发明的制作多层式阵列型发光二极管的方法的流程图。
第二图为显示本发明的制作多层式阵列型发光二极管的方法的基板立体示意 图。
第三图为沿第二图的 ΠΙ-Ϊ Ι Ι割线的平面剖视图。
第四图为显示本发明的制作多层式阵列型发光二极管的方法的导线架示意图。 第五图为显示本发明的制作多层式阵列型发光二极管的方法的封装模块示意 图。
第六图为显示本发明的制作多层式阵列型发光二极管的方法的发光二极管晶 粒示意图。
第七图为显示本发明的制作多层式阵列型发光二极管的方法的连接导线示意 图。 第八图为显示本发明的制作多层式阵列型发光二极管的方法的保护层示意图。 第九图为显示本发明的制作多层式阵列型发光二极管的方法的荧光层示意图。 第十图为显示本发明的制作多层式阵列型发光二极管的方法的透镜罩示意图。 第十一图为显示本发明的制作多层式阵列型发光二极管的方法的金属反光镜 杯的示意图。
第十二图为显示本发明的封装模块的透镜嵌合槽的一实施例示意图。
第十三图为显示对应于第十二图的透镜嵌合槽而形成的透镜罩的示意图。
【主要组件符号说明】
S10、 S20、 S30、 S40、 S50、 S60、 S70、 S80步骤
1紘
11出光区
13导线架容置槽
15第一固定孔
17穿孔
19第一卡合槽
131凹槽
151凸缘
3导线架
31第二固定孔
31a第二卡合槽
33焊孔
5封装模块
51上封装模块
511透镜嵌合槽
6发光二极管晶粒
7保护层
8荧光层
9透镜罩
96 反光面
98 荧光墙 99 金属反光镜杯
w连接导线。 具体实施方式
以下配合图标及组件符号对本发明的实施方式做更详细的说明，俾使熟习该项 技艺者在^^本说明书后能据以实施。
.参阅第一图至第三图。 如第一图的步骤 S10所示， 首先制备一基板 1 , 该基板 1是藉一冲压成型法、 一化学蚀刻法或一高电压线割法或其它适当方法制备而成， 该基板 1是为一金属材质， 该金属材质可以是一铜、 铝、 铜合金、 铝合金或其它适 当金属材质， 该基板 1 的上表面可进一步包含被镀上的一反光层（图面未显示）， 该反光层的材质可以是一钯（Pal ladium ), —镍、 一银、 一白金合金或其它适当材 质， 该反光层具有优良的热传导性与优良的光线反射性。
其中制备完成后的该基板 1至少具有一出光区 11及两导线架容置槽 13， 第三 图中斜纹部分为_¾ ^剖切后的实体部份， 其中该出光区 11是位于该 1的中间 区块， 与该两导线架容置槽 13是位于该基板 1的前后侧区块， 以及相对应于该两 导线架容置槽的每一导线架容置槽的至少两凹槽， 该出光区 11 的周缘环设有一第 一" ^合槽 19, 该第一^ ^合槽 19具有一 V型、 凹型、 -U型或其它适当形状织缎面， 该第一卡合槽 19是预留于后面封装时使用， 该基板 1底面的边缘配置有两相互分 隔的两凹槽 131 , 该两凹槽 131概呈长条型， 其中该基板 1进一步包含有在该基板 1的一左侧与一右侧的每一侧的至少一第一固定孔 15及至少一穿孔 17， 该第一固 定孔 15的内壁面形成有一凸缘 151， 或者亦可如本实施方式所示，在左、右侧边的 区块各设置有一个第一固定孔 15及两个穿孔 17， 两穿孔 17可设置于第一固定孔 15的两侧或该羞 1的端角处。
参阅第四图， 本发明的制作多层式阵列型发光二极管的方法的导线架示意图。 接着进入步骤 S20,分别定位两导线架 3于该两导线架容置槽 13所定义的容置空间 中， 其中该两导线架 3不接触于该基板 1的上表面， 该导线架 3的上表面至少不低 于与该出光区 11的表面，其中每一导线架 3包含有位在相邻于该出光区 11的一内 连接区， 以及一位在相对远离于该出光区 11 的一外连接区， 该外连接区至少须超 出该 1的周缘，该外连接区并设有多个焊孔 33,每一导线架 3的该内连接区及 该外连接区之间具有至少一第二固定孔 31及至少一第二卡合缝 31a，或可依照图面 所式， 设置有三个第二固定孔 31及两焊孔 33, 其中该第二卡合槽 31a的断面可以 是 V型、 一凹型、 一 U型或其它适当形状。
参阅第五图， 本发明的制作多层式阵列型发光二极管的方法的封装模块示意 图。 接着进入步骤 S30, 以射出成型方式在基板 1上形成有一封装模块 5， 其中该 封装模块 5 包围该出光区 11 , 以及该封装模块 5是位于该出光区 11及该穿孔 17 之间， 该封装模块 5 由一环氧树脂 ( Epoxy )或其它适当材质制成， 其中该封装模 块 5相继地覆盖该凹槽 131、 填满该导线架容置槽 13并包埋该导线架 3, 该封装模 块 5不包埋该内连接区的上表面与该外连接区的周围，也就是该导线架 3的该第二 固定孔 31及该第二卡合缝 31a的内部空间会被填满， 又该封装模块 5包埋于该出 光区 11的周边部分并填满该第一固定孔 15及该第一- ^合槽 19的内部空间， 如此 该封装模块 5会与该基板 1及该导线架 3紧密地封装成一体。
该封装模块 5在出光区 11表面以上的部分在此定义成一上封装模块 51， 该上 封装模块 5包含上配置有一反光面 96与一荧光墙 98的一内侧壁 51 ,该上封装模块 5进一步在该上封装模块 5的该反光面 96上的一顶部配置有一透镜嵌合槽 511，该 透镜嵌合槽 511具有一 V型、 I 凹型或一 U型或其它适当形状的断面，该荧光墙 98 是位于该上封装模块 5的内侧壁之下，该荧光墙 98相对于该出光区 11的上表面是 以一 30度至 60度范围之间的一倾斜角度而配置于该出光区 11周围以限制一磷化 合物于其中。 较佳地， 该反光面 96相对于该出光区 11的上表面是以 30度至 60度 范围之间的一倾斜角度而配置。该反光面 96较佳地为该上封装模块 51的该内侧壁 上的一光线反射面， 该光线反射面是藉溅镀以沉积镍或铬到该上封装模块 51的该 内侧壁之上而配置。
参阅第六图，本发明的制作多层式阵列型发光二极管的方法'的发光二极管晶粒 示意图， 参阅第七图， 本发明的制作多层式阵列型发光二极管的方法的连接导线示 意图。 接着进入步骤 S40, 将多个发光二极管晶粒 6以阵列型式其它排列方式配置 于该 的该出光区 11的一上表面之上，接着 步骤 S50,利用多个连接导线 W将该等发光二极管晶粒 6与该导线架 3形成电性连接， 藉使该等发光二极管晶粒 6与该导线架 3形成一电路。
参阅第八图， 本发明的制作多层式阵列型发光二极管的方法的保护层示意图， 参阅第九图， 本发明的制作多层式阵列型发光二极管的方法的荧光层示意图。接着 进入步骤 S60， 该等发光二极管晶粒 6与该等连接导线 W之上形成一保护层 7， 保 护层 7包覆于该等发光二极管晶粒 6 , 该保护层 7是以一黏附方式包覆该等发光二 极管晶粒 6， 该保护层 7是由一非导电材料制成， 较佳地该保护层 7可以由一硅型 透光环氧化物制成， 接着进入步骤 S70, 该保护层 7之上形成有一荧光层 8 , 其中 该荧光层 8藉由一荧光墙 98所界定的区域之中提供一磷化合物而形成， 该磷化合 物是涂布或灌注于该保护层 7的上表面， 并且是限制于由该荧光墙 98与该出光区 11周围定义的区域内，。
参阅第十图， 本发明的制作多层式阵列型发光二极管的方法的透镜罩示意图， 最后进入步骤 S80, 藉由射出成型方法于该封装模块 5-的上形成一透镜罩 9， 其中 该透镜罩 9的底部会将该透镜嵌合槽 511内部整个填满，如此该透镜罩 5可稳固地 与该封装模块 5结合， 同时保护包覆内部的重要组件， 其中该透镜罩 9由一硅胶或 一硅型材料制成。
参阅第十一图，本发明的制作多层式阵列型发光二极管的方法的佥属反光镜杯 的示意图。 依据本发明的另一实施例， 第十一图显示配置于该反光面 96与该反光 墙 98之上的一金属反光镜杯 99， 该内侧壁相对于该出光区 11的上表面以 30度至 60度范围之间的" ^倾斜角度而配置，该金属反光镜杯 99是装设于该上封装模块 51 的该反光面 96与该荧光墙 98之的上，该金属反光镜杯 99相对于该出光区 11的上 表面是以一 30度至 60度范围之间的一倾斜角度而安装。
参阅第十二图与第十三图，其中透镜嵌合槽 511可以是一 U型的断面并配置千 该上封装模块 51的该反光面 96上的一顶部周边处，并且该透镜嵌合槽 511相对于 该出光区 11的上表面是以 0度至 80度范围之间的一倾斜角度而配置，接着藉由射 出成型方法于该封装模块 5之上形成一透镜罩 9， 其中该透镜罩 9的底部对应于透 镜嵌合槽 511处会将该透镜嵌合槽 511内部整个填满，如此该透镜罩 5可稳固地与 该封装模块 5结合， 以保护包覆内部的重要组件。
以上所述者仅为用以解释本发明的较佳实例，并非企图据以对本发明做任何形 式上的限制， 是以， 凡有在相同的发明精神下所作有关本发明的任何修饰或变更， 皆仍应包括在本发明意图保护的范畴。

Claims

权利要求
1.一种制作多层式阵列型发光二极管的方法， 包含有：
制备一包含至少有一出光区及两导线架容置槽的基板，其中该出光区是位于该 的中间区块， 以及该两导线架容置槽是位于该羞 的前后侧， 其中该羞 进一 步包含有在该基板的一左侧与一右侧的每一个的至少一第一固定孔及至少一穿孔， 以及相对应于该两导线架容置槽的每-导线架容置槽的至少两凹槽；
分别定位两导线架于该两导线架容置槽所定义的容置空间中，其中每一导线架 容置槽包含有位在相邻于该出光区的一内连接区以及一位在相对远离于该出光区 的一外连接区，其中该外连接区超出该基板的周缘以及每一导线架的该内连接区及 该外连接区之间具有至少一第二固定孔及至少一第二卡合缝；
以射出成型方式于基板上形成有一封装模块，其中该封装模块包围该出光区并 填满该第一固定孔， 以及该封装模块是位于该出光区及该穿孔之间， 其中该封装模 块相继地覆盖该凹槽、 填满该导线架容置槽并包埋该导线架, 其中该封装模块不包 埋该内连接区的上表面与该外连接区的周围，其中该封装模块在出光区表面以上的 部分定义成一上封装模块， 并且该上封装模块包含一内侧壁， 该内侧壁的上是配置 一反光面、 一配置在该上封装模块的一顶部且位于该反光面之上的一透镜嵌合槽， 以及一位于在该上封装模块的内侧壁的下的荧光墙；
将多个发光二极管晶粒以阵列形式配置于该基板的一上表面之上；
利用多个连接导线将该等发光二极管晶粒电性连接到该两导线架以形成一电 路；
该等发光二极管晶粒与该等连接导线的上形成一保护层；
该保护层的上形成一荧光层，其中该荧光层藉由一荧光墙所界定的区域之中提 供一磷化合物而形成； 以及
藉由射出成型方法而于该封装模块之上形成一透镜罩，其中该透镜罩的底部会 将该透镜嵌合槽内部整个填满。
2. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该反 光面为该上封装模块的该内侧壁上的一光线反射面， 以及所述的方法进一步包含有 在该反光面及该荧光墙上配置有镍或铬的一薄层的一步骤。
3. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该反 光面为一安置于该内侧壁与该荧光墙上的金属反光镜杯。
4. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该出 光区的周缘环设有一第一卡合槽。
5. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该两 导线架与该基板的上表面保持非接触。
6. 如权利要求 4所述的一种制作多层式阵列型发光二极管的方法， 其中该第 一" ^合槽具有—— U型或一 V型的断面。
7. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该基 板是藉一冲压成型法、 一化学蚀刻法或一高电压线割法制备而成。
8. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该基 板为一金属材质， 该金属材质至少包含有一铜（Cu)、 铝（Al)、 铜合金、 铝合金的至 少其中的一。
9. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 该基板的 上表面包含一反光层， 该反光层具有一优良的热传导性及一优良的光反射性。
10. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该外 连接区设有多个焊孔。
11. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该保 护层是由一非导电材料制成并形成于该等发光二极管晶粒与该等连接导线之上。
12. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该保 护层是由一硅型透光环氧化物制成。
13. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中一磷 化合物是灌注于该保护层的一上表面，并且是限制于由该荧光墙与该出光区周围定 义的区域内。
14. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该封 装模块由一环氧树脂制成。
15. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该荧 光墙相对于该出光区的上表面是以一 30度至 60度范围之间的一倾斜角度而配置。
16. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该反 光面相对于该出光区的上表面具有 30度至 60度范围之间的一倾斜角度。
17. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该透 镜嵌合槽具有一 U型或一 V型的断面。
18. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该透 镜罩由一硅胶或一硅型材料制成。
19. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该金 属反光镜杯相对于该出光区的上表面是以一 30度至 60度范围之间的一倾斜角度而 安装。
20. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该两 凹槽是配置于该基板底面的边缘， 并该两凹槽为相互分隔。
21. 如权利要求 1所述的一种制作多层式阵列型发光二极管的方法， 其中该透 镜嵌合槽是为一 U型的断面并配置于该上封装模块的该反光面上的一顶部周边处， 其中该透镜嵌合槽相对于该出光区的上表面是以 0度至 80度范围之间的一倾斜角 度而配置， 再藉由射出成型方法于该封装模块之上形成一透镜罩， 其中该透镜罩的 底部对应于透镜嵌合槽处会将该透镜嵌合槽内部整个填满， 进而与该封装模块结 合。
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JP2008047908A (ja) * 2006-08-14 2008-02-28 Chien-Chung Chen 発光モジュールおよびその製造プロセス

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