WO2011123984A1 - 多层式阵列型发光二极管装置 - Google Patents

多层式阵列型发光二极管装置 Download PDF

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Publication number
WO2011123984A1
WO2011123984A1 PCT/CN2010/000461 CN2010000461W WO2011123984A1 WO 2011123984 A1 WO2011123984 A1 WO 2011123984A1 CN 2010000461 W CN2010000461 W CN 2010000461W WO 2011123984 A1 WO2011123984 A1 WO 2011123984A1
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WO
WIPO (PCT)
Prior art keywords
emitting diode
light emitting
array type
lead frame
type light
Prior art date
Application number
PCT/CN2010/000461
Other languages
English (en)
French (fr)
Inventor
胡仲孚
吴永富
Original Assignee
盈胜科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 盈胜科技股份有限公司 filed Critical 盈胜科技股份有限公司
Priority to PCT/CN2010/000461 priority Critical patent/WO2011123984A1/zh
Publication of WO2011123984A1 publication Critical patent/WO2011123984A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/642—Heat extraction or cooling elements characterized by the shape

Definitions

  • Multilayer array type light emitting diode device Multilayer array type light emitting diode device
  • the present invention relates to a package structure of a multilayer array type light emitting diode, and more particularly to a package structure which is compact in structure and easy to manufacture, and which can greatly reduce manufacturing cost and manufacturing time. Background technique
  • LED illumination According to the principle of LED illumination, it is different from the inherent characteristics of semiconductors. It is different from the discharge and heat-emitting principle of incandescent lamps. Instead, it flows light when it flows into the PN junction of the semiconductor. Therefore, the LED is called Cold light source (cold l ight). LEDs are widely used in the lighting industry because of their high durability, long life, light weight, low power consumption, and no harmful substances such as mercury. They are usually applied to electronic advertising in LED array packaging. Cards, traffic signs and other fields.
  • the existing LED package array comprises a plurality of LEDs, and each LED structure has a chip mounted on a lead frame, and the chip and the partial lead frame are covered by a package colloid, so that the metal lead of the lead frame The outer portion of the encapsulant is exposed as an external contact; when assembled into an LED array, the metal pins of the plurality of LEDs are mounted on a metal connection of a printed circuit board, thereby electrically connecting the LEDs to each other.
  • such an LED package array is limited by the package size of the LED structure itself, resulting in a volume that cannot be limited; and because the heat dissipation path of each LED can only pass through the metal pins, the heat dissipation effect is limited.
  • Another LED package array is to directly package a plurality of LED chips on a printed circuit board for packaging.
  • a metal interconnection layer corresponding to each LED chip is disposed on the printed circuit board, and the LED chips are directly mounted on the printed circuit board and electrically connected with the metal interconnection layer;
  • An LED package array can be completed by encapsulating the components on the printed circuit board.
  • the circuit pattern on the board has been shaped. If the matching board is customized according to each application place, the cost is increased, time-consuming and labor-intensive, and the heat dissipation effect of the printed circuit board is limited. Therefore, a heat sink must be added to help dissipate heat. This increases the cost and makes the structure even larger. Therefore, the industry needs a package structure of a multilayer array type light emitting diode which is light in weight and short in structure, but which is easy to manufacture and has elasticity of use. Summary of the invention
  • the main purpose of this ⁇ month is to provide a multi-layer array type light emitting diode, the multi-layer array type
  • the photodiode has a multi-layer structure, and its structure is simple and easy to manufacture, so that the manufacturing cost and the manufacturing time can be greatly reduced.
  • the material of the substrate is made of metal, so the substrate has excellent thermal conductivity of the metal, and can effectively dissipate the heat energy of the LED. .
  • Another object of the present invention is to provide a multi-layer array type light emitting diode, wherein the LED chips are arranged on the substrate in an array manner, so that the density of the LED chips can be adjusted according to the application, and the light is emitted.
  • the diode die is electrically connected to the lead frame by the wire, so that even if several LED chips are damaged, the brightness and efficiency of the overall illumination are not affected.
  • the front and rear side blocks are formed with two spaced apart grooves along the outer bottom edge of the lower body of the two lead frame receiving slots, and the left and right side blocks adjacent to the light exiting area are provided with at least one a first fixing hole and at least one through hole, wherein an inner wall surface of the first fixing hole is formed with a flange; a package module is formed on the periphery by an injection molding, and the package module is higher than a surface of the light exiting area
  • the upper portion of the bottom surface of the upper package module is formed with two convex plates, and the position and shape of the two convex plates are corresponding to the lead frame receiving groove, and the length of the two convex plates is at least The length of the lead frame is greater than the longest length of the lead frame receiving groove, and the first convex portion is extended inwardly from the bottom of the lead frame.
  • the upper package module has a top surface, a first inner wall surface, a fixed surface and a reflective surface, wherein the top surface is a planar portion on an upper peripheral edge of the upper package module, the top surface includes a An inner side of the first inner wall surface of the upper package module, the first inner wall surface is substantially perpendicular to the top surface, and the first inner wall surface includes a bottom connected to the fixing surface of the upper package module a side, wherein a bottom edge of the first inner wall surface is substantially perpendicular to the fixing surface, and the fixing surface is parallel to the top surface; a lead frame, the lead frame is sealed in the convex plate, the lead frame The portion closest to the side of the light exiting
  • Fig. 2 is an exploded perspective view showing a part of the components of the multilayer array type light emitting diode of the present invention.
  • the third figure is a schematic cross-sectional view showing the _ ⁇ , the package module and the cover of the present invention.
  • the fourth figure is a schematic cross-sectional view of the first figure.
  • Fig. 5 is a schematic view showing the surface of the multilayer array type light emitting diode of the present invention.
  • Fig. 6 is a view showing another embodiment of the lead frame of the multilayer array type light emitting diode of the present invention.
  • Fig. 7 is a schematic view showing a metal mirror cup of the multilayer array type light emitting diode package structure of the present invention.
  • the eighth figure is a schematic view showing an embodiment of a lens fitting groove of the package module of the present invention.
  • the ninth drawing is a schematic view showing a lens cover formed corresponding to the lens fitting groove of the twelfth figure.
  • FIG. 1 a schematic diagram of the appearance of the multi-layer array type light-emitting diode of the present invention, referring to the second figure, the multi-layer array type light-emitting diode of the present invention!
  • FIG. 3 A schematic exploded view of a portion of the components of the pole tube, see Fig. 3, a schematic plan view of the multilayer array type of light-emitting diode of the present invention.
  • the present invention relates to a multi-layer array type light emitting diode comprising a substrate 1, a package module 3, two lead frames 5 and a cover 10.
  • the light exiting area 11 is the intermediate block of the 1 1 , and the first light-emitting area 11 is provided with a first engaging groove.
  • the two lead frame receiving slots 13 are located on the front and rear side blocks of the light exiting area 11, and two spaced apart grooves 131 are formed at the bottom side of the outer edge of the lower body of the two lead frame receiving slots 13
  • the two recesses 131 have a rectangular shape or other suitable shape.
  • FIG. 4 is a schematic cross-sectional view of the first figure.
  • the package module 3 is formed around the light exiting area of the substrate 1 in an injection molding manner, so that the package module 3 is tightly coupled to the package 1.
  • the material of the package module 5 is an epoxy resin (Epoxy). Or a suitable material shield, the portion of the package module 3 higher than the upper surface of the light exiting area 11 is defined as an upper package module 31.
  • the upper package module 31 is only defined for convenience in describing the embodiment, and is not Independent of the components of the package module 3.
  • the front and rear sides of the bottom surface of the upper package module 31 are formed with two convex plates 311.
  • the positions and shapes of the two convex plates 311 are corresponding to the lead frame receiving slots 13 .
  • the length of the two protruding plates 311 is at least greater than the length.
  • the longest length of the lead frame accommodating groove 13 is beyond the portion of the lead frame accommodating groove 13 and extends downwardly with a first convex portion 3111, and the bottom end of the first convex portion 3111 is inward.
  • Two protrusions 3111a are formed in parallel, and the two protrusions 3111a are configured to be correspondingly assembled with the two grooves 131.
  • the bottom surface of the upper package module 31 is formed with a second portion corresponding to the first fixing hole 15
  • the convex portion 33b is formed with a concave edge 331b at a position corresponding to the flange 151.
  • the lead frame 311 is embedded in the lead frame 311.
  • the portion of each lead frame 5 closest to the side of the light exiting area 11 is an internal electrical connection area.
  • Engaging and being embedded in the intermediate portion of the two convex plates 311, the portion of the lead frame 5 farthest from the light exiting region 11 and not embedded in the two convex plates 311 is an external electrical connection region, the external electrical property
  • the connection area must be at least beyond the circumference.
  • the external electrical connection area is provided with a plurality of soldering holes 53 for electrically connecting to the external components, and at least one second is disposed between the inner electrical connection area and the external electrical connection area.
  • the fixing hole 51 and the at least one second engaging groove 51a are provided, or the second engaging groove 51a is disposed on each side of the second fixing hole 51, and three second fixing holes 51 and two are disposed.
  • the second fixing hole 51 and the second engaging groove 51a are embedded in the package module 3, and the internal electrical connection region of the lead frame 5 and the external electrical property of the lead frame 5 are formed.
  • the connection area is reserved for being unsealed in the package module 3 for wire bonding and electrical connection.
  • Upper surface of the bobbin is not less than 5 or at least parallel to the surface of the zone 11. It is to be noted that the number and arrangement of the second fixing holes 51 and the two welding holes 53 are determined according to actual needs, and are merely illustrative examples and are not intended to limit the scope of the present invention.
  • the sixth figure shows another embodiment of the lead frame.
  • the package module 3 will be the first of the substrate 1 during injection molding.
  • the engaging groove 19, the groove 131, the first fixing hole 15 and the lead frame receiving groove 13 are filled, so that the protrusion 3111a of the package module 3 and the two grooves 131 and the flange 151 and the concave edge 331 are mutually
  • the encapsulation material 3 of the package module 3 also fills the second engagement groove 51a of the lead frame 5 and the hollow portion of the second fixing hole 51, so that the package module 3 and the substrate 1 and the The lead frames 5 are tightly integrated into one body.
  • the cross-sectional shape of the first engaging groove 19 and the second engaging groove 51a may be V-shaped or other suitable shape.
  • the upper package module 31 has a top surface 33, an inner wall surface 331, a fixed surface 3311 and a reflective surface 96.
  • the top surface 33 is a planar portion on the upper circumference of the upper package module 31.
  • the top surface 33 An inner side of the inner wall surface 331 of the upper package module 31 is defined.
  • the inner wall surface 331 is substantially perpendicular to the top surface 33, and the inner wall surface 331 includes a fixing surface connected to the upper package module 31.
  • the bottom edge of the inner wall surface 331 is substantially perpendicular to the fixing surface 3311, and the fixing surface 3311 is parallel to the top surface 33.
  • the fixing surface 3311 is provided with a cover fitting groove 3311a.
  • the cover fitting groove 3311a has a V-shaped, concave, U-shaped or other suitable shape, wherein the reflective surface 96 is disposed at an angle of a range of 30 degrees to 60 degrees around the light exiting area 11, the reflective surface. 96 has an innermost edge, and the inner side of the reflective surface 96 is joined to the fluorescent wall 98.
  • the fluorescent wall 95 is inclined at an angle of between 30 degrees and 60 degrees with respect to the upper surface of the light exiting region 11. Formed from angles, in some cases In order to have a better reflective effect, the reflective surface 96 and the fluorescent wall 98 are formed by sputtering to form a nickel coating or a chromium coating or a metal reflective coating coated with a nickel coating or a chromium coating.
  • a mirror cup is disposed on the reflective surface and the fluorescent wall to improve the reflective performance of the multilayer array type light emitting diode.
  • FIG. 7 a schematic plan view of the multilayer array type light emitting diode of the present invention is shown in conjunction with the third figure.
  • An illumination unit 7 is disposed on the upper surface of the light exiting area 11.
  • the light emitting unit 7 is disposed on the surface of the light exiting area 11.
  • the light emitting unit 7 includes a plurality of light emitting diode chips 71.
  • the light emitting diode chips 71 are mutually Wire-bonding and bonding the wires W to the two lead frames 5 to form a circuit, wherein the LED chips 71 are arranged on the light-emitting region 11 in an array arrangement or other suitable arrangement, the LED chips
  • the protective layer 8 is coated on the LED die 71 and the bonded wire W.
  • the protective layer 8 is made of a silica gel or other suitable material.
  • the protective layer 8 is provided on the protective layer 8. Having at least one phosphor layer 9 formed by providing a phosphorus compound in a region defined by a fluorescent wall 98, wherein the phosphor compound is mixed with silicon, and the phosphor layer 9 is coated with the fluorescent layer In the portion of 98, the material shield of the phosphor layer 9 is a phosphorus compound or other suitable material, and the fluorescent wall 98 is inclined at a range of 30 degrees to 60 degrees with respect to the upper surface of the light exit region 11. Formed at an oblique angle, the fluorescent wall 98 is disposed at the periphery 11 of the light exiting region.
  • the cover 10 is formed on the light-emitting unit 7 by a light-transmissive silica gel in an injection molding manner.
  • the cover module and the light-emitting unit 7 are covered to protect the light-emitting unit and the light-emitting unit.
  • the bottom periphery of the cover 10 is extended with an extension seat 101.
  • the bottom surface of the extension base 101 is provided with a fitting portion. 1011.
  • the fitting position of the fitting portion 1011 corresponds to the cover fitting groove 3311a, and the length between the extending seats 101 is at least not less than the length between the first inner wall surfaces 331 of the upper package module 31.
  • the material of the cover 10 is made of a silica gel material and has light transmissibility.
  • the fitting portion 1011 of the cover body 10 is aligned with the cover body fitting groove 3311a, and the end faces of the extension seat 101 are simultaneously closely fitted to the first inner wall surface 331 so that the cover body 10 is It is firmly fixed to the package module 3.
  • the soldering holes 53 of the two lead frames 5 can be respectively connected to the power wires (not shown).
  • the LED chips 71 are driven by the power source, and the LED chips 71 are arrayed.
  • the illuminating manner of the arrangement has a high-luminance illuminating property, and when the light source light passes through the fluorescent layer 9, an effect of mixing light is produced.
  • the cover fitting groove 3311a may be a U-shaped cross section and disposed at a top periphery of the reflective surface 96 of the upper package module 31, and the cover fitting groove
  • the upper surface of the light-emitting area 11 is disposed at an oblique angle between 0 degrees and 80 degrees, and the bottom periphery of the cover 10 is extended with an extension seat 101, and the bottom surface of the extension base 101 is provided.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Led Device Packages (AREA)

Description

多层式阵列型发光二极管装置
技术领域
本发明是有关一种多层式阵列型发光二极管的封装结构，尤其是一种结构精简 且制造容易， 可大幅减少制造成本及制造时间的封装结构。 背景技术
按， LED的发光原理是利用半导体固有特性，它不同于以往的白炽灯管的放电、 发热发光原理， 而是将电流顺向流入半导体的 PN接面时便会发出光线， 所以 LED 被称为冷光源（cold l ight)。 由于 LED是具有高耐久性、 寿命长、 轻巧、 耗电量低 且不含水银等有害物质等的优点，故可广泛应用于照明设备产业中，且其通常以 LED 阵列封装方式应用在电子广告牌、 交通号志等领域。
现有的 LED封装阵列是包括多个 LED, 且每一个 LED结构是具有一芯片安装于 一导线架上， 并藉由一封装胶体包覆芯片及部份导线架， 使导线架的金属引脚露出 封胶体的外而作为对外接点； 在组装成 LED阵列时， 其是将多个 LED的金属引脚安 装至一印刷电路板的金属联机上， 以藉此使该等 LED相互电性连接。 但此种 LED封 装阵列受限于该 LED结构本身的封装尺寸， 导致体积无法限缩； 且因每一 LED的散 热途径仅能透过金属引脚而已， 散热效果有限。
现有另有一种 LED封装阵列是将多个 LED芯片直接配置于印刷电路板上进行封 装。 详言之， 在印刷电路板上设有与各个 LED芯片相互对应的金属联机层， 将该等 LED芯片直接安装于印刷电路板上， 并与该金属联机层形成电性连接； 最后再利用 一封装胶体包覆印刷电路板上的各组件， 即可完成一 LED封装阵列。 板上的线路图案已被定形， 若依据每个应用场所订制相符合的电路板， 亦使得成本 提高且耗时耗力，并且印刷电路板散热效果有限，因此必须外加散热装置帮助散热， 连带使得成本增加， 也使得结构更为庞大， 因此业界需要一种结构轻薄短小， 但制 造容易且兼具有使用上弹性的一种多层式阵列型发光二极管的封装结构。 发明内容
本^ ^月的主要目的在于提供一种多层式阵列型发光二极管，该多层式阵列型发 光二极管为多层式结构， 其结构精简且制造容易， 因此可大幅减少制造成本及制造 时间， 其中基板的材质为金属材质， 因此基板具有金属优异的热传导性， 可有效排 散发光二极管的热能。
本发明的另一目的在于提供一种多层式阵列型发光二极管，该发光二极管晶粒 以阵列方式配置于基板上， 如此可依据应用场合来调整来发光二极管晶粒的密集 度， 又该发光二极管晶粒藉由导线与导线架形成电性连接， 如此即使数颗发光二极 管晶粒损坏， 亦不影响对整体发光亮度及效率。
本发明具体的技术手段包含有一基板，该基板至少具有一出光区及两导线架容 置槽， 该出光区是为该 1 的中间区块， 该两导线架容置槽是相连于该出光区的前 后侧区块， 沿该两导线架容置槽下方板体的外侧底缘处形成有两呈间隔设置的凹 槽， 而相邻于该出光区的左、 右侧边区块设置有至少一第一固定孔及至少一穿孔， 该第一固定孔的内壁面形成有一凸缘； 一封装模块， 其是以一射出成型方式形成于 该 周围， 该封装模块高于该出光区的表面的部份定义成一上封装模块， 该上封 装模块底面的前后两侧向下形成有两凸板，该两凸板的配置位置及形状相对应于该 导线架容置槽， 该两凸板的长度至少大于该导线架容置槽的最长长度， 该两凸板超 '出于该导线架容置槽的部份并向卞延设有一第一凸部，该第一凸部底端向内平行延 设有两突块， 该两突块的配置位置及形状相对应于该两凹槽， 该上封装模块底面在 相对应于该第一固定孔处皆形成有一第二凸部，该第二凸部对应于该凸缘的位置则 形成有一凹缘，又该上封装模块具有一顶面、一第一内壁面、一固定面及一反光面， 其中该顶面为一位于该上封装模块上侧周缘的平面部分，该顶面包含一连接于该上 封装模块的该第一内壁面的内边， 该第一内壁面基本上是垂设该顶面， 且该第一内 壁面包含一连接于该上封装模块的该固定面的底边，其中该第一内壁面的底边基本 上垂直于该固定面， 且该固定面是平行于该顶面； 一导线架， 该导线架是被封设于 该凸板内， 该导线架最靠近该出光区一侧的部份为一内电性连接区， 该导线架最远 离于该出光区一侧的部份为一外电性连接区，该内电性连接区及该外电性连接区之 间设有至少一第二卡合槽及至少一第二固定孔，该第二卡合槽与该第二固定孔皆包 埋于该封装模块内 ,该内电性连接区的上方及该外电性连接区整体外露于该封装模 块， 该外电性连接区设有多个焊孔， 该外电性连接区至少须超出该基板的周缘； 一 罩体， 该罩体可罩盖于该封装模块上以保护包覆将该发光单元， 该罩体的底周缘向 外延设有一延伸座， 该延伸座的底面设有一嵌合部， 该嵌合部相对应于该罩体嵌合 槽； 一发光单元， 该发光单元是设置于该出光区的表面， 该发光单元包含有多个发 光二极管晶粒， 该等发光二极管晶粒与该两导线架藉多个导线构成一电性连接； 一 保护层， 该保护层是包覆该等发光二极管晶粒； 以及至少一荧光层， 该荧光层位于 该保护层上方。 附图说明
第一图为显示本发明的多层式阵列型发光二极管的外观示意图。
第二图本发明的多层式阵列型发光二极管的部份构件的分解示意图。
第三图为显示本发明的_^ 、 封装模块及罩体的断面示意图。
第四图为第一图的断面示意图。
第五图为显示本发明的多层式阵列型发光二极管的½面示意图。
第六图为显示本发明的多层式阵列型发光二极管的导线架另一实施结构。 第七图为显示本发明的多层式阵列型发光二极管封装结构 的金属反光镜杯 的示意图。
第八图为显示本发明的封装模块的透镜嵌合槽的一实施例示意图。
第九图为显示对应于第十二图的透镜嵌合槽而形成的透镜罩的示意图。
【主要组件符号说明】
1
11出光区
13导线架容置槽
131凹槽
15第一固定孔
151凸缘
17穿孔
19第一卡合槽
3封装模块
31上封装模块
311凸板
3111第一凸部
3111a 两突块
33b第二凸部
331b凹缘 33顶面
331第一内壁面
3311固定面
3311a罩体嵌合槽
5导线架
51第二固定孔
51a第二卡合槽
53焊孔
96 反光面
98 光墙
99金属反光镜杯
10罩体
101延伸座
1011延伸座嵌合部 具体实施方式
以下配合图标及组件符号对本发明的实施方式做更详细的说明，俾使熟习该项 技艺者在研读本说明书后能据以实施。
参阅第一图， 本发明的多层式阵列型发光二极管的外观示意图， 参阅第二图， 本发明的多层式阵列型发光二！极管的部份构件的分解示意图， 参阅第三图， 本发明 的多层式阵列型发光 极管的俯面示意图。
参阅第一图，本发明是有关一种多层式阵列型发光二极管，其包含有一基板 1、 一封装模块 3、 两导线架 5及一罩体 10。
该 至少具有一出光区 11及两导线架容置槽 13， 如图二所示， 该出光区 11是为该 1 1的中间区块， 该出光区 11的环周边设有一第一卡合槽 19 , 该两导 线架容置槽 13是位于该出光区 11的前后侧区块， 该两导线架容置槽 13下方板体 的外缘底侧处形成有两间隔设置的凹槽 131， 该两凹槽 131概呈一长方型或其它适 当形状， 其中该基板 1进一步具有设置于该基板 1的左、 右侧边区块的至少一第一 固定孔 15及至少一穿孔 17， 以及对应于该两导线架容置槽 13的至少两凹槽 131， 该第 固定孔 15的内壁面形成有一凸缘 151， 或者亦可如本实施方式所示， 在左、 右侧边的区块各设置有一个第一固定孔 15及两个穿孔 17， 两穿孔 17可设置于第 一固定孔 15的两侧或该基板 1的端角处。 其中该 _ϋ 1的材盾可以是一铜、 铝、 铜合金、铝合金或其它适当金属材。该基板 1的表面可进一步电镀一导热反光层（图 面未显示）， 该导热反光层的材质可以是一镍、 一钯、 一白金、 一银、 一白金合金 或其它适当材质。
参阅第三图， 本发明的 «1、 封装模块及罩体的断面示意图， 参阅第四图， 第 四图为第一图的断面示意图。该封装模块 3是以一射出成型方式形成于该基板 1的 出光区周围， 以使该封装模块 3紧固地与该^ 1相结合， 该封装模块 5的材质为 一环氧树脂（Epoxy )或其它适当材盾， 该封装模块 3高于该出光区 11上表面的部 份定义成一上封装模块 31， 要注意的是， 该上封装模块 31只是为了方便描述本实 施方式所定义出来， 并非独立于该封装模块 3的构件。
该上封装模块 31底面的前后两侧向下形成有两凸板 311， 该两凸板 311的配 置位置及形状相对应于该导线架容置槽 13,该两凸板 311的长度至少大于该导线架 容置槽 13的最长长度，该两凸板 311超出于该导线架容置槽 13的部份并向下延设 有一第一凸部 3111， 该第一凸部 3111底端向内平行延设有两突块 3111a， 该两突 块 3111a是用以对应地与该两凹槽 131相组装， 该上封装模块 31底面在相对应于 该第一固定孔 15处皆形成有一第二凸部 33b，该第二凸部 33 b在对应于该凸缘 151 的位置则形成有一凹缘 331b。
请再参阅第四图， 该凸板 311内包埋有该导线架 5 , 其中每一导线架 5最靠近 该出光区 11一侧的部份为一内电性连接区，一用以打线接合且包埋于该两凸板 311 内的中间区， 该导线架 5最远离于该出光区 11且未包埋于该两凸板 311 内的部份 为一外电性连接区， 该外电性连接区至少须超出该 的周缘， 其中该外电性连 接区设有多个供与外部组件电性连接的焊孔 53，该内电性连接区及该外电性连接区 之间设有至少一第二固定孔 51及至少一第二卡合槽 51a，或如本实施方式可在该第 二固定孔 51两侧各设置有该第二卡合槽 51a, 并设置有三个第二固定孔 51及两焊 孔 53， 因此该第二固定孔 51与该第二卡合槽 51a会包埋于该封装模块 3内， 而该 导线架 5的该内电性连接区与该导线架 5的该外电性连接区是保留未封入于该封装 模块 3以供打线接合与电性连接使用，该导线架 5的上表面至少不低于或平行于该 出光区 11的表面。 要注意的是， 上述该第二固定孔 51与两焊孔 53的配置数量及 位置是视实际需求而定，在此仅是说明用的实例而已，并非用以限制本发明的范围。 第六图为导线架的另一实施结构。
参阅第三图及第四图所示， 该封装模块 3在射出成型时， 就会把基板 1的第一 卡合槽 19、 凹槽 131、 第一固定孔 15及导线架容置槽 13都填满， 因此封装模块 3 的突块 3111a与两凹槽 131以及该凸缘 151与该凹缘 331会互相卡合， 同时该封装 模块 3的封装材料 3也填满了该导线架 5的第二卡合槽 51a及该第二固定孔 51的 空心部分， 藉使得该封装模块 3与该基板 1及该导线架 5紧密地结合成一体。 其中 该第一卡合槽 19及该第二卡合槽 51a的断面形状可以是 V型或其它适当形状。
该上封装模块 31具有一顶面 33、 一内壁面 331、 一固定面 3311及一反光面 96 , 其中该顶面 33为一位于该上封装模块 31上侧周缘的平面部分， 该顶面 33包 含一连接于该上封装模块 31的该内壁面 331的内边， 该内壁面 331基本上是垂设 该顶面 33 ,且该内壁面 331包含一连接于该上封装模块 31的该固定面 3311的底边， 其中该内壁面 331的底边基本上垂直于该固定面 3311， 且该固定面 3311是平行于 该顶面 33 , 该固定面 3311并设有一罩体嵌合槽 3311a , 该罩体嵌合槽 3311a的断 面呈 V型、 凹型、 U型或其它适当形状， 其中该反光面 96以一 30度至 60度范围的 间的倾斜角度设置在该出光区 11周边， 该反光面 96具有一最内边， 该反光面 96 的内边是与该荧光墙 98相接合， 该荧光墙 95相对于该出光区 11的上表面是以一 30度至 60度范围之间的一倾斜角度而形成， 在 I些情形中， 为了要有更好的反光 效应，该反光面 96与该荧光墙 98是藉溅镀方式而形成一镍涂层或一铬涂层或设置 涂布有一镍涂层或铬涂层的一金属反光镜杯于该反光面与该荧光墙之上，以改善该 多层式阵列型发光二极管的反光性能。
参阅第五图， 本发明的多层式阵列型发光二极管的俯面示意图， 并配合第三图 所示。该出光区 11的上表面并设置有一发光单元 7，该发光单元 7设置于该出光区 11的表面， 该发光单元 7包含有多个发光二极管晶粒 71 , 该等发光二极管晶粒 71 是互相打线接合并接合导线 W到该两导线架 5以构成一电路，其中该等发光二极管 晶粒 71是以阵列排列或其它适当排列方式配置于该出光区 11之上，该等发光二极 管晶粒 71上具有一保护层 8， 该保护层 8是涂布于该等发光二极管晶粒 71及接合 的导线 W之上， 该保护层 8的材质为一硅胶或其它适当材质， 该保护层 8上具有至 少一荧光层 9，该荧光层 9在由一荧光墙 98所定义的区域内藉提供一磷化合物剂而 形成， 其中该磷化合物是与硅混合， 该荧光层 9包覆有该荧光墙 98的部分， 该荧 光层 9的材盾为一磷化合物或其它适当材质，该荧光墙 98相对于该出光区 11的上 表面是以一 30度至 60度范围之间的一倾斜角度而形成， 该荧光墙 98是配置于该 出光区周边 11。
该罩体 10由可透光性硅胶以射出成形方式制成于该发光单元 7之上， 该罩体 10可罩覆该封装模块与该发光单元 7 以保护包覆将该发光单及元， 其中该罩体 10 的底周缘向外延设有一延伸座 101， 该延伸座 101的底面设有一嵌合部 1011 , 该嵌 合部 1011的设置位置相对应于该罩体嵌合槽 3311a，该延伸座 101间的长度至少不 小于该上封装模块 31的该第一内壁面 331间的长度。其中该罩体 10的材质为一硅 胶材质且具有可透光性。
将该罩体 10的该嵌合部 1011对准于该罩体嵌合槽 3311a后即可相互结合，并 且该延伸座 101端面同时紧密面合于该第一内壁面 331 ,使得该罩体 10稳固地固定 于该封装模块 3上。
该两导线架 5的焊孔 53可分别引接电源导线（图面未显示），当施加一偏压时， 该等发光二极管晶粒 71则受电源驱动发光，该等发光二极管晶粒 71以阵列排列方 式的发光方式具有高亮度的发光特性， 当光源光线穿过该荧光层 9产生有混光的效 果。
参阅第八图与第九图，该罩体嵌合槽 3311a可以是一 U型的断面并配置于该上 封装模块 31的该反光面 96上的一顶部周边处，并且该罩体嵌合槽 3311a相对于该 出光区 11的上表面是以 0度至 80度范围之间的一倾斜角度而配置， 而该罩体 10 的底周缘向外延设有一延伸座 101 , 该延伸座 101的底面设有一嵌合部 1011， 该嵌 合部 1011的设置位置相对应于该罩体嵌合槽 3311a , 以使该罩体 10固定于该封装 模块 3上。
以上所述者仅为用以解释本发明的较佳实施例，并非企图据以对本发明做任何 形式上的限制，是以，凡有在相同的发明精神下所作有关本发明的任何修饰或变更， 皆仍应包括在本发明意图保护的范畴。

Claims

权利要求
1. 一种多层式阵列型发光二极管， 是包含：
该基板至少具有一出光区及两导线架容置槽， 其中该出光区是位于该 «I的中间区块， 该两导线架容置槽是位于该基板的前后侧区块， 其中该基板进一 步具有设置于该基板的左、 右侧边区块的至少一第一固定孔及至少一穿孔， 以及 对应于该两导线架容置槽的至少两凹槽；
一封装模块， 其是以一射出成型方式形成于该 的该出光区周围， 该封装模 块高于该出光区的表面的部份定义成一上封装模块，其中该上封装模块底面的前后 两侧向下形成有两凸板， 该两凸板的配置位置相对应于该导线架容置槽， 该两凸板 的长度至少大于该导线架容置槽的最长长度，该两凸板超出于该导线架容置槽的部 份并向下延设有一第一凸部， 该第一凸部底端向内平行延设有两突块， 该两突块是 用以对应地与该两凹槽相组装，其中该上封装模块底面在相对应于该第一固定孔处 皆形成有一第二凸部， 该第二凸部对应于该凸缘的位置则形成有一凹缘， 又该上封 装模块具有一顶面、 一第一内壁面、 一固定面及一反光面， 其中该顶面为一位于该 上封装模块上侧周缘的平面部分，该顶面包含一连接于该上封装模块的该第一内壁 面的内边， 该第一内壁面基本上是垂设该顶面， 且该第一内壁面包含一连接于该上 封装模块的该固定面的底边， 其中该第一内壁面的底边基本上垂直于该固定面， 且 该固定面是平行于该顶面；
两导线架， 该两导线架是部份地被包埋于该凸板内， 其中每一导线架最靠近该 出光区一侧的部份为一内电性连接区，一用以打线接合并包埋于该两凸板内的中间 区， 以及 I远离于该出光区及未包埋于该两凸板内的外电性连接区， 其中该内电性 连接区及该外电性连接区的间设有至少一第二卡合槽及至少一第二固定孔，该第二 卡合槽与该第二固定孔皆包埋于该封装模块内， 而该导线架的该内电性连接区与该 导线架的该外电性连接区是保留未封入于该封装模块以供打线接合与电性连接使 用， 其中该外电性连接区设有多个供与外部组件电性连接的焊孔， 且该外电性连接 区至少须超出该！ 的周缘；
一发光单元， 该发光单元是设置于该出光区之上， 其中该发光单元包含有多个 发光二极管晶粒，该等发光二极管晶粒是互相打线接合并接合导线到该两导线架以 构成一电路；
一罩体， 该罩体由可透光性硅胶以射出成形方式制成， 该罩体可罩覆该封装模 块与该发光单元以保护该发光单元， 其中该罩体的底周缘向外延设有一延伸座， 该 延伸座的底面设有一嵌合部， 该嵌合部相对应于该罩体嵌合槽的设置位置;
一保护层， 该保护层是涂布于该等发光二极管晶粒及接合的导线的上； 以及 一荧光层， 该荧光层形成于该保护层上方， 其中该荧光层在由一荧光墙所定义 的区域内藉提供一磷化合物剂而形成， 该反光面的内边是与该荧光墙相接合。
2.如权利要求 1所述的一种多层式阵列型发光二极管，其中该基板进一步包含 设置有分别相对应于该两导线架容置槽的每一导线架容置槽的一凹槽， 以及该两导 线架是定位于定义为该两导线架容置槽的侧边配置空间内，其中该两导线架与该基 板保持非接触。
3. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该基板的材质可 以是一铜、 一铝、 一铜合金或一铝合金的至少其中之一。
4. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该出光区的周边 是设有一第一卡合槽。
5. 如权利要求 4所述的一种多层式阵列型发光二极管， 其中该第一卡合槽的 断面是呈一 V型。
6. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该第二卡合槽的 断面是呈一 V型。
7. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该 的表面进 一步设有一导热反光层，该导热反光层的材质至少包含有一镍或一银的至少其中的
8. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该导线架的表面 至少不低于该出光区的表面。
9. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该罩体嵌合槽的 断面呈一 V型。
10. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该延伸座间的长 度至少不小于该上封装模块的该第一内壁面间的长度。
11. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该等发光二极管 晶粒是以阵列排列配置于该出光区的表面。
12. 如^又利要求 1所述的一种多层式阵列型发光二极管， 其中该绝缘保护层是 为一透光性硅胶薄层以保护该等发光二极管晶粒及接合的导线。
13. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该磷化合物是与 硅混合， 并且该荧光墙所定义的区域内提供该磷化合物， 其中该荧光墙于该出光区 周边以一 30度至 60度范围之间的一倾斜角度而设置。
14. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该反光面与该荧 光墙是涂布有一镍涂层或一铬涂层的至少其中的一。
15. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该反光面与该荧 光墙上设置有一金属反光镜杯，其中该金属反光镜杯是涂布有一镍涂层或一铬涂层 并具有一较佳于该反光面与该反光墙的光学反射性。
16. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该荧光墙相对于 该出光区的上表面是以一 30度至 60度范围之间的一倾斜角度而形成。
17. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该反光面相对于 该出光区的上表面以一 30度至 60度范围的间的一倾斜角度而形成。
18. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该罩体是以硅胶 ^成。
19. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该罩体具有可透 光性。
20. 如权利要求 1所述的一种多层式阵列型发光二极管， 其中该罩体嵌合槽是 为一 U型的断面并配置于该上封装模块的该反光面上的一顶部周边处，并且该罩体 嵌合槽相对于该出光区的上表面是以 0度至 80度范围之间的一 斜角度而配置， 而该罩体的底周缘向外延设有一延伸座， 该延伸座的底面设有一嵌合部， 该嵌合部 的设置位置相对应于该罩体嵌合槽， 以使该罩体固定于该封装模块上。
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