WO2011113414A2 - Procédé de frittage ntv d'un composant semi-conducteur - Google Patents

Procédé de frittage ntv d'un composant semi-conducteur Download PDF

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Publication number
WO2011113414A2
WO2011113414A2 PCT/DE2011/000231 DE2011000231W WO2011113414A2 WO 2011113414 A2 WO2011113414 A2 WO 2011113414A2 DE 2011000231 W DE2011000231 W DE 2011000231W WO 2011113414 A2 WO2011113414 A2 WO 2011113414A2
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WO
WIPO (PCT)
Prior art keywords
sintering
ntv
layer
plasma deposition
nanopowder
Prior art date
Application number
PCT/DE2011/000231
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German (de)
English (en)
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WO2011113414A4 (fr
WO2011113414A3 (fr
Inventor
Mathias Kock
Original Assignee
Danfoss Silicon Power Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Danfoss Silicon Power Gmbh filed Critical Danfoss Silicon Power Gmbh
Publication of WO2011113414A2 publication Critical patent/WO2011113414A2/fr
Publication of WO2011113414A3 publication Critical patent/WO2011113414A3/fr
Publication of WO2011113414A4 publication Critical patent/WO2011113414A4/fr

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Definitions

  • the invention relates to a method for NTV sintering of a semiconductor device according to the preamble of the main claim.
  • a modern method of bonding semiconductors to substrates is low temperature pressure sintering (NTV low temperature bonding) with silver.
  • NTV low temperature bonding low temperature pressure sintering
  • the semiconductor is pressed onto the substrate with a compound layer of silver using temperature (180 ° C to 350 ° C) and pressure (3-30 MPa).
  • Such an advantageous compound has a particularly high thermal and current carrying capacity if the porosity of the sintered compound is particularly low (for example less than 15%).
  • the sintering pressure is set correspondingly high.
  • the initial silver layer before pressing is usually a dried suspension of particulate silver. If the silver particles are nanoscale (ie they are l-100nm in diameter), a lower pressure is required (3-10 MPa). For macroscale suspensions (1 ⁇ - 20 ⁇ ) a pressure of 10- 30 MPa is required. The best results are obtained when the pressure is transferred to the semiconductor device and the surrounding substrate by a press with heatable lower punch and an upper punch with a flexible or deformable pressure plate.
  • the semiconductors to be sintered are also pressed into the silver suspension with hard (eg ceramic stamp surfaces) and the sintering is initiated. Subsequently, the sintered semiconductors are electrically contacted, for example, by ultrasonic wire bonding or tape bonding.
  • the relatively high relative pressure also generates local stress peaks with a yielding upper punch layer which lead to shear and tensile stresses, in particular in the semiconductor and its structures.
  • the particularly exposed elevations on the semiconductor as points of maximum force transmission are at risk.
  • These geometrically towering structures on the predominantly planar semiconductors are the isolation edges around contact surfaces.
  • an IGBT transistor is provided on its upper side with isolation structures around the gate contact for isolation between gate and emitter.
  • diodes are isolated in the same way between the contact surfaces of the anode and cathode by a raised against the remaining semiconductor surfaces insulating wall.
  • Such insulation walls consist for example of brittle layers, such as S13N4, Si0 2 or glasses. Typical for these isolation walls are heights of 2 - ⁇ ⁇ . Furthermore, insulating walls of polymers (especially polyimides) are also common. These have a low brittleness, but are characterized by the sintering pressure. drlindbar. Cracks, destructions and / or delaminations occur in the area of the insulation walls due to the pressure of the sintering punch, even in cases where you do not come into direct contact with the sintering punch. Such damage is also occasionally observed after the wire (ribbon) bonding cutoff when the cut wire or ribbon end is pulled over the edges of the insulation walls.
  • the contact surface or contact surfaces of the semiconductor are first provided with an electrically conductive additional layer which has at least the thickness of the highest insulation walls, but preferably is significantly higher to ensure relief of the insulation walls.
  • an electrically conductive additional layer which has at least the thickness of the highest insulation walls, but preferably is significantly higher to ensure relief of the insulation walls.
  • a particularly advantageous effect has been found in about three to five times the layer thickness compared to the height of the insulation walls.
  • the layer should also be bondable so that the typical contacts obtained by ultrasonic bonding of contact wires and tapes to conduct electricity can be.
  • preferably good conductive materials such as Al, Cu or Ag or their alloys are used.
  • the additional metal layer according to the invention additionally acts advantageously as a pressure transmitter to avoid mechanical stress peaks over the semiconductor surface and thus solves a further problem.
  • a further preferred improvement results from the use of thermally highly conductive layer materials by the thermal spreading and buffering effect of the thick metal layer.
  • the application of the layer is preferably to produce in the wafer composite and can be done selectively by masked chemical, electroplating or physical deposition technique.
  • the selective spraying of metal powders (nanoscale) by a low-temperature plasma has proven to be particularly economical.
  • layer thicknesses up to several ⁇ be produced.
  • This method can also be used for already sawn wafers on film and for already sintered chips on substrates. Further advantages and features will become apparent from the following description of a preferred embodiment. Showing:
  • Fig. 1 shows a cross section of a power semiconductor (the example of an IGBT) sintered on a ceramic substrate with the protective layers according to the invention against destructive consequences of the sintering pressure.
  • the inventive method for NTV sintering of a semiconductor device 5 for the power electronics under which a sintered layer 6 is provided, which provides the heat dissipation and which is provided with the metallic contact areas, insulating, over the flat contact areas protruding edges or insulating walls 3, draws by the following steps: 1.) over the above insulating walls 3, the contact areas are filled by the application of at least one further, planar, electrically and thermally conductive, preferably metallic layer 4, 2.) Sinterstkov then act on these applied (n ) further layer 4 during sintering and 3) bonding wires 1a, 1b are bonded to this applied further electrically and thermally conductive layer (s), preferably metallic layer (s).
  • bonding wires 1a, 1b are, after sintering for contacting e.g. made of an IBGT transistor with gate or emitter contact.
  • At least one of the further layers is formed by vacuum plasma deposition.
  • one of the further layers consists of copper and / or one of the further layers is made thick as a second heat sink with a total thickness of the layers of 30 ⁇ m.
  • the metallic contact areas consist of an aluminum compound and / or the copper layer (s) of nanoparticles are sprayed on (N anopowder plasma deposition).
  • the nanopowder plasma deposition is carried out without preparatory etching and etching steps on the semiconductor components before they are separated by sawing a wafer.
  • temperatures of 60 to 140 ° C for nanopowder plasma deposition suggest, the temperatures of 130 ° C to 140 ° C are reserved for thinner layers and thicker preferably at temperatures between 95 ° and 115 ° C. become. Nanopowder plasma deposition will already be successful at atmospheric pressure.
  • nanopowder plasma deposition is preferred in which pure powdered copper with grain diameters of 0.05 to 0.5 ⁇ m is sprayed without further admixtures.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Powder Metallurgy (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Die Bonding (AREA)

Abstract

L'invention concerne un procédé de frittage NTV (technique de connexion à basse température) d'un élément semi-conducteur (5) conçu pour l'électronique de puissance et muni de zones de contact, sous lequel est disposée une couche frittée (6) chargée d'évacuer la chaleur, qui est pourvue d'une autre couche plane (4) électroconductrice et thermoconductrice sur laquelle les fils ou les bandes de connexion (1a, 1b) sont connectés. La ou les autres couches (4) sont appliquées sur les zones de contact par le biais de bords faisant saillie (3) et, durant le frittage, des tampons de frittage agissent sur la ou les autres couches (4) appliquées.
PCT/DE2011/000231 2010-03-19 2011-03-02 Procédé de frittage ntv d'un composant semi-conducteur WO2011113414A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102010012231.9 2010-03-19
DE102010012231A DE102010012231A1 (de) 2010-03-19 2010-03-19 Verfahren zum NTV-Sintern eines Halbleiterbausteins

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WO2011113414A2 true WO2011113414A2 (fr) 2011-09-22
WO2011113414A3 WO2011113414A3 (fr) 2012-03-15
WO2011113414A4 WO2011113414A4 (fr) 2012-05-03

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CN102394235A (zh) * 2011-11-15 2012-03-28 株洲南车时代电气股份有限公司 一种绝缘栅双极晶体管模块及其制作方法
CN102881589B (zh) * 2012-09-24 2015-05-13 株洲南车时代电气股份有限公司 一种压接式igbt模块的制作方法及压接式igbt模块
JP6436247B2 (ja) 2015-12-14 2018-12-12 三菱電機株式会社 半導体装置及びその製造方法
DE102020202845A1 (de) 2020-03-05 2021-09-09 Volkswagen Aktiengesellschaft Verfahren zur Herstellung eines elektrischen Moduls

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US20090244868A1 (en) 2008-03-31 2009-10-01 Toshiaki Morita Semiconductor device and bonding material

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DE58908749D1 (de) * 1988-03-03 1995-01-26 Siemens Ag Verfahren zum Befestigen von elektronischen Bauelementen auf Substraten und Anordnung zur Durchführung desselben.
JP4930894B2 (ja) * 2005-05-13 2012-05-16 サンケン電気株式会社 半導体装置
US7754533B2 (en) * 2008-08-28 2010-07-13 Infineon Technologies Ag Method of manufacturing a semiconductor device

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US20090244868A1 (en) 2008-03-31 2009-10-01 Toshiaki Morita Semiconductor device and bonding material

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WO2011113414A4 (fr) 2012-05-03
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