WO2011100738A1

WO2011100738A1 - Single phase multilevel inverter

Info

Publication number: WO2011100738A1
Application number: PCT/US2011/024864
Authority: WO
Inventors: Yaosuo Xue; Madhav Manjrekar
Original assignee: Siemens Corporation
Priority date: 2010-02-15
Filing date: 2011-02-15
Publication date: 2011-08-18
Also published as: CN102763316A; CA2789705A1; KR20120117940A; IN2012DN06603A; US20130014384A1; EP2537245A1; US9009956B2

Abstract

Systems and methods are described that provide multilevel inverters having a plurality of levels using a simplified topology. For single phase systems, embodiments provide a full-bridge topology using bidirectional switching interconnections

Description

SINGLE PHASE MULTILEVEL INVERTER

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 61/304,538, filed on February 15, 2010, the disclosure which is incorporated herein by reference in its entirety .

BACKGROUND OF THE INVENTION

[0002] The invention relates generally to DC to ac inverters. More specifically, the invention relates to methods and systems for multilevel inverters having a simplified topology.

[0003] Today, the power industry has revived and entered a new age using renewable energy, and high efficiency power

generation, transmission and distribution where multilevel power converters can assume significant roles.

[0004] Multilevel power converters emerged from the

realization that single power semiconductors cannot meet the voltage requirements required for medium voltage power conversion. Multilevel power conversion has rapidly grown in the field of power enqineerinq for the applications of medium voltage ac drive, Flexible AC Transmission System (FACTS) devices, Medium Voltage DC (MVDC) transmission, and High

Voltage DC (HVDC) transmission systems. Despite today's high power semiconductor technology that has reached 6.5 kV and 2.5 kA power ratings, multilevel power converters built with mature medium power semiconductor technology present- competitive alternative solutions with many advantages over conventional 2-level converters due to their ability to synthesize waveforms exhibiting lower distortio and better dv

harmonic cancellation, smaller — and common-mode voltage, and low switching frequency operation, and attain higher voltages using semiconductor devices with smaller voltage ratings,

[0005] Topological.lv, a. multilevel structure can be considered as an ac voltage synthesizer realized from multiple discrete DC voltage sources. Multiple, equal DC sources are required. Multilevel inverters provide an ac output waveform at discrete voltage levels. The more steps or levels generate a. smoother sinusoidal waveform and reduce the amount of output filtering. Practically, it is a trade-off to select the number of levels considering the converter complexity and filter requirements. By optimizing the angles and heights of steps, certain lower order harmonics can be cancelled. In addition, the harmonics spectrum can be reduced by using Pulse Width Modulation (PWM) techniques at each level.

[0006] Numerous multilevel inverter topologies have been proposed and studied for power utility and motor drive applications. FIGs . 1A and IB show prior art half-bridge and full-bridge diode-clamped or neutral-point-clamped (NPC) inverters. FIGs. 2A and 2B show prior art half-bridge and full-bridge capacitor-clamped or flying-capacitor inverters. FIG. 3 s ows a. prior art cascaded H-bridge inverter with separate dc supplies and an ac output at nodes A and B . FIG. 4 s ows a prior art topology that replaces an H-bridge architecture with cascaded 2-terminal submodules without separate dc sources to form a modular structure.

[0007] The diode-clamped multilevel converter is the most widely used inverter topology. However, this topology is cumbersome to implement for levels beyond five. [0008] There is a need for a simplified inverter topology that allows for levels greater than five.

SUMMARY OF THE INVEN ION

[0009] The inventors have discovered that it would be

desirable to have methods and systems for multilevel inverters having a plurality of levels using a simplified topology. For single phase systems, embodiments provide a full-bridge topology using unidirectional and bidirectional controlled switching interconnections. Since the ac output is obtained differentially, the required amount of DC sources can be reciuced by ha1 f .

[0010] Embodiments provide a class of single phase multilevel inverter topologies using a full-bridge approach with

bidirectional interconnections. Compared to diode-clamped or flying-capacitor multilevel topologies, the required

split-rail dc inputs are less, and the required power switch number can be reduced, by removing redundant switching states. With asymmetrical DC sources, the number of output levels may be increased in the proposed generalized, multilevel structure.

[0011] One aspect of the invention provides a method for a single phase inverter topology. Methods according to this aspect of the invention comprise selecting a number of desired inverter output levels m , where m>5, is an integer and an odd number, determining a number of equal DC sources n , where m— \

« = -—— , coupling the n DC sources in series, wherein the source series has a first DC source that defines a positive node P and a last DC source that defines a negative node N , defining one or more source series nodes between each DC source in the source series wherein the source series node after the first DC source that defines a positive node P is the first source series node and the source series node before the last DC source that defines a negative node N is the last source series node, determining a number of unidirectional controlled switches ucs , assembling one or more inverter cells, wherein an inverter cell comprises six unidirectional ucs

controlled switches and the quotient of —^- determines the number of inverter cells required for the selected number of inverter output levels m , arranging four of the

unidirectional controlled switches for each inverter cell as two bidirectional controlled switches, for each inverter cell, coupling two bidirectional controlled switches together forming a cell series node and coupling the other terminal of each bidirectional controlled switch to the emitter terminal of one unidirectional controlled switch forming two cell nodes, coupling the cell series node of a cell to the first source series node and coupling the collector terminals of the cell's two unidirectional controlled switches to the node P , for each remaining inverter cell, coupling the cell series node to a following source series node and coupling each unidirectional controlled switch's collector terminal to a respective cell node of a previous inverter cell, and coupling the emitter terminal for each of the two remaining

unidirectional controlled, switches to the node N and coupling the each collector terminal to a respective cell node of the last inverter cell.

[0012] Another aspect of the invention is a single phase inverter topology method. Methods according to this aspect of the invention comprise selecting a number of desired inverter output levels m , where m > 5 , is an integer and an odd number, m^■— 1 determining a number of equal DC sources n , where n =— -— , coupling the n DC sources in series, wherein the source series has a first DC source that defines a positive node P and a last DC source that defines a negative node N , defining one or more source series nodes between each DC source in the source series wherein the source series node after the first DC source that defines a positive node P is the first source series node and the source series node before the last DC source that defines a negative node N is the last source series node, determining a number of unidirectional controlled switches ucs , assembling one or more inverter cells, wherein an inverter cell comprises six unidirectional controlled

ucs

switches and the quotient of -^— determines the number of inverter cells required for the selected number of inverter output levels m , arranging four of the unidirectional

controlled switches for each inverter cell as two

bidirectional controlled switches, for each inverter cell, coupling two bidirectional controlled switches together forming a cell series node and coupling the other terminal of each bidirectional controlled switch to the emitter terminal of one unidirectional controlled switch forming two cell nodes, coupling the cell series node of a first inverter cell to the last source series node and coupling the emitter terminal for each of the two remaining unidirectional

controlled switches to the node N and coupling each collector terminal to a. respective cell node of the first inverter cell, for each remaining inverter cell, coupling the cell series node to a previous source series node and coupling each cell node to a unidirectional controlled switch' s collector terminal of a. following inverter cell, and for the last inverter cell, coupling the collector terminals of the last cell's two unidirectional controlled switches to the node P . [0013] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the

invention will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1A is a prior art half -bridge diode-clamped

5-level inverter topology.

[0015] FIG, IB is a prior art full-bridge diode-clamped

5-level inverter topology.

[0016] FIG. 2A is a prior art half-bridge flying-capacitor

5-level inverter topology.

[0017] FIG. 2B is a prior art full-bridge flying-capacitor 5-level inverter topology.

[0018] FIG. 3 is a prior art cascaded H-bridge 5-level inverter topo1ogy .

[0019] FIG, 4 is a prior art modular 5-level inverter

topology .

[0020] FIG. 5A is an exemplary 5-level inverter topology with a full number of power semiconductor switches.

[0021] FIG. 5B is an exemplary s-level inverter topology with a reduced number of power semiconductor switches. [0022] r^'IG. 6A is a table showing the power switching for the full topology 5-level inverter in FIG, 5A.

[0023] FIG. 6B is a table showing the power switching for the reduced topology 5-level inverter in FIG. 5B.

[0024] FIG. 7 is an exemplary plot of the power switching and V_AB output for the reduced topology 5-level inverter in FIG. 5B.

[0025] FIG. 8 is an exemplary plot of capacitor voltage and Vac output for the reduced topology 5-level inverter in FIG. 5B under light load.

[0026] FIG. 9 is an exemplary plot of capacitor voltage and Vac output for the reduced topology 5-level inverter in FIG. 5B under heavy load.

[0027] FIG. 10A is an exemplary 7-level inverter with ac output from the last inverter cell in full (left) and reduced (right) topologies .

[0028] FIG. 10B is an exemplary 7-level inverter with ac output from the first inverter cell in full (left) and reduced. ( right ) topo1ogies .

[0029] FIG. 11 is an exemplary 9-level inverter with ac output from the second inverter cell in full (left) and reduced

(right) topologies. [0030] FIG. 12 is a table showing the power switching for the 7-level full (left) and reduced (right) topologies in FIG. 10B,

[0031] FIG. 13 is a table comparing the number of switching- devices for full and reduced embodiment topologies and the prior art.

[0032] FIG. 14 is a table comparing the number of components between embodiments and the prior art.

[0033] FIG. 15 is a multilevel inverter topology method.

[0034] FIG. 16 is an exemplary inverter cascading topology.

[0035] FIG. 17 is an exemplary output plot of two cascaded 5-level inverters.

3 DE AILED DESCRIP ION

[0036] Embodiments of the invention will be described with reference to the accompanying drawing figures wherein like numbers represent like elements throughout. Before embodiments of the invention are explained in detail, it is to be

understood that the invention is not limited in its

application to the details of the examples set forth in the following description or illustrated in the figures. The invention is capable of other embodiments and of being practiced or carried out in a variety of applications and in various 'ways. Also, it is to be understood that the

phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including,," "comprising," or "having," and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

[0037] The terms "connected" and "coupled" are used broadly and encompass both direct and indirect connecting, and coupling. Further, "connected" and "coupled" are not

restricted to physical or mechanical connections or couplings.

[0038] It should be noted that the invention is not limited to any particular software language described or that is implied in the figures. One of ordinary skill in the art will

understand that a variety of software languages may be used for implementation of the invention. It should also be understood that some: of the components and items are

illustrated and described as if they were hardware elements, as is common practice within the art. However, one of ordinary skill in the art, and based on a reading of this detailed description, would understand that, in at least one

embodiment, components in the method and system may be implemented in software or hardware. [0039] Embodiments of the invention provide methods, system, frameworks, and a computer-usable medium storing

computer-readable instructions that provide multilevel inverters having a plurality of levels using a simplified topology. The invention may be deployed as software as an application program tangibly embodied on a program storage device. The application code for execution can reside on a plurality of different types of computer readable media known to those skilled in the art.

[0040] FIG. 5A shows a 5-leveI single phase inverter topology with ac obtained between differential output nodes A and B . The 5-level inverter comprises four unidirectional controlled switches 5, , S_{2 f} S₃ , S₄ , two bidirectional controlled switches

S₅ , S₆ and two DC sources ~V , ~V in series. y ical unidirectional controlled switches comprise power

semiconductors such as Insulated-Gate Bipolar Transistors (IGBTs) with an anti-parallel diode across their

emitter-collector junctions. An IGBT is a three-terminal power semiconductor device having an isolated Field Effect

Transistor (FET) for the control input (gate) and a bipolar power transistor as a switch, (collector-emitter) . The power semiconductor devices can also be Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) , Integrated Gate-Commutated Thyristors (IGCTs) , Gate Turn-Off Thyristors (GTOs) , or other types. The IGBT emitter is equivalent to a MOSFET source, or an IGCT or GTO anode. The IGBT collector is equivalent to a MOSFET drain or an IGCT or GTO cathode. For this disclosure, the unidirectional controlled switches are treated as two terminal (collector-emitter) devices. For the unidirectional controlled switches 5,, S₂, S_~ , S₄ the anode of the

anti-parallel diode is coupled to the emitter. A bidirectional controlled switch can be formed by coupling together the emitters of two unidirectional controlled switches. The two DC sources —V , —V may be two discrete DC supplies or two capacitors (C_l , C₁ ) , which split one common DC supply \V) across nodes P and N into two discrete DC supplies in series. The total number of unidirectional and bidirectional controlled switches (six) is the same as used in a prior art 5-level topology. The neutral ground, node O can be positioned flexibly since 0 Vac is obtained differentially and not by clamping to a neutral .

[ 0041 ] To avoid short circuiting the DC bus or the two DC sources ~¥ , -~ F , the following constraints are imposed on the switch control scheme:

[ 0042 ] S, and S\ can not be turned on simultaneously;

[ 0043 ] S_j and S₅ can not be turned on simultaneously;

[ 0044 ] 5-, and S₅ can not be turned on simultaneously;

[ 0045 ] S₂ and 5'₄ can not be turned on simultaneously;

[ 0046 ] S₂ and S, can not be turned on simultaneously; and

[ 0047 ] S_A and S₆ cannot be turned on simultaneously. [0048] Under these switching constraints, a 5-level ac output waveform is synthesized from the differential voltage across output nodes A and B . For convenience, the series source node

1 1

between the two DC sources —V , —V is grounded. Output nodes

A and B can be switched using the four unidirectional controlled switches S_x , S₂ , , S₄ and two bidirectional controlled switches S₅ , S₆ to connect to the positive P , common O , and negative N DC nodes (potentials) ,

[0049] FIG. 6A shews a table listing all combinations of switch S„ states that generate a 5-level sinusoid {V_AB} at output nodes A and B . At any time, only two switches are required to be closed to output a specific voltage level. The redundant switching choices can be alternated cycle by cycle to balance the DC source voltage sharing and utilization.

[0050] FIG. 5B s ows a 5-level inverter topology using four unidirectional (5',, S, , S₃ , S₄ ) and one bidirectional (S₆) controlled switches. The required output voltage levels are still achieved with the removal of one bidirectional

controlled switch «S₅ from the full topology (FIG. 5A) . FIG. 6B shows a table listing all combinations of the switch S_i:

states .

[0051] During the positive half cycle, node A is clamped to node P ( 5, = ON, 5₃= OFF) and node B is switched, among nodes

Ρ,Ο,οτΝ to obtain OF, +~V and ÷¥ respectively. During the negative half cycle, node A is clamped to node N (5= OFF, 5,= ON) and node B is switched among nodes N,0,orP to obtain OF, -—V , and -V respectively. FIG. 7 snows the switch conduction states 5, , S₂ , S, , S₄ , S₆ and resultant output ac

topology 5-level inverter shown in FIG . 5B.

[0052] A MATLAB/Simulink model of the embodiment was built to simulate the basic operating principle. Under the lowest frequency switching scheme (close to the fundamental frequency, 60 Hz) . FIGs . 8 and 9 plot the DC sources ~F , ~F , configured as capacitors C, , C₂ (with one common DC supply (v) across nodes P and N ) , their voltages V_a , V_a under different ac load conditions (top plots) and an observed ac waveform generated (bottom plots) .

[0053] Two zero voltage states are used alternatively to balance the capacitor voltages V_c , ν . FIG. 8 (upper plot) shows that when capacitors C. and C₂ are large enough

(2,000 iP, 400 VDC) and the ac load is not heavy (10 Ω and 1 mH in series), the output (lower plot) V_AB waveform (stepped line) will be odd-symmetric and mirror-symmetric, which eliminates the DC component and all even-order harmonics. To cancel certain lower-order harmonics, the proper angle for each level of the 5-level inverter is chosen to satisfy

4V ( 1

[0054] )sηθ, + cosmi, I ===^: 0

ηπ v Ί

(1) [0055] where Θ-, and Θ-, are the angles in radians for different voltage levels (FIG, 7, V_AB versusa* ) and n is the harmonic order to be cancelled,

[0056] At each inverter output level, increasing switching pulses or using Pulse Width Modulation (PWM) techniques can control the output voltage magnitude and further depress the lower-order harmonic spectrum and reduce output filter

(inductor and capacitor) size.

[0057] Embodiments are scaleable and allow for the number of inverter output levels to be increased by adding split-rail DC sources and inverter cells (unidirectional and bidirectional contro11ed switches) .

[0058] FIGs. 10A and 10B (left) show 7-level inverters having full topologies with three equal DC sources (C) , six

unidirectional controlled switches S₁ , S, , S₃ , S₄ , S₅ , S₆ and four bidirectional controlled switches S-, , S_s , S_{g f} S_]0. The ac output may be obtained either across the last inverter cell (across cell nodes A and B , FIG. 10A) or the first inverter cell (across cell nodes A and B , FIG. 10B) .

[0059] For a 7-level inverter full topology, there are

redundant states to achieve one specific voltage level. For example, there are four choices to obtain zero voltage, three

1 1 2

choices to obtain a +—V or —V , two cfioices for +—V or

3 3 3

2

-—V , and one choice for +V or -V voltage level. By- sacrificing the voltage stress of a single switch, the amount of switches may be reduced and generate the same output. FIGs. 10A and 10B (right) show a reduction in the total number of unidirectional controlled switches from six to four and a reduction in the number of bidirectional controlled switches from four to two,

[0060] FIG. 11 shows a similar reduction for a 9-level inverter. FIG. 12 shows a table listing all combinations of the switch states for both, full and reduced. 7-level inverter topologies shown in FIG. 10B.

[0061] For higher level inverters, the switch reduced topology is not unique. However, the minimum number of required

semiconductor switches is unique for a desired m level inverter. Embodiments provide a method to arrive at the number of DC sources, and the number of unidirectional and

bidirectional controlled switches for a desired multilevel inverter output.

[0062] FIG. 13 shows a table comparing different inverter levels and their required number of switching devices. For example, a 13-level inverter would require six split-rail DC sources. For a full topology version, each DC source is available. For a reduced topology version, the connections to some DC sources are omitted. For a 13-level inverter, the maximum reduction of switching elements is twelve arriving at a minimum number of twenty.

[0063] FIG. 14 is a. table comparing the number of electrical components used in multilevel embodiment topologies with prior art multilevel inverter topologies. FIG. 13 shows that full topology embodiments are not desirable in terms of switch number, while reduced topology embodiments offer a substantial reduction in switches. For reduced topologies, the reverse blocking voltages of different semiconductor switches can be asymmetrical because some switches are across higher DC voltages than other switches. Additionally, using less split-rail DC sources, the voltage stress of switches is higher compared to the same level conventional topology.

[0064] FIG. 15 shows a method for arriving at full and reduced multilevel inverter topology embodiments . A desired number of inverter output levels m is selected, where m > 5 , is an integer and an odd number (step 1501) . The number of DC sources n in series is determined based on the output levels

m-\

m , where ------—-— . The DC sources n may be n equal discrete DC supplies or n equal capacitors splitting a common DC supply (step 1503) .

[0065] The n DC sources are coupled together in series (where the DC sources add together) and define a positive node P at the first DC source positive end, a negative node N at the last DC source negative end and one or more series source nodes at each DC source series coupling beginning with a first series source node after the first DC source (steps 1505, 1507) . If n capacitors are used, one common DC supply (v) is coupled across the nodes P and N .

[0066] From the selected number of output levels m , a number of unidirectional controlled switches ucs is determined depending on whether a full (steps 1509, 1513) or reduced (steps 1509, 1511) inverter topology is desired. FIG. 13 shows the relationships of the full and reduced inverter topology unidirectional controlled switch requirements. From the total number ucs of unidirectional control switches, inverter cells are asserab1ed . [0067] An inverter cell comprises two unidirectional

coritro11ed switches and two bidirectiona1 contro11ed s itches . An inverter cell therefore requires six unidirectional

controlled switches. From the total number ucs of

ucs

unidirectional control switches, (quotient) determines the

6

number of inverter cells for the number of selected inverter output levels m . Out of the total number ucs of unidirectional control switches, two unidirectional controlled switches remain (remainder) (step 1515) . As described above, a

bidirectional controlled switch comprises two unidirectional controlled switches coupled together, emitter-to-emit er.

[0068] For each inverter cell, the two bidirectional

controlled switches are coupled together and their common node forms a cell series node. The other terminal of each

bidirectional controlled switch is coupled to the emitter terminal of one unidirectional controlled switch, forming two cell nodes (step 1517) . Each inverter cell therefore has one cell series node and two cell nodes,

[0069] Each inverter cell series node is coupled to a source series node. The first source series node is coupled to the cell series node for a cell and the collector terminals of that cell's two unidirectional controlled, switches are coupled, to the node P (step 1519) . For each remaining inverter cell, the cell series node for a cell is coupled to a following source series node, and. each unidirectional controlled

switch's collector terminal is coupled to a respective cell node of a previous inverter cell (step 1521) . [0070] After all inverter cells have been coupled to

respective source series nodes and previous inverter cell's cell nodes,, two unidirectional controlled switches remain .

[0071] The emitter terminal for each, of the two remaining unidirectional controlled, switches is coupled to the node N and each collector terminal is coupled, to a respective cell node of the last inverter cell (step 1523) . The ac output may^¬ be taken differentially across two series bidirectional controlled switches in one inverter cell (step 1525) , or from two cell nodes, where each cell node is in a. different inverter cell and. the ac obtained differentially across two bidirectional controlled switches where one or more DC sources may interpose the two bidirectional controlled switches (step 1527) .

[0072] Alternatively, rather than starting at the first source series node, the last source series node is coupled to a cell series node for first cell and the emitter terminals of the cell' s two unidirectional controlled s-witches are coupled to the node N . For each remaining inverter cell, the cell series node for a cell is coupled to a preceding source series node, and each, unidirectional controlled switch' s emitter terminal is coupled to a respective cell node of a previous inverter cell. The collector terminal for each of the two remaining unidirectional controlled switches is coupled to the node P and. each emitter terminal is coupled to a respective cell node of the last inverter cell.

[0073] One or more m -level inverters may be cascaded together to form a combined output having m + levels. FIG. 16 shows three or more 5-level inverters inverter 1, inverter 2, inverter x coupled together in a series cascade. The symbology indicates inverter unidirectional controlled switches and bidirectional controlled switches used in the topology. The cascaded topology defines two output nodes A_C and B_c across the entire cascade. Each individual inverter inverter 1, inverter 2, inverter x used in a cascade has two

differential output nodes A,B .

[ 0074 ] The output across two cascaded 5-level (m ------ 5} inverters produces a 9-level cascaded output (A_C , B_C ) . If another 5-level inverter were cascaded, a 13-level inverter output would result. A cascade may be continued until a desired number of output levels are reached depending on the levels of the inverters used in the cascade. For example, a cascade of x 5-level inverters outputs (4x + lj levels.

[ 0075 ] FIG. 17 shows plots for two 5-level inverters inverter 1 A , B, _F inverter 2 A_{2 >} B₂ and a plot of their cascaded output A_C, B_C over one cycle (2π) . A 9-level (with x = 2; 4x + i = 9 ) output is obtained. The individual DC sources V in inverter 1 and inverter 2 add depending when their DC sources are switched {a a_{2 >} c _j,c_A,..) during the cycle. All of the DC sources used in one inverter are equal and each inverter' s DC sources are isolated from another inverter's DC sources. However, each individual inverter in a cascade may have DC source voltages that are different from another inverter in the cascade, and inverter levels can be different from one another .

[ 0076 ] The cascade topology reduces the voltage and current limitations of the power semiconductors used, and with increasing inverter levels, the output approaches a pure sinusoidal ac waveform exhibiting low distortion without requiring passive filtering components.

[0077] Embodiments are single phase multilevel inverter topologies using a full-bridge approach with bidirectional interconnections. Compared to prior art diode- clamped or flying-capacitor multilevel topologies, the required

split-rail DC sources are less, and the number of required power switches can be reduced by removing redundant switching states. Using asymmetrical DC sources, the output levels can be significantly increased. Embodiments can be applied to solar photovoltaics (micro-inverters) and energy storage (multiple battery cells) applications.

[0078] One or more embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are -within the scope of the following claims.

Claims

What is claimed is:

1, A single phase inverter topology method comprising:

selecting a number of desired inverter output levels m, where m≥5 , is an integer and an odd number;

determining a number of equal DC sources n , where

m-\

n⁼— '^"

coupling the n DC sources in series, wherein the source series has a first DC source that defines a positive node P and a last DC source that defines a negative node N ;

defining one or more source series nodes between each DC source in the source series wherein the source series node after the first DC source that defines a positive node P is the first 3 O LI∑ Ce series node and the source series node before the last DC source that defines a negative node N is the last source series node;

determining a number of unidirectional controlled switches ucs ;

assembling one or more inverter cells, wherein an inverter cell comprises six unidirectional controlled switches

ucs

and the Quotient of determines the number of inverter

6

cells required for the selected number of inverter output levels m ;

arranging four of the unidirectional controlled switches for each inverter cell as two bidirectional controlled switches ;

for each inverter cell, coupling two bidirectional controlled switches together forming a cell series node and coupling the other terminal of each bidirectional controlled switch to the emitter terminal of one unidirectional

controlled switch forming two cell nodes; coupling the cell series node of a cell to the first- source series node and coupling the collector terminals of the cell's two unidirectional controlled switches to the node P ; for each remaining inverter cell, coupling the cell series node to a following source series node and coupling each unidirectional controlled switch's collector terminal to a respective cell node of a previous inverter cell; and

coupling the emitter terminal for each of the two remaining unidirectional controlled switches to the node N and coupling the each collector terminal to a Γ^*Θ SpΘCfive cell node of the last inverter cell.

2. The method according to claim 1 wherein a bidirectional controlled switch comprises two unidirectional controlled switches coupled together, emitter-to-emitter.

3. The method according to claim 1 further comprising

outputting ac from one inverter cell, differentially across the two series bidirectional controlled switches from the two cell nodes .

4. The method according to claim 1 further comprising

outputting ac from two cell nodes, each cell node in a different inverter cell, the ac obtained differentially across two bidirect onal controlled s itches -wherein one or more DC sources may interpose the two b d rectional controlled switches .

5. The method according to claim 1 wherein determining a number of unidirectional controlled switches ucs comprises: for a reduced topology:

m-5

if m = 7,11,15,19,23, ucs = 2(m~l) 3; and

2 m-5

if m = 9, 13, 17, 21, 25,... , ucs = l{m-\ )

2

6. The method according to claim 1 wherein determining a number of unidirectional controlled switches ucs comprises: for a full topology:

if m≥5 , ucs 2{m -1)+ (m -5) .

7. The method according to claim 1 -wherein a unidirectional controlled switch is a power semiconductor with an

anti-parallel diode across its switching junction.

8. The method according to claim. 7 wherein the power

semiconductor is an Insulated-Gate Bipolar Transistor (IGBT) .

9. The method according to claim. 1 wherein a. DC source is a capacitor .

10. The method according to claim 1 wherein a DC source is a DC power supply.

11. The method according to claim 1 wherein a DC source is a battery .

12. A single phase inverter topology method comprising:

selecting a number of desired inverter output levels m , where m≥5 , is an integer and an odd number;

determining a number of equal DC sources n , where

m-\

n = coupling the n DC sources in series, wherein the source series has a first DC source that defines a positive node P and a last DC source that defines a negative node N ; defining one or more source series nodes between each DC source i the source series wherein the source series node after the first DC source that defines a positive node P is the first source series node and the source series node before the last DC source that defines a negative node N is the last source series node;

determining a number of unidirectional controlled switches ucs ;

assembling one or more inverter cells, wherein an inverter cell comprises six unidirectional controlled switches ucs

and the quotient of — determines the number of inverter cells required for the selected number of inverter output levels m ;

controlled switch forming two cell nodes;

coupling the cell series node of a first inverter cell to the last source series node and coupling the emitter terminal for each of the two remaining unidirectional controlled switches to the node N and coupling each collector terminal to a respective cell node of the first inverter cell;

for each remaining inverter cell, coupling the cell series node to a previous source series node and coupling each cell node to a unidirectional controlled switch's collector terminal of a following inverter cell; and

for the last inverter cell, coupling the collector terminals of the last cell's two unidirectional controlled switches to the node P ,

13. The method according to claim 12 wherein a bidirectional controlled switch comprises two unidirectional controlled switches coupled together, emitter-to-emitter.

14. The method according to claim 12 further comprising outputting ac from one inverter cell, differentially across the two series bidirectional controlled switches from the two cell nodes .

15. The method according to claim 12 further comprising outputting ac from two cell nodes, each cell node in a different inverter cell, the ac obtained differentially across two bidirectional controlled switches wherein one or more DC sources may interpose the two bidirectional controlled switches .

16. The method according to claim 12 wherein determining number of unidirectional controlled switches ucs comprise

for a reduced topology:

i f m = 5 , ucs = 2{m - 1) ; if «2 = 7,11,15,19,23,..., ucs = 2{m - 1)- - 3 ; and i f m = 9- 13.17, 21.25 ucs = 2{m - 1)- .

17. The method according to claim. 12 wherein determining a number of unidirectional controlled switches ucs comprises : for a full topology:

if m >5 , ucs = 2 m -1)+ (m - 5) .

18. The method according to claim 12 wherein a unidirectional controlled switch is a power semiconductor with an

anti-parallel diode across its switching junction.

19. The method according to claim 18 wherein the power semiconductor is an Insulated-Gate Bipolar Transistor (IGBT),

20. The method according to claim 12 wherein a DC source is a capacitor .

21. The method according to claim 12 wherein a DC source is a DC power supply.

22. The method according to claim 12 wherein a DC source is a battery .