WO2011082857A2

WO2011082857A2 - Production of a component

Info

Publication number: WO2011082857A2
Application number: PCT/EP2010/066447
Authority: WO
Inventors: Georg Bischopink; Christina Leinenbach
Original assignee: Robert Bosch Gmbh
Priority date: 2009-12-15
Filing date: 2010-10-29
Publication date: 2011-07-14
Also published as: WO2011082857A3; DE102009054659A1; TW201126649A

Abstract

The invention relates to a method for producing a component. The method comprises providing a first substrate (110) and forming a layer arrangement (120) on the first substrate (110), wherein the layer arrangement (120) has at least one component layer (123). The method further comprises forming circuit structures in the region of the component layer (123) and providing a second substrate (150, 151). The invention further relates to producing a bond between the second substrate (150, 151) and the component layer (123) and carrying out an etching process for separating at least one part of the first substrate (110).

Description

description

title

Production of a component

The present invention relates to a method for manufacturing a component.

State of the art

So-called power semiconductor components, which are designed for operation with high electrical currents and voltages, are used in different areas. This includes, for example, the automotive sector, with applications ranging from the combustion engine to the processing of electrical energy in hybrid vehicles. Other examples include the use in drive and automation technology, as well as in energy and communication technology. For such and future applications of power semiconductors, criteria such as miniaturization of the electrical systems, system integration, improvement of performance and reliability at higher operating temperatures as well as cost reduction are in the foreground.

In order to meet the increasing demands, the use of new materials is being pursued as an alternative to the currently used silicon. Suitable materials include, for example, silicon carbide and gallium nitride, which have advantages over silicon such as greater band gap, higher thermal conductivity, better electron mobility, and better high frequency characteristics. The disadvantage, however, is that the (defect-free) production of starting substrates or wafers from these materials is associated with a high production and cost. In the case of silicon carbide, adding to this is the fact that it is currently not possible to produce substrates with dimensions comparable to conventional silicon wafers (non-scalability). With regard to gallium nitride, there are attempts to grow this material heteroepitaxially on extraneous substrates of silicon carbide or sapphire. However, the use of such foreign substrates is associated with corresponding costs. One solution to this problem is the use of low-cost silicon substrates as a basis for the growth of gallium nitride. The main challenges here are the lattice mismatch of the materials as well as different thermal expansion coefficients. In order to overcome such problems, the generation of different layer sequences is proposed within the framework of the so-called "GaN-on-silicon" technology platform.

Power semiconductors, which are based on substrates which are not or poorly conductive (made of silicon), are generally constructed laterally, with corresponding connections (for example, source and drain) lying in one plane. However, this results in a relatively large (lateral) extension and disadvantages in terms of the performance of the device in question. In particular, the achievement of high breakdown voltages is associated with a large distance of the terminals. Furthermore, the possibilities of construction and connection techniques are limited in lateral components. A simultaneously poor heat conduction of the substrate also has a disadvantageous effect on the component

Reliability.

Cheaper in terms of spatial dimensions and performance, components with a vertical structure prove. The prerequisite for this is sufficient conductivity in the substrate material in order to form corresponding connections on opposite sides (upper or lower substrate side). Correspondingly suitable starting substrates (of gallium nitride or silicon carbide, for example), however, have the above-mentioned disadvantages. Optionally, vias may alternatively be provided in a silicon substrate, but this is associated with expensive manufacturing processes.

Such disadvantages can be solved by the use of vertically constructed thin-film power semiconductors, which are produced on conventional silicon substrates and subsequently applied to any conductive substrates, whereby an adaptation to the respective application is possible. This requires a separation of the power semiconductor layer composite from the silicon substrate ahead. One way to do this is to perform a backside dulling or polishing process, which, however, involves additional costs. Another method proposed for the transfer of gallium nitride layers of sapphire substrates consists of a so-called "laser lift-off process. In this case, the gallium nitride layer composite is bonded on the front side to a further substrate, and the gallium nitride layer composite is separated from the sapphire substrate by using a laser. Possible disadvantages of this method range from mechanically strained gallium nitride layers to possible cracks. The solution for working in numerous intermediate layers results in complex and costly manufacturing processes.

Disclosure of the invention

It is an object of the invention to specify an improved method for producing a component.

This object is achieved by a method according to claim 1. Further advantageous embodiments of the invention are specified in the dependent claims.

According to the invention, a method for producing a component is proposed. The method comprises providing a first substrate and forming a layer arrangement on the first substrate, wherein the layer arrangement has at least one component layer. The method further comprises forming circuit structures in the region of the device layer, and providing a second substrate. It is further provided to establish a connection between the second substrate and the component layer, and to carry out an etching process for separating at least a part of the first substrate.

In the method, the first substrate serves as a starting base on which the component or the corresponding circuit structures can be produced. Performing the etching process offers the possibility of separating the first substrate or a partial area of the first substrate from the component. In this respect, a cost-effective substrate for the first substrate, while For example, a silicon substrate can be used. The separation with the aid of an etching process can furthermore be carried out in a simple and cost-effective manner. Also, damage or risk to the component functionality can be avoided.

In a preferred embodiment, the layer arrangement formed on the first substrate at least additionally has a sacrificial layer. In this embodiment, carrying out the etching process results in a removal of the sacrificial layer and thus the desired separation of the component.

In a further preferred embodiment, the method further comprises implanting a filler material into the first substrate to form a sacrificial region in the first substrate. In this case, carrying out the etching process results in removal of the sacrificial region, as a result of which separation is likewise possible. By implanting the additional material into the first substrate, it is possible to avoid contamination of the component layer (possibly occurring when the layer arrangement or the component layer is formed). In a further preferred embodiment, the method further comprises

Forming a trench structure in the device layer prior to establishing the connection between the second substrate and the device layer. Furthermore, the second substrate is formed with an opening structure. Here, the trench structure and the opening structure are formed such that an etching medium used in the etching process through the opening structure and the

Trench structure can be moved to the first substrate. This embodiment, in which neither a sacrificial layer nor a sacrificial area is provided, can be carried out in a relatively simple and fast manner. By forming circuit patterns on the first substrate and

Further, transferring the same to the second substrate provides the method with high flexibility. The device layer and the circuit structures may first be generated in view of predetermined requirements on the first substrate. The second substrate, which may for example serve as the end substrate of the component, may be provided with an embodiment. which is adapted to the respective field of use of the component and satisfies (further) requirements of the component.

In a further preferred embodiment, the method produces a power semiconductor component. With regard to the device layer, a material suitable for producing power semiconductors is used. These include materials such as silicon, but also wide bandgap materials such as gallium nitride, silicon carbide, zinc selenide, and diamond. Such materials may have advantages over silicon such as higher thermal conductivity, better Electron mobility, and have better high frequency properties.

In another preferred embodiment, the method further comprises providing a third substrate, establishing a connection between the third substrate and the device layer after performing the etching process, and separating the second substrate from the device layer. Here, the second substrate acts as a transfer substrate, whereas the third substrate now serve as a final substrate and therefore may have an adapted to the particular application of the device configuration.

In a further preferred embodiment, a connection layer which comprises a metal, a metallic alloy, a solder, or a conductive adhesive is used to establish a connection between the second or third substrate with the component layer. Such materials have a high thermal conductivity, as a result of which a quantity of heat generated during operation of the relevant component can be reliably transferred to the respective final substrate. In this context, the second substrate or the third substrate according to a further preferred embodiment, a metallic material. In this way, the corresponding end substrate can provide a high thermal conductivity, whereby an amount of heat generated during operation of the component in question can be effectively dissipated.

The invention will be explained in more detail below with reference to FIGS. Show it: FIG. 1 shows a flow diagram of a method for producing a component;

FIGS. 2 to 8 show the production of a component, each in a schematic perspective view;

FIG. 9 shows a further flow chart of a method for producing a component;

Figures 10 and 1 1 are further perspective views for illustrating the manufacture of a device;

FIG. 12 shows a further flow chart of a method for producing a component; and

Figures 13 and 14 further perspective views for illustrating the manufacture of a device. FIG. 1 shows a flow chart of a method for producing a component. The device produced according to the method is, for example, a power semiconductor device which can be used in different areas. Possible applications include the automotive sector, use in drive and automation technology, as well as in energy and communication technology. In the production process, customary processes and materials can be used in semiconductor production or in the power semiconductor sector.

In the method, in a step 101, a layer arrangement or

Layer sequence formed on a first substrate provided, which serves as a starting substrate. Since the starting substrate acts merely as the starting base which is separated from the (later) device, a low cost and poorly conductive substrate, such as a common silicon wafer, may be used. The layer arrangement produced in step 101 comprises a sacrificial layer and a device layer. In addition to the two layers mentioned, the layer arrangement may optionally have further layers in order to promote the formation of individual layers. These include, for example, nucleation and gradient layers. The device layer has a greater distance from the first substrate than the sacrificial layer (which may optionally be arranged directly on the first substrate).

As a material for the sacrificial layer is, for example, germanium into consideration. Also alternative are other sacrificial materials, such as silicon-based

Sacrificial materials (for example silicon or silicon germanium), possible. The choice of the sacrificial material is dependent, in particular, on the material of the starting substrate and on an etching medium provided for removing the sacrificial layer. The component layer has a semiconductor material. With regard to the production of a power semiconductor, a suitably suitable material is chosen. These include, for example, materials with a relatively large bandgap such as gallium nitride (GaN), silicon carbide (SiC), zinc selenide (ZnSe) and diamond. Alternatively, silicon can also be used for the component layer. For the application of the layers conventional epitaxial growth methods such as chemical vapor deposition or CVD (chemical vapor deposition) or a physical vapor deposition or PVD (physical vapor deposition), but also other Depositi- onsverfahren such as sputtering process (for example a nucleation layer).

In a further step 102, circuit structures are formed in the region of the component layer. For this purpose, processes known from semiconductor technology can be carried out, which can be, for example, structuring methods, doping methods, as well as other methods for forming or producing further layers, for example insulation layers. The circuit structures may be formed in the form of laterally and / or vertically provided arrangements (relative to the substrate plane). In this case, it is also possible to produce a structure suitable for producing a vertical power semiconductor component. In a further step 103, the device layer (provided with circuit structures) is connected to a second substrate provided. The connection can take place via a corresponding adhesive or bonding layer. Further, in a step 104, an etching process is performed, thereby removing the sacrificial layer and, as a result, removing the first substrate from the sacrificial layer

Layer composite of the second substrate is separated. The removal of the sacrificial layer can be carried out in the context of a plasmaless dry chemical gas-phase etching process in which an etching medium suitable for etching the sacrificial layer is used. In the case of the above mentioned geranium as sacrificial material, this is, for example, a fluorine-based etching gas such as, for example, chlorine trifluoride (CIF3). The etching of the sacrificial layer for separating the first substrate can be carried out in a simple and cost-effective manner. There is also no risk of damage or impairment of the component or the associated circuit structures.

The second substrate may (already) be a final substrate which has a configuration adapted to the respective field of use of the component. With regard to a power semiconductor component, the second substrate (or a large part of the second substrate) may, for example, comprise a metallic material (and thus a high thermal conductivity) in order to dissipate a quantity of heat occurring during operation of the component with a high degree of effectiveness. In the same way, the connection layer used to connect the component layer and the second substrate may have a suitable material in order to reliably transmit a heat quantity that arises during operation of the component to the second substrate. Possible materials for the bonding layer are, for example, a metal, a metallic alloy, a solder, or a conductive adhesive. For such materials, a wafer bonding, soldering or bonding process may be used to bond the device layer and the second substrate (step 103).

Instead of using the second substrate as the final substrate of the device, the second substrate can also serve merely as a transfer substrate. In this case, the second substrate may, for example, comprise silicon, or be made, for example, from a cost-effective silicon, glass or polymer or plastic material. A connection between component layer and second Substrate (step 103) can in this case be produced via a (re) releasable adhesive layer, for example a thermally dissolvable lacquer layer.

In the case of the second substrate serving as the transfer substrate, moreover, as indicated in FIG. 1, after performing the etching process for removing the sacrificial layer (step 104), in a further step 105, the component layer is connected (via a connection layer) to a third substrate which now can act as a final substrate. With regard to details, reference is made to the above statements (second substrate as final substrate). Further, in a step 106, the second substrate is separated from the device layer, which may include, for example, performing a temperature step (to dissolve the adhesive layer between the device layer and the second substrate).

As already indicated, the method shown in FIG. 1 can be advantageously used to produce a vertical power semiconductor component. To further illustrate the following figures 2 to 8, the production of such a power semiconductor device or - chip according to a possible embodiment, each in a schematic perspective view.

At the beginning of the process, a starting substrate 110 is provided, which may be a conventional silicon wafer. Further, as shown in FIG. 2, a layer arrangement 120 is applied to the initial substrate 1 10 provided, it being possible to use conventional layer application methods such as, for example, sputtering, growth and vapor deposition methods.

The layers of the illustrated layer arrangement 120 are a gradient layer 121 applied to the starting substrate 110, a sacrificial layer 122 and a component layer 123. The sacrificial layer 122 has, for example, germanium. In this case, a gradient layer 121 of silicon germanium can be used to produce a crystallographic transition from the silicon starting substrate 110 to the germanium sacrificial layer 122. The germanium content can be adapted to the respective application. As the material for the device layer 123, which is formed with a thickness of, for example, several micrometers, gallium nitride is considered, for example. In such a case, further between the component layer 123 and the sacrificial layer 122, a further optional Zwischenbzw. Nucleation layer may be provided (not shown) to allow a good layer growth despite factors such as a lattice mismatch of the materials and different coefficients of thermal expansion. In particular, a nucleation layer of germanium nitride (Ge3N4) or aluminum nitride (AIN) is considered, whereby the heteroepitaxial

Growth of gallium nitride is favored on germanium, taking into account certain crystal orientations. Such nucleation layer may also favor the growth of other materials such as silicon or silicon germanium.

After the formation of the layer arrangement, circuit structures for the later power semiconductor component (or for a number of such components) are formed in the region of the device layer 123 (not shown). For this purpose, customary (photolithographic) patterning and etching processes, doping methods and others known from semiconductor manufacturing can be used

Procedures are performed. In this context, further layers can also be formed on or in the region of the device layer 123, which are attributed to the device layer 123, which is also referred to as "thin-film power semiconductor." These further layers of the device layer 123 include, for example, insulation, passivation layers. , Contact layers, etc. The circuit structures can be produced with a structure which is suitable for a vertical power semiconductor component In the context of the formation of circuit structures, also referred to as "front-end" fabrication, separation trenches 125 are additionally produced in the component layer 123, as illustrated in FIG. whereby the different components or chips (in one step) are separated from each other.

Subsequently, the composite of the starting substrate 110 and the layer arrangement 120 is bonded to a transfer substrate 150 as shown in FIG. Due to the separating trenches 125, the "thin-film chips" of the component layer 123 are arranged separately on the transfer substrate 150 Transfer substrate 150 is, for example, a low cost silicon or plastic substrate. This (temporary) bond may be made via a releasable bonding layer 140 of, for example, a thermally-releasable paint material disposed between the device layer 123 and the transfer substrate 150.

For the subsequent removal of the germanium sacrificial layer 122 and thus for the transfer or release of the (gallium nitride) components (or the corresponding circuit structures) onto the transfer substrate 150, a plasmaless dry chemical etching is carried out, as shown in FIG. 5, whereby the component layer 123 of the Starting substrate 1 10 is separated. In this method step, a suitable etching medium 160 is used, which can attack on the sacrificial layer 122 via lateral entry regions (wafer circumference) as indicated in FIG. 5 by arrows. Suitable etching medium 160 is, for example, chlorine trifluoride. In the course of the etching process, as shown in FIG. 5, the gradient layer 121 can also be removed.

In order to carry out the etching process more simply and, if necessary, faster, an alternative transfer substrate 151 can be used instead of the transfer substrate 150 shown in FIGS. 4 and 5, as shown in FIG.

The transfer substrate 151 has, in contrast to the transfer substrate 150, additional vertical opening structures 155 for passing through the etching medium 160. In this case, the opening structures 155 are adapted to the dimensions and the position of the separating trenches 125 of the component layer 123, or the opening structures 125 have sections adapted to the dimensions and the position of the separating trenches 125, for example channel feed lines. In this way, the etching medium 160 may (also) pass from the top of the transfer substrate 151 to the sacrificial layer 122, whereby the etching process can be accelerated.

Following the detachment of the starting substrate 110, the component layer 123 connected to the transfer substrate 150 or 151 is bonded to a final substrate 180, wherein the connection is established via a connection layer 170. This is illustrated in FIG. 7 for the case of the transfer substrate 151. For bonding, for example, a wafer bonding, soldering or bonding process can be performed. The end substrate 180 has a configuration corresponding to the desired application of the power semiconductor components. In particular, the end substrate 180 may be a metallic substrate in order to provide a high heat dissipation in the operation of the components and thus a high component reliability. Correspondingly, thermally conductive materials such as a metal, a metallic alloy, a solder or a conductive adhesive may be considered for the bonding layer 170.

When using the above-described nucleation layer of, for example, germanium nitride or aluminum nitride (which may be disposed between device layer 123 and sacrificial layer 122 before removing sacrificial layer 122), there is the possibility that this nucleation layer may still be present on the underside of device layer 123, and thus after fabrication the connection with the end substrate 180 between the device layer 123 and connection layer 170 is disposed (not shown). In an alternative embodiment, the nucleation layer may also be removed prior to bonding to the final substrate 180. For this purpose, for example, a wet or dry chemical etching process can be performed. It is also possible a mechanical removal, which can be done for example in the context of a polishing process such as CMP (chemical mechanical polishing).

Instead of providing the interconnection layer 170 in the form of a "large area" layer, the interconnect layer 170 may be patterned to provide separate sections (not shown) through corresponding insulative regions of isolation material 16. In this manner, portions of the interconnect layer 170 may be used as electrical contact areas to provide electrical contact between mating contact areas and locations of the end substrate 180 and the device layer 123. In such an embodiment, the end substrate 180 may also be provided with corresponding pads on the exposed underside (not shown).

Following the establishment of the connection with the end substrate 180, a detachment of the transfer substrate 150 or 151 takes place, as shown in FIG. For this purpose, for example, a temperature step can be carried out, by means of which the connection layer 140 can be dissolved or removed. By detachment of the transfer substrate 150, 151, the upper side of the component layer 123 and, thus, contact points (not shown) provided on this side (if appropriate) can be exposed. These upper-side contact points may have a relatively large distance from the above-described lower-side contact points of the end substrate 180, as a result of which the relevant components may have high breakdown voltages. In addition to the described method steps, further method steps can be performed in order to complete or complete the production of the power semiconductor components. In particular, a singulation method is contemplated to provide separate power semiconductor devices. For this purpose, for example, a mechanical sawing process can be carried out in which a saw blade is the individual

Components (according to the pre-structuring by the separation trenches 125) separated from each other. Alternatively, it is possible to perform a so-called "laser cutting", in which a focused laser beam is used.

With regard to the component layer 123, in addition to the abovementioned gallium nitride, it is also possible to use a further material suitable for the production of power semiconductors. A possible example is silicon carbide. In such a case, the growth process of the device layer 123 can be adapted accordingly, whereby an (optional) intermediate layer (nucleation layer) can again be used. Also, due to a possible high growth temperature of silicon carbide optionally a silicon germanium alloy instead of germanium as waxing and sacrificial layer 122 may be used (with an additional gradient layer 121 may be omitted).

In addition, it is alternatively possible to use only two substrates instead of three substrates. This means that no transfer substrate is used, but rather that the corresponding wafer layer composite is bonded to a final substrate after the production of circuit structures. Such an approach can, for example, with reference to the figures 3 to 5 are illustrated. Here, the substrate 150 is not a transfer but a final substrate, which may have a configuration and properties corresponding to the substrate 180. In a corresponding manner, the layer 140 may be formed comparable to the connection layer 170. With regard to the component layer 123, the corresponding (vertical)

Circuit structures are preferably designed such that an electrical contacting of contact points on the (exposed after the removal of the sacrificial layer 122 and in Figure 5 downward) side of the device layer 123 is possible. Associated upper-side contact points may in this case be provided on the substrate 150.

The following figures explain further methods for producing a component or a power semiconductor component which are comparable or similar to the methods described above. With regard to details of matching method steps and features, reference is therefore made to the above statements.

FIG. 9 shows a further flowchart of a method for producing a (power semiconductor) component. In this method, a filler material is implanted in a first substrate provided in a step 201, in order to form a sacrificial region serving as a sacrificial layer in the first substrate. The first substrate may again be a low-cost substrate, in particular a silicon wafer. The additive material implanted in a defined depth of the first substrate is, for example, germanium, or alternatively another suitable additive material.

In a further step 202, a layer arrangement is formed on the first substrate. The layer arrangement comprises a component layer, for example of gallium nitride or another (power) semiconductor material. In addition to the component layer, the layer arrangement may comprise further layers, in particular a nucleation layer.

In a further step 203, circuit structures are formed in the region of the component layer. Further, in a step 204, the device layer is connected to a second provided substrate using a suitable interconnect layer. It can be at the second substrate be a final substrate, or alternatively a transfer substrate. This determines in particular (as described above) the choice of material of the second substrate and the connection layer.

Subsequently, in a step 205, an etching process (for example a dry-chemical gas-phase etching process) is carried out in which an etching medium suitable for etching the sacrificial region of the first substrate (for example a fluorine-based etching gas such as, for example, chlorine trifluoride) is used. In the course of the etching process, the sacrificial region (and optionally further regions of the first substrate) is removed, as a result of which the first substrate or a part thereof is separated from the layer composite of the second substrate.

In the event that the second substrate serves as a transfer substrate, as indicated in FIG. 9, after the etching process has been carried out, the component layer is connected in a further step 206 to a third substrate, which can now function as a final substrate. Further, in a step 207, the second substrate is separated from the device layer.

To further illustrate the method of FIG. 9, FIGS. 10 and 11 show individual stages of the method, each in a schematic perspective view.

FIG. 10 shows a starting substrate 110 after carrying out an implantation process for introducing a sacrificial material and after forming a device layer 123 on the starting substrate 1 10. The starting substrate 110, which is, for example, a silicon wafer, is due to of the introduced into a given substrate depth additional material (for example, germanium) two areas 1 1 1, 1 13, which are separated from one another by the additional material formed and serving as a sacrificial layer sacrificial area. The component layer 123, which, for example, has gallium nitride, is located on top of the upper substrate region 13, as shown in FIG. 10. Optionally, an intermediate or nucleation layer of, for example germanium nitride or not shown, may be provided between the device layer 123 and the upper substrate region 13 Aluminum nitride be provided. The formation of a sacrificial region 1 12 in a given substrate depth offers the advantage of avoiding contamination of the component layer 123 during its formation. Deposition processes for depositing the device layer 123 (eg, CVD or PVD processes) may be associated with relatively high temperatures, resulting in vaporization of a sacrificial material

(For example, germanium) may result in contamination of the device layer 123. By introducing the additional material at a defined depth in the starting substrate 110, such an effect can be avoided.

Depending on the temperature of the method used to form the device layer 123, mixing of the implanted material with the material of the starting substrate 110 may take place, which is also referred to as "interdiffusion." In the case of introducing germanium into a silicon wafer 110 Therefore, a silicon germanium sacrificial area 1 12 or a

Silicon germanium layer 1 12 form. Such a layer 1 12 may also extend (contrary to the representation in FIGS. 10 and 11) as far as the upper side of the starting substrate 110, as a result of which there is no upper subregion 13. Without an interdiffusion, a sacrificial area 112 of essentially germanium can be present.

Following the method steps described with reference to FIG. 10, further method steps, such as the formation of circuit structures for the or a number of (vertical power semiconductor) components, and, if appropriate, the formation of singulation trenches 125, are carried out.

Also, as shown in Figure 1 1, the composite of the starting substrate 1 10 and the device layer 123 are bonded to a low-cost transfer substrate 151, which may have adapted to the separating trenches 125 opening structures 155 to facilitate a subsequent etching process. In the bonding method, a releasable connection layer 140

(For example, a thermally dissolvable paint material) can be used.

Subsequently, as further illustrated in FIG. 11, an etching process is carried out in the course of which an etching medium 160 (for example chlorotrifluoride) removes the sacrificial region 12, whereby the starting substrate 110 or its lower substrate region 11 is removed. In this case, the etching medium 160 both attack via lateral entry regions (wafer circumference) at the sacrificial region 1 12, as well as, due to the opening structures 155 and the separation trenches 125, proceed from the upper side of the transfer substrate 151 to the sacrificial region 1 12. For this purpose, the separating trenches 125 are formed not only in the region of the component layer 123, but (at least) also in the region of the upper substrate region 13 (if present).

The etching process can furthermore be carried out or adapted so that the remaining substrate region 13 (if present) is also removed below the component layer 123. For this purpose, etching parameters, such as a temperature, a pressure, a concentration of the etching medium 160, etc., may be changed during the etching process and, if appropriate, a plasma may be added in order to make the etching process more aggressive. Furthermore, an optionally provided nucleation layer can also be removed from the component layer 123 in this etching process.

As with the method shown in FIGS. 2 to 8, it is possible to apply the arrangement comprising the transfer substrate 151 and the component layer 123 to a final substrate 180 after the etching process (corresponding to FIG. 7) and to detach the transfer substrate 151 (corresponding to FIG. 8). Alternatively, it is possible that the substrate 151 already functions as a final substrate, whereby such method steps can be dispensed with. Instead of the substrate 151 shown in FIG. 11 with the opening structures 155, the substrate 150 of FIG. 5 can also be used without such opening structures 155. For further details, for example, with regard to the provision or exposure of contact points and areas, the implementation of a dicing process, etc., reference is made to the above statements.

FIG. 12 shows a further flow chart of a method for producing a (power semiconductor) component. In this method, neither a sacrificial layer nor a sacrificial area is provided, whereby the method can be carried out in a relatively simple and fast manner.

In this method, in a step 301, a layer arrangement is formed on a first provided substrate, which has at least one component layer. The first substrate may be a low cost silicon Wafer, and the device layer may comprise a (performance) semiconductor material such as gallium nitride. Optionally, in addition, a nucleation layer may be provided to improve the application of the device layer.

In a further step 302, circuit structures are formed in the region of the component layer. Subsequent to or during the formation of the circuit structures, a trench structure is formed in the device layer in a step 303. Following this, the component layer is connected to a second substrate, which serves as a final substrate, or alternatively as a transfer substrate. The second substrate has an opening structure which is adapted to the trench structure or has sections adapted to the trench structure (eg channel feed lines).

Subsequently, in a step 305, an etching process (for example a dry chemical gas phase etching process) is carried out in which an etching medium suitable for etching material of the first substrate (for example a fluorine-based etching gas such as, for example, chlorine trifluoride) is used. With regard to the etching process, the aforementioned trench structure in the device layer and the opening structure in the second substrate are formed such that the etching medium can be led to the first substrate. As a result, an area of the first substrate below the component layer can be removed or an undercutting of the component layer take place, as a result of which (at least) a component (connected to the second substrate) is released.

In the event that the second substrate serves as a transfer substrate, as indicated in FIG. 9, after the etching process has been carried out, the component layer is connected in a further step 306 to a third substrate, which can now function as a final substrate. Further, in a step 307, the second substrate is separated from the device layer.

To further illustrate the method of FIG. 12, FIGS. 13 and 14 show individual stages of the method, each in a schematic perspective view. FIG. 13 shows a starting substrate 110 (for example a silicon wafer) after application of a component layer 123 (for example made of gallium nitride) and formation of circuit structures and a trench structure in the form of isolation trenches 125. Optionally, between the device layer 123 and the substrate 1 10 a not shown intermediate or

Nucleation layer may be provided, for example, germanium nitride or aluminum nitride. Contrary to the representation in FIG. 13, the separating trenches 125 can also extend into the starting substrate 110.

Subsequently, as shown in FIG. 14, the composite of the starting substrate 110 and the component layer 123 can be bonded to a low-cost transfer substrate 151, which has opening structures 155 adapted to the separating trenches 125. In the bonding method, a releasable bonding layer 140 (of, for example, a thermally-releasable paint material) may be used.

Subsequently, as shown in FIG. 14, an etching process is carried out, wherein a corresponding etching medium 160 (for example chlorine trifluoride) can reach regions of the starting substrate 1 10 below the device layer 123, in particular via the opening structures 155 and the separating trenches 125, so that starting from the Separation trenches 125 a substantially isotropic etching of the starting substrate 1 10 can take place. As soon as the etching fronts emerging from two adjacent separating trenches 125 or adjacent trench sections meet, the component composite consisting of the component layer 123 and the substrate 151 is detached from the substrate 110.

In the etching process, as indicated in FIG. 14, optionally a part of the substrate 110 may remain in the form of a remaining region 15 below the component layer 123. This residual region 15 can be removed by continuing or adjusting the etching process (for example by changing etching parameters, connecting a plasma). Also, an optional nucleation layer may be removed from the device layer 123. Thereafter, according to the method of Figures 2 to 8, the

Arrangement of the transfer substrate 151 and the device layer 123 on a final substrate 180 is applied (corresponding to FIG. 7) and the transfer substrate 151 is detached (corresponding to FIG. 8). Alternatively, there is the possibility that the substrate 151 already acts as a final substrate, as a result of which such method steps can be dispensed with. For further details, for example with regard to the provision or exposure of contact points and areas, the implementation of a dicing process, etc., reference is made to the above statements.

The embodiments explained with reference to the figures represent preferred or exemplary embodiments of the invention. In addition to the described and illustrated embodiments, further embodiments are conceivable which may comprise further modifications or combinations of features. In particular, other materials can be used instead of the materials mentioned. For example, instead of chlorotrifluoride, other fluorine-based etching media such as bromine trifluoride (BrF3), xenon difluoride (XeF2) and sulfur hexafluoride (SF6) may be used. In addition, not only power semiconductor components, but also other components or semiconductor components can be produced with the described concepts. For example, light emitting diodes (LED, light emitting diode) and smart cards are possible.

Claims

claims

1 . Method for producing a component, characterized by the method steps:

Providing a first substrate (110),

Forming a layer arrangement (120) on the first substrate (1 10), the layer arrangement (120) having at least one component layer (123),

Forming circuit structures in the region of the device layer (123),

Providing a second substrate (150, 151),

Establishing a connection between the second substrate (150, 151) and the device layer (123), and

Performing an etching process to sever at least a portion of the first substrate (110).

2. The method of claim 1, wherein the layer assembly formed on the first substrate comprises at least one additional sacrificial layer, and wherein performing the etching process results in removal of the sacrificial layer.

3. The method of claim 1, further comprising:

Implanting an additive material into the first substrate (1 10) to form a sacrificial region (1 12) in the first substrate (1 10), wherein performing the etching process results in removal of the sacrificial region (1 12).

The method of claim 1, further comprising:

Forming a trench structure (125) in the device layer (123) prior to establishing the connection between the second substrate (151) and the device layer (123), and

Providing the second substrate (151) with an opening structure (155), wherein the trench structure (125) and the opening structure (155) are formed such that an etching medium (160) used in the etching process passes through the opening structure (155) and the trench structure (FIG. 125) to the first substrate (1 10) can be moved.

The method of any one of the preceding claims, wherein a power semiconductor device is fabricated, and wherein the device layer (123) comprises one of the following materials:

Silicon, gallium nitride, silicon carbide, zinc selenide, diamond.

Method according to one of the preceding claims, further comprising:

Providing a third substrate (180),

Establishing a connection between the third substrate (180) and the device layer (123) after performing the etching process, and

Separating the second substrate (150, 151) from the device layer (123).

Method according to one of the preceding claims, wherein for establishing a connection between the second or third substrate with the component layer (123) a connection layer (170) is used, wherein the connection layer (170) of one of the following materials has:

Metal, metallic alloy, solder, conductive adhesive.

8. The method according to any one of the preceding claims, wherein the second substrate or the third substrate (180) comprises a metallic material.

9. The method according to any one of the preceding claims, wherein the second substrate (150, 151) and the device layer (123) via a thermally dissolvable paint material (140) are connected.

10. The method of claim 1, wherein the etching process is a dry chemical etching process.