WO2011082834A1 - Correction d'erreurs - Google Patents

Correction d'erreurs Download PDF

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Publication number
WO2011082834A1
WO2011082834A1 PCT/EP2010/050230 EP2010050230W WO2011082834A1 WO 2011082834 A1 WO2011082834 A1 WO 2011082834A1 EP 2010050230 W EP2010050230 W EP 2010050230W WO 2011082834 A1 WO2011082834 A1 WO 2011082834A1
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WO
WIPO (PCT)
Prior art keywords
data
error correction
vertical error
plural
vertical
Prior art date
Application number
PCT/EP2010/050230
Other languages
English (en)
Inventor
Imed Bouazizi
Lukasz Kondrad
Original Assignee
Nokia Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corporation filed Critical Nokia Corporation
Priority to PCT/EP2010/050230 priority Critical patent/WO2011082834A1/fr
Publication of WO2011082834A1 publication Critical patent/WO2011082834A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0066—Parallel concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0065—Serial concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/007—Unequal error protection

Definitions

  • This invention relates to methods and apparatuses for enabling error correction of data portions.
  • this specification describes a method comprising: receiving plural data portions; forming plural data frames, each data frame comprising one of the plural data portions conjoined with horizontal error correction data generated on the basis of the one of the plural data portions; and generating at least one vertical error correction portion on the basis of the data portions by creating plural elements of vertical error correction data, each element of error correction data being generated on the basis of corresponding elements in each of the plural data portions, each vertical error correction portion comprising plural error correction elements.
  • this specification describes apparatus comprising: at least one processor; and memory, the memory having stored thereon computer readable code, which when executed by the at least one processor causes the at least one processor to: receive plural data portions; form plural data frames, each data frame comprising one of the plural data portions conjoined with horizontal error correction data generated on the basis of the one of the plural data portion; and generate at least one vertical error correction portion on the basis of the plural data portions by creating plural elements of vertical error correction data, each element of error correction data being generated on the basis of corresponding elements in each of the plural data portions, each vertical error correction portion comprising plural error correction elements.
  • this specification describes a method comprising: receiving plural data frames, each data frame comprising a data portion and horizontal error correction data; receiving at least one vertical error correction portion, each vertical error correction portion comprising plural elements; for each of the plural data frames, horizontally decoding the data portion in conjunction with the horizontal error correction data; and vertically decoding the horizontally decoded data portions of the plural data frames in conjunction with the at least one vertical error correction portion by using each element of the at least one vertical error correction portion to decode corresponding elements in the plural horizontally decoded data portions.
  • this specification describes apparatus comprising: at least one processor; and memory, the memory having stored thereon computer readable code, which when executed by the at least one processor causes the at least one
  • processors to: receive plural data frames, each data frame comprising a data portion and horizontal error correction data; receive at least one vertical error correction portion, each vertical error correction portion comprising plural elements; for each of the plural data frames, horizontally decode the data portion in conjunction with the horizontal error correction data; and vertically decode the horizontally decoded data portions of the plural data frames in conjunction with the at least one vertical error correction portion by using each element of the at least one vertical error correction portion to decode corresponding elements in the plural horizontally decoded data portions.
  • this specification describes computer readable code, optionally stored on a non-transitory computer readable medium, which when executed by computer apparatus causes the computer apparatus to perform the method of either of the first or third aspects described above.
  • apparatus comprising: means for receiving plural data portions; means for forming plural data frames, each data frame comprising one of the plural data portions conjoined with horizontal error correction data generated on the basis of the one of the plural data portions; and means for generating at least one vertical error correction portion on the basis of the data portions by creating plural elements of vertical error correction data, each element of error correction data being generated on the basis of corresponding elements in each of the plural data portions, each vertical error correction portion comprising plural error correction elements.
  • this specification also describes apparatus comprising: means for receiving plural data frames, each data frame comprising a data portion and horizontal error correction data; means for receiving at least one vertical error correction portion, each vertical error correction portion comprising plural elements; means for horizontally decoding, for each of the plural data frames, the data portion in conjunction with the horizontal error correction data; and means for vertically decoding the horizontally decoded data portions of the plural data frames in conjunction with the at least one vertical error correction portion by using each element of the at least one vertical error correction portion to decode
  • padding data may be appended to one or more of the plural data portions so as to ensure that each of the data portions is of an equal length. This may occur at any time prior to generating the at least one vertical error correction portion.
  • the generated at least one vertical error correction portions is of a length equal to the length of each of the plural data portions.
  • Exemplary embodiments describe computer readable code, optionally stored on a non-transitory computer readable medium, which when executed by computer apparatus causes the computer apparatus to perform described methods.
  • Figure 1 is a simplified schematic overview of a communication system in which exemplary embodiments of the invention can be implemented
  • FIG. 2 is a schematic view of broadcast apparatus in which exemplary
  • Figure 3 is a flow chart depicting an exemplary operation according to the present invention of the broadcast apparatus of Figure 2;
  • Figure 4 is an exemplary schematic depiction of the format of data throughout the operation depicted in Figure 3;
  • Figure 5A illustrates a first signalling method according to exemplary embodiments of the invention
  • Figure 5B illustrates a second signalling method according to exemplary
  • Figure 6 is a schematic view of receiver apparatus according to exemplary embodiments of the invention.
  • Figure 7 is a flow chart depicting an exemplary operation performed by the receiver apparatus of Figure 6;
  • Figure 8A is a schematic illustration of a horizontal step of an exemplary decoding operation
  • Figure 8B is a schematic illustration of a vertical step of an exemplary decoding operation.
  • Figure 9 is a simplified schematic view of an exemplary decoder that can be used to perform the decoding steps of the operation of Figure 7. Detailed Description of Embodiments
  • Figure 1 shows a simplified schematic overview of parts of a communication system.
  • the system comprises broadcaster apparatus 10, which receives logical data streams from one or more service providers 11, 12.
  • the broadcast apparatus 10 operates on the data streams and then broadcasts or multicasts the resulting data via intermediary apparatus 13, such as television masts, to one or more receiver apparatuses 14 which are able to reproduce the data streams for consumption by one or more users.
  • Data can be lost or corrupted during transmission.
  • Figure 2 is a schematic view of apparatus 10 according to exemplary embodiments of the invention. More particularly Figure 2 is a schematic view of broadcast apparatus 10 according to exemplary embodiments of the invention.
  • the broadcast apparatus 10 comprises a digital broadcasting module 20.
  • an input preprocessor 21 is also included.
  • the input pre-processor module 21 is not part of the digital broadcasting module 20.
  • the input pre-processor 21 could operate as a service splitter, a scheduler or a de-multiplexer.
  • the digital broadcasting module 20 comprises an input processing module 22, a bit interleaving and coding modulation module 23, a frame builder 24 and a modulator 25. An output of the digital broadcasting module 20 is broadcast via an antenna 26.
  • the operation of various components of the digital broadcasting module 20 will be discussed below. The below methods and apparatuses are discussed within a Digital Video Broadcast Second Generation Terrestrial (DVB-T2) context, the standard for which is described in ETSI EN 302 755 (version 1.1.1 2009-09).
  • the input to the digital broadcasting module 20 consists of one or more logical data streams received from the one or more service providers 11, 12.
  • Each logical data stream may be carried by a respective physical layer pipe (PLP).
  • PLP physical layer pipe
  • PSI program specific information
  • SI service information
  • a PLP is a fully transparent data pipe which generally enables data of a structure with freely selectable, but PLP-specific physical parameters, to be transported.
  • the capacity and also the service robustness may be adjusted according to particular requirements, depending on the type of receiver apparatus 14 and/or its usage environment.
  • Figure 3 is a flow chart depicting an exemplary operation of the digital broadcasting module 20.
  • Figure 4 is schematic showing the format of the incoming data of one logical data stream as it is processed by the digital
  • step SI of the flow chart of Figure 3 the input processing module 22 receives a first portion of a logical data stream that is to be broadcast.
  • step S2 the input processing module 22 slices the first portion of the data stream to form a data segment 40 (see Figure 4).
  • a data segment 40 may also be referred to as a "data portion”.
  • the input processing module 22 operates separately on the contents of each incoming PLP.
  • Each data segment 40 is comprised of a
  • Figure 4 shows plural data segments 40 formed from sequential portions of the incoming logical data stream. The flow chart of Figure 3 handles each of the plural data segments 40 separately as they are formed by the input processing module 22.
  • a BB data frame 41 comprises a BB header 41-1 and a data segment (or field) 40.
  • the size of the data field 40 in BB data frame 41 may be fixed for a given PLP.
  • the size of the data field 40 may depend on the forward error correction code rate which is later applied on the BB data frame 41.
  • step S4 it is determined whether the data within the BB data frame 41 requires additional forward error correction protection against transmission errors. It may be more important that some components of a service to be correctly reproduced than it is for other components to be correctly reproduced. For example, it may be more important for audio and base layer video components of a scalable video coding (SVC) stream to be correctly reproduced than it is for enhancement layer video to be correctly reproduced. Thus, in step S4, it may be determined that BB data frames 41 comprising data segments 40 relating to important components require additional forward error correction protection and that BB data frames 41 comprising data segments 40 relating to less important components do not require additional forward error correction protection. It will be understood that a different criterion for determining whether additional forward error correction protection is required may instead be used.
  • SVC scalable video coding
  • step S4 If, in step S4, it is determined that the BB data frame 41 does not require additional forward error correction protection, the operation proceeds to steps S5 and S6. Steps S5 and S6 are described in some detail below, and so a discussion of these steps is not provided at this point.
  • step S7 the input processing module 22 arranges the BB data frame 41 in a data structure 42.
  • the data structure 42 comprises plural rows of BB data frames 41.
  • step S8 it is determined whether the data structure 42 is complete. This may be dependent on the current size of the data structure 42. This is discussed in greater detail later, and so a discussion of this step is not provided at this point. If, in step S8, the data structure 42 is found not to be complete, the operation returns to step SI .
  • FIG. 4 shows a complete data structure 42.
  • Each of the BB data frames 41 that is found in step S4 to require additional forward error correction protection is provided in a different row 42-1 of the data structure 42.
  • the BB data frame 41 that includes the data segment 40 relating to the first portion of the data stream is arranged in the first row 42- la of the data structure 42.
  • the BB data frame 41 that includes the data segment 40 relating to a latest portion of the data stream is placed in the last row 42-lb. .
  • the number of BB data frames 41 that constitute the data structure 42 may be dependent on the decoding process carried out by the receiver apparatus 14. For example, there may be a maximum allowable decoding delay. Thus, the number of BB data frames 41 arranged in the data structure 42 may be constrained by the duration of the data stream data that is contained within the data structure 42. For example, if the maximum allowed decoding delay of a receiver is 1 second, the number of BB data frames 41 must be such that the duration of data stream contained within the BB data frames 41 does not exceed 1 second.
  • the data structure 42 is found to be complete, the operation proceed to step S9.
  • step S9 the input processing module 22 generates one or more repair segments 43.
  • a repair segment may also be termed a "vertical error correction portion".
  • the repair segments 43 are generated based on the data segments 40 of the BB data frames 41 within the data structure 42.
  • Each of the generated repair segments 43 comprises plural bits of parity data 43-1.
  • the number of parity data bits 43-1 in the repair segments 43 is the same as the number of data bits in the data segment 40 of each of the BB data frames 41 in the data structure 42.
  • the repair segments 43 may be formed by performing a single forward error correction encoding operation on data bits 40 which are in the same position in their respective BB data frame 41. As such, the first parity bits 43- la in each of the repair segments 43 are generated based on the first data bits 40- la in the data field 40 of each of the BB data frames 41 in the data structure 42.
  • the forward error correction encoding operation used to generate the repair segments 43 may include block erasure encoding operations such as Reed-Solomon or Bose-Chaudhuri-Hocquenghem multiple error correction binary block code (BCH) operations.
  • BCH Bose-Chaudhuri-Hocquenghem multiple error correction binary block code
  • the forward error correction encoding operation used to generate the repair segments 43 may be a bit error correction code such as a simple parity check code.
  • the number of repair segments 43 that are generated may be dependent on the number of the rows 42-1 of BB data frames 41 in the data structure 42 and on the code rate of the forward error correction encoding operation.
  • the input processing module 22 forms a BB repair frame 44 from each of the generated repair segments 43 by adjoining a BB-header 44-1.
  • the newly formed BB repair frames 44 are appended to the data structure 42.
  • the data structure 42 having the BB repair frames 44 appended thereto is known as a "source block" 45.
  • the repair segments 43 are only effective to correct post-transmission errors in the data segments 40 if, during decoding, they are in the position in which they were generated.
  • the BB repair frames 44 are positioned in the source block 45 in the order in which their corresponding repair segments 43 were generated.
  • the input processing module 22 provides each of the BB data frames 41 and each of the BB repair frames 41, 44 in the source block 45 with signalling data (not shown).
  • the signalling data allows a receiver apparatus 14 to reproduce the source block 45 and thereby to correct transmission errors in the data segments 40.
  • the signalling data may include an indication of the data type within the BB data/repair frame 41, 44, i.e. whether the BB data/repair frame 41, 44 contains a data field or a repair segment.
  • the signalling data may include an indication as to whether the BB data/repair frame 41, 44 is the last of its type in a source block.
  • the signalling data may also include an indication of the source block from which the BB data/repair frame 41, 44 originates.
  • the signalling data may include an indication of the original position of BB data/repair frame 41, 44 within the source block.
  • the BB data/repair frames 41, 44 are passed to the bit interleaving and coding modulation module 23 where, in step S5, parity data 46, 47 for each of the BB data/repair frames 41, 44 is generated and appended to its corresponding BB data/repair frame 41, 44.
  • the parity data 46, 47 is generated by first implementing an outer encoding step.
  • the outer encoding step may comprise performing a BCH encoding operation on the bits in the BB data/repair frame 41, 44, including those bits that make up the BB header 41-1, 44-1.
  • an inner encoding step is performed.
  • the inner encoding step may comprise performing a low density parity check (LDPC) encoding operation on the bits in the BB data/repair frame 41, 44 including those in the BB header 41-1, 44-1.
  • LDPC low density parity check
  • the generated parity data 46, 47 is appended to the BB data/repair frame 41, 44.
  • BCH parity data 46 which was generated during the outer encoding step, is appended directly after the BB-frame 41, 44.
  • LPDC parity data 47 which was generated during the inner encoding step, is appended after the BCH parity data 46.
  • a BB data/repair frame 41, 44 which has BCH and LPDC parity data appended to it may be known as an FEC frame 48.
  • those FEC frames 48 which include data segments 40 are labelled 48-1 (and include parallel line hatching) and those FEC frames 48 which include repair segments 43 are labelled 48-2 (and include cross-hatching).
  • BB data frames 41 that, in step S4, are determined not to require additional forward error correction protection are passed directly to the bit interleaving and coding modulation module 23 where a FEC frame 48-1 is formed from the BB data frame 41 in the same manner as described above.
  • step S6 after formation of the FEC frame 48, the FEC frame 48 is passed to the frame builder 24.
  • the frame builder 24 is configured to arrange the link layer frame 48 in a physical layer frame 49.
  • a physical layer frame 49 may comprise a plurality of FEC frames 48, a PI symbol 49-1 and one or more P2 symbols 49-2.
  • Each physical layer frame 49 includes FEC frames 48 from one or more source block 45.
  • Link layer FEC frames 48 corresponding to a single source block 45 may be spread over a plurality of different physical layer frames 49.
  • Figure 4 shows four physical layer frames 49.
  • the FEC frames 48 from the source block 45 are distributed over four physical layer frames 49.
  • the FEC Frames 48-2 carrying a repair segment 43 are all located in a single physical layer frame 49. However, this may not be the case. Instead, one FEC Frame 48-2 carrying a repair segment 43 may be in one physical layer frame 49 and the other two may be in a different physical layer frame 49.
  • step SI in which a next portion of an incoming data stream is received.
  • the physical layer frames 49 are modulated using the modulator 25, and are then transmitted to one or more receivers 14 via the antenna 26. These operations are not shown on Figure 3.
  • the modulator 25 may modulate the physical layer frames 49 using orthogonal frequency division multiplexing (OFDM). Alternatively, another type of modulation may be used.
  • the BB data/repair frames 41, 44 of a source block are provided with signalling data (see step S6 of Figure 3). According to some exemplary embodiments, the signalling data is provided in the BB-header 41-1, 44-1. According to other exemplary embodiments, the signalling data is provided within padding (not shown) appended to the data/repair segment 40, 43 of the BB data/repair frame 41, 44.
  • Figure 5A illustrates a signalling method according to exemplary embodiments wherein the signalling data is provided in the BB-header 41-1, 44-1.
  • Figure 5B illustrates a signalling method in according to exemplary embodiments wherein signalling data is provided within padding data appended to the data/repair segment 40, 43 of the BB data/repair frame 41, 44.
  • the BB header may comprise six different fields, which are shown in Figure 5A. These fields are: MATYPE 51-1, which is two bytes in size; UPL 51-2, which is two bytes in size; DFL 51-3, which is two bytes in size; SYNC 51-4, which is one byte in size; SYNCD 51-5, which is two bytes in size; and CRC-8 MODE 51-6, which is one byte in size.
  • MATYPE 51-1 which is two bytes in size
  • UPL 51-2 which is two bytes in size
  • DFL 51-3 which is two bytes in size
  • SYNC 51-4 which is one byte in size
  • SYNCD 51-5 which is two bytes in size
  • CRC-8 MODE 51-6 which is one byte in size.
  • the UPL 51-2, SYNC 51-4, and SYNCD, 51-5 fields are proposed to be reserved for future use. Thus, five bytes are available.
  • the signalling data is provided using the available three bytes of the UPL 51-2 and SYNC 51-4 fields.
  • the signalling data is provided using the available three bytes of the SYNCD 51-5 and SYNC 51-4 fields. Table 1 below shows how the signalling data is distributed over the three bytes. Field Size
  • the DATA_TYPE field uses one bit, and indicates whether the segment 40, 43 within the BB data/repair frame 41, 44 is a data (or source) segment 40, or a FEC (or repair) segment.
  • a '1 ' in this field may indicate that the segment 40, 43 contained in the BB data/repair frame 41, 44 is a data segment 40
  • a '0' in this field may indicate that the segment 40, 43 contained in the BB data/repair frame 41, 44 is a repair segment 43.
  • '1 ' may indicate a repair segment 43 and '0' may indicate a data segment 40.
  • the LAST_SYMBOL field uses one bit and indicates whether the BB data/repair frame 41, 44 is the last one of its type (i.e. a BB data frame or a BB repair frame), of its source block 45. For example, a '1 ' may indicate that the BB data/repair frame 41, 44 is the last of its type, and a '0' may indicate that the BB data/repair frame 41, 44 is not the last of its type, or vice versa.
  • This field is used by the receiver apparatus 14 in conjunction with DATA_TYPE field.
  • the RESERVED_1 field contains 6 bits which are reserved for future use.
  • the RESERVED_1 field may be used to identify the type of FEC code used to generate the repair segments, so that the decoder is able to construct the appropriate generator or check matrix that corresponds to the one used by the broadcast apparatus 10 for the source block.
  • the FEC_SOURCE_BLOCK_NR field comprises 8 bits and indicates the number or identity of the source block 45 to which the BB data/repair frame 41, 44 belongs.
  • the FEC_SYMBOL_NR field comprises 8 bits and indicates the location of the BB data/repair frame 41, 44 within the source block. For example, this field may indicate a row number.
  • the signalling data is provided within padding bytes appended to the end of the BB data/repair frame 41, 44.
  • the padding bytes may be appended to the BB data/repair frames 41, 44 between the operations of steps 10 and 11 of Figure 3.
  • DVB-T2 incorporates in-band signalling, known as Type-A signalling, in the BB data/repair frame 41, 44.
  • the presence of in-band signalling is indicated by an IN_BAND_FLAG field in an LI -post- signalling header being set to ⁇ '.
  • the Ll- post- signalling header is part of the P2 symbol 49-2 of the physical layer frame 49.
  • the Type-A signalling data 52-1 can be seen in Figure 5B located immediately after the data/repair segment 40, 43 in the FEC Frame 48.
  • a second set of signalling data, Type-B FEC signalling data 52-2 is provided in the FEC frame 48.
  • Padding data 52-3 located after the Type-B signalling data 52-2, may also be included in the FEC frame 48.
  • the Type-B signalling data 52-2 is 3 bytes in size.
  • the mapping of the various fields is illustrated in Table 2, below: Field Size
  • the PADDING_TYPE field uses 2 bits and indicates the type of signalling data (i.e. Type-A or Type-B FEC) to which the field belongs.
  • Type-A or Type-B FEC type of signalling data
  • '00' indicates that the signalling data is Type-A signalling data 52-1
  • '01 ' indicates that the signalling data is Type-B FEC signalling data 52-2
  • Type-A signalling data 52-1 may be indicated by any of '01 ', '10', and 11
  • Type- B FEC signalling data 52-2 may be indicated by any of '00', '10' and '11 '.
  • the OTHER IN_BAND_SIGNALLING field is used to indicate if there is more in-band signalling within the FEC frame 48 after this particular set of signalling data, which is, in this example, Type-B FEC signalling data 52-2.
  • '1 ' may indicate that there is other signalling data
  • '0' may indicate that there is not any other signalling data, or vice versa.
  • the DATA_TYPE field uses one bit, and indicates whether the segment 40, 43 within the BB data/repair frame 41, 44 is a data (or source) segment 40, or a repair segment 43.
  • a '1 ' in this field may indicate that the segment 40, 43 contained in the BB data/repair frame 41 , 44 is a data segment 40
  • a '0' in this field may indicate that the segment 40, 43 contained in the BB data/repair frame 41 , 44 is a repair segment 43.
  • '1 ' may indicate a repair segment 43
  • '0' may indicate a data segment 40.
  • the LAST_S YMB OL field uses one bit and indicates whether the BB data/repair frame 41 , 44 is the last one of its type (i.e. a BB data frame or a BB repair frame), of its source block 45. For example, a '1 ' may indicate that the BB data/repair frame 41 , 44 is the last of its type, and a '0' may indicate that the BB data/repair frame is not the last of its type, or vice versa.
  • This field is used by the receiver apparatus 14 in conjunction with DATA_TYPE field.
  • the RESERVED_1 field contains 5 bits which are reserved for future use.
  • the RESERVED_1 field may be used to identify the type of FEC code used to generate the repair segments, so that the decoder is able to construct the appropriate generator or check matrix that corresponds to the one used by the broadcast apparatus 10 for the source block.
  • the FEC_SOURCE_BLOCK_NR field comprises 8 bits and indicates the number or identity of the source block to which the BB data/repair frame 41 , 44 belongs.
  • the FEC_SYMBOL_NR field comprises 8 bits and indicates the location of the BB data/repair frame 41 , 44 within the source block. For example, this field may indicate a row number.
  • an additional field, OTHER IN_BAND_SIGNALLING, is included in the Type-A signalling data 52- 1.
  • the Type-A signalling data is mapped as is shown in Table 4, below.
  • the receiver apparatus 14 is notified that, after the last bit of Type-A signalling data 52-1, there is more signalling data to be checked.
  • FIG. 6 is a schematic view of receiver apparatus 14 according to exemplary embodiments of the invention.
  • the receiver apparatus 14 comprises receiver circuitry 60 which is configured to receive incoming signals from an antenna 61.
  • the receiver circuitry 60 is configured to convert the incoming signal into data.
  • the receiver apparatus 14 also comprises memory 62, such as RAM or ROM, for storing incoming and part-processed data.
  • the receiver apparatus also comprises a decoder module 63 for decoding the incoming data and thereby correcting erasure and corruption that may have occurred during transmission.
  • the receiver apparatus 14 also comprises a controller 64 for controlling the other components of the receiver apparatus 14.
  • the controller 64 may include one or more processors or microprocessors under the control of software stored on the memory 62.
  • the receiver apparatus 14 also comprises an output interface 65 for outputting the decoded data. In some embodiments multiple antennas may be used.
  • the receiver apparatus 14 may also include a reproduction module (not shown) for reproducing a data stream from the decoded data.
  • the receiving apparatus 14 may include features relating to other functionality.
  • the receiving apparatus may be a mobile terminal, a telephone handset, a smartphone or any other similar device, in which case other conventional features of telephone handsets, such as a microphone, a second antenna and a transceiver configured to transmit and receive voice data over a telephone network may be included.
  • other features are included depending on its required functionality.
  • the apparatus may be part of a TV set or a setup-box or any other similar device.
  • Step Tl incoming physical layer frames 49 are received at the receiver circuitry 60.
  • the received physical layer frames 49 may then be written to memory 62 to await decoding at an appropriate time.
  • step T2 the PI symbols and P2 symbols of each of the first physical layer frames 49 are decoded by the decoder module 63.
  • the IN_BAND_FLAG field in the LI -post-signalling header to is checked to determine if the FEC frames 48 contain in-band signalling.
  • step T3 one of the FEC frames 48 of which the received physical frames are comprised is passed to the decoder 63.
  • step T4 the FEC frame 48 is horizontally decoded by the decoder module 63.
  • Horizontal decoding comprises the BB data/repair frame 41, 44 contained within the FEC frame 48 being decoded in conjunction with the BCH 46 and LDPC data 47 appended thereto.
  • the horizontal decoding step is illustrated in Figure 8A.
  • Figure 8A shows the horizontal nature of the decoding operation, in that the decoding operation is along a single BB data/repair frame 41, 44. A plurality of iterations of the horizontal decoding step may be carried out in step T4.
  • step T5 following the horizontal decoding of the FEC frame 48, the controller 64 determines if the decoded BB data/repair frame 41, 44 includes vertical error correction signalling. This determination may be carried out, for example, by checking the signalling field of the decoded BB data frame 41.
  • step T6 the decoded BB data frame 41 is forwarded to the output interface 65.
  • the decoded BB data frame 41 may then be forwarded to the reproduction module (not shown).
  • step T6 the operation returns to step T3 in which another BB data/repair frame 41, 44 from the received physical layer frames 49 is passed to the decoder 63.
  • step T5 If it is determined in step T5 that the decoded BB data/repair frame 41, 44 does include vertical error correction signalling, the operation proceeds to step T7.
  • step T7 the signalling data of the decoded BB data/repair frame 41, 44 is checked. This may be located in the BB header 41-1, 44-1 or in the padding data appended to the data/repair segment 40, 43.
  • the decoded BB data/repair frame 41, 44 is stored in a buffer.
  • the buffer may be part of the memory 62.
  • BB data/FEC frames 41, 44 which originated from the same source block 45 are stored in the same buffer.
  • the identity of the originating source block 45 may be determined based on the FEC_SOURCE_BLOCK_NR field of the signalling data.
  • the location within the buffer at which the BB data/repair frame 41, 44 is stored may be determined based on the DATA_TYPE field and the FEC_SYMBOL_NR field. In this way, it is possible to recreate the originating source block 45 at the receiver.
  • step T9 it is determined whether the stored BB data/repair frame 41, 44 is the last of its source block (SB) 45, and thus whether the sourceblock 45 is complete. This may be determined based on the LAST_SYMBOL field of the signalling data.
  • step T9 If in step T9, it is determined that the stored BB data/repair frame 41, 44 is not the last of its source block 45, and thus that the source block 45 is not complete, the operation returns to step T3. A positive determination in step T9 indicates that the source block 45 has been fully recreated. Following a positive determination, in step T9, the operation proceeds to step T10.
  • the receiver apparatus 14 may also include a timer (not shown).
  • the timer may be started when a first BB data/repair frame 41, 44 of a particular source block 45 is received. If a pre-determined time limit is reached before it is determined in step T9 that the last BB data/repair frame 41, 44 of the source block has been stored in the buffer, the operation may proceed to step T10, without the source block 45 having been reproduced in its entirety.
  • step T10 it is determined whether vertical decoding of the source block 45 is required. This may be determined based on a bit error rate of the BB data frames 41 within the source block 45. For example, if the bit error rate is below a threshold, the data stream may be able to be correctly recreated from the BB data frames 41 and thus it may be determined that additional error correction by vertical decoding is not be required. If, however, the bit error rate is above the threshold and thus the data stream may not be able to be correctly recreated, it may be determined that vertical decoding is required. Following a negative determination in step T10, the operation proceeds to step T6 in which the decoded BB data frames 41 stored in the buffer are forwarded to the output interface 65. The BB data frames 41 may then be forwarded to the reproduction module (not shown). The BB repair frames 44 stored within the buffer may be disregarded as they are not required to reproduce the data stream. Following step T6, the operation returns to step T3.
  • step T10 the operation proceeds to step Ti l , in which a counter is set to zero.
  • step T12 vertical decoding of the BB data frames 41 stored in the buffer is performed.
  • Vertical decoding comprises the data segments 40 of each of the BB data frames 41 in the buffer being decoded in conjunction with the repair segments 43 of the BB repair frames 44 stored in the buffer. More particularly, the data bits 40 which are in the same position in their respective data segment 40 are decoded in conjunction with the parity bits 43-1 which are in the same position in their respective FEC data segment 44 . For example, the first data bits 41-la in each of the data segments 40 are decoded in conjunction with the first parity bits 43- la in each of the repair segments 43. Vertical decoding allows the bit error rate of the received data to be further reduced.
  • Figure 8B illustrates the vertical nature of the decoding step of step T12, in that the decoding operation is performed across plural rows of the source block 45. According to some exemplary embodiments, only a single iteration of the vertical decoding is performed in step T12. According to other exemplary embodiments, plural iterations of vertical decoding are performed in step T12.
  • step T13 after vertical decoding, the counter, which was set to zero in step Ti l, is incremented by one.
  • step T14 it is determined whether further error correction of the BB data frames 41 is required. This may be determined based on a bit error rate of the BB data frames 41. For example, if the bit error rate is below a threshold, the data stream may be able to be correctly reproduced from the BB data frames 41 and so it may be determined that further error correction is not required. If, however, the bit error rate is above the threshold and the data stream may not be able to be correctly reproduced, it may be determined that further error correction is required.
  • step T14 may also be carried out on the basis of a comparison of a current value of the counter started in step Ti l, with a maximum value. For example, if the counter is found to be equal to a maximum value, it will be determined in step T14 that no further decoding is to be performed. In this way, the decoder 63 may be prevented from performing an infinite number of error correction operations. This may be particularly beneficial in situations wherein the initial bit error rate of one or more received physical layer frames 49 is so high that the data stream cannot be correctly reproduced, regardless of the number of error correction iterations that are performed.
  • step T14 If it determined, in step T14, that further error correction is required, the operation proceeds to step T15.
  • step T15 one or more further iterations of horizontal decoding are performed.
  • the BB data frames that have already undergone one or more iterations of horizontal and vertical decoding are again horizontally decoded in conjunction with the BCH 46 and LDPC data 47 of their respective FEC frame 48.
  • step T15 the method returns to step T12, in which the data segments 40 of the BB data frames 41 are vertically decoded in conjunction with the repair segments 43 of the BB repair frames 44.
  • steps T15 and T12 are repeated until a negative determination is returned in step T14.
  • step T6 in the decoded BB data frames 41 are forwarded to the output interface 65.
  • the BB data frames 41 may then be forwarded to the reproduction module (not shown).
  • the BB repair frames 44 stored within the buffer may be disregarded as they are not required to reproduce the data stream.
  • the operation returns to step T3.
  • Figure 9A is a simplified schematic view of a decoder 63 that can be used to perform the decoding steps of the operation of Figure 7.
  • the decoder 63 comprises a first soft-decision decoder 101 to perform horizontal decoding, a second soft- decision 102 decoder to perform vertical decoding and a hard-decision decoder 103.
  • Soft-decision decoders 101, 102 output log likelihood ratio representations of a bit, or a vector of symbol value probabilities. Thus, the soft-decision decoders 101, 102 do not output definite results but instead output indications of the likely results. Examples of soft-decision decoders include Bahl-Cocke-Jelinek-Raviv (BCJR) decoders or forward-backward decoders.
  • the hard-decision decoder 103 converts the indications of the likely results into definite results.
  • the horizontal decoding step T4 of Figure 7 is carried out by the first soft-decision decoder 101. If, following the horizontal decoding step of T4, it is decided that the BB data frame 41 does not include vertical error correction signalling, the output of the first soft-decision decoder 101 is fed to the hard-decision decoder 103, which converts the indications of the likely results into definite results.
  • step T4 If in step T4 it is determined that the BB data frame 41 does include vertical error correction signalling, following reproduction of the source block, the outputs of the first soft-decision decoder 101 are fed to the second soft-decision decoder 102 which performs the vertical decoding of step T12.
  • step T14 If in step T14, it is determined that no further error correction is to be carried out, the outputs of the second soft-decision decoder 101 is fed into the hard decision decoder 103.
  • step T14 If, however, in step T14, it is determined that further error correction is to be carried out, the output of the second soft-decision decoder 102 is fed back into the first soft-decision decoder 101 for additional horizontal decoding. The output of the first soft-decision decoder 101 is then fed into the second soft-decision decoder 102 for further vertical decoding. This is repeated until a negative determination is reached in step T14. Following a negative determination in step T14, the output of the second soft- decision decoder 102 is fed into the hard-decision decoder 103, which converts the indications of the likely results into definite results.
  • the output of the hard-decision decoder 103 is sent to the output interface 65 of the receiver apparatus 14.
  • Each of the broadcast apparatus 10 and the receiver apparatus 14 described above may be comprised of hardware, such as one or more processors or microprocessors operating under the control of computer programs, optionally stored on one or more memories.
  • the above described methods and apparatuses provide improved receiver performance due in a significant part to the provision of two sets of FEC data, instead of just one. More particularly, the above described methods and
  • apparatuses make it possible to confine a single erasure error to one BB data/repair frame 41, 44, thus preventing the erasure error from being fragmented over multiple data or FEC segments 40, 43.
  • the broadcast apparatus 10 depicted in Figure 1 may instead be multicast apparatus.
  • the source block 45 comprises plural horizontal rows of BB data or repair frames 41, 44.
  • the BB data or repair frames 41, 44 could instead be arranged in the source block in a column-wise fashion.
  • each element of repair segment data may be generated on the basis of the elements of the data segments 40 in corresponding positions in their respective column.

Abstract

L'invention concerne un procédé qui consiste à recevoir de multiples parties de données ; former de multiples trames de données, chaque trame de données comprenant l'une des multiples parties de données jointes à des données de correction d'erreurs horizontales générées à partir de ladite une des multiples parties de données ; et générer au moins une partie de correction d'erreurs verticale sur la base des parties de données en créant de multiples éléments de données de correction d'erreurs verticale, chaque élément de données de correction d'erreurs étant généré à partir d'éléments correspondants dans chacune des multiples parties de données, chaque partie de correction d'erreurs verticale comprenant de multiples éléments de correction d'erreurs.
PCT/EP2010/050230 2010-01-11 2010-01-11 Correction d'erreurs WO2011082834A1 (fr)

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CN112486725B (zh) * 2020-11-05 2022-10-18 杭州华澜微电子股份有限公司 一种对压缩数据进行纠错编码的方法和装置

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