WO2011078017A1 - Noeud de communication et système de communication - Google Patents

Noeud de communication et système de communication Download PDF

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Publication number
WO2011078017A1
WO2011078017A1 PCT/JP2010/072488 JP2010072488W WO2011078017A1 WO 2011078017 A1 WO2011078017 A1 WO 2011078017A1 JP 2010072488 W JP2010072488 W JP 2010072488W WO 2011078017 A1 WO2011078017 A1 WO 2011078017A1
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WIPO (PCT)
Prior art keywords
address
packet
slave
data
output
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PCT/JP2010/072488
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English (en)
Japanese (ja)
Inventor
康夫 國吉
吉幸 大村
晶彦 長久保
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国立大学法人東京大学
独立行政法人産業技術総合研究所
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Publication of WO2011078017A1 publication Critical patent/WO2011078017A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks

Definitions

  • the present invention relates to a communication node and a communication system, and is suitably applied to a communication system that transmits and receives packet data between a plurality of communication nodes connected in a ring shape via a cable, for example.
  • robots and FA Field Automation
  • sensors eg, angle sensors, tactile sensors, force sensors, proximity sensors, vibration sensors, etc.
  • actuators such as motors
  • peripheral circuits eg, drivers, current sensors, Temperature sensor, encoder circuit, etc.
  • MPU Micro / Processor / Unit
  • an object of the present invention is to propose a communication node and a communication system that can efficiently transmit and receive packets with a smaller delay than conventional ones.
  • claim 1 of the present invention provides an input means for inputting a wait area from the outside following an address area of a packet, and outputting the address area to the outside, or the address area
  • An address verification means for determining whether the address added to the packet matches or does not match with the self address set in advance when the wait area is output to the outside.
  • the address matching means determines that the address of the packet and the self address match
  • the packet acquisition means for acquiring received data input subsequent to the wait area; and
  • the wait area is Immediately after the output, self data stored in advance in the sending means is added to the end of the wait area and output to the outside, and the address of the packet does not match the self address by the address checking means.
  • switching means for outputting the received data to the outside as it is after the address area and the wait area.
  • a plurality of slaves each including the address matching unit, the packet acquisition unit, and the sending unit that stores the self-data, and the packet input to the input unit.
  • the switching means capable of transmitting to each slave, and the switching means includes a slave determined by the address matching means that the address of the packet and the self-address match among the plurality of slaves. In some cases, the self data is received from the slave.
  • a destination address indicating a destination that is being output to the outside or has already been output is routed through a route connected to the output means.
  • the feedback address is returned, it is determined whether the destination address and the feedback address match or do not match, and when it is determined that the destination address and the feedback address do not match, the current output It is characterized by comprising retransmission means for interrupting packet output in the middle and outputting the packet to the outside again from the beginning.
  • a plurality of slaves including the address matching unit and the packet acquisition unit, and a switching input / output unit that connects each of the slaves to an external device.
  • the means is characterized by receiving data as the self data from the external device, selecting one of the slaves according to the type of the data, and transmitting the data to the slave.
  • the apparatus includes a slave including the address matching unit and the packet acquisition unit, and a plurality of input / output units that connect the slave to an external device.
  • One of the plurality of input / output means is selected in accordance with the type of data, and the received data is transmitted to the input / output means.
  • switching input / output means for connecting each of the slaves and an external device, and the switching input / output means receives data as the self data from the external device, and One of the slaves is selected according to the type, and the data is transmitted to the slave.
  • At least one of the slaves is connected to an external device via a plurality of input / output means, and a plurality of the input / output means are provided according to the type of the received data. Any one of them is selected and the received data is transmitted to the input / output means.
  • An eighth aspect of the present invention is characterized in that the communication node according to any one of the first to seventh aspects is connected to a transmission path, and the packet circulates a plurality of the communication nodes. It is.
  • the packet received by performing address verification by the address verification means and data exchange Even when exchanging data, it is possible to efficiently transmit and receive packets with a delay time equivalent to that when simply transferring packets.
  • Communication system 2a Master node (communication node) 2b-2j Slave node (communication node) 4 External devices 10a to 10c Slave 11a, 11b IO (input / output means) 12 Switching IO (Switching input / output means) 15 Address verification means (retransmission means) 21,93 Switching means 22 Address matching means 23 Input means 24 Packet acquisition means 25 Sending means 26 Output means 30 Transfer means
  • reference numeral 1 denotes a communication system having a configuration in which a plurality of communication nodes 2a to 2j are connected by a transmission line 3 in a ring shape.
  • the communication nodes 2a to 2j are master nodes, and the other communication nodes can function as slave nodes.
  • the master node may be a fixed communication node, or a transmission right (token) is transferred between the communication nodes 2a to 2j as necessary, and any one of the plurality of communication nodes 2a to 2j is used.
  • a plurality of communication nodes may have a transmission right to function as a master node.
  • the communication node 2a functions as a master node having the transmission right (hereinafter, the communication node 2a is called the master node 2a), and all the other communication nodes 2b to 2j are A case of functioning as a slave node (hereinafter, communication nodes 2b to 2j are called slave nodes 2b to 2j) will be described below.
  • the case where the communication system 1 according to the present invention is applied to, for example, a robot is described, and a slave is connected to an external device in which a plurality of motors, sensors, and the like are densely arranged, such as hands and feet of the robot. Assume that nodes 2b to 2j are provided.
  • the external device 4 including a plurality of motors 6a and 6b, a plurality of sensors 7a and 7b, and an AD conversion unit 8 connected to the sensors 7a and 7b is illustrated, and attention is paid to the external device 4. This will be described below.
  • a transmission signal is first transmitted from the master node 2a, and this transmission signal sequentially passes through all the slave nodes 2b to 2j along the transmission path 3, and is connected in a ring shape.
  • the nodes 2b to 2j go around in a certain direction and return to the master node 2a again.
  • the transmission signal transmitted from the master node 2a can circulate at high speed on the transmission line 3 provided with the plurality of slave nodes 2b to 2j. Since all the slave nodes 2b to 2j have the same configuration, the following description will be given focusing on the slave node 2d having the plurality of slaves 10a to 10c to which the external device 4 is connected.
  • the master node 2a adds, for example, an address indicating the slave 10a connected to the predetermined motor 6a and data 0 indicating a command value for the motor 6a to the packet P, and uses the packet P as a transmission signal.
  • the slave 10a of the slave node 2d normally transfers the transmission signal to the slave 10b.
  • the slave 10a acquires the address added to the packet P, and is the packet P addressed to itself based on this address. Whether or not it can be judged.
  • the slave 10a determines that the packet P is addressed to another slave, the slave 10a continues to transfer the packet P as it is to the next slave 10b as a transmission signal.
  • the slave 10a when determining that the packet P is addressed to the slave 10a, the slave 10a obtains the data 0 added to the packet P, and at the same time, replaces the data 1 indicating the current value of the motor 6a with the data 0. It is added to the packet P, this packet P is transmitted as a transmission signal, and the downstream slaves 10b and 10c and the slave nodes 2e to 2j can make a round and be received by the master node 2a.
  • the master node 2a can acquire the data 1 added to the packet P when receiving the transmission signal that has circulated around the slave nodes 2b to 2j.
  • the slave node 2d includes a plurality of slaves 10a to 10c, a plurality of IOs (Input / Output) 11a and 11b for connecting the motors 6a and 6b corresponding to the slaves 10a and 10b, and any one of the slaves.
  • An IO (hereinafter referred to as a switching IO) 12 serving as an input / output means that is configured to be switchable between 10a to 10c and has a switching function for distributing the data 1 acquired from the AD conversion unit 8 to a predetermined slave 10a. Is provided.
  • the slave 10a When the slave 10a acquires the data 0 added to the packet P, the slave 10a can transmit this to the motor 6a via the IO 11a. Accordingly, the motor 6a can be controlled based on the data 0.
  • the slave 10a acquires the data 0 added to the packet P and outputs it to the IO 11a.
  • the present invention is not limited to this, and the data 0 acquired by the slave 10a. May be acquired by the IO 11a at an arbitrary timing.
  • the motor 6a is connected to a sensor 7a, and the current value of the motor is detected by the sensor 7a, for example.
  • the current value detected by the sensor 7a is digitized by the AD conversion unit 8, and this is transmitted as data 1 to the switching IO 12 and distributed from the switching IO 12 to a predetermined slave 10a.
  • the communication system 1 performs a predetermined transmission / reception process (described later) when acquiring the packet P in each of the slaves 10a to 10c, and an address verification that is verified by the address verification means 15 in the master node 2a. It is characterized in that retransmission processing (to be described later) is performed based on the result, and switching processing in which the switching IO 12 switches the delivery destination slaves 10a to 10c in accordance with the data 1 acquired from the AD conversion unit 8.
  • the delay is reduced in all the slaves including the slaves 10a to 10c by a predetermined transmission / reception process so that each slave can efficiently acquire the packet P addressed to itself.
  • the master node 2a can also receive the packet P transmitted by itself within a short time, the master node 2a can shorten the time required for retransmission processing necessary for re-output of the packet P when the packet is damaged. Is planned. Further, in this communication system 1, by reducing the delay in all the slaves including the slaves 10a to 10c, each of the slaves efficiently acquires the packet P addressed to itself, and the motors 6a, 6b and By taking the correspondence of the sensors 7a and 7b, the communication cycle is speeded up and the external device 4 is downsized.
  • a packet P generated by the master node 2a includes, for example, an address area AD to which an address indicating the slave 10a is added, a wait area W having a predetermined number of bits, a master It consists of a data area DT to which either data 0 from the node 2a or data 1 received from the external device 4 is added, and a CRC (Cyclic Redundancy Check) (not shown) indicating a check code for detecting a data error.
  • the address area AD can be generated first, followed by the wait area W, the data area DT, and the CRC.
  • description of CRC not related to transmission / reception processing according to the present invention is omitted, and description will be made focusing on address area AD, wait area W, and data area DT.
  • the slave node 2d can be received by the slave 10a from the upstream slave node 2c using the packet P generated by the master node 2a as a transmission signal.
  • the slave 10a is configured to be able to transfer the packet P received from the upstream slave node 2c as it is to the downstream slave 10b by the switching means 21, and acquires the packet P by simply transferring the packet P. Then, the delay can be reduced when the data is output to the downstream slave 10b.
  • the slave 10a transfers the wait area W of the packet P
  • the slave 10a collates the address added to the address area AD by the address collating means 22, and if the address is addressed to itself, the slave 10a Data 0 stored in the buffer is added after the wait area W, and the contents of the data area DT of the packet P changed from data 0 to data 1 downstream
  • the slave 10b can receive it.
  • the slave 10a has an input means 23 to which the packet P is input from the upstream slave node 2c, a switching means 21 for switching the passage route of the packet P in the slave 10a, and a packet P.
  • an output means 26 for outputting the packet P input to the switching means 21 to the downstream slave 10b.
  • the switching means 21 is provided with a transfer means 30 and a route selection means 31.
  • the route selection unit 31 of the switching unit 21 is configured to be able to connect either the transfer unit 30 or the transmission unit 25 and the output unit 26, and is an idle signal output before the packet output from the master node 2a. Can be brought into a transfer state in which the output means 26 is connected to the transfer means 30.
  • the route selection unit 31 changes the connection destination of the output unit 26 from the transfer unit 30 to the transmission unit 25 according to the collation result of the address added to the address area AD of the packet P. Switch.
  • the route selection means 31 continues to connect the output means 26 and the transfer means 30 when the address added to the address area AD is addressed to another slave, and the packet P with the data 0 added to the data area DT. Can be output from the output means 26 as a transmission signal.
  • the path selection means 31 outputs the wait area W of the packet P from the output means 26 as a transmission signal.
  • the route selection means 31 passes the address area AD and the wait area W received from the transfer means 30 as they are, because the output means 26 is connected to the transfer means 30 in advance before receiving the packet P,
  • the address area AD and wait area W are output as transmission signals from the output means 26 to the downstream slave 10b.
  • the packet acquisition unit 24 acquires the packet P from the transfer unit 30 and temporarily stores the acquired packet P.
  • the address verification means 22 determines whether or not the address area AD has been received from the packet P stored in the packet acquisition means 24. When the address area AD has been received, the address verification means 22 The self address set in advance can be collated.
  • the path selection means 31 sends the output means 26 to the transfer means 30 assuming that the packet P is addressed to another slave. Keep connecting.
  • the slave 10a converts the address area AD of the packet P input to the input means 23, the wait area W, and the data area DT to which data 0 is added into the path selection means 31. Can be output as it is as a transmission signal from the output means 26 and transferred to the downstream slave 10b.
  • the address acquisition unit 22 discards the address area AD, the wait area W, and the data area DT received from the transfer unit 30, and waits for the next packet P to be sent from the transfer unit 30.
  • the route selection means 31 is connected to the transfer means 30 in advance based on the idle signal, so that the address area AD and the wait area W received from the transfer means 30 And the address area AD and wait area W are output as transmission signals from the output means 26 to the downstream slave 10b.
  • the packet acquisition unit 24 receives the packet P from the transfer unit 30 and temporarily stores the received packet P. If the address matching means 22 determines that the address of the address area AD matches the self address as a result of matching the address of the address area AD acquired by the packet acquiring means 24 with the self address, the packet P is addressed to the self slave. If there is, a switching signal is sent to the route selection means 31. As a result, the route selection means 31 switches the connection destination of the output means 26 from the transfer means 30 to the sending means 25 as shown in FIG. As shown in FIG.
  • the slave 10a reads the data 1 stored in the sending means 25, adds it to the data area DT, adds the data area DT to the end of the wait area W, Can be output from the output means 26 as a transmission signal and sent to the downstream slave 10b.
  • the address matching means 22 determines that the address added to the address area AD matches the self address, the address matching means 22 extends from the end of the address area AD to a predetermined number of bits.
  • this position is determined as the end of the wait area W, and a data addition command is sent to the sending means 25.
  • the sending means 25 sends the data 1 as its own data to the route selection means 31 based on the data addition command, and adds the data 1 to the location that is the end of the wait area W.
  • the route selection means 31 can output the data area DT of the data 1 added immediately after the end of the weight area W from the output means 26 as a transmission signal.
  • the route selection means 31 interrupts the transfer of the wait area W from the transfer means 30. Therefore, the route selection means 31 generates a transmission signal corresponding to the wait area W from the end of the address area AD to a predetermined number of bits, and outputs it to the output means 26 from the time when the transfer of the wait area W is interrupted. Continue to output.
  • the transmission timing of the data 1 from the transmission means 25 to the path selection means 31 is adjusted, so that the address added to the end has been described, the present invention is not limited to this, and the route according to the end of the weight region W when the end of the weight region W passes the route selection means 31.
  • Data 1 may be added to the end of the weight area W by switching the connection path of the selection means 31 to the sending means 25. In short, if new data 1 can be added to the end of the weight area W, the other Various methods may be applied.
  • the slave nodes 2b to 2j transmit their own data 1 from the position of a predetermined number of bits from the end of the address area AD. As long as it is mounted, the content of the weight area W may be changed.
  • the master node 2a sends a packet P in which valid data is written to the slave areas 10a to 10c in the wait area W, and the slave 10b that is the destination acquires the data in the wait area W and the data area DT, and addresses
  • the implementation is such that its own data 1 is transmitted from the position of a predetermined number of bits from the end of the area AD, but in this case as well, the content of the wait area W received by the master node 2a may be changed. Good.
  • the master node 2a places data in the wait area W.
  • the address verification means 22 is configured to send a data holding command to the packet acquisition means 24 when the address added to the address area AD matches the self address.
  • the packet acquisition means 24 stores the data 0 as the reception data added to the packet P as shown in FIG. 4C based on the data holding command, and stores the data 0 in the slave 10a.
  • the information can be transmitted to the associated IO 11a (FIG. 1).
  • the address area AD is collated with the address of the address area AD while the wait area W having a predetermined number of bits added in advance following the address area AD is being output from the output unit 26.
  • the collation and the switching operation for switching the connection route to the sending means 25 in the route selection means 31 when the address of the address area AD matches the self address are performed.
  • the delay caused in each slave when the packet passes through many slaves included in the slave nodes 2b to 2j is also related to data exchange. It can be shortened to the same time as a simple transfer process.
  • the delay of the slave 10a is 1 bit or less, that is, 10 nsec or less.
  • the path selection means 31 uses the output means 26.
  • the timing for switching the connection destination to the sending means 25 is delayed, the data exchange for exchanging data 0 to data 1 in the data area DT at the end of the address area AD may not be in time, and the packet P may be destroyed.
  • the wait area W is provided in advance between the address area AD and the data area DT, address matching performed in the address matching means 22 and switching operation in the route selecting means 31 are performed. Can be performed within the wait transfer time, data exchange from data 0 to data 1 can be executed reliably in the data area DT, and the packet P can be prevented from being destroyed.
  • the communication system 1 shown in FIG. 1 has a very short packet transmission delay in each of the slave nodes 2b to 2j. Therefore, even when the number of slave nodes is relatively large, the master node 2a transmits the packet P to the downstream slave node 2b. Before the transmission of all signals is completed, the head of the transmission signal returns to the master node 2a again via all the slave nodes 2b to 2j.
  • the address verification means 15 of the master node 2a adds the address added to the address area AD of the currently output packet P and the address area AD among the packets that have returned through all the slave nodes 2b to 2j.
  • An error determination process is performed for checking the added address (hereinafter referred to as a feedback address).
  • the master node 2a can determine whether or not the packet acquired after making a round of the slave nodes 2b to 2j is damaged by noise or the like during transmission.
  • the address verification means 15 of the master node 2a is provided with storage means (not shown), and the address added to the address area AD among the packets P currently sent to the downstream slave node 2b is It can be stored in the storage means as an address for error determination.
  • the address verification means 15 of the master node 2a receives a transmission signal that makes a round of all the slave nodes 2b to 2j when the packet P is being output to the downstream slave node 2b, and receives the address area AD of the packet P. Can be determined whether or not the feedback address added to the address area AD matches the error determination address stored in the storage means.
  • the address verification means 15 does not perform after the address area AD has all fed back, but sequentially checks the signal to be fed back with the address for error determination in units of 1 bit before the area AD has all fed back. The damage of the area AD can be determined.
  • the address verification unit 15 as the retransmission unit of the master node 2a performs the error determination process, the return address of the packet P that has made a round of all the slave nodes 2b to 2j, and the error determination address stored in the storage unit Is determined to be inconsistent, it is determined that the packet P is damaged due to noise or the like during transmission, the output of the currently transmitted transmission signal is immediately interrupted, and an idle signal is output instead of the transmission signal. Let it be idle. As a result, the slave nodes 2b to 2j interrupt the input of the transmission signal, and when the idle signal is input instead of the transmission signal, the slave node 2b-2j discards the packet P stored in the packet acquisition means 24 (FIG. 2). Wait until a new transmission signal is input.
  • the master node 2a starts to output the packet P again to the downstream slave node 2b as a transmission signal in order from the head address area to the wait area and the data area.
  • the master node 2a determines whether or not there is a possibility that the packet P is damaged before completing the output of all the packets P.
  • the packet P is output again from the beginning without waiting for the completion of output.
  • the master node 2a prevents the slave nodes 2b to 2j from acquiring the packet P that may be damaged during transmission, and shortens the communication time required for re-outputting the packet P when the packet is damaged. And real-time performance can be improved.
  • the damage of the packet P due to noise or the like is conventionally determined using a CRC (not shown) added to the end of the packet P. Therefore, the master node 2a receives all the transmission signals that have made a round of all the slave nodes 2b to 2j, and after acquiring the entire packet, determines whether or not the packet P is damaged by CRC, and the packet P is damaged. If it is determined, the packet P is re-output.
  • CRC not shown
  • the master node 2a can detect whether or not the packet P is damaged without acquiring the whole packet, and when the whole packet is output to the downstream slave node 2b, the packet P again. Can be output again from the beginning, and accordingly, the re-output time of the packet P when the packet is damaged can be shortened.
  • the master node 2a of the present invention can determine whether the address area AD is damaged without acquiring the entire address area AD by sequentially performing address collation in units of 1-bit feedback signal. It is.
  • the processing circuit is prevented from becoming complicated, and the processing content is simple, so that the master node 2a
  • the internal circuit configuration of the IC constituting the circuit is also simple and can be reduced in size.
  • the IOs 11a and 11b and the switching IO 12 are, for example, a parallel bus or a serial bus (SPI (Serial Peripheral Interface), SMBus (System Management Bus), I2O ((Intelligent Input / Output)), UART (Universal Asynchronous Receiver) Transmitter)) and the like, and the motors 6a and 6b of the external device 4 are connected to the IOs 11a and 11b via the buses, and the AD converter 8 of the external device 4 is connected to the switching IO 12 respectively.
  • SPI Serial Peripheral Interface
  • SMBus System Management Bus
  • I2O Intelligent Input / Output
  • UART Universal Asynchronous Receiver
  • the IO 11a can acquire data 0, which is a command value to the motor 6a, from the slave 10a via the parallel bus, and can output data 0 to the motor 6a of the external device 4.
  • the external device 4 includes a multi-channel AD conversion unit 8, sensors 7a and 7b provided for the respective motors 6a and 6b are connected to the AD conversion unit 8, and a plurality of the AD conversion units 8 are provided.
  • the measurement signals sent from the sensors 7a and 7b can be subjected to AD conversion processing.
  • the external device 4 is provided with an AD conversion unit individually for each of the sensors 7a and 7b as in the prior art, and is reduced in size as compared with an external device including a plurality of AD conversion units.
  • a bus such as SMBus is connected to the switching IO 12, and the AD conversion unit 8 of the external device 4 is connected to the switching IO 12 via the bus.
  • the switching IO 12 receives from the AD conversion unit 8 a data string obtained by AD converting the measurement signals from the sensors 7a and 7b, the switching IO 12 selects, for example, the slave 10a associated with the data string from the slaves 10a to 10c.
  • the data 1 added to the data string can be output only to the selected slave 10a.
  • the data string received by the switching IO 12 from the AD conversion unit 8 is composed of a slave ID indicating an ID previously associated with each of the slaves 10a to 10c, a data length, and data 1 sent to the master node 2a.
  • the switching IO 12 selects, for example, the slave 10a corresponding to the slave ID of the data string as the connection destination, and selects the data string corresponding to the data length of the data string as the connection destination slave. It is configured to output to 10a.
  • the switching IO 12 can output data 1 which is a current value in the same motor 6a to the slave 10a which has transferred the data 0 from the master node 2a to the motor 6a.
  • the slave that delivers the data 0 from the master node 2a to the motor 6a and the slave to which the data 1 obtained from the motor 6a is input can be the same slave 10a.
  • Data 0 and data 1 can be exchanged in the data area of the packet P at the timing when P is acquired and address verification is performed.
  • FIG. 5 in which the same reference numerals are assigned to the parts corresponding to those in FIG.
  • Each of the motor modules 43a and 43b receives the measurement results from a plurality of sensors 7a and 7b that measure the currents of the motors 6a and 6b, AD conversion units 44a and 44b that perform AD conversion processing, and a rotation angle of a predetermined part Counters 46a and 46b.
  • the external device 42 as a comparative example is connected to a sensor network 49 and an AD converter 48 connected to a predetermined sensor 47, separately from the AD converters 44a and 44b and the counters 46a and 46b. MPU50 is provided.
  • the AD modules 44a and 44b and the counters 46a and 46b are provided for the respective motor modules 43a and 43b, so that the motor modules 43a and 43b are enlarged. As a result, there is a problem that the overall size of the external device 42 is increased.
  • an external device 52 as shown in FIG. .
  • the predetermined sensor 47 and the sensors 7A and 7B of the motor modules 53A and 53B are connected to one AD converter 48 to share the AD converter 48, Instead of the counter, the rotation angle is measured by one MPU 50.
  • the AD conversion unit and the counter of each motor module 53A, 53B can be omitted, so that the size of each motor module 53A, 53B can be reduced.
  • data 1 from the AD conversion unit 48 related to the motor 6a is input to a slave 10c different from the slave 10a that outputs data 0 to the motor 6a.
  • Data input / output related to one motor 6a is performed using different slaves 10a and 10c.
  • Switching IOs 12a and 12b with a switching function for freely distributing them are provided.
  • a slave 10a that outputs data 0 to the motor 6a, and a slave 10a that receives data 1 related to the motor 6a Therefore, the data 0 and data 1 in the data area of the packet P can be exchanged at the timing when the slave 10a acquires the packet P and checks the address.
  • the switching IO 12a By appropriately switching the connection-destination slaves 10a to 10d at 12b, for example, data 0 and data 1 related to the motor 6a can be exchanged by the same slave 10a.
  • the slave node 61 can exchange data 0 and data 1 in the data area DT of the packet P at the timing when each of the slaves 10a to 10d acquires the packet P. Therefore, in the slave node 61, it is not necessary to align the communication cycle between the slaves 10a to 10d as in the slave node 41 shown in FIG. The speed can be increased.
  • data exchanged in one packet can be associated with one motor module 53a or 53b, so that the processing in the computer connected to the master node 2a can be made simple and efficient.
  • the command to the motor 6a, the sensor 7a, and the rotation angle 53a can be handled in a unified manner.
  • Tc between the slave ID and data 1 indicates the data length.
  • the MPU 50 selects any one of the slaves 10a to 10d via the switching IO 12b, and not only sends data 1 to the selected slave but also receives data 0 from the selected slave. That is, the MPU 50 can select one of the slaves 10a to 10d and exchange data with the selected slave.
  • the packet P is continuously output from the output means 26 to the downstream slave 10b via the transfer means 30 and the path selection means 31, and the packet acquisition means 24 The packet P acquired by is discarded.
  • the address area AD is analyzed and whether the packet is addressed to itself. I was deciding whether or not.
  • the data in the data area DT is exchanged, and the packet fetched in the buffer is output to the downstream slave as a transmission signal in order from the top address area AD.
  • the slave 10a when the packet P is input from the input means 23, the packet P is immediately output to the downstream slave 10b, and at the same time, the address verification of the address added to the packet P is performed.
  • the delay time that occurs when the packet P is transferred to the downstream slave 10b can be shortened compared to the conventional case, and the packet P can be transmitted and received efficiently.
  • the delay time when transmitting and receiving the packet P can be shortened compared to the conventional slave.
  • the slave 10a acquires the data 0 added to the data area DT from the packet P acquired by the packet acquisition means 24. At this time, the slave 10a disconnects the connection between the output unit 26 and the transfer unit 30 in the route selection unit 31, and connects the transmission unit 25 to the output unit 26, and the data 1 stored in the transmission unit 25 in advance. Is added to the end of the wait area W instead of the data 0, and this is output from the output means 26 to the downstream slave 10b.
  • the output unit 26 when the output unit 26 outputs a predetermined number of wait areas W in the packet P from the output unit 26, the address verification by the address verification unit 22 and the route selection unit 31 By switching the connection path, even after it is determined that the packet P is addressed to itself, the data 1 can be reliably added to the end of the wait area W instead of the data 0, and the packet P is destroyed. Can be prevented.
  • the wait area W since the wait area W is provided, when the wait area W is output from the output means 26, the address verification by the address verification means 22 and the switching of the connection route by the path selection means 31 are performed. Therefore, the data 1 can be output without delay immediately after the transfer of the address area AD and the wait area W of the packet P in each of the slaves 10a to 10c provided on the transmission path 3, and the delay can be made smaller than before. Packet P can be transmitted and received efficiently. Further, in the communication system 1, the time of the packet P returning from the master node 2a to the master node 2a again through all the slave nodes 2b to 2j can be shortened.
  • the address verification is performed within the preset transfer time of the wait area W.
  • the delay of the entire packet is the product of the transfer delay of each slave node and the total number of slave nodes. . Since the delay of the slave node is 1 bit or less in the harmonized method (described later) and is shorter in the repeat method (described later), the communication system 1 realizing high-speed response can be constructed even when there are many slave nodes.
  • each of the slaves 10a to 10c has an extremely short delay and can efficiently transmit and receive the packet P, and a high-speed response of data communication between the master node 2a and the slave nodes 2b to 2j can be achieved. Therefore, for example, it is extremely effective in reducing the size of the external device 4.
  • a communication system 71 in which MPUs 73a to 73d are respectively provided in a plurality of communication nodes 72a to 72f as shown in FIG. 8 will be described as an example.
  • motors 74a and 74b are provided in MPUs 73a and 73b via drivers 75a and 75b, and sensors 76a and 76b are provided in MPUs 73c and 73d via amplifiers 77a and 77b.
  • a device 79a including the communication nodes 72e and 72f provided is provided.
  • devices 79b and 79c having communication nodes 72a and 72b, respectively, and having sufficient space in the installation space G are provided.
  • the high-performance PU (Processor Unit) 83a, 83b that functions in place of the MPU is provided in the installation space G of the other device 79b, 79c, so that one device 82 is small enough to omit the MPU. Can be achieved.
  • packet communication can be made to respond at high speed like the buses of the high-performance PUs 83a and 83b. Even when the high-performance PUs 83a and 83b are away from each other, packet communication similar to the communication system 71 shown in FIG. 8 can be realized.
  • the amount of data per unit time is very large in sensors that require high-speed sampling, such as vibration sensors and acceleration sensors. Therefore, in the slave node of the communication system, if the data collection cycle by the packet P is slow, it is necessary to buffer the data from the sensor. However, if the slave nodes 2b to 2j can collect data at high speed by the packet P in the communication system 1, the amount of buffers and RAMs to be arranged in the slaves 10a to 10c can be greatly reduced, and the ICs to be used Since the rank of the MPU can be lowered, the slaves 10a to 10c can be further downsized.
  • the head of the packet P currently output to the downstream slave node 2c is again transmitted to the master node 2a via all the slave nodes 2b to 2j. Is returned to the address area AD of the currently output packet P, and the address added to the address area AD of the packet P that has returned around the slave nodes 2b to 2j is checked.
  • the master node 2a Even if it makes a round of the nodes 2b to 2j, the slave nodes 2b to 2j do not change the address of the packet P, so the packet P is damaged by noise or the like while making a round of the downstream slave nodes 2b to 2j.
  • the master node 2a immediately interrupts the currently output packet P, and again outputs the packet P from the head address area AD to the downstream slave node 2c. It is possible to shorten the time required for re-outputting the packet P at the time and improve the real-time property.
  • the switching IO 12 that connects the slave 10a and the AD conversion unit 8 of the external device 4 has a plurality of connection destinations according to the slave ID of the data string received from the AD conversion unit 8.
  • the switching IO 12 that connects the slave 10a and the AD conversion unit 8 of the external device 4 has a plurality of connection destinations according to the slave ID of the data string received from the AD conversion unit 8.
  • the data 0 received from the AD converter 8 is associated with the motor 7a that has obtained the data 0. Since the data can be directly output to the slave 10a, the data exchange of the data 0 and the data 1 of the packet P can be performed at the timing when the packet P is acquired in the slave 10a and the address verification is finished. Thus, in the slave node 2d, data 1 and data 0 can be transmitted / received at high speed by the communication cycle of the slaves 10a to 10c.
  • the present invention is not limited to the present embodiment, and various modifications can be made within the scope of the gist of the present invention, and a communication system used for a robot or FA system. It can be applied not only to various communication systems.
  • each slave 10a to 10c is configured to be freely switchable to any one of the plurality of IOs 11a, 11b and switching IO12 to any one of IO11a, 11b or switching IO12. Also good.
  • the data 0 has been described as a command value to the motor 6a, for example, and the data 1 has been described as a current value of the motor 6a, for example.
  • the present invention is not limited to this, and a plurality of communication nodes are connected to a line.
  • Various other communication systems such as a communication system connected in a type, a communication system in which a plurality of communication nodes are connected in a star shape, and a communication system in which a plurality of communication nodes are connected in a tree shape may be applied.
  • the IOs 11a and 11b are configured to have a PWM (Pulse Width Modulation) output as an output to the motors 6a and 6b, or a counter input of a rotation angle sensor (rotary encoder) connected to the motor.
  • PWM Pulse Width Modulation
  • the IO having various other configurations such as the configuration having the above may be applied.
  • the packet acquisition unit 22 uses the data area DT received from the transfer unit 30 without discarding it.
  • An implementation is also possible.
  • sending means is used for the circuit unit that stores data 1 as its own data.
  • the sending means 25 does not necessarily have to be implemented to send, for example, The sending means 25 may simply store the self data, and actually the switching means 21 may read and send the self data.
  • the sending means 25 may store the self data and send the self data to the switching means 21, and the switching means 21 may simply output the self data to the outside via the route selecting means 31.
  • the packet P having the address area AD at the head is applied has been described.
  • the present invention is not limited to this, and the packet having the wait area W immediately after the address area AD is used. If there is, for example, a packet in which there are various other data at the head and there is an address area AD immediately after that may be applied.
  • slaves when there are a plurality of slaves in the slave node, there may be an implementation in which the slaves share the address verification unit 22 and the packet acquisition unit 24.
  • the slave node 2d is different from the above-described embodiment only in that a switching unit 93 is provided outside the slaves 92a to 92c.
  • the slaves 92a to 92c have the same configuration, for convenience of explanation, attention is paid to the slave 92b.
  • the slave 92b acquires the data 0 added to the packet P and stores the data stored in the slave 92b. A case where 1 is added to the packet P will be described below.
  • the slave 92b includes an address matching means 22, a packet acquisition means 24, and a sending means 25, and is provided outside the slave 92b.
  • the packet acquisition means 24 is connected to the transfer means 94 of the switching means 93, and compared with the above-described embodiment, the size is reduced by the amount that the switching means 93 is not provided in the slave 92b. Is planned.
  • the switching unit 93 when the packet P is input from the input unit 23, the switching unit 93 outputs the packet P to the respective slaves simultaneously by the transfer unit 94 and outputs the packet to the route selection unit 95 as it is.
  • the packet P can be directly transferred to the downstream slave node 2e (FIG. 10) via the route selection means 95 and the output means 26.
  • the slave 92b performs the address verification by the address verification unit 22 and outputs the connection path to the path selection unit 31 when the wait area W is output from the output unit 26. Can be switched. At the same time, the slaves 92a and 92c perform address verification.
  • each slave 92a, 92b, 92c determines that the data 0 added to the received packet P is not addressed to itself, it discards the packet P.
  • each slave 92a, 92c discards the packet P because the data 0 added to the received packet P is not addressed to itself, but the slave 92b
  • the address added to the address area AD matches the self address
  • the data 0 added to the data area DT is acquired from the packet P acquired by the packet acquisition means 24.
  • the path operation means 95 receives the switching signal from the address collating means 22 of the slave 92b, cuts off the connection between the output means 26 and the transfer means 30 based on the switching signal, and outputs the output means 26 and each slave.
  • the sending means 25 of 92a to 92c is connected.
  • the path operation unit 95 receives the data 1 from the transmission unit 25 of the slave 92b, adds the data 1 to the end of the wait area W instead of the data 0, and outputs the data 1 from the output unit 26 to the downstream slave node. It is made to be able to do.
  • the switching means 93 is not provided in each of the slaves 92a to 92c.
  • the slave node 2d itself can be reduced in size.
  • the transfer processing in each slave 92a to 92c can be executed by one switching means 93. Therefore, even if a slave is provided in addition to the slaves 92a to 92c and the number of slaves is increased, the slave node The transfer time for transferring the packet P from 2d to the downstream slave node can be maintained as the transfer time before the number of slaves is increased. That is, in this case, the delay time does not depend on the number of slaves, and is configured to be proportional to the number of slave nodes, so that the delay time can be significantly shortened. Furthermore, the circuits in each of the slave nodes 2b to 2j can be simplified, and the miniaturization of the IC can be promoted.
  • the transfer means 30 has a built-in receiver element, etc., whereby the received transmission signal is binarized and further sampled at the timing of the clock in the slave, so that the jitter of the transmission signal (in the time axis) The waveform collapse due to the fluctuation component generated along the line) and the skew (tilt) is corrected and converted into a harmonized signal.
  • the tuned signal is sent to the route selection means 31 and the packet acquisition means 24.
  • the path selection means 21 sends the tuned signal or the signal from the sending means 25 downstream through a driver element or the like.
  • the delay of this harmonizing method is mainly caused when sampling is performed at the timing of the clock in the slave, and is 1 bit or less.
  • the packet length is made sufficiently smaller than 5000 bits, it is not necessary to introduce a delay due to a clock error, so that the delay due to the harmonic wave can be minimized.
  • the packet length is shortened, there is a disadvantage that the substantial data transfer efficiency is lowered.
  • the packet length is shortened, and the delay caused by the switching means 21 in the wave shaping method is limited to 1 bit or less.
  • the switching means 100 using the repeater system branches the transmission signal received from the input means 23 (FIG. 2) into two, and one of the branch signals is adjusted by the wave shaping means 101. After being waved, it is output to the packet acquisition means 24.
  • the wave shaping means binarizes the transmission signal received by the receiver element 102, and then samples it at the timing of the clock 103 by the sampling unit 104, thereby correcting the waveform distortion of the transmission signal and converting the wave shaped signal. Output.
  • the other branch signal can be output to the output side via the repeater element 106.
  • the signal from the sending means 25 is output to the output side via the driver element 107 in the switching means 100.
  • the repeater element 106 outputs a signal similar to the input signal, but is an element having a function of improving output impedance and the like, and the delay is extremely small.
  • the outputs of the repeater element 106 and the driver element 107 can be validated / invalidated, and for example, those having high impedance due to the invalidation are used.
  • the validation / invalidation of the repeater element 106 and the driver element 107 is controlled by the address collating means 22, and the function equivalent to the path selection means is achieved by enabling only one of them. As a result, either the transmission signal from the input means 23 (FIG. 2) or the signal from the sending means 25 is output from the switching means 100.
  • the delay in the switching means 100 at this time is the same as the delay of the repeater element 106, it can be shortened as compared with the harmonizing method or the like. Normally, only the repeater element 106 is enabled, and the received transmission signal is output as it is through the repeater element 106. When outputting the sending means 25, only the driver element 107 connected to the sending means 25 is valid. When the data transmission from the transmission means 25 is completed, only the repeater element is validated again.
  • the switching means 21 shown in FIG. 2 includes a transfer means 30 and a route selection means 31, but the transfer means 30 and the route selection means 31 are not necessarily provided as physical structures.
  • a switching unit that functions in a similar manner may be constructed without providing a transfer unit and a route selection unit as a physical structure.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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Abstract

La présente invention se rapporte à un noeud de communication et à un système de communication qui, par comparaison avec des technologies existantes, peuvent réduire le retard et peuvent transmettre et recevoir de manière efficace des paquets. Lorsqu'un dispositif esclave (10a) sort d'une région d'attente (W) par l'intermédiaire d'un moyen de sortie (26), un moyen d'appariement d'adresses (22) effectue un appariement d'adresses et un moyen de sélection de route (31) effectue une commutation d'une route de connexion ; ainsi, chaque dispositif esclave (10a à 10c) utilisé sur un canal (3) peut transmettre des données (1) sans aucun retard immédiatement après le transfert d'une région d'adresse (AD) et d'une région d'attente (W) d'un paquet (P).
PCT/JP2010/072488 2009-12-21 2010-12-14 Noeud de communication et système de communication WO2011078017A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
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JP7438471B1 (ja) 2023-07-10 2024-02-26 三菱電機株式会社 機器、通信システム、通信制御方法およびプログラム

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JPH0425254A (ja) * 1990-05-21 1992-01-29 Matsushita Electric Ind Co Ltd ループ状伝送装置
JPH08154100A (ja) * 1994-09-30 1996-06-11 Matsushita Electric Ind Co Ltd 通信装置

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Publication number Priority date Publication date Assignee Title
JPS56147541A (en) * 1980-04-17 1981-11-16 Mitsubishi Electric Corp Remote process input and output controller for computer
JPH0425254A (ja) * 1990-05-21 1992-01-29 Matsushita Electric Ind Co Ltd ループ状伝送装置
JPH08154100A (ja) * 1994-09-30 1996-06-11 Matsushita Electric Ind Co Ltd 通信装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7438471B1 (ja) 2023-07-10 2024-02-26 三菱電機株式会社 機器、通信システム、通信制御方法およびプログラム

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