WO2011074154A1 - Dc-dc converter - Google Patents

Dc-dc converter Download PDF

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Publication number
WO2011074154A1
WO2011074154A1 PCT/JP2010/004633 JP2010004633W WO2011074154A1 WO 2011074154 A1 WO2011074154 A1 WO 2011074154A1 JP 2010004633 W JP2010004633 W JP 2010004633W WO 2011074154 A1 WO2011074154 A1 WO 2011074154A1
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Prior art keywords
current
converter
inductor
switching frequency
control means
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PCT/JP2010/004633
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French (fr)
Japanese (ja)
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竹島由浩
永井孝佳
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2011545929A priority Critical patent/JP5318966B2/en
Publication of WO2011074154A1 publication Critical patent/WO2011074154A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Definitions

  • the present invention relates to a DC / DC converter that stores energy with a large current in a storage means characterized by a large capacity such as an electric double layer capacitor.
  • the present invention has been made to solve the above problems, and when charging an electric storage means such as an electric double layer capacitor, even if the output current of the DC / DC converter increases, the ripple amount is increased. It is an object of the present invention to provide a DC / DC converter that can suppress and efficiently and reliably charge power storage means such as an electric double layer capacitor.
  • the DC / DC converter includes a switching element and an inductor, and the switching element is turned on / off at a predetermined switching frequency to convert the voltage of the input DC power source and output it to the storage means to charge the storage means.
  • DC / DC converter current detection means for detecting current flowing through the inductor, and control means for sending an ON / OFF drive signal by PWM (pulse width modulation) control to the switching element so as to charge the storage means with the commanded predetermined charging power
  • PWM pulse width modulation
  • the control means changes the switching frequency of the on / off drive signal sent to the switching element in accordance with the inductor current detected by the current detection means, the current flowing through the inductor Even in a large range, an increase in the ripple of the current is suppressed, and the power storage means can be charged efficiently and reliably.
  • Embodiment 1 the circuit configuration of the DC / DC converter according to Embodiment 1 of the present invention will be described with reference to FIG.
  • an input DC power supply 1 is connected to DC input terminals 2a and 2b of a DC / DC converter in order to supply a DC stabilized voltage having a necessary voltage range to the DC / DC converter.
  • the drain terminal of the MOSFET 3a that is the first switching element is connected to the DC input terminal 2a
  • the source terminal of the MOSFET 3b that is the second switching element is connected to the DC input terminal 2b.
  • the source terminal of the MOSFET 3a that is the first switching element, the drain terminal of the MOSFET 3b that is the second switching element, and one terminal of the inductor 4 are connected.
  • the other terminal of the inductor 4 is connected to the terminal 5 a of the current detector 5.
  • the terminal 5b of the current detector 5, the source terminal of the MOSFET 3c that is the third switching element, and the drain terminal of the MOSFET 3d that is the fourth switching element are connected.
  • the drain terminal of the MOSFET 3c as the third switching element is connected to the DC output terminal 6a, the source terminal of the MOSFET 3b as the second switching element, the source terminal of the MOSFET 3d as the fourth switching element,
  • the DC output terminal 6b is connected and grounded.
  • the MOSFETs 3a to 3d, which are the first to fourth switching elements, and the inductor 4 constitute a DC / DC converter shown in the claims of the present application.
  • the electric double layer capacitor 7 is connected to the DC output terminals 6a and 6b.
  • the terminal 5 c of the current detector 5 is connected to the terminal 8 a of the calculation means 8, and the DC output terminal 6 a is connected to the terminal 8 b of the calculation means 8.
  • the terminal 8 c of the calculation means 8 is connected to the terminal 9 e of the PWM control means 9.
  • the gate terminal of the MOSFET 3a which is the first switching element and the terminal 9a of the PWM control means 9 are connected, the gate terminal of the MOSFET 3b which is the second switching element and the terminal 9b of the PWM control means 9 are connected, and the third switching The gate terminal of the MOSFET 3c as the element and the terminal 9c of the PWM control means 9 are connected, and the gate terminal of the MOSFET 3d as the fourth switching element and the terminal 9d of the PWM control means 9 are connected.
  • the calculation means 8 and the PWM control means 9 constitute the control means shown in the claims of the present application.
  • FIGS. 2 shows the characteristics of each part when the voltage across the electric double layer capacitor 7 is low (V C1 ), and FIG. 3 shows the characteristics of each part when the voltage across the electric double layer capacitor 7 is high (V C2 ). Show the characteristics.
  • the duty ratio (on / off ratio) is calculated by the calculation means 8 from the current value detected by the current detector 5 and the target current value, and an on / off drive signal by PWM (pulse width modulation) control is supplied via the PWM control means 9. Generate.
  • This on / off drive signal is sent to the gate terminals of the MOSFETs 3a to 3d, which are the first to fourth switching elements, to drive the switching element MOSFETs 3a to 3d on and off.
  • the charging to the electric double layer capacitor 7 is performed with the commanded predetermined charging power. This assumes a case where regenerative power generated by a generator or the like is stored in the electric double layer capacitor 7, for example. For this reason, as shown in the uppermost graphs of FIGS. 2 and 3, there is a characteristic that the charging current decreases as the charging progresses and the voltage across the electric double layer capacitor 7 increases. . Therefore, when the voltage across the electric double layer capacitor 7 is low, a large charging current is supplied.
  • the inductor 4 has a magnetic characteristic of the iron core used in the inductor 4, and when a large current of a certain level or more flows through the inductor 4 as shown in the second graph of FIGS. A sudden inductance drop occurs.
  • the ripple amount increases in the range where the charging current is large, and the electric double layer capacitor 7 is hindered.
  • the charging current value detected by the current detector 5 is compared with a plurality of switching reference current values.
  • the switching frequency of PWM control is switched stepwise according to the charging current value.
  • the switching frequency becomes high, and the switching element is turned off at an early timing, thereby suppressing an increase in the ripple current.
  • the ripple of the inductor current remains in a certain range, and the switching frequency is switched to a low level. The increase in loss is suppressed.
  • the graphs at the bottom of FIGS. 2 and 3 show that the ripple current component is maintained within the allowable ripple current range of the electric double layer capacitor 7 regardless of the magnitude of the charging current value. .
  • the switching frequency of PWM control is increased stepwise in accordance with the increase in the charging current detected by the current detector 5.
  • an increase in the ripple amount of the charging current is suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably.
  • the first embodiment of the present invention has been described using a MOSFET as a switching element, a bipolar transistor, an insulated bipolar transistor (IGBT), or a transistor formed of a wide band gap semiconductor such as silicon carbide.
  • a MOSFET insulated bipolar transistor
  • MOSFET metal-oxide-semiconductor
  • the present invention in the first embodiment of the present invention, the case where a non-insulated buck-boost converter circuit is used as the DC / DC converter which is the main circuit in the DC / DC converter has been described.
  • the present invention can also be applied to a non-insulated converter circuit or an isolated converter circuit using various inductors.
  • an electric double layer capacitor is used as the power storage means, but the same effect can be obtained even when a secondary battery is used.
  • the inductor has a characteristic that the inductance is a constant value up to a predetermined current value and the inductance is decreased above the predetermined current value. A similar effect can be obtained by using an inductor having a characteristic of decreasing to the right as it increases.
  • an inductor through which a large current flows has been increased in size as a countermeasure against saturation.
  • a reduction in inductance in a large current region can be improved by the present DC / DC converter. It is also possible to achieve energy saving and energy saving.
  • FIG. FIG. 4 shows a circuit configuration of the DC / DC converter according to the second embodiment of the present invention, and the following description will focus on the differences from the first embodiment. That is, in FIG. 1 of the first embodiment, the current flowing through the inductor 4, and hence the charging current to the electric double layer capacitor 7, is detected by the current detector 5 connected in series with the inductor 4. In FIG. 3 of the second embodiment, the calculation means 8 calculates the predetermined charging power value and the charging voltage detection value of the electric double layer capacitor 7 detected from the DC output terminal 6a.
  • the increase in the charging current detected by calculation from the commanded predetermined charging power value and the charging voltage detection value of electric double layer capacitor 7 is increased. Accordingly, the PWM control switching frequency is increased stepwise, so that an increase in the charging current ripple is suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably. Furthermore, since the current detector 5 is unnecessary, there is an advantage that the configuration is simplified and the cost is reduced as compared with the case of the first embodiment.
  • FIG. 5 shows the circuit configuration of the DC / DC converter according to the third embodiment of the present invention, and the following description will focus on the differences from the first embodiment. That is, in FIG. 1 of the first embodiment, the analog output from the current detector 5 that detects the current flowing through the inductor 4 and the DC output terminal 6a that detects the voltage of the electric double layer capacitor 7 is directly input to the computing means 8. In FIG. 5 of the third embodiment, the analog value is converted into a digital value through the newly provided A / D converter 10 and A / D converter 11, respectively. The detected value is sent to the calculation means 12 for processing.
  • the switching frequency corresponding to the charging current value can be changed in a stepped manner.
  • the inductor current-inductance characteristics can be self-learned, and by taking into account the self-learned characteristics, the suppression of charging current ripple by switching the switching frequency can be further improved. It can be performed with high accuracy.
  • the inductor current-inductance characteristic for example, as shown in FIG. 6A, the maximum and minimum points of the inductor current are detected from the current waveform of the inductor 4, and the inductance L Is calculated by the following equation.
  • the inductor current-inductance characteristic is self-learned, and as a result, more appropriate switching frequency switching processing can be performed.
  • the PWM control is performed according to the increase in the charging current detected by the current detector 5 and further converted into a digital value by the A / D converter 10. Since the switching frequency is increased stepwise, an increase in the ripple amount of the charging current is more appropriately suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably.
  • FIG. 7 shows a circuit configuration of the DC / DC converter according to the fourth embodiment of the present invention, and the following description will focus on the parts different from the second embodiment. That is, in FIG. 4 of the second embodiment, the current flowing through the inductor 4 is detected from the commanded predetermined charging power value and the detected value of the charging voltage of the electric double layer capacitor 7 based on the analog detected value detected from the DC output terminal 6a. In FIG. 6 of the fourth embodiment, the A / D converter 11 is newly provided and detected from the commanded predetermined charging power value and the DC output terminal 6a. Further, it is obtained by calculation by the calculation means 12 from the charge voltage detection value of the electric double layer capacitor 7 obtained by conversion into a digital detection value by the A / D converter 11.
  • the increase in the charging current detected by calculation from the commanded predetermined charging power value and the charging voltage detection value of electric double layer capacitor 7 is increased. Accordingly, the PWM control switching frequency is increased stepwise, so that an increase in the charging current ripple is suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably. Further, since the charging current is calculated using the digital detection value obtained via the A / D converter 11 as the charging voltage detection value of the electric double layer capacitor 7, it is compared with the case of the second embodiment. Thus, the charging current is calculated with higher accuracy, the increase of the ripple of the charging current is more appropriately suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably.
  • Embodiment 5 The circuit configuration of the DC / DC converter according to the fifth embodiment of the present invention is the same as that shown in FIG. Also, the operation of the DC / DC converter in the fifth embodiment of the present invention is basically the same as that described in the third embodiment, and the description thereof will be omitted.
  • the difference is that, in the calculation unit 12, the switching frequency is set while the charging current value and the switching frequency have a linear function according to the charging current value detected by the current detector 5. Continuously variable. Thereby, the high frequency ripple current flowing through the electric double layer capacitor 7 can be suppressed more accurately and appropriately. In analog control, it is difficult to continuously change the switching frequency by a function, but in digital control, it can be easily realized.
  • the charging current value and the switching frequency are continuously varied while having a quadratic function relationship, so that the electric double layer capacitor 7 can be appropriately and accurately adjusted.
  • the flowing high frequency ripple current can be suppressed.
  • the linear function is applied to the charging current value detected by the current detector 5 and further converted into a digital value by the A / D converter 10 and the switching frequency.
  • the linear function is applied to the charging current value detected by the current detector 5 and further converted into a digital value by the A / D converter 10 and the switching frequency.
  • Embodiment 6 The circuit configuration of the DC / DC converter according to the sixth embodiment of the present invention is the same as that shown in FIG.
  • the commanded predetermined charge power value and the charge voltage detection value of the electric double layer capacitor 7 are further calculated from the digital detection value obtained via the A / D converter 11.
  • the switching frequency is continuously changed with the characteristics of the linear function or the quadratic function. Yes. Accordingly, an increase in the ripple amount of the charging current is more appropriately suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably.
  • Embodiment 7 FIG.
  • the core shape of the inductor 4 satisfying the relationship between the inductor current and the inductance shown in the second graphs of FIGS. 2 and 3 and FIGS. 8 and 9 of the previous embodiments.
  • Various modifications will be described with reference to FIG.
  • FIG. 10 (a) is the most general type in which a gap layer having a constant distance is provided between two core legs.
  • FIG. 10 (b) shows a gap having a constant distance between the core leg and a remaining part. This type is provided.
  • FIG. 10 (c) is a type in which a gap is changed according to the opposite location of the core by giving a certain inclination to one core leg
  • FIG. 10 (d) shows a magnetic field that is easily saturated between the two core legs.
  • This is a type that sandwiches the body 100.
  • FIG. 10 (e) is a type in which a valley shape is applied to one core leg to change the gap according to the location where the core leg faces
  • FIG. 10 (f) is a W shape applied to one core leg. With this type, the gap is changed according to the location where the core leg faces. Further, it is possible to easily align the two cores by cutting a groove at a position opposite to the core leg not having the W shape in FIG.

Abstract

Disclosed is a DC-DC converter, which is provided with: a DC-DC conversion device, which has switching elements (3a-3d) and an inductor (4), converts the voltage of an inputting direct current power supply (1) by driving the switching elements to turn on/off at predetermined switching frequencies, and which charges an electrical storage means (7); a current detecting means (5), which detects a current flowing in the inductor (4); and control means (8, 9), which transmit PWM (pulse width modulation) controlled on/off drive signals such that the electrical storage means (4) is charged with instructed predetermined charge power. The control means (8, 9) change the switching frequencies of the on/off drive signals to be transmitted to the switching elements corresponding to the current in the inductor (4), said current having been detected by means of the current detecting means (5).

Description

ＤＣ／ＤＣコンバータDC / DC converter
　本発明は、電気二重層キャパシタ等の大容量を特徴とする蓄電手段に大電流でエネルギーを蓄電するＤＣ／ＤＣコンバータに関するものである。 The present invention relates to a DC / DC converter that stores energy with a large current in a storage means characterized by a large capacity such as an electric double layer capacitor.
　電気二重層キャパシタ等の大容量を特徴とする蓄電手段に対して、大電流で充電を行うことにより大きなエネルギーを蓄電することが可能である。
　従来、電気二重層キャパシタ等の蓄電手段への蓄電を行う場合、例えば、特許文献１に示されるような回路構成が用いられており、電気二重層キャパシタ等の蓄電手段への充電はエネルギー変換器であるＤＣ／ＤＣコンバータを介して行われる。 It is possible to store a large amount of energy by charging a power storage unit characterized by a large capacity such as an electric double layer capacitor with a large current.
Conventionally, when power is stored in a power storage means such as an electric double layer capacitor, for example, a circuit configuration as shown in Patent Document 1 is used, and charging to the power storage means such as an electric double layer capacitor is performed by an energy converter. This is done via a DC / DC converter.
特開平０７－２３１５１１号公報（第１図）Japanese Patent Laid-Open No. 07-231511 (FIG. 1)
　ところで、蓄電手段として電気二重層キャパシタを使用する場合、その等価直列抵抗は、アルミ電解キャパシタなどの他のキャパシタに比べると圧倒的に大きいため、大きな高周波リプル電流を流すことができないという問題がある。そして、この電気二重層キャパシタに所定の電力で蓄電する場合、特に、電気二重層キャパシタ電圧が低い時に、ＤＣ／ＤＣコンバータから大きな充電電流を電気二重層キャパシタに供給する必要がある。
　ＤＣ／ＤＣコンバータが電気二重層キャパシタに大きな充電電流を供給する際、ＤＣ／ＤＣコンバータの構成要素であるインダクタに大きな電流が流れることになり、その電流値に応じて急激なインダクタンス低下が発生する。その結果、電気二重層キャパシタへの充電電流でもあるＤＣ／ＤＣコンバータの出力電流のリプル分が大きくなり、電気二重層キャパシタの特性を大幅に悪化させ、または、電気二重層キャパシタの急激な温度上昇により故障に至ることがあるという問題があった。この問題は電気二重層キャパシタ以外の大容量の蓄電装置、例えばリチウムイオン電池等の２次電池でも発生することがある。 By the way, when an electric double layer capacitor is used as a power storage means, its equivalent series resistance is overwhelmingly large compared to other capacitors such as an aluminum electrolytic capacitor, and therefore there is a problem that a large high-frequency ripple current cannot flow. . When storing electric power in the electric double layer capacitor with a predetermined power, it is necessary to supply a large charging current from the DC / DC converter to the electric double layer capacitor, particularly when the electric double layer capacitor voltage is low.
When the DC / DC converter supplies a large charging current to the electric double layer capacitor, a large current flows through the inductor, which is a component of the DC / DC converter, and an abrupt inductance drop occurs depending on the current value. . As a result, the ripple of the output current of the DC / DC converter, which is also the charging current for the electric double layer capacitor, is increased, the characteristics of the electric double layer capacitor are greatly deteriorated, or the temperature of the electric double layer capacitor is rapidly increased. There was a problem that it might lead to failure. This problem may also occur in a large-capacity power storage device other than the electric double layer capacitor, for example, a secondary battery such as a lithium ion battery.
　本発明は上記の課題を解決するためになされたものであり、電気二重層キャパシタ等の蓄電手段への充電を行う場合、ＤＣ／ＤＣコンバータの出力電流が大きくなってもそのリプル分の増大を抑制して、電気二重層キャパシタ等の蓄電手段を効率良く確実に充電することができるＤＣ／ＤＣコンバータを提供することを目的としている。 The present invention has been made to solve the above problems, and when charging an electric storage means such as an electric double layer capacitor, even if the output current of the DC / DC converter increases, the ripple amount is increased. It is an object of the present invention to provide a DC / DC converter that can suppress and efficiently and reliably charge power storage means such as an electric double layer capacitor.
　この発明のＤＣ／ＤＣコンバータは、スイッチング素子とインダクタとを有しスイッチング素子を所定のスイッチング周波数でオンオフ駆動して入力直流電源の電圧を変換し蓄電手段に出力して当該蓄電手段を充電するＤＣ／ＤＣ変換器、インダクタに流れる電流を検出する電流検出手段、および指令された所定の充電電力で蓄電手段を充電するようＰＷＭ（パルス幅変調）制御によるオンオフ駆動信号をスイッチング素子に送出する制御手段を備え、
　制御手段は、電流検出手段で検出したインダクタの電流に応じてスイッチング素子に送出するオンオフ駆動信号のスイッチング周波数を変化させるようにしたものである。 The DC / DC converter according to the present invention includes a switching element and an inductor, and the switching element is turned on / off at a predetermined switching frequency to convert the voltage of the input DC power source and output it to the storage means to charge the storage means. DC / DC converter, current detection means for detecting current flowing through the inductor, and control means for sending an ON / OFF drive signal by PWM (pulse width modulation) control to the switching element so as to charge the storage means with the commanded predetermined charging power With
The control means changes the switching frequency of the on / off drive signal sent to the switching element in accordance with the inductor current detected by the current detection means.
　この発明のＤＣ／ＤＣコンバータによれば、制御手段が、電流検出手段で検出したインダクタの電流に応じてスイッチング素子に送出するオンオフ駆動信号のスイッチング周波数を変化させるようにしたので、インダクタに流れる電流が大きい範囲においてもその電流のリプル分の増大が抑制され、蓄電手段を効率良く確実に充電することができる。 According to the DC / DC converter of the present invention, since the control means changes the switching frequency of the on / off drive signal sent to the switching element in accordance with the inductor current detected by the current detection means, the current flowing through the inductor Even in a large range, an increase in the ripple of the current is suppressed, and the power storage means can be charged efficiently and reliably.
本発明の実施の形態１によるＤＣ／ＤＣコンバータの構成を示す回路図である。It is a circuit diagram which shows the structure of the DC / DC converter by Embodiment 1 of this invention. 本発明の実施の形態１によるＤＣ／ＤＣコンバータの各部特性を模式的に示す図である。It is a figure which shows typically each part characteristic of the DC / DC converter by Embodiment 1 of this invention. 本発明の実施の形態１によるＤＣ／ＤＣコンバータの各部特性を模式的に示す図である。It is a figure which shows typically each part characteristic of the DC / DC converter by Embodiment 1 of this invention. 本発明の実施の形態２によるＤＣ／ＤＣコンバータの構成を示す回路図である。It is a circuit diagram which shows the structure of the DC / DC converter by Embodiment 2 of this invention. 本発明の実施の形態３によるＤＣ／ＤＣコンバータの構成を示す回路図である。It is a circuit diagram which shows the structure of the DC / DC converter by Embodiment 3 of this invention. 本発明の実施の形態３によるＤＣ／ＤＣコンバータにおいて、自己学習でインダクタ電流－インダクタンス特性を求める方法を説明するための図である。In the DC / DC converter according to Embodiment 3 of the present invention, it is a diagram for explaining a method for obtaining inductor current-inductance characteristics by self-learning. 本発明の実施の形態４によるＤＣ／ＤＣコンバータの構成を示す回路図である。It is a circuit diagram which shows the structure of the DC / DC converter by Embodiment 4 of this invention. 本発明の実施の形態６によるＤＣ／ＤＣコンバータの各部特性を模式的に示す図である。It is a figure which shows typically each part characteristic of the DC / DC converter by Embodiment 6 of this invention. 本発明の実施の形態６によるＤＣ／ＤＣコンバータの各部特性を模式的に示す図である。It is a figure which shows typically each part characteristic of the DC / DC converter by Embodiment 6 of this invention. 本発明の実施の形態７によるインダクタのコア形状の種別を模式的に示す図である。It is a figure which shows typically the classification of the core shape of the inductor by Embodiment 7 of this invention.
実施の形態１．
　先ず、本発明の実施の形態１におけるＤＣ／ＤＣコンバータの回路構成について、図１に基づいて説明する。
　図１に示すように、入力直流電源１は必要な電圧範囲を有する直流安定化電圧をＤＣ／ＤＣコンバータに供給するために、ＤＣ／ＤＣコンバータの直流入力端子２ａおよび２ｂに接続されている。第１のスイッチング素子であるＭＯＳＦＥＴ３ａのドレイン端子が直流入力端子２ａに接続されており、第２のスイッチング素子であるＭＯＳＦＥＴ３ｂのソース端子が直流入力端子２ｂに接続されている。第１のスイッチング素子であるＭＯＳＦＥＴ３ａのソース端子と、第２のスイッチング素子であるＭＯＳＦＥＴ３ｂのドレイン端子と、インダクタ４の一方の端子とが接続されている。インダクタ４の他方の端子が、電流検出器５の端子５ａに接続されている。電流検出器５の端子５ｂと、第３のスイッチング素子であるＭＯＳＦＥＴ３ｃのソース端子と、第４のスイッチング素子であるＭＯＳＦＥＴ３ｄのドレイン端子とが接続されている。そして、第３のスイッチング素子であるＭＯＳＦＥＴ３ｃのドレイン端子が直流出力端子６ａに接続されており、第２のスイッチング素子であるＭＯＳＦＥＴ３ｂのソース端子と、第４のスイッチング素子であるＭＯＳＦＥＴ３ｄのソース端子と、直流出力端子６ｂとが接続され接地されている。
　ここで、第１～第４のスイッチング素子であるＭＯＳＦＥＴ３ａ～３ｄとインダクタ４とにより、本願特許請求の範囲に示すＤＣ／ＤＣ変換器を構成する。 Embodiment 1 FIG.
First, the circuit configuration of the DC / DC converter according to Embodiment 1 of the present invention will be described with reference to FIG.
As shown in FIG. 1, an input DC power supply 1 is connected to DC input terminals 2a and 2b of a DC / DC converter in order to supply a DC stabilized voltage having a necessary voltage range to the DC / DC converter. The drain terminal of the MOSFET 3a that is the first switching element is connected to the DC input terminal 2a, and the source terminal of the MOSFET 3b that is the second switching element is connected to the DC input terminal 2b. The source terminal of the MOSFET 3a that is the first switching element, the drain terminal of the MOSFET 3b that is the second switching element, and one terminal of the inductor 4 are connected. The other terminal of the inductor 4 is connected to the terminal 5 a of the current detector 5. The terminal 5b of the current detector 5, the source terminal of the MOSFET 3c that is the third switching element, and the drain terminal of the MOSFET 3d that is the fourth switching element are connected. The drain terminal of the MOSFET 3c as the third switching element is connected to the DC output terminal 6a, the source terminal of the MOSFET 3b as the second switching element, the source terminal of the MOSFET 3d as the fourth switching element, The DC output terminal 6b is connected and grounded.
Here, the MOSFETs 3a to 3d, which are the first to fourth switching elements, and the inductor 4 constitute a DC / DC converter shown in the claims of the present application.
　電気二重層キャパシタ７は、直流出力端子６ａ及び６ｂに接続されている。電流検出器５の端子５ｃが演算手段８の端子８ａと接続され、直流出力端子６ａが演算手段８の端子８ｂに接続されている。
　演算手段８の端子８ｃは、ＰＷＭ制御手段９の端子９ｅに接続されている。第１のスイッチング素子であるＭＯＳＦＥＴ３ａのゲート端子とＰＷＭ制御手段９の端子９ａが接続され、第２のスイッチング素子であるＭＯＳＦＥＴ３ｂのゲート端子とＰＷＭ制御手段９の端子９ｂが接続され、第３のスイッチング素子であるＭＯＳＦＥＴ３ｃのゲート端子とＰＷＭ制御手段９の端子９ｃが接続され、第４のスイッチング素子であるＭＯＳＦＥＴ３ｄのゲート端子とＰＷＭ制御手段９の端子９ｄが接続されている。
　ここで、演算手段８とＰＷＭ制御手段９とにより、本願特許請求の範囲に示す制御手段を構成する。 The electric double layer capacitor 7 is connected to the DC output terminals 6a and 6b. The terminal 5 c of the current detector 5 is connected to the terminal 8 a of the calculation means 8, and the DC output terminal 6 a is connected to the terminal 8 b of the calculation means 8.
The terminal 8 c of the calculation means 8 is connected to the terminal 9 e of the PWM control means 9. The gate terminal of the MOSFET 3a which is the first switching element and the terminal 9a of the PWM control means 9 are connected, the gate terminal of the MOSFET 3b which is the second switching element and the terminal 9b of the PWM control means 9 are connected, and the third switching The gate terminal of the MOSFET 3c as the element and the terminal 9c of the PWM control means 9 are connected, and the gate terminal of the MOSFET 3d as the fourth switching element and the terminal 9d of the PWM control means 9 are connected.
Here, the calculation means 8 and the PWM control means 9 constitute the control means shown in the claims of the present application.
　次に、本発明の実施の形態１におけるＤＣ／ＤＣコンバータの動作について図１～図３を用いて説明する。なお、図２は、電気二重層キャパシタ７の両端電圧が低い時（ＶＣ１）の各部の特性を示し、図３は、電気二重層キャパシタ７の両端電圧が高い時（ＶＣ２）の各部の特性を示す。 Next, the operation of the DC / DC converter according to Embodiment 1 of the present invention will be described with reference to FIGS. 2 shows the characteristics of each part when the voltage across the electric double layer capacitor 7 is low (V C1 ), and FIG. 3 shows the characteristics of each part when the voltage across the electric double layer capacitor 7 is high (V C2 ). Show the characteristics.
　入力直流電源１が直流入力端子２ａおよび２ｂに印加されると、その時点での電気二重層キャパシタ７の両端電圧が検出されて演算手段８に入力される。また、電流検出器５で検出された電流値と目標電流値からデューティ比（オンオフ比）を演算手段８で演算し、ＰＷＭ制御手段９を介してＰＷＭ（パルス幅変調）制御によるオンオフ駆動信号を生成する。このオンオフ駆動信号は、第１～第４のスイッチング素子であるＭＯＳＦＥＴ３ａ～３ｄのゲート端子に送出され、各スイッチング素子ＭＯＳＦＥＴ３ａ～３ｄをオンオフ駆動させる。 When the input DC power source 1 is applied to the DC input terminals 2a and 2b, the voltage across the electric double layer capacitor 7 at that time is detected and input to the computing means 8. Further, the duty ratio (on / off ratio) is calculated by the calculation means 8 from the current value detected by the current detector 5 and the target current value, and an on / off drive signal by PWM (pulse width modulation) control is supplied via the PWM control means 9. Generate. This on / off drive signal is sent to the gate terminals of the MOSFETs 3a to 3d, which are the first to fourth switching elements, to drive the switching element MOSFETs 3a to 3d on and off.
　電気二重層キャパシタ７への充電は、指令された所定の充電電力で行われる。これは、例えば、発電機等で発電する回生電力を電気二重層キャパシタ７に蓄電する様な場合を想定したものである。このため、図２及び図３の最上段のグラフに示すように、充電が進んで電気二重層キャパシタ７の両端電圧が上昇していくと、充電電流は減少していくという特有の特性がある。従って、電気二重層キャパシタ７の両端電圧が低い状態では、大きな充電電流を供給することになる。 The charging to the electric double layer capacitor 7 is performed with the commanded predetermined charging power. This assumes a case where regenerative power generated by a generator or the like is stored in the electric double layer capacitor 7, for example. For this reason, as shown in the uppermost graphs of FIGS. 2 and 3, there is a characteristic that the charging current decreases as the charging progresses and the voltage across the electric double layer capacitor 7 increases. . Therefore, when the voltage across the electric double layer capacitor 7 is low, a large charging current is supplied.
　また、インダクタ４は、それに使用されている鉄心の磁気特性から、図２及び図３の２段目のグラフに示すように、インダクタ４に一定以上の大きな電流が流れると、電流値に応じて急激なインダクタンス低下が発生する。
　この結果、背景技術で既述したように、充電電流の大きい範囲でそのリプル分が増大し、電気二重層キャパシタ７に支障を及ぼすことになる。 Further, the inductor 4 has a magnetic characteristic of the iron core used in the inductor 4, and when a large current of a certain level or more flows through the inductor 4 as shown in the second graph of FIGS. A sudden inductance drop occurs.
As a result, as already described in the background art, the ripple amount increases in the range where the charging current is large, and the electric double layer capacitor 7 is hindered.
　そこで、本発明の実施の形態１では、図２及び図３の３段目のグラフに示すように、電流検出器５で検出された充電電流値と複数の切換基準電流値との比較を行い、充電電流値に応じてＰＷＭ制御のスイッチング周波数をステップ状に切換えていく。
　これにより、充電電流値が大きいとき（インダクタ平均電流ＩＬ＝ＩＬ１：図２）は、スイッチング周波数が高くなり、早いタイミングでスイッチイング素子がオフされることで、リプル電流の増大を抑制できる。また、充電電流値が小さいとき（インダクタ平均電流ＩＬ＝ＩＬ２：図３）は、インダクタ４のインダクタンス低下が無いのでインダクタ電流のリプル分は一定の範囲に留まっており、スイッチング周波数は低いレベルとしてスイッチング損失の増加を抑制している。
　図２及び図３の最下段のグラフは、充電電流値の大小に拘わらず、リプル電流分がほぼ一定の、電気二重層キャパシタ７の許容リプル電流範囲内に保たれていることを示している。 Therefore, in the first embodiment of the present invention, as shown in the third graph of FIGS. 2 and 3, the charging current value detected by the current detector 5 is compared with a plurality of switching reference current values. The switching frequency of PWM control is switched stepwise according to the charging current value.
As a result, when the charging current value is large (inductor average current IL = IL1: FIG. 2), the switching frequency becomes high, and the switching element is turned off at an early timing, thereby suppressing an increase in the ripple current. Further, when the charging current value is small (inductor average current IL = IL2: FIG. 3), since the inductance of the inductor 4 does not decrease, the ripple of the inductor current remains in a certain range, and the switching frequency is switched to a low level. The increase in loss is suppressed.
The graphs at the bottom of FIGS. 2 and 3 show that the ripple current component is maintained within the allowable ripple current range of the electric double layer capacitor 7 regardless of the magnitude of the charging current value. .
　以上のように、本発明の実施の形態１におけるＤＣ／ＤＣコンバータにおいては、電流検出器５で検出される充電電流の増大に応じてＰＷＭ制御のスイッチング周波数をステップ状に増大させるようにしたので、充電電流のリプル分の増大が抑制され電気二重層キャパシタ７を効率良く確実に充電することができる。 As described above, in the DC / DC converter according to Embodiment 1 of the present invention, the switching frequency of PWM control is increased stepwise in accordance with the increase in the charging current detected by the current detector 5. As a result, an increase in the ripple amount of the charging current is suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably.
　なお、本発明の実施の形態１では、スイッチング素子としてＭＯＳＦＥＴを用いて説明を行ったが、バイポーラトランジスタ、または絶縁型バイポーラトランジスタ（ＩＧＢＴ）、さらに炭化珪素等のワイドバンドギャップ半導体により形成されたトランジスタ（ＩＧＢＴ）やＭＯＳＦＥＴを用いても同様の効果が得られる。 Although the first embodiment of the present invention has been described using a MOSFET as a switching element, a bipolar transistor, an insulated bipolar transistor (IGBT), or a transistor formed of a wide band gap semiconductor such as silicon carbide. The same effect can be obtained by using (IGBT) or MOSFET.
　また、本発明の実施の形態１では、ＤＣ／ＤＣコンバータにおける主回路であるＤＣ／ＤＣ変換器として非絶縁型昇降圧コンバータ回路を用いた場合の説明を行ったが、本発明はそれ以外の種々のインダクタを用いる非絶縁形コンバータ回路あるいは絶縁形コンバータ回路にも適用できる。 In the first embodiment of the present invention, the case where a non-insulated buck-boost converter circuit is used as the DC / DC converter which is the main circuit in the DC / DC converter has been described. The present invention can also be applied to a non-insulated converter circuit or an isolated converter circuit using various inductors.
　なお、本発明の実施の形態１では、蓄電手段として電気二重層キャパシタを用いて説明を行ったが、２次電池を用いても同様の効果が得られる。
　更に、本発明の実施の形態１では、インダクタの特性として所定の電流値まではインダクタンスは一定値で、所定の電流値以上ではインダクタンスが減少する特性のもので説明を行ったが、インダクタ電流の増加に伴って右肩下がりの減少傾向を示す特性のインダクタを用いても同様の効果が得られる。 In the first embodiment of the present invention, an electric double layer capacitor is used as the power storage means, but the same effect can be obtained even when a secondary battery is used.
Furthermore, in the first embodiment of the present invention, the inductor has a characteristic that the inductance is a constant value up to a predetermined current value and the inductance is decreased above the predetermined current value. A similar effect can be obtained by using an inductor having a characteristic of decreasing to the right as it increases.
　また、従来は大きな電流が流れるインダクタは飽和対策のため大型化していたが、本発明の実施の形態１では、大電流領域でのインダクタンス低下は本ＤＣ／ＤＣコンバータで改善できるため、インダクタを小型化、また省エネ化できる効果も得られる。 Conventionally, an inductor through which a large current flows has been increased in size as a countermeasure against saturation. However, in the first embodiment of the present invention, a reduction in inductance in a large current region can be improved by the present DC / DC converter. It is also possible to achieve energy saving and energy saving.
実施の形態２．
　図４は、本発明の実施の形態２におけるＤＣ／ＤＣコンバータの回路構成を示し、以下、先の実施の形態１と異なる部分を中心に説明する。
　即ち、先の実施の形態１の図１では、インダクタ４に流れる電流、従って、電気二重層キャパシタ７への充電電流を、インダクタ４と直列に接続された電流検出器５により検出していたが、この実施の形態２の図３では、指令された所定の充電電力値と直流出力端子６ａから検出される電気二重層キャパシタ７の充電電圧検出値とから演算手段８により演算で求めている。 Embodiment 2. FIG.
FIG. 4 shows a circuit configuration of the DC / DC converter according to the second embodiment of the present invention, and the following description will focus on the differences from the first embodiment.
That is, in FIG. 1 of the first embodiment, the current flowing through the inductor 4, and hence the charging current to the electric double layer capacitor 7, is detected by the current detector 5 connected in series with the inductor 4. In FIG. 3 of the second embodiment, the calculation means 8 calculates the predetermined charging power value and the charging voltage detection value of the electric double layer capacitor 7 detected from the DC output terminal 6a.
　この充電電流値検出に係る構成以外の構成および充電に係る動作は、先の実施の形態１の場合と変わるところがないので、説明は省略する。 Since the configuration other than the configuration related to the detection of the charging current value and the operation related to the charging are not different from those in the first embodiment, the description thereof will be omitted.
　以上のように、本発明の実施の形態２におけるＤＣ／ＤＣコンバータにおいては、指令された所定の充電電力値と電気二重層キャパシタ７の充電電圧検出値とから演算により検出される充電電流の増大に応じてＰＷＭ制御のスイッチング周波数をステップ状に増大させるようにしたので、充電電流のリプル分の増大が抑制され電気二重層キャパシタ７を効率良く確実に充電することができる。
　更に、電流検出器５が不要となるので、先の実施の形態１の場合に比較して、その分構成が簡単になりコストも低減するという利点がある。 As described above, in the DC / DC converter according to the second embodiment of the present invention, the increase in the charging current detected by calculation from the commanded predetermined charging power value and the charging voltage detection value of electric double layer capacitor 7 is increased. Accordingly, the PWM control switching frequency is increased stepwise, so that an increase in the charging current ripple is suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably.
Furthermore, since the current detector 5 is unnecessary, there is an advantage that the configuration is simplified and the cost is reduced as compared with the case of the first embodiment.
　なお、実施の形態１の巻末で触れた、スイッチング素子、ＤＣ／ＤＣ変換器、蓄電手段およびインダクタに関しての他の適用例の可能性に係る説明は、この実施の形態２の場合も同様に該当する。 Note that the description relating to the possibility of other application examples relating to the switching element, the DC / DC converter, the power storage means, and the inductor mentioned at the end of the first embodiment also applies to the second embodiment. To do.
実施の形態３．
　図５は、本発明の実施の形態３におけるＤＣ／ＤＣコンバータの回路構成を示し、以下、先の実施の形態１と異なる部分を中心に説明する。
　即ち、先の実施の形態１の図１では、インダクタ４に流れる電流を検出する電流検出器５および電気二重層キャパシタ７の電圧を検出する直流出力端子６ａからのアナログ出力を直接演算手段８に送出して処理していたが、この実施の形態３の図５では、新たに設けた、それぞれＡ／Ｄコンバータ１０およびＡ／Ｄコンバータ１１を介することでアナログ値をデジタル値に変換し、デジタル検出値を演算手段１２に送出して処理している。 Embodiment 3 FIG.
FIG. 5 shows the circuit configuration of the DC / DC converter according to the third embodiment of the present invention, and the following description will focus on the differences from the first embodiment.
That is, in FIG. 1 of the first embodiment, the analog output from the current detector 5 that detects the current flowing through the inductor 4 and the DC output terminal 6a that detects the voltage of the electric double layer capacitor 7 is directly input to the computing means 8. In FIG. 5 of the third embodiment, the analog value is converted into a digital value through the newly provided A / D converter 10 and A / D converter 11, respectively. The detected value is sent to the calculation means 12 for processing.
　これにより、演算手段１２での演算に高機能化を施すことが可能である。充電電流値とスイッチング周波数の相関関係を演算手段１２にプログラムしておくことにより、充電電流値に見合ったスイッチング周波数をステップ状に変化させることができる。 Thus, it is possible to increase the functionality of the calculation in the calculation means 12. By programming the correlation between the charging current value and the switching frequency in the calculating means 12, the switching frequency corresponding to the charging current value can be changed in a stepped manner.
　更に、アナログ処理からデジタル処理にすることで、インダクタ電流－インダクタンス特性を自己学習することができ、自己学習した特性を考慮に入れることで、スイッチング周波数切り換えによる充電電流のリプル分の抑制動作をより精度良く行うことができる。
　インダクタ電流－インダクタンス特性を自己学習する方法としては、例えば、図６（ａ）に示すように、インダクタ４の電流波形からインダクタ電流の最大ポイントと最小ポイントを検出し、その情報を用いてインダクタンスＬを、下式にて演算する。 Furthermore, by switching from analog processing to digital processing, the inductor current-inductance characteristics can be self-learned, and by taking into account the self-learned characteristics, the suppression of charging current ripple by switching the switching frequency can be further improved. It can be performed with high accuracy.
As a method of self-learning the inductor current-inductance characteristic, for example, as shown in FIG. 6A, the maximum and minimum points of the inductor current are detected from the current waveform of the inductor 4, and the inductance L Is calculated by the following equation.
　Ｌ＝（Ｖｉｎ－Ｖｏ）／（ΔＩＬ×Ｔ１）
　但し、
Ｌ：インダクタ４のインダクタンス
Ｖｉｎ：入力直流電源１の電圧
Ｖｏ：電気二重層キャパシタ７の電圧
ΔＩＬ：電流リプル分
Ｔ１：リプル分の半周期の時間 L = (Vin−Vo) / (ΔIL × T1)
However,
L: Inductance Vin of inductor 4: Voltage of input DC power supply 1 Vo: Voltage of electric double layer capacitor 7 ΔIL: Current ripple portion T1: Time of half cycle of ripple
　以上の演算式に基づき、図６（ｂ）に示すように、インダクタ電流－インダクタンス特性を自己学習し、その結果、より適切なスイッチング周波数の切り換え処理を行うことができる。 Based on the above arithmetic expression, as shown in FIG. 6B, the inductor current-inductance characteristic is self-learned, and as a result, more appropriate switching frequency switching processing can be performed.
　このデジタル処理に係る構成以外の構成および充電に係る動作は、先の実施の形態１の場合と変わるところがないので、説明は省略する。 Since the configuration other than the configuration related to the digital processing and the operation related to charging are not different from those in the first embodiment, the description thereof will be omitted.
　以上のように、本発明の実施の形態３におけるＤＣ／ＤＣコンバータにおいては、電流検出器５で検出され更にＡ／Ｄコンバータ１０でデジタル値に変換された充電電流の増大に応じてＰＷＭ制御のスイッチング周波数をステップ状に増大させるようにしたので、充電電流のリプル分の増大がより適切に抑制され電気二重層キャパシタ７を効率良く確実に充電することができる。 As described above, in the DC / DC converter according to the third embodiment of the present invention, the PWM control is performed according to the increase in the charging current detected by the current detector 5 and further converted into a digital value by the A / D converter 10. Since the switching frequency is increased stepwise, an increase in the ripple amount of the charging current is more appropriately suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably.
　なお、実施の形態１の巻末で触れた、スイッチング素子、ＤＣ／ＤＣ変換器、蓄電手段およびインダクタに関しての他の適用例の可能性に係る説明は、この実施の形態３の場合も同様に該当する。 In addition, the description regarding the possibility of the other application examples regarding the switching element, the DC / DC converter, the power storage unit, and the inductor described at the end of the first embodiment also applies to the third embodiment. To do.
実施の形態４．
　図７は、本発明の実施の形態４におけるＤＣ／ＤＣコンバータの回路構成を示し、以下、先の実施の形態２と異なる部分を中心に説明する。
　即ち、先の実施の形態２の図４では、インダクタ４に流れる電流を、指令された所定の充電電力値と直流出力端子６ａから検出されアナログ検出値による電気二重層キャパシタ７の充電電圧検出値とから演算手段８により演算で求めていたが、この実施の形態４の図６では、Ａ／Ｄコンバータ１１を新たに設け、指令された所定の充電電力値と直流出力端子６ａから検出され、更に、Ａ／Ｄコンバータ１１によりデジタル検出値に変換して得られる電気二重層キャパシタ７の充電電圧検出値とから演算手段１２により演算で求めている。 Embodiment 4 FIG.
FIG. 7 shows a circuit configuration of the DC / DC converter according to the fourth embodiment of the present invention, and the following description will focus on the parts different from the second embodiment.
That is, in FIG. 4 of the second embodiment, the current flowing through the inductor 4 is detected from the commanded predetermined charging power value and the detected value of the charging voltage of the electric double layer capacitor 7 based on the analog detected value detected from the DC output terminal 6a. In FIG. 6 of the fourth embodiment, the A / D converter 11 is newly provided and detected from the commanded predetermined charging power value and the DC output terminal 6a. Further, it is obtained by calculation by the calculation means 12 from the charge voltage detection value of the electric double layer capacitor 7 obtained by conversion into a digital detection value by the A / D converter 11.
　この充電電流値検出に係る構成以外の構成および充電に係る動作は、先の実施の形態２の場合と変わるところがないので、説明は省略する。 Since the configuration other than the configuration related to the detection of the charging current value and the operation related to the charging are not different from those in the second embodiment, the description thereof will be omitted.
　以上のように、本発明の実施の形態４におけるＤＣ／ＤＣコンバータにおいては、指令された所定の充電電力値と電気二重層キャパシタ７の充電電圧検出値とから演算により検出される充電電流の増大に応じてＰＷＭ制御のスイッチング周波数をステップ状に増大させるようにしたので、充電電流のリプル分の増大が抑制され電気二重層キャパシタ７を効率良く確実に充電することができる。
　更に、電気二重層キャパシタ７の充電電圧検出値をＡ／Ｄコンバータ１１を介して得られるデジタル検出値を用いて充電電流を演算するようにしたので、先の実施の形態２の場合に比較して、充電電流がより精度良く演算され充電電流のリプル分の増大がより適切に抑制され電気二重層キャパシタ７を効率良く確実に充電することができる。 As described above, in the DC / DC converter according to Embodiment 4 of the present invention, the increase in the charging current detected by calculation from the commanded predetermined charging power value and the charging voltage detection value of electric double layer capacitor 7 is increased. Accordingly, the PWM control switching frequency is increased stepwise, so that an increase in the charging current ripple is suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably.
Further, since the charging current is calculated using the digital detection value obtained via the A / D converter 11 as the charging voltage detection value of the electric double layer capacitor 7, it is compared with the case of the second embodiment. Thus, the charging current is calculated with higher accuracy, the increase of the ripple of the charging current is more appropriately suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably.
　なお、実施の形態１の巻末で触れた、スイッチング素子、ＤＣ／ＤＣ変換器、蓄電手段およびインダクタに関しての他の適用例の可能性に係る説明は、この実施の形態４の場合も同様に該当する。 In addition, the description regarding the possibility of other application examples regarding the switching element, the DC / DC converter, the power storage unit, and the inductor described at the end of the first embodiment also applies to the fourth embodiment. To do.
実施の形態５．
　本発明の実施の形態５におけるＤＣ／ＤＣコンバータの回路構成については、先の実施の形態３の図５で示したものと同様のため、説明を割愛する。
　また、本発明の実施の形態５におけるＤＣ／ＤＣコンバータの動作についても、基本的には先の実施の形態３で説明したものと同様であるため、説明は割愛する。 Embodiment 5 FIG.
The circuit configuration of the DC / DC converter according to the fifth embodiment of the present invention is the same as that shown in FIG.
Also, the operation of the DC / DC converter in the fifth embodiment of the present invention is basically the same as that described in the third embodiment, and the description thereof will be omitted.
　異なる点は、図８に示すように、演算手段１２において、電流検出器５で検出された充電電流値に応じて、充電電流値とスイッチング周波数に１次関数の関係を持たせながらスイッチング周波数を連続的に可変させることである。これにより、更に精度良く適切に、電気二重層キャパシタ７に流れる高周波リプル電流を抑制することができる。
　アナログ制御では、関数によりスイッチング周波数を連続的に変化させることは困難であるが、デジタル制御では容易に実現することができる。 As shown in FIG. 8, the difference is that, in the calculation unit 12, the switching frequency is set while the charging current value and the switching frequency have a linear function according to the charging current value detected by the current detector 5. Continuously variable. Thereby, the high frequency ripple current flowing through the electric double layer capacitor 7 can be suppressed more accurately and appropriately.
In analog control, it is difficult to continuously change the switching frequency by a function, but in digital control, it can be easily realized.
　また、図９に示すように、演算手段１２において、充電電流値とスイッチング周波数に２次関数の関係を持たせながら連続的に可変させることで、更に精度良く適切に、電気二重層キャパシタ７に流れる高周波リプル電流を抑制することができる。 In addition, as shown in FIG. 9, in the calculation means 12, the charging current value and the switching frequency are continuously varied while having a quadratic function relationship, so that the electric double layer capacitor 7 can be appropriately and accurately adjusted. The flowing high frequency ripple current can be suppressed.
　以上のように、本発明の実施の形態５におけるＤＣ／ＤＣコンバータにおいては、電流検出器５で検出され更にＡ／Ｄコンバータ１０でデジタル値に変換された充電電流値とスイッチング周波数に１次関数または２次関数の関係を持たせながら連続的に変化させるようにしたので、充電電流のリプル分の増大がより適切に抑制され電気二重層キャパシタ７を効率良く確実に充電することができる。 As described above, in the DC / DC converter according to Embodiment 5 of the present invention, the linear function is applied to the charging current value detected by the current detector 5 and further converted into a digital value by the A / D converter 10 and the switching frequency. Alternatively, since it is continuously changed while having a quadratic function relationship, an increase in the ripple amount of the charging current is more appropriately suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably.
　なお、実施の形態１の巻末で触れた、スイッチング素子、ＤＣ／ＤＣ変換器、蓄電手段およびインダクタに関しての他の適用例の可能性に係る説明は、この実施の形態５の場合も同様に該当する。 In addition, the description regarding the possibility of other application examples regarding the switching element, the DC / DC converter, the power storage unit, and the inductor mentioned at the end of the first embodiment also applies to the fifth embodiment. To do.
実施の形態６．
　本発明の実施の形態６におけるＤＣ／ＤＣコンバータの回路構成については、先の実施の形態４の図７で示したものと同様のため、説明を割愛する。
　そして、この実施の形態６の演算手段１２では、指令された所定の充電電力値と電気二重層キャパシタ７の充電電圧検出値を更にＡ／Ｄコンバータ１１を介して得られるデジタル検出値とから演算により検出される充電電流に対して、先の実施の形態５の図８及び図９で説明したように、１次関数または２次関数の特性を持たせてスイッチング周波数を連続的に変化させている。
　従って、充電電流のリプル分の増大がより適切に抑制され電気二重層キャパシタ７を効率良く確実に充電することができる。 Embodiment 6 FIG.
The circuit configuration of the DC / DC converter according to the sixth embodiment of the present invention is the same as that shown in FIG.
In the calculation means 12 of the sixth embodiment, the commanded predetermined charge power value and the charge voltage detection value of the electric double layer capacitor 7 are further calculated from the digital detection value obtained via the A / D converter 11. As described with reference to FIGS. 8 and 9 of the fifth embodiment, the switching frequency is continuously changed with the characteristics of the linear function or the quadratic function. Yes.
Accordingly, an increase in the ripple amount of the charging current is more appropriately suppressed, and the electric double layer capacitor 7 can be charged efficiently and reliably.
　なお、実施の形態１の巻末で触れた、スイッチング素子、ＤＣ／ＤＣ変換器、蓄電手段およびインダクタに関しての他の適用例の可能性に係る説明は、この実施の形態６の場合も同様に該当する。 In addition, the description regarding the possibility of the other application examples regarding the switching element, the DC / DC converter, the power storage unit, and the inductor mentioned at the end of the first embodiment also applies to the sixth embodiment. To do.
実施の形態７．
　この実施の形態７では、先の各実施の形態の図２及び図３や図８及び図９の第２段目のグラフで示した、インダクタ電流とインダクタンスの関係を満足するインダクタ４のコア形状の各種変形例を図１０を参照して説明する。 Embodiment 7 FIG.
In the seventh embodiment, the core shape of the inductor 4 satisfying the relationship between the inductor current and the inductance shown in the second graphs of FIGS. 2 and 3 and FIGS. 8 and 9 of the previous embodiments. Various modifications will be described with reference to FIG.
　インダクタ電流とインダクタンスの間には、所定のインダクタ電流限度までは一定のインダクタンスを維持し、当該電流限度以上ではインダクタが徐々に飽和を行いインダクタンスが減少していく特性を実現させるインダクタのコア形状を図１０（ａ）～図１０（ｆ）に示す。
　図１０（ａ）は、２つのコア脚間に一定距離のギャップ層を設ける最も一般的なタイプであり、図１０（ｂ）は、一部分のみコア脚を接触させ残りの部分に一定距離のギャップを設けるタイプである。 Between the inductor current and the inductance, a constant inductance is maintained up to a predetermined inductor current limit. 10 (a) to 10 (f).
FIG. 10 (a) is the most general type in which a gap layer having a constant distance is provided between two core legs. FIG. 10 (b) shows a gap having a constant distance between the core leg and a remaining part. This type is provided.
　図１０（ｃ）は、１つのコア脚に一定の傾斜をつけることでコアの対向場所に応じてギャップを変えるタイプであり、図１０（ｄ）は、２つのコア脚間に飽和しやすい磁性体１００を挟むタイプである。図１０（ｅ）は、１つのコア脚に谷形状を施すことでコア脚の対向場所に応じてギャップを変えるタイプであり、図１０（ｆ）は、１つのコア脚にＷ形状を施すことでコア脚の対向場所に応じてギャップを変えるタイプである。
　また、図１０（ｆ）のＷ形状を施していないコア脚の対向場所に溝を切り込むことで、２つのコア位置合わせを容易にすることが可能になる。 FIG. 10 (c) is a type in which a gap is changed according to the opposite location of the core by giving a certain inclination to one core leg, and FIG. 10 (d) shows a magnetic field that is easily saturated between the two core legs. This is a type that sandwiches the body 100. FIG. 10 (e) is a type in which a valley shape is applied to one core leg to change the gap according to the location where the core leg faces, and FIG. 10 (f) is a W shape applied to one core leg. With this type, the gap is changed according to the location where the core leg faces.
Further, it is possible to easily align the two cores by cutting a groove at a position opposite to the core leg not having the W shape in FIG.

Claims (8)

  1. 　スイッチング素子とインダクタとを有し前記スイッチング素子を所定のスイッチング周波数でオンオフ駆動して入力直流電源の電圧を変換し蓄電手段に出力して当該蓄電手段を充電するＤＣ／ＤＣ変換器、
    　前記インダクタに流れる電流を検出する電流検出手段、
    　指令された所定の充電電力で前記蓄電手段を充電するようＰＷＭ（パルス幅変調）制御によるオンオフ駆動信号を前記スイッチング素子に送出する制御手段を備えたＤＣ／ＤＣコンバータにおいて、
    　前記制御手段は、前記電流検出手段で検出した前記インダクタの電流に応じて前記スイッチング素子に送出するオンオフ駆動信号のスイッチング周波数を変化させるようにしたＤＣ／ＤＣコンバータ。     A DC / DC converter having a switching element and an inductor, driving the switching element on and off at a predetermined switching frequency, converting the voltage of the input DC power supply, outputting the voltage to the storage means, and charging the storage means;
    Current detecting means for detecting a current flowing through the inductor;
    In a DC / DC converter comprising control means for sending an ON / OFF drive signal by PWM (pulse width modulation) control to the switching element so as to charge the power storage means with a prescribed charging power commanded,
    The DC / DC converter wherein the control means changes a switching frequency of an on / off drive signal sent to the switching element in accordance with the current of the inductor detected by the current detection means.
  2. 　前記制御手段は、前記インダクタに流れる電流の増大に応じて前記スイッチング周波数をステップ状に変化させるようにした請求項１に記載のＤＣ／ＤＣコンバータ。 2. The DC / DC converter according to claim 1, wherein the control means changes the switching frequency stepwise in accordance with an increase in current flowing through the inductor.
  3. 　前記制御手段は、前記インダクタに流れる電流の増大に応じて前記スイッチング周波数を前記電流の１次関数特性で変化させるようにした請求項１に記載のＤＣ／ＤＣコンバータ。 2. The DC / DC converter according to claim 1, wherein the control means changes the switching frequency with a linear function characteristic of the current in accordance with an increase in current flowing through the inductor.
  4. 　前記制御手段は、前記インダクタに流れる電流の増大に応じて前記スイッチング周波数を前記電流の２次関数特性で変化させるようにした請求項１に記載のＤＣ／ＤＣコンバータ。 2. The DC / DC converter according to claim 1, wherein the control means changes the switching frequency according to a quadratic function characteristic of the current according to an increase in current flowing through the inductor.
  5. 　前記電流検出手段は、前記インダクタと直列に接続され前記インダクタに流れる電流を直接検出する電流検出器である請求項１から請求項４のいずれか１項に記載のＤＣ／ＤＣコンバータ。 The DC / DC converter according to any one of claims 1 to 4, wherein the current detection means is a current detector that is connected in series with the inductor and directly detects a current flowing through the inductor.
  6. 　前記電流検出器で検出した出力をアナログ／デジタル変換するＡ／Ｄコンバータを備え、前記制御手段は、前記Ａ／Ｄコンバータで変換されたデジタル出力に応じて前記スイッチング周波数を変化させるようにした請求項５に記載のＤＣ／ＤＣコンバータ。 An A / D converter for analog / digital conversion of an output detected by the current detector is provided, and the control means changes the switching frequency according to the digital output converted by the A / D converter. Item 6. The DC / DC converter according to Item 5.
  7. 　前記電流検出手段は、前記蓄電手段の電圧を検出する電圧検出手段を備え、前記指令された所定の充電電力の値と前記蓄電手段の電圧の検出値とから前記インダクタに流れる電流を演算により検出する電流演算手段である請求項１から請求項４のいずれか１項に記載のＤＣ／ＤＣコンバータ。 The current detection means includes voltage detection means for detecting the voltage of the power storage means, and detects the current flowing through the inductor from the commanded predetermined charge power value and the voltage detection value of the power storage means by calculation. The DC / DC converter according to any one of claims 1 to 4, wherein the DC / DC converter is a current calculation means.
  8. 　前記電圧検出手段で検出した出力をアナログ／デジタル変換するＡ／Ｄコンバータを備え、前記電流検出手段は、前記指令された所定の充電電力の値と前記Ａ／Ｄコンバータで変換されたデジタル出力とから前記インダクタに流れる電流を演算により検出する電流演算手段であり、前記制御手段は、前記電流演算手段で演算されたデジタル出力に応じて前記スイッチング周波数を変化させるようにした請求項７に記載のＤＣ／ＤＣコンバータ。 An A / D converter that performs analog / digital conversion on the output detected by the voltage detection unit; and the current detection unit includes a value of the commanded predetermined charging power and a digital output converted by the A / D converter. The current calculation means for detecting the current flowing from the inductor to the inductor by calculation, wherein the control means changes the switching frequency according to the digital output calculated by the current calculation means. DC / DC converter.
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