WO2011071250A2 - Procédé et appareil pour turbo décodeur à traitement parallèle - Google Patents

Procédé et appareil pour turbo décodeur à traitement parallèle Download PDF

Info

Publication number
WO2011071250A2
WO2011071250A2 PCT/KR2010/008136 KR2010008136W WO2011071250A2 WO 2011071250 A2 WO2011071250 A2 WO 2011071250A2 KR 2010008136 W KR2010008136 W KR 2010008136W WO 2011071250 A2 WO2011071250 A2 WO 2011071250A2
Authority
WO
WIPO (PCT)
Prior art keywords
decoders
decoder
set forth
data
memory
Prior art date
Application number
PCT/KR2010/008136
Other languages
English (en)
Other versions
WO2011071250A3 (fr
Inventor
Eran Pisek
Yan Wang
Original Assignee
Samsung Electronics Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co., Ltd. filed Critical Samsung Electronics Co., Ltd.
Priority to EP10836146.0A priority Critical patent/EP2510637B1/fr
Publication of WO2011071250A2 publication Critical patent/WO2011071250A2/fr
Publication of WO2011071250A3 publication Critical patent/WO2011071250A3/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6525—3GPP LTE including E-UTRA
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0001—Arrangements for dividing the transmission path
    • H04L5/0003—Two-dimensional division
    • H04L5/0005—Time-frequency
    • H04L5/0007—Time-frequency the frequencies being orthogonal, e.g. OFDM(A), DMT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2739—Permutation polynomial interleaver, e.g. quadratic permutation polynomial [QPP] interleaver and quadratic congruence interleaver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2978—Particular arrangement of the component decoders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2978—Particular arrangement of the component decoders
    • H03M13/2987—Particular arrangement of the component decoders using more component decoders than component codes, e.g. pipelined turbo iterations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3972—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using sliding window techniques or parallel windows
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6519—Support of multiple transmission or communication standards
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0066—Parallel concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03171—Arrangements involving maximum a posteriori probability [MAP] detection

Definitions

  • the present application relates generally to wireless communications devices and, more specifically, to decoding data received by a wireless communication device.
  • a low-density parity-check (LDPC) code is an error correcting code for transmitting a message over a noisy transmission channel.
  • LDPC codes are a class of linear block codes. While LDPC and other error correcting codes cannot guarantee perfect transmission, the probability of lost information can be made as small as desired. LDPC was the first code to allow data transmission rates close to the theoretical maximum known as the Shannon Limit. LDPC was impractical to implement when developed in 1963.
  • Turbo codes discovered in 1993, became the coding scheme of choice in the late 1990s. Turbo codes are used for applications such as deep-space satellite communications. In modern modems designed for emerging high bit rate callular standards such as Long Term Evolution (LTE) and LTE advanced (LTE/ADV), Turbo decoders pose the highest design complexity and consume the most power.
  • LTE Long Term Evolution
  • LTE/ADV LTE advanced
  • a receiver capable of decoding encoded transmissions includes a number of receive antennas configure to receive data; a plurality of memory units that store the received data; and a plurality of decoders configured to perform a Turbo decoding operation. Each of the plurality of decoders decodes at least a portion of the received data using at least a portion of a decoding matrix.
  • the receiver also includes a data switch coupled between the plurality of decoders and the plurality of memory units. The data switch configured to vary a decode operation from an long term evolution (LTE) based operation to a Wideband Code Division Multiple Access (WCDMA) operation.
  • LTE long term evolution
  • WCDMA Wideband Code Division Multiple Access
  • a decoder capable of decoding encoded transmissions includes a plurality of memory units that store data.
  • the decoder also includes a plurality of unit decoders.
  • Each of the plurality of unit includes a processor array and a plurality of instructions. A portion of the plurality of instructions is stored in an instruction controller.
  • the plurality of instructions causes each of the unit decoders to perform a Turbo decoding operation and decode at least a portion of the received data using at least a portion of a decoding matrix.
  • the decoder also includes a data switch coupled between the plurality of decoders and the plurality of memory units. The data switch is configured to vary a decode operation from an long term evolution (LTE) based operation to a Wideband Code Division Multiple Access (WCDMA) operation.
  • LTE long term evolution
  • WCDMA Wideband Code Division Multiple Access
  • a method for decoding transmissions in a wireless communications network includes receiving a data transmission.
  • the data is stored in a plurality of memory units.
  • a plurality of decoders perform a parallel Turbo decoding operation.
  • Each of the plurality decoders performs the parallel Turbo decoding in one of: a long term evolution (LTE) based operation to a Wideband Code Division Multiple Access (WCDMA) operation.
  • LTE long term evolution
  • WCDMA Wideband Code Division Multiple Access
  • FIGURE 1 illustrates an exemplary wireless network 100, which transmits ACK/NACK messages according to an exemplary embodiment of the disclosure
  • FIGURE 2A illustrates a high-level diagram of an orthogonal frequency division multiple access transmit path according to an exemplary embodiment of the disclosure
  • FIGURE 2B illustrates a high-level diagram of an orthogonal frequency division multiple access receive path according to an exemplary embodiment of the disclosure
  • FIGURE 3 illustrates a Turbo CRISP top-level architecture according to embodiments of the present disclosure
  • FIGURE 4 illustrates an example decoder 400 with duplicated MAPS
  • FIGURE 5 illustrates a decoder 500 that includes a parallel processing LTE switch fabric according to embodiments of the present disclosure
  • FIGURES 6 through 13 illustrate alpha and beta iterations according to embodiments of the present disclosure
  • FIGURE 14 illustrates a QPP cell according to embodiments of the present disclosure
  • FIGURE 15 illustrates an example operation of parallel QPP cells 1400 according to embodiments of the present disclosure.
  • FIGURE 16 illustrates an LTE parallel QPP processing switch according to embodiments of the present disclosure.
  • FIGURES 1 through 16 discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged wireless communications device.
  • FIGURE 1 illustrates an exemplary wireless network 100, which transmits ACK/NACK messages according to the principles of the present disclosure.
  • wireless network 100 includes base station (BS) 101, base station (BS) 102, base station (BS) 103, and other similar base stations (not shown).
  • Base station 101 is in communication with base station 102 and base station 103.
  • Base station 101 is also in communication with Internet 130 or a similar IP-based network (not shown).
  • Base station 102 provides wireless broadband access (via base station 101) to Internet 130 to a first plurality of subscriber stations within coverage area 120 of base station 102.
  • the first plurality of subscriber stations includes subscriber station 111, which may be located in a small business (SB), subscriber station 112, which may be located in an enterprise (E), subscriber station 113, which may be located in a WiFi hotspot (HS), subscriber station 114, which may be located in a first residence (R), subscriber station 115, which may be located in a second residence (R), and subscriber station 116, which may be a mobile device (M), such as a cell phone, a wireless laptop, a wireless PDA, or the like.
  • SB small business
  • E enterprise
  • HS WiFi hotspot
  • R first residence
  • subscriber station 116 which may be a mobile device (M), such as a cell phone, a wireless laptop, a wireless PDA, or
  • Base station 103 provides wireless broadband access (via base station 101) to Internet 130 to a second plurality of subscriber stations within coverage area 125 of base station 103.
  • the second plurality of subscriber stations includes subscriber station 115 and subscriber station 116.
  • base stations 101-103 may communicate with each other and with subscriber stations 111-116 using OFDM or OFDMA techniques.
  • Base station 101 may be in communication with either a greater number or a lesser number of base stations. Furthermore, while only six subscriber stations are depicted in FIGURE 1, it is understood that wireless network 100 may provide wireless broadband access to additional subscriber stations. It is noted that subscriber station 115 and subscriber station 116 are located on the edges of both coverage area 120 and coverage area 125. Subscriber station 115 and subscriber station 116 each communicate with both base station 102 and base station 103 and may be said to be operating in handoff mode, as known to those of skill in the art.
  • Subscriber stations 111-116 may access voice, data, video, video conferencing, and/or other broadband services via Internet 130.
  • one or more of subscriber stations 111-116 may be associated with an access point (AP) of a WiFi WLAN.
  • Subscriber station 116 may be any of a number of mobile devices, including a wireless-enabled laptop computer, personal data assistant, notebook, handheld device, or other wireless-enabled device.
  • Subscriber stations 114 and 115 may be, for example, a wireless-enabled personal computer (PC), a laptop computer, a gateway, or another device.
  • FIGURE 2A is a high-level diagram of an orthogonal frequency division multiple access (OFDMA) transmit path.
  • FIGURE 2B is a high-level diagram of an orthogonal frequency division multiple access (OFDMA) receive path.
  • the OFDMA transmit path is implemented in base station (BS) 102 and the OFDMA receive path is implemented in subscriber station (SS) 116 for the purposes of illustration and explanation only.
  • BS base station
  • SS subscriber station
  • the OFDMA receive path may also be implemented in BS 102 and the OFDMA transmit path may be implemented in SS 116.
  • the transmit path in BS 102 comprises channel coding and modulation block 205, serial-to-parallel (S-to-P) block 210, Size N Inverse Fast Fourier Transform (IFFT) block 215, parallel-to-serial (P-to-S) block 220, add cyclic prefix block 225, up-converter (UC) 230.
  • the receive path in SS 116 comprises down-converter (DC) 255, remove cyclic prefix block 260, serial-to-parallel (S-to-P) block 265, Size N Fast Fourier Transform (FFT) block 270, parallel-to-serial (P-to-S) block 275, channel decoding and demodulation block 280.
  • DC down-converter
  • FFT Fast Fourier Transform
  • FIGURES 2A and 2B may be implemented in software while other components may be implemented by configurable hardware or a mixture of software and configurable hardware.
  • the FFT blocks and the IFFT blocks described in this disclosure document may be implemented as configurable software algorithms, where the value of Size N may be modified according to the implementation.
  • the value of the N variable may be any integer number (i.e., 1, 2, 3, 4, etc.), while for FFT and IFFT functions, the value of the N variable may be any integer number that is a power of two (i.e., 1, 2, 4, 8, 16, etc.).
  • channel coding and modulation block 205 receives a set of information bits, applies coding (e.g., LDPC coding) and modulates (e.g., QPSK, QAM) the input bits to produce a sequence of frequency-domain modulation symbols.
  • Serial-to-parallel block 210 converts (i.e., de-multiplexes) the serial modulated symbols to parallel data to produce N parallel symbol streams where N is the IFFT/FFT size used in BS 102 and SS 116.
  • Size N IFFT block 215 then performs an IFFT operation on the N parallel symbol streams to produce time-domain output signals.
  • Parallel-to-serial block 220 converts (i.e., multiplexes) the parallel time-domain output symbols from Size N IFFT block 215 to produce a serial time-domain signal.
  • Add cyclic prefix block 225 then inserts a cyclic prefix to the time-domain signal.
  • up-converter 230 modulates (i.e., up-converts) the output of add cyclic prefix block 225 to RF frequency for transmission via a wireless channel.
  • the signal may also be filtered at baseband before conversion to RF frequency.
  • the transmitted RF signal arrives at SS 116 after passing through the wireless channel and reverse operations to those at BS 102 are performed.
  • Down-converter 255 down-converts the received signal to baseband frequency and remove cyclic prefix block 260 removes the cyclic prefix to produce the serial time-domain baseband signal.
  • Serial-to-parallel block 265 converts the time-domain baseband signal to parallel time domain signals.
  • Size N FFT block 270 then performs an FFT algorithm to produce N parallel frequency-domain signals.
  • Parallel-to-serial block 275 converts the parallel frequency-domain signals to a sequence of modulated data symbols.
  • Channel decoding and demodulation block 280 demodulates and then decodes the modulated symbols to recover the original input data stream.
  • Each of base stations 101-103 may implement a transmit path that is analogous to transmitting in the downlink to subscriber stations 111-116 and may implement a receive path that is analogous to receiving in the uplink from subscriber stations 111-116.
  • each one of subscriber stations 111-116 may implement a transmit path corresponding to the architecture for transmitting in the uplink to base stations 101-103 and may implement a receive path corresponding to the architecture for receiving in the downlink from base stations 101-103.
  • the channel decoding and demodulation block 280 decodes the received data.
  • the channel decoding and demodulation block 280 includes a decoder configured to perform a Turbo decoding operation.
  • the channel decoding and demodulation block 280 comprises one or more Context-based operation Reconfigurable Instruction Set Processors (CRISPs) such as the CRISP processor described in one or more of Application Number 11,123,313 filed May 06, 2005, entitled “CONTEXT-BASED OPERATION RECONFIGURABLE INSTRUCTION SET PROCESSOR AND METHOD OF OPERATION”; Patent Number 7,483,933 issued January 27, 2009 entitled “CORRELATION ARCHITECTURE FOR USE IN SOFTWARE-DEFINED RADIO SYSTEMS"; Application Number 11,142,504 filed June 01, 2005, entitled “MULTISTANDARD SDR ARCHITECTURE USING CONTEXT-BASED OPERATION RECONFIGURABLE INSTRUCTION SET PROCESSORS”; Application Number 11,225,4
  • FIGURE 3 illustrates an example of a Turbo CRISP top-level architecture according to embodiments of the present disclosure.
  • the embodiment of the Turbo CRISP top-level architecture 300 shown in FIGURE 3 is for illustration only. Other embodiments of the Turbo CRISP top-level architecture 300 could be used without departing from the scope of this disclosure.
  • the example of the Turbo CRISP 300 shown in FIGURE 3 is for illustration and example only and should not be construed as limiting.
  • the Turbo CRISP 300 can include host interface 305 and multiple Maximum a posteriori (MAP) interfaces.
  • MAP Maximum a posteriori
  • the interfaces for MAP0 310 are illustrated.
  • the interfaces for MAP1 315, MAP2 320 and MAP3 325 are not depicted, those interfaces are the same as the MAP0 310 interfaces with signal names ending in _1, _2 and _3 respectively, instead of _0 as shown for MAP0.
  • the host and MAP0 interfaces are described in Table 1:
  • the rising edge of the clock signal (CLK) 330 is used to operate all synchronous logic in the Turbo CRISP 300.
  • the reset signal 331 is an active high asynchronous reset. The reset signal 331 returns all logic and registers to their initial power-up values. Reset can be asserted at any time but should be de-asserted synchronously with the rising edge of the CLK signal 330.
  • the host 305 signals allow the external system or host processor (not shown) to communicate with the Turbo CRISP 300 for the purpose of writing and reading the configuration registers, program memory, interleaver memory, and output buffer memory.
  • Two chip select signals are asserted to perform a read or write access. The first chip select indicates which MAP decoder 310-325 is being accessed, and the second indicates which address space within the selected MAP decoder 310-325 to access (register, program memory, interleaver memory, or output buffer memory).
  • the Host Address 332 is the offset address of the register or memory location which the host is accessing for a read or write operation.
  • the Host Read Enable 333 is the active high read enable signal. For example, if the Host asserts this signal for one clock cycle, the Turbo CRISP 300 will output valid data during the following clock cycle.
  • the Host Write Enable 334 is the active high write enable. For example, during a clock cycle where HOST_WR is asserted, the data on HOST_WR_DATA will be written to the memory or registers selected by the Chip Select signal and by HOST_ADDR.
  • the MAP0 Host Chip Select 335 is the active high chip select for Turbo CRISP MAP0 310. Asserting this signal enables the registers or memory in MAP0 310 to be read or written.
  • the MAP1 Host Chip Select is the active high chip select for Turbo CRISP MAP1 315. Asserting this signal enables the registers or memory in MAP1 315 to be read or written.
  • the MAP2 Host Chip Select is the active high chip select for Turbo CRISP MAP2 320. Asserting this signal enables the registers or memory in MAP2 320 to be read or written.
  • the MAP3 Host Chip Select is the active high chip select for Turbo CRISP MAP3 325. Asserting this signal enables the registers or memory in MAP3 to be read or written.
  • the Register Chip Select 336 is the active high chip select that indicates that the Host is accessing the register address space. The access will go to the MAP decoder selected by the active HOST_n_CS signal.
  • the Program Memory Chip Select 337 is the active high chip select that indicates that the Host is accessing the Program Memory address space. The access will go to the MAP decoder selected by the active HOST_n_CS signal.
  • the Interleaver Memory Chip Select 338 is the active high chip select that indicates that the Host is accessing the Interleaver Memory address space. The access will go to the MAP decoder selected by the active HOST_n_CS signal.
  • the Output Buffer Chip Select 339 is the active high chip select that indicates that the Host is accessing the Output Buffer address space. The access will go to the MAP decoder selected by the active HOST_n_CS signal.
  • the Host Write Data 340 is the Data that the host is writing to a register or memory. The data is written on the rising edge of CLK when HOST_WR is high.
  • the Turbo CRISP 300 outputs data on the Host Read Data 341 in any clock cycle assertion of HOST_RD.
  • the Turbo CRISP 300 includes internal buffers (not shown) that store the decoded hard bits.
  • the buffers are accessed using the Host Address Bus. Each address accesses a 32-bit little endian word of decoded data.
  • FIGURE 4 illustrates an example decoder 400 with duplicated MAPS.
  • the decoder 400 can be used for decoding in a Wideband Code Division Multiple Access (WCDMA) environment.
  • the decoder 400 includes four MAPs decoders.
  • the decoder 400 includes a single interleaver (I/L) 405 for the MAPS 310-325.
  • Each MAP 310-325 is coupled to a single respective memory unit 410-425 for an independent operation. That is, each MAP 310-325 uses the respective memory unit 410-425 to which the MAP 310-325 is coupled.
  • MAP0 310 is coupled to and uses Mem0 410
  • MAP1 315 is coupled to and uses Mem1 415
  • MAP2 320 is coupled to and uses Mem2 420
  • MAP3 325 is coupled to and uses Mem3 425.
  • Each MAP 310-325 processes a separate block of data. Therefore, multiple blocks are processed in parallel.
  • a Turbo decoder is a block code and dividing a single block to several sub blocks (1 sub block per 1 MAP decoder) can introduce Bit Error Rate/Frame Error Rate (BER/FER) performance degradation to the overall block. Latency also can occur as a result of buffering four blocks that have to be released together. For example, each memory 410-415 is required to buffer blocks until all the blocks are processed and ready to be released.
  • Turbo Decoders for LTE standard are required to achieve high bit rate (up to 300Mbps for Cat. 5 3GPP release 8 LTE and up to 1Gbps for 3GPP Rel. 10 LTE/ADV).
  • a quadratic permutation polynomial (QPP) interleaver enables parallel processing Turbo Decoder.
  • QPP interleaver enabled LTE Turbo Decoding to easily perform multiple MAP decoders over a single data block in parallel (illustrated further herein below with respect to FIGURES 6 and 13).
  • Embodiments of the present disclosure provide new architectures to allow parallel processing of multiple MAP decoders (M) to process simultanously with no performance degradation.
  • embodiments of the present disclosure provide an efficient QPP I/L cell architecture to allow efficient parallel processing Turbo Decoder and discloses methods that utilize the disclosed QPP I/L HW cell in a system that uses parallel MAP decoder machines to process a single block with size k.
  • FIGURE 5 illustrates a decoder 500 that includes a parallel processing LTE switch fabric according to embodiments of the present disclosure.
  • the embodiment of the decoder 500 shown in FIGURE 5 is for illustration only. Other embodiments could be used without departing from the scope of this disclosure.
  • the decoder 500 includes an I/L block 305, a number of MAP decoders 310-325 and a number of memory blocks 410-425.
  • the decoder 500 further includes an LTE switch fabric 505.
  • the decoder 500 is capable of performing parallel processing over single block in order to significantly reduce memory and processing delay (and significantly reduce power) as compared to the duplicated MAP architecture decoder 400 that includes multiple MAP decoders 310-325 processing multiple blocks in parallel.
  • the decoder 500 also is capable of operating in a WCDMA environment or an LTE environment.
  • the decoder 500 is capable of switching itself between modes of operation for WCDMA and LTE.
  • the LTE switch fabric 505 can be enabled to perform switching for parallel processing or disabled such that the decoder 500 operates in a manner similar to the decoder 400.
  • the switch fabric 505 can be configured to enable each MAP decoder 310-325 to decode independently using a respective one of the memory units 410-425.
  • the switch fabric 505 can be configured to enable each MAP decoder 310-325 to decode in parallel using cross connections to one or more of the memory units 410-425.
  • the switch fabric 505 is configured to synchronize operations such that each MAP decoder 310-325 receives one or two bits (e.g., two data bits from one memory unit or one data bit from two memory units) without conflicting with operation from another of the MAP decoders 310-325. As such, the switch fabric 505 is configured to maintain contention free operations from each MAP decoder 310-325.
  • Each of the MAP decoders 310-325 includes a number of interfaces adapted to receive a number of signals. These signals are used by the Turbo CRISP to read encoded symbols from an external memory buffer.
  • Each MAP decoder 310-325 Interface (including the Tail) has a set of identical signals as shown in Table 2 (and shown in FIGURE 3):
  • Each of the MAP decoders 310-325 also includes control inputs that receive signals to control or activate the Turbo CRISP, as described in Table 3 (and shown in FIGURE 3):
  • Each of the MAP decoders 310-325, memories 410-425 and the LTE switch is responsive to a shared Parallel processing enable 510 (PAR_EN_IN shown in FIGURE 3).
  • the parallel processing enable 510 can set LTE switch fabric 505 to not switch for WCDMA applications and to vary from a switch disabled to a switch enabled in LTE applications.
  • the parallel processing enable 510 sets the LTE switch fabric 505 based on a signal received by the parallel processing enable 510.
  • the parallel processing enable 510 sets the LTE switch fabric 505 based on the received signal and a corresponding block size.
  • the parallel processing enable 510 can set the LTE switch fabric 505 based on Table 4. It will be understood that the block sizes shown in Table 4 are for illustration only and other block sizes could be used for each setting without departing from the scope of this disclosure.
  • the LTE switch fabric 505 when the block size is 512, the LTE switch fabric 505 is disabled and the MAP decoders 310-325 process the blocks directly.
  • the block size is 896, the LTE switch fabric 505 is disabled and the MAP decoders 310-325 segment the blocks into two segments. For example, for MAP0 310, a block is segmented into two blocks of 448 in memory 410. Then, MAP0 310 processes the block twice by processing the first segment in a first operation and the second segment in a second operation. Segmenting can be increased for larger sized blocks.
  • Table 5 WCDMA Segmentation
  • the LTE switch fabric 505 is enabled. For example, when the block size is 1792, the LTE switch fabric 505 is enabled and the MAP decoders 310-325 process the blocks using memories 410-425. Then, each of the MAP decoders 310-325 can process a portion of the block, such as a sub-block of 448, using any one or more of memories 410-425. In addition, larger block sizes also can be segmented such as when the block size is 6144. The LTE switch fabric 505 is enabled and the MAP decoders 310-325 segment the blocks into four segments.
  • each of the MAP decoders 310-325 can process a portion of the block in segments using any one or more of memories 410-425.
  • MAP0 can process a sub-block of1536 in four segments of 384 using any one or more of memories 410-425.
  • MAP0 310 processes the block four times by processing the first segment in a first operation, the second segment in a second operation, the third segment in a third operation and the fourth segment in a fourth operation.
  • the parallel MAP decoders 310-325 process a single block.
  • Some embodiments of the Turbo CRISP decoder 300 disclosed herein rely upon the learning period of Beta at the end of each sub block to write the first segment of the next sub block and also add learning Alpha at the beginning of each sub block as shown in FIGURES 6 through 11 and referred to as LTE Option 1.
  • the Turbo CRISP decoder 300 also support Cascading of Alpha/Beta values between consecutive sub blocks. Cascading is not required, which is a big advantage in gate count, but procesing power may increase due to the overlapped segment processing.
  • FIGURES 6 through 8 illustrate how the Turbo CRISP decoder 300 processes a 256-bit block size using the four MAP decoders 310-325 working in parallel.
  • FIGURE 6 illustrates an LTE 256-bit Half Iteration #0.
  • FIGURE 7 illustrates an LTE 256-bit Half Iteration #1.
  • the Lambda address shown is related to the pre-interleaved address.
  • the Turbo CRISP decoder 300 when initializing the cascading in the first two-half iterations (Non-I/L and I/L sessions), initializes with the ALL state for both sessions, which may still result with performance degradation over the full block processing. In the ALL state all states are initialized to the same value. In some embodiments, the Turbo CRISP decoder 300, before processing the block, executes a small learning period over the border between each of two sub-blocks and records the Alpha and/or Beta state values per each first two-half iterations. The Turbo CRISP decoder 300 uses those values to initilize the cascading.
  • the Turbo CRISP decoder 300 does not require alpha cascading between the MAPs. Both alpha and beta include a learning period (with alpha/beta cascading as optional). However, for the system to keep in sync between all MAP decoders 310-325, the learning period is in the same size of the segment. In most cases, learning period can be much smaller than one segment with no performance degradation.
  • Some embodiments of the Turbo CRISP decoder 300 disclosed herein rely upon cascading between sub-blocks as shown in FIGURES 12 through 13 also referred to as LTE Option 2.
  • the cascading can be Alpha only cascading, Beta only cascading, or both.
  • Cascading means that the init Alpha/Beta per each sub block comes from a previous full iteration from previous/next sub block last state values. Different state values may exist for non I/L session and for I/L sessions; therefore, the states are saved in both sessions seperately.
  • the BER/FER performance can be regained back as processing the full block.
  • each MAP decoder 310-325 processes N/4 bits plus tail for learning.
  • the training period is 32 bits.
  • Cascading is connected in order to maintain reliable alpha values in the beginning of each MAP processing.
  • LTE Option 2 allows any size of learning period (L) regardless of the segment size (T) and, thus, avoids the big learning period as in LTE Option 1.
  • the MAP decoders 310-325 work concurrently and in Sync.
  • Beta processing init_state is equal All for MAP0 310, MAP1 315, and MAP2 320.
  • the Turbo CRISP decoder 300 performs Beyond Sub Block - Synchronous parallel processing.
  • the last MAP decoder such MAP3 325 that processes the last Subblock, performs special processing on tail bits and is maintained in sync with the rest of the MAP decoders, such as MAP decoders310-320, without interfering the rest of the MAP decoders, such as MAP decoders310-320.
  • the I/L Table/machine will wrap around to 0, adding the block size value. For example: in case of 256 bit block size, address 16'h0000 will become 16'h0100.
  • the WR switch detects those cases and will not switch them to any memory block (no real write will occur). It is optional to write to extra logic.
  • the RD switch detects those cases and will place strong "0" values (such as 16'h0180) on the reading bus if it is not a tail bit. In case of tail bits, the RD switch will put 16'h0000 on the reading bus.
  • the six tail bit addresses (in the case of 256 bits, the 3 identity addresses ($100,$0101,$0102) for non-I/L, and the first 3 addresses of the I/L table for the I/L plus 16'h0100), are detected. It is also optional to read from extra logic.
  • the input buffer to the 4-MAP solution is divided to four sub-blocks that are addressed the same way as the non-interleaved extrinsic memories.
  • the input switch differs from the extrinsic (lambda) switch by sequentially accessing the data (non-interleaved) memories. The same consideration is taken in case of beyond block size. Beyond Block size data will be fixed to strong "0" ($7F).
  • a special tail input memory can be implemented separately (a fifth memory in a four MAP solution).
  • FIGURE 14 illustrates a QPP cell according to embodiments of the present disclosure.
  • the embodiment of the QPP cell 1400 shown in FIGURE 14 is for illustration only. Other embodiments could be used without departing from the scope of this disclosure.
  • a QPP I/L machine supports the LTE parallel processing Turbo decoder 300.
  • the QPP I/L is implemented in hardware and, as such, can save memory in the handset (especially in the case of parallel processing to achieve 50Mbps bit rate) as well as saving DSP calculations.
  • the QPP I/L is based on the following. Given an information block length K, the x-th interleaved output is read from an address given by Math Figure 1:
  • the QPP I/L addresses can be computed recursively without multiplication or modulo operations.
  • a simplified illustration is shonw in Math Figures 2 and 3:
  • the QPP cell 1400 is a fundamental hardware block that performs the QPP I/L.
  • the QPP cell 1400 includes multiple inputs 1405-1440.
  • a first input 1405 is configured to receive f1 and f2 and a second input 1410 is configured to receive k.
  • the f1, f2 data can come as separate f1 and f2 or already in another format such as f1+f2 and 2*f2 to reduce the calculation complexity.
  • f1, f2 and k all may come from a table.
  • Control signals are received via inputs for enable 1415, increment decrement (inc/dec) 1420 and load 1425.
  • the enable 1415, inc/dec 1420 and load 1425 signals determine the operation of the QPP cell 1400. When the enable 1415 signal is off, then no change in the logic is performed. When the enable 1415 signal is on, the QPP state (P and G internal registers) is incremented or decremented based on the inc/dec 1420 signal. QPP increment can be used in an Alpha session while QPP decrement can be used in a Beta session of the Turbo decoding.
  • Initial values for P and G interal registers are received via inputs for P_init_val 1430 and G_init_val 1435.
  • the load 1425 signal is on
  • the P_init_val 1430 data and G_init_val 1435 data are loaded to the internal P and G registers respectively.
  • the P_init_val 1430 data and G_init_val 1435 signals are used to load and restore a certain state to the QPP I/L (windowing support is illustrated further herein below).
  • the QPP cell 1400 also includes an input for skip data 1440 to receive a skip data signal.
  • the skip data signal received in the skip data 1440 determines by how much the QPP skips between consecutive outputs, which required to increase the Turbo decoder 300 bit rate support without the need for double buffering.
  • the QPP cell 1400 also includes outputs 1445, 1450 for P_out and G_out.
  • the P_out 1445 can be the final output from the QPP cell 1400.
  • both outputs 1445, 1450 are used to save and restore states in case of segmentation and windowing (such as, a learning period) where overlapped segments are processed to save alpha memory or parallel processing.
  • the saved P_out and G_out values will be restored and loaded through the P_init_val and G_init_val respectively to restore the QPP state.
  • FIGURE 15 illustrates an example operation of parallel QPP cells 1400 according to embodiments of the present disclosure.
  • the embodiment of the QPP cells 1400 shown in FIGURE 15 is for illustration only. Other embodiments could be used without departing from the scope of this disclosure.
  • multiple QPP Interleavers are connected to Multiple MAP decoders to support the paraller processing necessary to achieve 50/100Mbps for LTE.
  • M Map decoders When connecting M Map decoders for each one, a QPP I/L cell 1400 is attached, each QPP I/L is initialized with the related P_init_val 1430 and G_init_val 1435 values as decribed in FIGURE 14.
  • the related Bank_sel signal is used to control the MxM data switch described in further detail with respect to FIGURE 16.
  • each Bank_sel signal points to a different (no repetition) Lambda memory bank 1505a-1505n out of the M possible Lambda Memory Banks (0:M-1).
  • Bank_sel 0
  • Mem_addr is derived by using P_out 0 and Bank_sel 0 .
  • the order of the P_init is based on the Interleaver table (based on f1 and f2 parameters per block size) and the number of processors. For example, as shown in Table 6, for 4 processing elements (MAP decoders) there are two possible orders for P_init (n is block size):
  • Table 7 illustrates eight MP processing elements (4 options):
  • FIGURE 16 illustrates an LTE parallel QPP processing switch according to embodiments of the present disclosure.
  • the embodiment of the QPP processing switch 1600 shown in FIGURE 16 is for illustration only. Other embodiments could be used without departing from the scope of this disclosure.
  • Multipe memory blocks 1605a-1605n can be coupled to one or more MAP decoders, such as MAP decoders 310-325, through LTE 2 ⁇ M ⁇ M data switch 1610. Each MAP can support two simultaneous read (RD) accesses and write (Wr) accesses to a memory block 1605a-1605n per cycle.
  • the memory blocks 1605a-1605n are 4/8 memory blocks total that can be divided into two sets (even/odd) of 4/8 memory blocks.
  • the same approach can be applied to 16 MAP and higher to support higher bit rate (1 Gbps) LTE/ADV.
  • the temporal values of P_out and G_out are saved in the end of the alpha session (assuming alpha session is extended also on the learning period for beta) to be reserved later for P_init and G_init of the beta session. This saves an extra complex calculation of QPP interleaver for address gap between the end of the alpha session to the init of the beta learning session.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Error Detection And Correction (AREA)
  • Radio Transmission System (AREA)

Abstract

L'invention porte sur un récepteur capable de décoder des transmissions codées. Le récepteur comprend un certain nombre d'antennes de réception configurées pour recevoir des données ; une pluralité d'unités de mémoire qui stockent les données reçues ; et une pluralité de décodeurs configurés pour réaliser une opération de turbo décodage. Chaque décodeur de la pluralité de décodeurs décode au moins une partie des données reçues à l'aide d'au moins une partie d'une matrice de décodage. Le récepteur comprend également un commutateur de données couplé entre la pluralité de décodeurs et la pluralité d'unités de mémoire. Le commutateur de données est configuré pour faire varier une opération de décodage, d'une opération basée sur le système d'évolution à long terme (LTE) à une opération basée sur l'accès multiple par répartition en code à large bande (WCDMA).
PCT/KR2010/008136 2009-12-08 2010-11-17 Procédé et appareil pour turbo décodeur à traitement parallèle WO2011071250A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP10836146.0A EP2510637B1 (fr) 2009-12-08 2010-11-17 Procédé et appareil pour turbo décodeur à traitement parallèle

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US28370309P 2009-12-08 2009-12-08
US61/283,703 2009-12-08
US12/814,157 US8811452B2 (en) 2009-12-08 2010-06-11 Method and apparatus for parallel processing turbo decoder
US12/814,157 2010-06-11

Publications (2)

Publication Number Publication Date
WO2011071250A2 true WO2011071250A2 (fr) 2011-06-16
WO2011071250A3 WO2011071250A3 (fr) 2011-11-17

Family

ID=44081974

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/008136 WO2011071250A2 (fr) 2009-12-08 2010-11-17 Procédé et appareil pour turbo décodeur à traitement parallèle

Country Status (4)

Country Link
US (1) US8811452B2 (fr)
EP (1) EP2510637B1 (fr)
KR (1) KR101756706B1 (fr)
WO (1) WO2011071250A2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8811452B2 (en) * 2009-12-08 2014-08-19 Samsung Electronics Co., Ltd. Method and apparatus for parallel processing turbo decoder
CN102480337B (zh) * 2010-11-30 2016-04-13 国际商业机器公司 无线电软件系统以及用于其的解码装置和方法
EP4358416A3 (fr) * 2018-11-07 2024-05-08 Telefonaktiebolaget LM Ericsson (publ) Mise en uvre optimisée d'entrelacement (dés) pour une nouvelle radio 3gpp

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090238066A1 (en) * 2008-03-24 2009-09-24 Jung-Fu Cheng Selection of retransmission settings for harq in wcdma and lte networks

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100557177B1 (ko) * 1998-04-04 2006-07-21 삼성전자주식회사 적응 채널 부호/복호화 방법 및 그 부호/복호 장치
EP1030457B1 (fr) * 1999-02-18 2012-08-08 Imec Méthodes et architectures de système pour décodage Turbo
US8112698B2 (en) * 2008-07-15 2012-02-07 Icomm Technologies Inc. High speed turbo codes decoder for 3G using pipelined SISO Log-MAP decoders architecture
US6813742B2 (en) * 2001-01-02 2004-11-02 Icomm Technologies, Inc. High speed turbo codes decoder for 3G using pipelined SISO log-map decoders architecture
US6392572B1 (en) * 2001-05-11 2002-05-21 Qualcomm Incorporated Buffer architecture for a turbo decoder
US6954832B2 (en) * 2002-05-31 2005-10-11 Broadcom Corporation Interleaver for iterative decoder
GB2409134B (en) * 2003-12-11 2005-11-09 Motorola Inc A decoder
WO2006027668A1 (fr) * 2004-09-08 2006-03-16 Nokia Corporation Systeme et procede pour le codage de controle de parite adaptatif a faible densite
US20060083174A1 (en) * 2004-10-04 2006-04-20 Texas Instruments Inc. Collision avoidance manager, method of avoiding a memory collision and a turbo decoder employing the same
US7571369B2 (en) * 2005-02-17 2009-08-04 Samsung Electronics Co., Ltd. Turbo decoder architecture for use in software-defined radio systems
US7769912B2 (en) * 2005-02-17 2010-08-03 Samsung Electronics Co., Ltd. Multistandard SDR architecture using context-based operation reconfigurable instruction set processors
US7483933B2 (en) * 2005-02-17 2009-01-27 Samsung Electronics Co., Ltd. Correlation architecture for use in software-defined radio systems
US7668992B2 (en) * 2005-02-17 2010-02-23 Samsung Electronics Co., Ltd. Context-based operation reconfigurable instruction set processor and method of operation
US7864832B2 (en) * 2005-05-06 2011-01-04 Samsung Electronics Co., Ltd. Multi-code correlation architecture for use in software-defined radio systems
JP2006324754A (ja) * 2005-05-17 2006-11-30 Fujitsu Ltd 最大事後確率復号方法及び復号装置
US7409606B2 (en) * 2005-08-31 2008-08-05 Motorola, Inc. Method and system for interleaving in a parallel turbo decoder
US7895497B2 (en) * 2006-06-26 2011-02-22 Samsung Electronics Co., Ltd. Apparatus and method using reduced memory for channel decoding in a software-defined radio system
US7984368B2 (en) * 2006-09-01 2011-07-19 Samsung Electronics Co., Ltd. Method and system for increasing decoder throughput
US7782820B2 (en) * 2006-09-26 2010-08-24 Alcatel-Lucent Usa Inc. Method of detecting discontinuous transmission (DTX) and method of generating a signal metric for use in DTX detection
US7882416B2 (en) * 2006-10-10 2011-02-01 Broadcom Corporation General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes
US7831894B2 (en) * 2006-10-10 2010-11-09 Broadcom Corporation Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves
US7979772B2 (en) * 2006-10-25 2011-07-12 Samsung Electronics Co., Ltd. Method and system for providing a contention-free interleaver for channel coding
JP2010508790A (ja) * 2006-11-01 2010-03-18 クゥアルコム・インコーポレイテッド 高データレートのためのターボインターリーバ
US8065588B2 (en) * 2007-01-17 2011-11-22 Broadcom Corporation Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave
US8140932B2 (en) * 2007-11-26 2012-03-20 Motorola Mobility, Inc. Data interleaving circuit and method for vectorized turbo decoder
WO2009093099A1 (fr) * 2008-01-21 2009-07-30 Freescale Semiconductor, Inc. Système d'accès en parallèle exempt de contention et procédé d'accès en parallèle exempt de contention à un groupe de blocs de mémoire
US8035537B2 (en) * 2008-06-13 2011-10-11 Lsi Corporation Methods and apparatus for programmable decoding of a plurality of code types
US8090896B2 (en) * 2008-07-03 2012-01-03 Nokia Corporation Address generation for multiple access of memory
US8335979B2 (en) * 2008-12-08 2012-12-18 Samsung Electronics Co., Ltd. Contention-free parallel processing multimode LDPC decoder
CN102396158A (zh) * 2009-06-18 2012-03-28 中兴通讯股份有限公司 一种lte中并行turbo译码的方法及装置
JP4820440B2 (ja) * 2009-08-21 2011-11-24 株式会社エヌ・ティ・ティ・ドコモ 移動通信方法、無線アクセスネットワーク装置及び交換局
US8543881B2 (en) * 2009-09-11 2013-09-24 Qualcomm Incorporated Apparatus and method for high throughput unified turbo decoding
US8255759B2 (en) * 2009-10-29 2012-08-28 Qualcomm Incorporated APP (a priori probability) storage design for LTE turbo decoder with quadratic permutation polynomial interleaver
US8811452B2 (en) * 2009-12-08 2014-08-19 Samsung Electronics Co., Ltd. Method and apparatus for parallel processing turbo decoder
US8438434B2 (en) * 2009-12-30 2013-05-07 Nxp B.V. N-way parallel turbo decoder architecture
US8514798B2 (en) * 2010-02-25 2013-08-20 Mediatek Inc. Methods for scheduling channel activities for multiple radio access technologies in a communications apparatus and communications apparatuses utilizing the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090238066A1 (en) * 2008-03-24 2009-09-24 Jung-Fu Cheng Selection of retransmission settings for harq in wcdma and lte networks

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
M.-C. SHIN ET AL.: 'SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards' IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS vol. 15, no. 7, July 2007, pages 801 - 810, XP008159273 *

Also Published As

Publication number Publication date
US8811452B2 (en) 2014-08-19
EP2510637A4 (fr) 2017-12-06
WO2011071250A3 (fr) 2011-11-17
US20110134969A1 (en) 2011-06-09
EP2510637B1 (fr) 2019-03-06
KR101756706B1 (ko) 2017-07-11
EP2510637A2 (fr) 2012-10-17
KR20110065319A (ko) 2011-06-15

Similar Documents

Publication Publication Date Title
EP2323265B1 (fr) Desentrelaceur multisymbole efficace
Ilnseher et al. A 2.15 GBit/s turbo code decoder for LTE advanced base station applications
US8090896B2 (en) Address generation for multiple access of memory
US7409606B2 (en) Method and system for interleaving in a parallel turbo decoder
US8719658B2 (en) Accessing memory during parallel turbo decoding
EP2399341B1 (fr) Entrelaceurs turbo étendus pour décodage turbo parallèle
WO2006123908A1 (fr) Architecture de turbo-decodeur utilise dans des systemes de radio logicielle
EP2356749A2 (fr) Decodeur ldpc multimode de traitement parallele sans collision
Studer et al. A 390Mb/s 3.57 mm 2 3GPP-LTE turbo decoder ASIC in 0.13 µm CMOS
WO2011071250A2 (fr) Procédé et appareil pour turbo décodeur à traitement parallèle
EP4156568A1 (fr) Procédé d'envoi de trame de données, procédé de réception de trame de données et appareil de communication
WO2009100612A1 (fr) Récepteur de communication sans fil, procédé de réception de communication sans fil et récepteur de télévision
US9071279B2 (en) Turbo decoder input reordering
WO2013115563A1 (fr) Appareil et procédé de transmission/réception de données dans un système de communication
US7752530B2 (en) Apparatus and method for a collision-free parallel turbo decoder in a software-defined radio system
WO2013154371A1 (fr) Système et procédé pour décodeur multiétage à contrôle de parité à faible densité à multiplexage par répartition dans le temps
WO2012154002A2 (fr) Décodeur ldpc haut débit
WO2018151545A1 (fr) Procédé de transmission d'informations et dispositif de transmission
WO2019139377A1 (fr) Procédé pour réaliser un entrelacement et entrelaceur
US20060083174A1 (en) Collision avoidance manager, method of avoiding a memory collision and a turbo decoder employing the same
Abdelbaky et al. New low area NB-IoT turbo encoder interleaver by sharing resources
Cheng et al. Design of a high parallelism high throughput HSPA+ Turbo decoder
CN111245447B (zh) 一种基于fpga的天线数据交织和解交织方法
Lapotre et al. A dynamically reconfigurable multi-ASIP architecture for multistandard and multimode turbo decoding
WO2024031286A1 (fr) Procédé, appareil et dispositif de traitement des données

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10836146

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2010836146

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE