WO2011070398A1 - Barrière de diffusion d'oxygène en mg métallique appliquée à des dispositifs microélectroniques - Google Patents

Barrière de diffusion d'oxygène en mg métallique appliquée à des dispositifs microélectroniques Download PDF

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WO2011070398A1
WO2011070398A1 PCT/IB2009/055667 IB2009055667W WO2011070398A1 WO 2011070398 A1 WO2011070398 A1 WO 2011070398A1 IB 2009055667 W IB2009055667 W IB 2009055667W WO 2011070398 A1 WO2011070398 A1 WO 2011070398A1
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deposition
metallic
substrate
oxygen
layer
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PCT/IB2009/055667
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English (en)
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Armando António CARDOSO DOS SANTOS LOURENÇO
Erwan Yann Rauwel
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Universidade De Aveiro
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities

Definitions

  • the present invention relates to a method of producing microelectronic devices with complete control of oxygen stoichiometry and/or oxidation level by using a metallic Mg layer.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • a recurrent problem is the diffusion of oxygen; in fact, oxygen can diffuse from the film to the substrate or from inside the substrate to the film (environment) mainly due to chemical interactions across the interface.
  • High- k dielectric films 1 have been investigated as alternatives to the Si0 2 - based insulator as gate dielectric since they reduce leakage current and improve reliability without causing a decrease in oxide capacitance.
  • a higher dielectric constant typically of the order of 20, allow the use of a thicker gate dielectric to drastically reduce the gate leakage current by increasing the gate capacitance, this results in improved performance.
  • Hf0 2 is considered as a serious alternative dielectric gate due to its high dielectric constant (17-26) and wide gap ( @ 5.68 eV) 2 . Its thermal stability with silicon at temperatures up to 1000°C is better than that of Zr0 2 .
  • Hf0 2 (and other Hf-based related compounds) appear presently as the most promising candidates to replace Si0 2 in various microelectronic applications like CMOS technology, MIM capacitors, Flash memory application.
  • High-k gate dielectrics are highly permeable to oxygen diffusion 3 which means that oxygen molecules (or molecules of oxygen compounds) can easily pass through pores in the high-k dielectric material. So, oxygen can potentially diffuse through the high-k gate dielectric in a transistor gate structure and oxidize the silicon present at the interface which is detrimental for the reliability of the component.
  • the formation or growth of an Si0 2 interfacial layer 111 between the Si substrate 100 and the High- k thin film 102 during deposition is observed in majority of cases (figure 1).
  • the deposition of the high-k gate dielectric is preceded 4 or followed 5 by the deposition of a nitride interlayer (HfSiN) using sputtering of Hf 6 .
  • HfSiN nitride interlayer
  • a few deposition techniques mostly based on atomic layer deposition process 7 8 were able to deposit an oxide on the top of a silicon substrate limiting the silicon oxide interfacial layer regrowth 9 10 .
  • Atomic layer deposition is an alternative to the traditional CVD method consisting in alternating reactant pulses into the reactor chamber during a cycle. The reaction chamber is purged of unreacted reactant and byproduct between each different reactant pulse.
  • Another deposition technique called molecular beam epitaxy (MBE) also allows growing epitaxial oxide thin films on silicon substrate without any silicon oxide interface 11 .
  • Another way is to directly grow the high dielectric constant material in the metallic form and then perform a thermal annealing treatment under oxygen or ozone to form the high-k oxide thin film 12 .
  • Metal-electrode capacitors are widely used in mixed- signal/radio frequency (RF) ICs for better linearity and higher Q (quality factor) (due to lower electrode resistance).
  • MIM metal-insulator-metal
  • CMOS complementary metal oxide silicon
  • One of the challenges concerning these devices is to grow an oxide on the top of the electrode without oxidizing said electrode.
  • Many deposition methods are used and the most common method concerns the ALD technique. T he problem of high permeability to oxygen diffusion coming from the utilization of high-k compounds also remains in this case.
  • MEMs Micro-Electro-Mechanical systems
  • MEMs Micro-Electro-Mechanical systems
  • These refer to the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through micro-fabrication technology.
  • the control of the oxygen stoichiometry is one of the most important challenges as from this parameter will depend the properties of the materials used for the fabrication of these MEMs.
  • the MEMS are micromechanical components which are fabricated using compatible 'micromachining' processes that selectively etch away parts of the silicon wafer or add new structural layers to form the mechanical and electromechanical devices.
  • the MEMs are mostly based on ferroelasticity and piezo- electricty properties and the most common integrated compound in these systems is Pb(Zr ! . x Ti x )0 3 (PZT).
  • the physical properties and more specifically the piezoelectric property of this compound highly depend of the oxygen stoichiometry.
  • the need of a method to prevent the oxygen escape from the PZT is an actual present reality.
  • the diffusion of oxygen through the interface must be blocked within a few atomic layers in the vicinity of the interface film layer/substrate and this barrier must block the oxygen diffusion in both ways: from film to the substrate and/or from substrate to the film.
  • One aspect of the present invention is a new method of producing oxide free interfaces in electronic devices.
  • the method of the present invention involves the use of an oxygen diffusion barrier, namely a Mg interlayer which prevents the oxidation from occurring.
  • the present method comprises the steps of:
  • the Mg interlayer avoids the diffusion of oxygen into the substrate during the deposition of the layer of material in the presence of an oxidant, thus avoiding the oxidation of its surface.
  • the Mg interlayer avoids the diffusion of oxygen out of the oxygen containing substrate to the material layer being deposited, thus avoiding its oxidation.
  • the oxidant is absent during the deposition of the layer of material, since it stays trapped within the substrate layer by the Mg interlayer.
  • the method of deposition and the resulting devices of different combinations of layers other than the above-mentioned such as: - the deposition of an oxygen containing substrate followed by a Mg interlayer and the deposition of a layer of material in the presence of an oxidant, for complete control of the oxygen stoichiometry and oxidation level;
  • the method further comprises the step of thermal treatment of the interfaces produced in the previous steps. This treatment diffuses the Mg interlayer into the substrate, material or both layers, thus creating a single interface where both substrate and material layers are not oxidized.
  • Another aspect of the present invention is the products containing the interfaces
  • the products include catalysts, sensors, OLED's, display panel or electronic devices.
  • CMOS complementary metal-oxide-semiconductor
  • transistors, capacitors or micro-electromechanical systems can use advantageously the method of producing oxide free interfaces.
  • the interlayer should be mostly composed of metallic magnesium but could also comprise some impurities of one or more of the following elements: B, N, Si, among others.
  • the present invention can also eliminate the problems of oxygen escape or atoms escape from the support or substrate into the chamber environment, thus avoiding oxidation and/or complete oxygen stoichiometry control during a deposition process.
  • Figure 1 Scheme of a NMOS transistor, wherein: 100 - Substrate (ex.: Si); 101 - SiO 2 interlayer; 102 - High-k material; 104 - Electrode; 105 - Source; 106 - Drain; 111 - semi-conductive region of the substrate .
  • Figure 2 Mg interlayer deposited between high-k gate oxide and silicon substrate, wherein: 100 - Substrate (ex.: Si); 102 - High-k material; 103 - Mg interlayer; 105 - Source; 106 - Drain; 111 - semi-conductive region of the substrate .
  • Figure 4 X-ray reflectometry measurement performed on a metallic Mg thin film deposited on silicon substrate.
  • Substrate (ex.: Si); 101 - Si0 2 interlayer; 103 - Mg interlayer; 108 - Metallic electrode
  • Figure 7 Mg interlayer deposited between high-k gate oxide and a metallic layer, wherein: 100 - Substrate (ex.: Si); 101 - Si0 2 interlayer; 102 - High-k material; 103 -
  • Figure 8 Dissolution of the Mg interlayer in the high-k gate and metallic electrode using an annealing treatment, wherein: 100 - Substrate (ex.: Si); 101 - Si0 2 interlayer;
  • FIG. 9 Mg interlayer deposited on the PZT buffer layer, wherein: 100 - Substrate (ex.: Si); 101 - Si0 2 interlayer; 103 - Mg interlayer; 109 - Oxide thin film
  • Figure 10 Mg interlayer deposited between PZT buffer and the alloy on the top, wherein: 100 - Substrate (ex.: Si); 101 - Si0 2 interlayer; 103 - Mg interlayer; 109 - Oxide thin film (Pb(ZrxTl-x)03); 110 - Alloy or any other oxidisable material.
  • Figure 11 Dissolution of the Mg interlayer in the PZT and alloy on the top using an annealing treatment, wherein: 100 - Substrate (ex.: Si); 101 - Si0 2 interlayer; 107 - Mg interlayer diffused into adjacent layers; 109 - Oxide thin film (Pb(ZrxTl-x)03); 110 - Alloy or any other oxidisable material.
  • Figure 12 X-ray reflectometry measurement performed on a 200 A Hf0 2 thin film deposited on a metallic Mg thin film.
  • the substrate is a Si wafer (Silicon).
  • the graph shows a very low surface roughness and a thickness of 200 A.
  • Figure 13 TEM image of the Hf0 2 thin film on metallic Mg interlayer deposited on silicon substrate at 400°C. The same film as in Fig. 12
  • the method of the present invention has a wide range of applications in the micro- and nanoelectronics but is not limited to them as it can be used in other processes where the oxygen control (stoichiometry or oxidation) is important.
  • the deposition of the Mg interlayer 103 is performed at a temperature ranging from room temperature to 630 °C, preferably in the range from 300 to 450°C, and most preferably at 400 °C.
  • the deposition is performed by sputtering under an atmosphere of inert gas
  • the sputtering target can be a pure metal of the alkaline rare earth metal Mg.
  • the deposition process can also be another physical deposition process (Pulse laser deposition (PLD), molecular beam epitaxy (MBE), electron Beam evaporation and all the derived processes) or a chemical deposition process (Chemical vapour deposition (CVD), Sol-gel deposition, Metalorganic chemical vapour deposition (MOCVD), Atomic layer deposition (ALD) and all the derived process from these processes).
  • PLD Pulse laser deposition
  • MBE molecular beam epitaxy
  • CVD chemical vapour deposition
  • MOCVD Metalorganic chemical vapour deposition
  • ALD Atomic layer deposition
  • This metallic magnesium interlayer prevents the oxygen diffusion into the silicon substrate during the following deposition process of the high- k gate dielectric, which usually involves the utilization of oxygen or ozone as an oxidizing agent.
  • the deposition of the oxide layer (Hf0 2 or other) is performed by the techniques known in the art.
  • the presence of this ultrathin Mg bulk metallic interface 103 between the high-k gate dielectric layers 102 and the semi-conductive region 111 of the silicon substrate 100 in the figure 2 would be detrimental for a CMOS application in an integrated circuit, as the metallic character of this interlayer will induce high leakage currents.
  • the CMOS component would present a behavior similar to a Metal-Insulator- Metal (MIM) component.
  • MIM Metal-Insulator- Metal
  • a thermal annealing treatment step under oxygen, nitrogen, hydrogen, ammonia or a mixing of these different gases causes the diffusion of this metallic Mg interlayer into the high-k gate dielectric thin film, or into the silicon substrate or into both.
  • the final state of the annealing treatment is shown Figure 3, and corresponds to the diffusion area 107 between the high-k gate dielectric 102 and the semi-conductive region 111.
  • the ultra thin Mg metallic interlayer approximates a thin semi-insulating layer
  • the Mg metallic interlayer should be ultra-thin in all the cases, with thickness between 0.2 and 5 nm.
  • the high-k gate dielectric oxide 102 it is possible to deposit the high-k gate dielectric oxide 102 directly on the top of this ultra thin Mg metallic interlayer without desorption or evaporation.
  • Figure 5 shows a TEM image of Hf0 2 thin films directly deposited on the top of the Mg interlayer without visible Si0 2 interface between the silicon substrate and the Mg metallic thin film. No oxidation of the Mg metallic interlayer was observed.
  • Another embodiment of the invention relates to integrated circuits and m etal- electrode capacitors, which are widely used in mixed-signal/radio frequency (RF) ICs for better linearity and higher Q (quality factor) (due to lower electrode resistance).
  • RF radio frequency
  • MIM metal-insulator-metal capacitors have been commercially available in the standard CMOS (complementary metal oxide silicon) mixed-signal process.
  • the metallic Mg interlayer 103 is deposited on the top of the metallic electrode 108 (TiN in the example figure 6, but can be also composed by another metal or alloy) using sputtering ( Figure 6) under the same conditions as defined above.
  • the deposition process can also be another physical deposition process (Pulse laser deposition (PLD), molecular beam epitaxy (MBE), electron Beam evaporation and all the derived processes) or a chemical deposition process (Chemical vapour deposition (CVD), Sol- gel deposition, Metalorganic chemical vapour deposition (MOCVD), Atomic layer deposition (ALD) and all the derived process from these processes).
  • the metallic electrode 108 is not oxidized during the deposition process.
  • This metallic magnesium interlayer prevents the oxygen diffusion into the metallic electrode 108 (TiN) during the following deposition process of the high-k dielectric, which involves the utilization of oxygen or ozone as an oxidizing agent.
  • MCMs Micro- Electro-Mechanical systems
  • the metallic Mg layer is deposited on the top of the oxide thin film 109 (Pb(Zri_ x Ti x )0 3 (PZT) under the conditions defined above (figure 9), but can be also an oxide with a different composition) using sputtering ( Figure 9).
  • the deposition process can also be another physical deposition process (Pulse laser deposition (PLD), molecular beam epitaxy (MBE), electron Beam evaporation and all the derived processes) or a chemical deposition process (Chemical vapour deposition (CVD), Sol-gel deposition, Metalorganic chemical vapour deposition (MOCVD), Atomic layer deposition (ALD) and all the derived process from these processes).
  • This metallic magnesium interlay er prevents the oxygen escape from the PZT oxide thin film 109 into the deposition chamber environment during the following deposition process of the metallic alloy 110, thus preventing the oxidation of the alloy.
  • Example 1 Deposition of Mg metallic interlayer at 400°C followed by the deposition of Hf0 2 thin film at 400°C
  • one silicon substrate that was previously cleaned by HF- last solution (9ml of water, 1 ml of methanol and 0,75ml of fluoric acid 40%) for 120s was introduced and fixed to the sample holder using a shadow mask. No thermal conductive paste was used.
  • the chamber was evacuated up to the pressure of 5.0E-8 mbar.
  • the plasma was ignited and was maintained for 15 minutes at 25 Watt rf power for target cleaning. During this pre-sputtering time a shutter was covering the substrate in order to prevent any deposition.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

La présente invention concerne un procédé de fabrication de dispositifs microélectroniques qui utilise une couche de Mg métallique mince en tant que barrière de diffusion d'oxygène. Ce procédé empêche la diffusion d'oxygène dans le substrat durant le procédé de développement de films minces d'oxyde et/ou empêche la sortie d'oxygène à partir du substrat dans l'environnement de traitement, permettant ainsi un contrôle complet de la stœchiométrie et/ou de l'oxydation d'oxygène au cours du procédé de fabrication du dispositif microélectronique. Si cela est nécessaire et/ou pratique, la couche mince de Mg peut être diffusée dans les couches adjacentes par traitement thermique.
PCT/IB2009/055667 2009-12-09 2009-12-10 Barrière de diffusion d'oxygène en mg métallique appliquée à des dispositifs microélectroniques WO2011070398A1 (fr)

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PT104865 2009-12-09
PT10486509A PT104865A (pt) 2009-12-09 2009-12-09 Barreira metálica de magnésio contra a difusão de oxigénio aplicada a dispositivos de microelectrónica

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Cited By (2)

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CN109950134A (zh) * 2019-03-19 2019-06-28 中国科学院上海高等研究院 具有氧化物薄膜的结构及其制备方法

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US8632745B1 (en) 2012-12-21 2014-01-21 Ut-Battelle, Llc Method and apparatus for controlling stoichiometry in multicomponent materials
CN109950134A (zh) * 2019-03-19 2019-06-28 中国科学院上海高等研究院 具有氧化物薄膜的结构及其制备方法

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