WO2011070398A1 - Metallic mg oxygen diffusion barrier diffusion applied for electronic devices - Google Patents

Metallic mg oxygen diffusion barrier diffusion applied for electronic devices Download PDF

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Publication number
WO2011070398A1
WO2011070398A1 PCT/IB2009/055667 IB2009055667W WO2011070398A1 WO 2011070398 A1 WO2011070398 A1 WO 2011070398A1 IB 2009055667 W IB2009055667 W IB 2009055667W WO 2011070398 A1 WO2011070398 A1 WO 2011070398A1
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deposition
metallic
substrate
oxygen
layer
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PCT/IB2009/055667
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French (fr)
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Armando António CARDOSO DOS SANTOS LOURENÇO
Erwan Yann Rauwel
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Universidade De Aveiro
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities

Definitions

  • the present invention relates to a method of producing microelectronic devices with complete control of oxygen stoichiometry and/or oxidation level by using a metallic Mg layer.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • a recurrent problem is the diffusion of oxygen; in fact, oxygen can diffuse from the film to the substrate or from inside the substrate to the film (environment) mainly due to chemical interactions across the interface.
  • High- k dielectric films 1 have been investigated as alternatives to the Si0 2 - based insulator as gate dielectric since they reduce leakage current and improve reliability without causing a decrease in oxide capacitance.
  • a higher dielectric constant typically of the order of 20, allow the use of a thicker gate dielectric to drastically reduce the gate leakage current by increasing the gate capacitance, this results in improved performance.
  • Hf0 2 is considered as a serious alternative dielectric gate due to its high dielectric constant (17-26) and wide gap ( @ 5.68 eV) 2 . Its thermal stability with silicon at temperatures up to 1000°C is better than that of Zr0 2 .
  • Hf0 2 (and other Hf-based related compounds) appear presently as the most promising candidates to replace Si0 2 in various microelectronic applications like CMOS technology, MIM capacitors, Flash memory application.
  • High-k gate dielectrics are highly permeable to oxygen diffusion 3 which means that oxygen molecules (or molecules of oxygen compounds) can easily pass through pores in the high-k dielectric material. So, oxygen can potentially diffuse through the high-k gate dielectric in a transistor gate structure and oxidize the silicon present at the interface which is detrimental for the reliability of the component.
  • the formation or growth of an Si0 2 interfacial layer 111 between the Si substrate 100 and the High- k thin film 102 during deposition is observed in majority of cases (figure 1).
  • the deposition of the high-k gate dielectric is preceded 4 or followed 5 by the deposition of a nitride interlayer (HfSiN) using sputtering of Hf 6 .
  • HfSiN nitride interlayer
  • a few deposition techniques mostly based on atomic layer deposition process 7 8 were able to deposit an oxide on the top of a silicon substrate limiting the silicon oxide interfacial layer regrowth 9 10 .
  • Atomic layer deposition is an alternative to the traditional CVD method consisting in alternating reactant pulses into the reactor chamber during a cycle. The reaction chamber is purged of unreacted reactant and byproduct between each different reactant pulse.
  • Another deposition technique called molecular beam epitaxy (MBE) also allows growing epitaxial oxide thin films on silicon substrate without any silicon oxide interface 11 .
  • Another way is to directly grow the high dielectric constant material in the metallic form and then perform a thermal annealing treatment under oxygen or ozone to form the high-k oxide thin film 12 .
  • Metal-electrode capacitors are widely used in mixed- signal/radio frequency (RF) ICs for better linearity and higher Q (quality factor) (due to lower electrode resistance).
  • MIM metal-insulator-metal
  • CMOS complementary metal oxide silicon
  • One of the challenges concerning these devices is to grow an oxide on the top of the electrode without oxidizing said electrode.
  • Many deposition methods are used and the most common method concerns the ALD technique. T he problem of high permeability to oxygen diffusion coming from the utilization of high-k compounds also remains in this case.
  • MEMs Micro-Electro-Mechanical systems
  • MEMs Micro-Electro-Mechanical systems
  • These refer to the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through micro-fabrication technology.
  • the control of the oxygen stoichiometry is one of the most important challenges as from this parameter will depend the properties of the materials used for the fabrication of these MEMs.
  • the MEMS are micromechanical components which are fabricated using compatible 'micromachining' processes that selectively etch away parts of the silicon wafer or add new structural layers to form the mechanical and electromechanical devices.
  • the MEMs are mostly based on ferroelasticity and piezo- electricty properties and the most common integrated compound in these systems is Pb(Zr ! . x Ti x )0 3 (PZT).
  • the physical properties and more specifically the piezoelectric property of this compound highly depend of the oxygen stoichiometry.
  • the need of a method to prevent the oxygen escape from the PZT is an actual present reality.
  • the diffusion of oxygen through the interface must be blocked within a few atomic layers in the vicinity of the interface film layer/substrate and this barrier must block the oxygen diffusion in both ways: from film to the substrate and/or from substrate to the film.
  • One aspect of the present invention is a new method of producing oxide free interfaces in electronic devices.
  • the method of the present invention involves the use of an oxygen diffusion barrier, namely a Mg interlayer which prevents the oxidation from occurring.
  • the present method comprises the steps of:
  • the Mg interlayer avoids the diffusion of oxygen into the substrate during the deposition of the layer of material in the presence of an oxidant, thus avoiding the oxidation of its surface.
  • the Mg interlayer avoids the diffusion of oxygen out of the oxygen containing substrate to the material layer being deposited, thus avoiding its oxidation.
  • the oxidant is absent during the deposition of the layer of material, since it stays trapped within the substrate layer by the Mg interlayer.
  • the method of deposition and the resulting devices of different combinations of layers other than the above-mentioned such as: - the deposition of an oxygen containing substrate followed by a Mg interlayer and the deposition of a layer of material in the presence of an oxidant, for complete control of the oxygen stoichiometry and oxidation level;
  • the method further comprises the step of thermal treatment of the interfaces produced in the previous steps. This treatment diffuses the Mg interlayer into the substrate, material or both layers, thus creating a single interface where both substrate and material layers are not oxidized.
  • Another aspect of the present invention is the products containing the interfaces
  • the products include catalysts, sensors, OLED's, display panel or electronic devices.
  • CMOS complementary metal-oxide-semiconductor
  • transistors, capacitors or micro-electromechanical systems can use advantageously the method of producing oxide free interfaces.
  • the interlayer should be mostly composed of metallic magnesium but could also comprise some impurities of one or more of the following elements: B, N, Si, among others.
  • the present invention can also eliminate the problems of oxygen escape or atoms escape from the support or substrate into the chamber environment, thus avoiding oxidation and/or complete oxygen stoichiometry control during a deposition process.
  • Figure 1 Scheme of a NMOS transistor, wherein: 100 - Substrate (ex.: Si); 101 - SiO 2 interlayer; 102 - High-k material; 104 - Electrode; 105 - Source; 106 - Drain; 111 - semi-conductive region of the substrate .
  • Figure 2 Mg interlayer deposited between high-k gate oxide and silicon substrate, wherein: 100 - Substrate (ex.: Si); 102 - High-k material; 103 - Mg interlayer; 105 - Source; 106 - Drain; 111 - semi-conductive region of the substrate .
  • Figure 4 X-ray reflectometry measurement performed on a metallic Mg thin film deposited on silicon substrate.
  • Substrate (ex.: Si); 101 - Si0 2 interlayer; 103 - Mg interlayer; 108 - Metallic electrode
  • Figure 7 Mg interlayer deposited between high-k gate oxide and a metallic layer, wherein: 100 - Substrate (ex.: Si); 101 - Si0 2 interlayer; 102 - High-k material; 103 -
  • Figure 8 Dissolution of the Mg interlayer in the high-k gate and metallic electrode using an annealing treatment, wherein: 100 - Substrate (ex.: Si); 101 - Si0 2 interlayer;
  • FIG. 9 Mg interlayer deposited on the PZT buffer layer, wherein: 100 - Substrate (ex.: Si); 101 - Si0 2 interlayer; 103 - Mg interlayer; 109 - Oxide thin film
  • Figure 10 Mg interlayer deposited between PZT buffer and the alloy on the top, wherein: 100 - Substrate (ex.: Si); 101 - Si0 2 interlayer; 103 - Mg interlayer; 109 - Oxide thin film (Pb(ZrxTl-x)03); 110 - Alloy or any other oxidisable material.
  • Figure 11 Dissolution of the Mg interlayer in the PZT and alloy on the top using an annealing treatment, wherein: 100 - Substrate (ex.: Si); 101 - Si0 2 interlayer; 107 - Mg interlayer diffused into adjacent layers; 109 - Oxide thin film (Pb(ZrxTl-x)03); 110 - Alloy or any other oxidisable material.
  • Figure 12 X-ray reflectometry measurement performed on a 200 A Hf0 2 thin film deposited on a metallic Mg thin film.
  • the substrate is a Si wafer (Silicon).
  • the graph shows a very low surface roughness and a thickness of 200 A.
  • Figure 13 TEM image of the Hf0 2 thin film on metallic Mg interlayer deposited on silicon substrate at 400°C. The same film as in Fig. 12
  • the method of the present invention has a wide range of applications in the micro- and nanoelectronics but is not limited to them as it can be used in other processes where the oxygen control (stoichiometry or oxidation) is important.
  • the deposition of the Mg interlayer 103 is performed at a temperature ranging from room temperature to 630 °C, preferably in the range from 300 to 450°C, and most preferably at 400 °C.
  • the deposition is performed by sputtering under an atmosphere of inert gas
  • the sputtering target can be a pure metal of the alkaline rare earth metal Mg.
  • the deposition process can also be another physical deposition process (Pulse laser deposition (PLD), molecular beam epitaxy (MBE), electron Beam evaporation and all the derived processes) or a chemical deposition process (Chemical vapour deposition (CVD), Sol-gel deposition, Metalorganic chemical vapour deposition (MOCVD), Atomic layer deposition (ALD) and all the derived process from these processes).
  • PLD Pulse laser deposition
  • MBE molecular beam epitaxy
  • CVD chemical vapour deposition
  • MOCVD Metalorganic chemical vapour deposition
  • ALD Atomic layer deposition
  • This metallic magnesium interlayer prevents the oxygen diffusion into the silicon substrate during the following deposition process of the high- k gate dielectric, which usually involves the utilization of oxygen or ozone as an oxidizing agent.
  • the deposition of the oxide layer (Hf0 2 or other) is performed by the techniques known in the art.
  • the presence of this ultrathin Mg bulk metallic interface 103 between the high-k gate dielectric layers 102 and the semi-conductive region 111 of the silicon substrate 100 in the figure 2 would be detrimental for a CMOS application in an integrated circuit, as the metallic character of this interlayer will induce high leakage currents.
  • the CMOS component would present a behavior similar to a Metal-Insulator- Metal (MIM) component.
  • MIM Metal-Insulator- Metal
  • a thermal annealing treatment step under oxygen, nitrogen, hydrogen, ammonia or a mixing of these different gases causes the diffusion of this metallic Mg interlayer into the high-k gate dielectric thin film, or into the silicon substrate or into both.
  • the final state of the annealing treatment is shown Figure 3, and corresponds to the diffusion area 107 between the high-k gate dielectric 102 and the semi-conductive region 111.
  • the ultra thin Mg metallic interlayer approximates a thin semi-insulating layer
  • the Mg metallic interlayer should be ultra-thin in all the cases, with thickness between 0.2 and 5 nm.
  • the high-k gate dielectric oxide 102 it is possible to deposit the high-k gate dielectric oxide 102 directly on the top of this ultra thin Mg metallic interlayer without desorption or evaporation.
  • Figure 5 shows a TEM image of Hf0 2 thin films directly deposited on the top of the Mg interlayer without visible Si0 2 interface between the silicon substrate and the Mg metallic thin film. No oxidation of the Mg metallic interlayer was observed.
  • Another embodiment of the invention relates to integrated circuits and m etal- electrode capacitors, which are widely used in mixed-signal/radio frequency (RF) ICs for better linearity and higher Q (quality factor) (due to lower electrode resistance).
  • RF radio frequency
  • MIM metal-insulator-metal capacitors have been commercially available in the standard CMOS (complementary metal oxide silicon) mixed-signal process.
  • the metallic Mg interlayer 103 is deposited on the top of the metallic electrode 108 (TiN in the example figure 6, but can be also composed by another metal or alloy) using sputtering ( Figure 6) under the same conditions as defined above.
  • the deposition process can also be another physical deposition process (Pulse laser deposition (PLD), molecular beam epitaxy (MBE), electron Beam evaporation and all the derived processes) or a chemical deposition process (Chemical vapour deposition (CVD), Sol- gel deposition, Metalorganic chemical vapour deposition (MOCVD), Atomic layer deposition (ALD) and all the derived process from these processes).
  • the metallic electrode 108 is not oxidized during the deposition process.
  • This metallic magnesium interlayer prevents the oxygen diffusion into the metallic electrode 108 (TiN) during the following deposition process of the high-k dielectric, which involves the utilization of oxygen or ozone as an oxidizing agent.
  • MCMs Micro- Electro-Mechanical systems
  • the metallic Mg layer is deposited on the top of the oxide thin film 109 (Pb(Zri_ x Ti x )0 3 (PZT) under the conditions defined above (figure 9), but can be also an oxide with a different composition) using sputtering ( Figure 9).
  • the deposition process can also be another physical deposition process (Pulse laser deposition (PLD), molecular beam epitaxy (MBE), electron Beam evaporation and all the derived processes) or a chemical deposition process (Chemical vapour deposition (CVD), Sol-gel deposition, Metalorganic chemical vapour deposition (MOCVD), Atomic layer deposition (ALD) and all the derived process from these processes).
  • This metallic magnesium interlay er prevents the oxygen escape from the PZT oxide thin film 109 into the deposition chamber environment during the following deposition process of the metallic alloy 110, thus preventing the oxidation of the alloy.
  • Example 1 Deposition of Mg metallic interlayer at 400°C followed by the deposition of Hf0 2 thin film at 400°C
  • one silicon substrate that was previously cleaned by HF- last solution (9ml of water, 1 ml of methanol and 0,75ml of fluoric acid 40%) for 120s was introduced and fixed to the sample holder using a shadow mask. No thermal conductive paste was used.
  • the chamber was evacuated up to the pressure of 5.0E-8 mbar.
  • the plasma was ignited and was maintained for 15 minutes at 25 Watt rf power for target cleaning. During this pre-sputtering time a shutter was covering the substrate in order to prevent any deposition.

Abstract

The present invention provides a method for the production of microelectronic devices that uses a thin metallic Mg layer as oxygen diffusion barrier. This method prevents the oxygen diffusion into the substrate during the growth process of oxide thin films and/or prevents the oxygen escape from the substrate into the processing environment allowing thus a complete control of the oxygen stoichiometry and/or oxidation during the production process of the microelectronic device. If necessary and/or convenient the Mg thin layer can be diffused into the adjacent layers by thermal treatment.

Description

Description
Title of Invention: METALLIC MG OXYGEN DIFFUSION
BARRIER DIFFUSION APPLIED FOR ELECTRONIC DEVICES
Technical Field
[1] The present invention relates to a method of producing microelectronic devices with complete control of oxygen stoichiometry and/or oxidation level by using a metallic Mg layer.
Background art
[2] A large variety of deposition techniques are used in the fabrication of integrated circuits and microelectronics devices, including physical vapor deposition (PVD) and chemical vapor deposition (CVD). The most important challenges concerning the deposition of oxides are the control of the oxygen stoichiometry and to prevent the undesirable oxidation of the substrate, more specifically in the case of deposition on silicon substrate or metallic electrodes.
[3] A recurrent problem is the diffusion of oxygen; in fact, oxygen can diffuse from the film to the substrate or from inside the substrate to the film (environment) mainly due to chemical interactions across the interface.
[4] Extensive miniaturization of integrated circuits and future increase in the performance of transistor has spurred on the search for gate dielectric oxides to replace Si02 in future Si-based microelectronic applications. In fact, integrated circuit memory devices such as dynamic random access memories (DRAMs), include in every storage cell, a transfer transistor and a capacitor for momentarily storing information. The increase in the number of storage cells per device shrinks the amount of space (device surface area) taken by each storage cell. Thus, the shrinkage has been accomplished reducing the storage cell components (i.e. transistor and capacitor).
[5] Several High- k dielectric films1 have been investigated as alternatives to the Si02 - based insulator as gate dielectric since they reduce leakage current and improve reliability without causing a decrease in oxide capacitance. A higher dielectric constant, typically of the order of 20, allow the use of a thicker gate dielectric to drastically reduce the gate leakage current by increasing the gate capacitance, this results in improved performance. Among the suggested materials, Hf02 is considered as a serious alternative dielectric gate due to its high dielectric constant (17-26) and wide gap ( @ 5.68 eV)2. Its thermal stability with silicon at temperatures up to 1000°C is better than that of Zr02. Thus Hf02 (and other Hf-based related compounds) appear presently as the most promising candidates to replace Si02 in various microelectronic applications like CMOS technology, MIM capacitors, Flash memory application. High-k gate dielectrics are highly permeable to oxygen diffusion3 which means that oxygen molecules (or molecules of oxygen compounds) can easily pass through pores in the high-k dielectric material. So, oxygen can potentially diffuse through the high-k gate dielectric in a transistor gate structure and oxidize the silicon present at the interface which is detrimental for the reliability of the component. The formation or growth of an Si02 interfacial layer 111 between the Si substrate 100 and the High- k thin film 102 during deposition is observed in majority of cases (figure 1). Presently, to prevent this low-k interlayer formation the deposition of the high-k gate dielectric is preceded4 or followed5 by the deposition of a nitride interlayer (HfSiN) using sputtering of Hf6. The drawback of this method is that this interlayer is also a low-k.
[6] Amongst the available techniques only a few are able to prevent the oxidation of the metallic electrode or the silicon oxide growth during the deposition process on silicon substrate. This oxidation can also occur during the post-deposition annealing following the deposition process.
[7] A few deposition techniques mostly based on atomic layer deposition process7 8 were able to deposit an oxide on the top of a silicon substrate limiting the silicon oxide interfacial layer regrowth9 10. Atomic layer deposition is an alternative to the traditional CVD method consisting in alternating reactant pulses into the reactor chamber during a cycle. The reaction chamber is purged of unreacted reactant and byproduct between each different reactant pulse. Another deposition technique called molecular beam epitaxy (MBE) also allows growing epitaxial oxide thin films on silicon substrate without any silicon oxide interface11. Another way is to directly grow the high dielectric constant material in the metallic form and then perform a thermal annealing treatment under oxygen or ozone to form the high-k oxide thin film12.
[8] However, in the case of atomic layer deposition, a post deposition annealing usually induces a silicon oxide interfacial layer regrowth13. This interfacial layer regrowth is detrimental in the case of CMOS transistor fabrication as the global capacitance decreases. All these methods present drawbacks; these drawbacks can be cost, can not be applied to all atom elements, reliability, carbon contamination, etc.
[9] Metal-electrode capacitors are widely used in mixed- signal/radio frequency (RF) ICs for better linearity and higher Q (quality factor) (due to lower electrode resistance). MIM (metal-insulator-metal) capacitors have been commercially available in the standard CMOS (complementary metal oxide silicon) mixed-signal process. One of the challenges concerning these devices is to grow an oxide on the top of the electrode without oxidizing said electrode. Many deposition methods are used and the most common method concerns the ALD technique. T he problem of high permeability to oxygen diffusion coming from the utilization of high-k compounds also remains in this case. Other devices such as the Micro-Electro-Mechanical systems (MEMs) require a careful control of the oxygen stoichiometry during its production. These refer to the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through micro-fabrication technology. In fact the control of the oxygen stoichiometry is one of the most important challenges as from this parameter will depend the properties of the materials used for the fabrication of these MEMs. Contrary to the electronics the MEMS are micromechanical components which are fabricated using compatible 'micromachining' processes that selectively etch away parts of the silicon wafer or add new structural layers to form the mechanical and electromechanical devices. The MEMs are mostly based on ferroelasticity and piezo- electricty properties and the most common integrated compound in these systems is Pb(Zr!.xTix)03 (PZT). The physical properties and more specifically the piezoelectric property of this compound highly depend of the oxygen stoichiometry. The need of a method to prevent the oxygen escape from the PZT is an actual present reality. In conclusion, the diffusion of oxygen through the interface must be blocked within a few atomic layers in the vicinity of the interface film layer/substrate and this barrier must block the oxygen diffusion in both ways: from film to the substrate and/or from substrate to the film.
Summary of the invention
One aspect of the present invention is a new method of producing oxide free interfaces in electronic devices. The method of the present invention involves the use of an oxygen diffusion barrier, namely a Mg interlayer which prevents the oxidation from occurring.
The present method comprises the steps of:
- providing an oxidisable substrate material or an oxygen containing substrate;
- depositing an interlayer of metallic magnesium over the substrate and;
- depositing a layer of material in the presence or absence of an oxidant onto the magnesium.
In one aspect of the present method the Mg interlayer avoids the diffusion of oxygen into the substrate during the deposition of the layer of material in the presence of an oxidant, thus avoiding the oxidation of its surface.
In another aspect of the invention the Mg interlayer avoids the diffusion of oxygen out of the oxygen containing substrate to the material layer being deposited, thus avoiding its oxidation. In this case, the oxidant is absent during the deposition of the layer of material, since it stays trapped within the substrate layer by the Mg interlayer.
Still within the scope of the present invention is the method of deposition and the resulting devices of different combinations of layers other than the above-mentioned, such as: - the deposition of an oxygen containing substrate followed by a Mg interlayer and the deposition of a layer of material in the presence of an oxidant, for complete control of the oxygen stoichiometry and oxidation level;
- the deposition of an oxidisable material followed by a Mg interlayer followed by the deposition of a layer of material in the absence of oxygen, to avoid oxidation by minute or residual amounts of oxygen present during the deposition process.
[16] In situations where the existence of the Mg interlayer is detrimental to the device performance the method further comprises the step of thermal treatment of the interfaces produced in the previous steps. This treatment diffuses the Mg interlayer into the substrate, material or both layers, thus creating a single interface where both substrate and material layers are not oxidized.
[17] Another aspect of the present invention is the products containing the interfaces
produced by the above-mentioned method. The products include catalysts, sensors, OLED's, display panel or electronic devices. Among the electronic devices or components CMOS, transistors, capacitors or micro-electromechanical systems can use advantageously the method of producing oxide free interfaces.
[18] The interlayer should be mostly composed of metallic magnesium but could also comprise some impurities of one or more of the following elements: B, N, Si, among others.
[19] It is an object of the present invention to eliminate the problems of oxygen diffusion or atoms diffusion from the environment into the support or substrate in the case of thin films deposition for microelectronics application or any application concerning coating or thin films deposition. However the present invention can also eliminate the problems of oxygen escape or atoms escape from the support or substrate into the chamber environment, thus avoiding oxidation and/or complete oxygen stoichiometry control during a deposition process.
Brief Description of the Drawings
[20] Figure 1: Scheme of a NMOS transistor, wherein: 100 - Substrate (ex.: Si); 101 - SiO 2 interlayer; 102 - High-k material; 104 - Electrode; 105 - Source; 106 - Drain; 111 - semi-conductive region of the substrate .
[21] Figure 2: Mg interlayer deposited between high-k gate oxide and silicon substrate, wherein: 100 - Substrate (ex.: Si); 102 - High-k material; 103 - Mg interlayer; 105 - Source; 106 - Drain; 111 - semi-conductive region of the substrate .
[22] Figure 3: Dissolution of the Mg interlayer in the high-k gate using an annealing
treatment, wherein: 100 - Substrate (ex.: Si); 102 - High-k material; 105 - Source; 106
- Drain; 107 - Mg interlayer diffused into adjacent layers; 111 - semi-conductive region of the substrate .
[23] Figure 4: X-ray reflectometry measurement performed on a metallic Mg thin film deposited on silicon substrate.
[24] Figure 5: TEM image of Hf02 thin film on metallic Mg interlayer deposited on
silicon substrate at 200°C.
[25] Figure 6: Mg interlayer deposited on a metallic electrode (TiN), wherein: 100 -
Substrate (ex.: Si); 101 - Si02 interlayer; 103 - Mg interlayer; 108 - Metallic electrode
(ex.: TiN).
[26] Figure 7: Mg interlayer deposited between high-k gate oxide and a metallic layer, wherein: 100 - Substrate (ex.: Si); 101 - Si02 interlayer; 102 - High-k material; 103 -
Mg interlayer; 108 - Metallic electrode (ex.: TiN).
[27] Figure 8: Dissolution of the Mg interlayer in the high-k gate and metallic electrode using an annealing treatment, wherein: 100 - Substrate (ex.: Si); 101 - Si02 interlayer;
102 - High-k material; 107 - Mg interlayer diffused into adjacent layers; 108 - Metallic electrode (ex.: TiN).
[28] Figure 9: Mg interlayer deposited on the PZT buffer layer, wherein: 100 - Substrate (ex.: Si); 101 - Si02 interlayer; 103 - Mg interlayer; 109 - Oxide thin film
(Pb(ZrxTl-x)03.
[29] Figure 10: Mg interlayer deposited between PZT buffer and the alloy on the top, wherein: 100 - Substrate (ex.: Si); 101 - Si02 interlayer; 103 - Mg interlayer; 109 - Oxide thin film (Pb(ZrxTl-x)03); 110 - Alloy or any other oxidisable material.
[30] Figure 11: Dissolution of the Mg interlayer in the PZT and alloy on the top using an annealing treatment, wherein: 100 - Substrate (ex.: Si); 101 - Si02 interlayer; 107 - Mg interlayer diffused into adjacent layers; 109 - Oxide thin film (Pb(ZrxTl-x)03); 110 - Alloy or any other oxidisable material.
[31] Figure 12: X-ray reflectometry measurement performed on a 200 A Hf02 thin film deposited on a metallic Mg thin film. The substrate is a Si wafer (Silicon). The graph shows a very low surface roughness and a thickness of 200 A.
[32] Figure 13: TEM image of the Hf02 thin film on metallic Mg interlayer deposited on silicon substrate at 400°C. The same film as in Fig. 12
Detailed Description of the Invention
[33] The following is a more detailed description of the present invention, which should be seen as preferred embodiments of the invention. Its purpose is to demonstrate particular applications of the invention and not to limit its scope or of the claims.
[34] The method of the present invention has a wide range of applications in the micro- and nanoelectronics but is not limited to them as it can be used in other processes where the oxygen control (stoichiometry or oxidation) is important.
[35] According to one aspect of the invention, for a silicon substrate 100 (Figure 2), the deposition of the Mg interlayer 103 is performed at a temperature ranging from room temperature to 630 °C, preferably in the range from 300 to 450°C, and most preferably at 400 °C.
[36] The deposition is performed by sputtering under an atmosphere of inert gas,
preferably Argon at a pressure of less than l.OE-1 mbar, preferably less than 5.0E-2 mbar and most preferably around 5E-3 mbar. Such pressures are preferred values for the steady state pressure within the reaction chamber during the deposition. The sputtering target can be a pure metal of the alkaline rare earth metal Mg.
[37] The deposition process can also be another physical deposition process (Pulse laser deposition (PLD), molecular beam epitaxy (MBE), electron Beam evaporation and all the derived processes) or a chemical deposition process (Chemical vapour deposition (CVD), Sol-gel deposition, Metalorganic chemical vapour deposition (MOCVD), Atomic layer deposition (ALD) and all the derived process from these processes). As this deposition is performed under reductive atmosphere, no Si02 or SiOx-based interlayer between the deposited metallic Mg layers 103 and the silicon substrate 100 is formed during the process. This metallic magnesium interlayer prevents the oxygen diffusion into the silicon substrate during the following deposition process of the high- k gate dielectric, which usually involves the utilization of oxygen or ozone as an oxidizing agent. The deposition of the oxide layer (Hf02 or other) is performed by the techniques known in the art.
[38] In one embodiment of the invention, the presence of this ultrathin Mg bulk metallic interface 103 between the high-k gate dielectric layers 102 and the semi-conductive region 111 of the silicon substrate 100 in the figure 2 would be detrimental for a CMOS application in an integrated circuit, as the metallic character of this interlayer will induce high leakage currents. In that case the CMOS component would present a behavior similar to a Metal-Insulator- Metal (MIM) component. So, a thermal annealing treatment step under oxygen, nitrogen, hydrogen, ammonia or a mixing of these different gases causes the diffusion of this metallic Mg interlayer into the high-k gate dielectric thin film, or into the silicon substrate or into both. The final state of the annealing treatment is shown Figure 3, and corresponds to the diffusion area 107 between the high-k gate dielectric 102 and the semi-conductive region 111.
[39] The deposition of metallic Mg layer requires a deposition technique which involves a higher surface energy to fix the Mg atoms onto the surface. Sputtering and PLD involve a much higher energy so that the link is stronger. Using sputtering we were able to grow thin Mg metallic thin film on silicon substrate without Si02 interlayer between the high-k gate dielectric 102 and the silicon substrate 100. Figure 4 shows a X-ray reflectometry measurements performed on a Mg metallic thin film deposited on HF-last pre-treated silicon substrate using sputtering process.
[40] The ultra thin Mg metallic interlayer approximates a thin semi-insulating layer,
which may induce valuable device applications. The isolation of different regions of an integrated circuit is a good example of application, but the Mg metallic interlayer should be ultra-thin in all the cases, with thickness between 0.2 and 5 nm. At 300°C or above it is possible to deposit the high-k gate dielectric oxide 102 directly on the top of this ultra thin Mg metallic interlayer without desorption or evaporation. Figure 5 shows a TEM image of Hf02 thin films directly deposited on the top of the Mg interlayer without visible Si02 interface between the silicon substrate and the Mg metallic thin film. No oxidation of the Mg metallic interlayer was observed.
[41] Another embodiment of the invention, relates to integrated circuits and m etal- electrode capacitors, which are widely used in mixed-signal/radio frequency (RF) ICs for better linearity and higher Q (quality factor) (due to lower electrode resistance). MIM (metal-insulator-metal) capacitors have been commercially available in the standard CMOS (complementary metal oxide silicon) mixed-signal process.
[42] The metallic Mg interlayer 103 is deposited on the top of the metallic electrode 108 (TiN in the example figure 6, but can be also composed by another metal or alloy) using sputtering (Figure 6) under the same conditions as defined above. The deposition process can also be another physical deposition process (Pulse laser deposition (PLD), molecular beam epitaxy (MBE), electron Beam evaporation and all the derived processes) or a chemical deposition process (Chemical vapour deposition (CVD), Sol- gel deposition, Metalorganic chemical vapour deposition (MOCVD), Atomic layer deposition (ALD) and all the derived process from these processes). As this deposition is performed under reductive atmosphere, the metallic electrode 108 is not oxidized during the deposition process. This metallic magnesium interlayer prevents the oxygen diffusion into the metallic electrode 108 (TiN) during the following deposition process of the high-k dielectric, which involves the utilization of oxygen or ozone as an oxidizing agent.
[43] In cases where the presence of this ultrathin metallic Mg bulk interface between the high-k and the metallic electrode 108 (TiN) is disadvantageous (Figure 7) for the MIM component in an integrated circuit a thermal annealing treatment step under oxygen, nitrogen, hydrogen, ammonia or a mixing of these different gases causes the diffusion of this metallic magnesium interlayer into the high-k gate dielectric thin film, or into the metallic electrode 108 (TiN) or into both. The process is shown Figure 8, and corresponds to the diffusion area 107 between the high-k dielectric and the metallic electrode 108 (TiN).
[44] Another embodiment c oncerning integrated circuits, relates to Micro- Electro-Mechanical systems (MEMs). This application corresponds to the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through micro-fabrication technology.
[45] The metallic Mg layer is deposited on the top of the oxide thin film 109 (Pb(Zri_xTix )03 (PZT) under the conditions defined above (figure 9), but can be also an oxide with a different composition) using sputtering (Figure 9). The deposition process can also be another physical deposition process (Pulse laser deposition (PLD), molecular beam epitaxy (MBE), electron Beam evaporation and all the derived processes) or a chemical deposition process (Chemical vapour deposition (CVD), Sol-gel deposition, Metalorganic chemical vapour deposition (MOCVD), Atomic layer deposition (ALD) and all the derived process from these processes). This metallic magnesium interlay er prevents the oxygen escape from the PZT oxide thin film 109 into the deposition chamber environment during the following deposition process of the metallic alloy 110, thus preventing the oxidation of the alloy.
[46] In cases where the metallic Mg bulk interface between the PZT oxide thin film 109 and the metallic alloy 110 is disadvantageous (Figure 10) for the MEM component functioning in an integrated circuit, a low temperature thermal annealing treatment step under oxygen, nitrogen, hydrogen, ammonia or a mixing of these different gases causes the diffusion of this metallic magnesium interlayer in the PZT oxide thin film 108, or into the metallic alloy 110 or into both. The Mg interlayer is shown Figure 11, and corresponds to the diffusion area 107 between the PZT oxide thin film 109 and the metallic alloy 110.
[47] The above described embodiments can be adapted to different materials and devices, whether electronic or not, as long as it is necessary to avoid the oxidation of the surface of the materials surfaces. The following example is a detailed explanation of one of the procedures, but does not limit the scope of the invention or its applicability with different deposition techniques, substrates or oxidants.
[48] Example 1: Deposition of Mg metallic interlayer at 400°C followed by the deposition of Hf02 thin film at 400°C
In the sputtering chamber, one silicon substrate that was previously cleaned by HF- last solution (9ml of water, 1 ml of methanol and 0,75ml of fluoric acid 40%) for 120s was introduced and fixed to the sample holder using a shadow mask. No thermal conductive paste was used.
[49] The chamber was evacuated up to the pressure of 5.0E-8 mbar.
[50] The sample holder inside the chamber was then heated up to 400°C under vacuum for about 5 hours and than Argon gas was introduced in the chamber up to the pressure of 5.0E-3 mbar. The pressure was controlled by a Mass Flow Controller.
[51] Then the plasma was ignited and was maintained for 15 minutes at 25 Watt rf power for target cleaning. During this pre-sputtering time a shutter was covering the substrate in order to prevent any deposition.
[52] After this pre-sputtering time the substrate shutter was opened and a Mg film was deposited under the following conditions: - Argon pressure: 5.0E-3 mbar
- Radiofrequency power: 25 Watt
- Target to substrate distance: 100 mm.
- Substrate temperature: 400 °C.
- Total deposition time: 3 minutes
[53] After the Mg deposition, the plasma was turned off, the substrate shutter was closed and the Hf02 plasma was ignited. The Hf02 target was cleaned for 10 minutes using 30 Watt of rf power. After this pre-sputter time a Hf02 thin film was deposited under the following conditions:
- Argon pressure: 5.0E-3 mbar
- Radiofrequency power: 28 Watt
- Target to substrate distance: 100 mm.
- Substrate temperature: 400 °C.
- Total deposition time: 20 minutes
[54] After the deposition of the Hf02 film, the plasma was turned off, the heater was
turned off and the film was allowed to cool down naturally at the deposition pressure of 5.0E-3 mbar (no active cooling was used).
[55] References
1 - J. Robertson, Reports on Progress in Physics 69, 327-396 (2006).
[56] 2 - G. D. Wilk, R. M. Wallace, and J. M. Anthony, J. Appl. Phys. 87, 484-492
(2000).
[57] 3 - K. Hyoungsub, C. M. Paul, C. Chi On, C. S. Krishna, and S. Susanne, Journal of
Applied Physics 96, 3467-3472 (2004).
[58] 4 - D. H. Triyoso, R. I. Hegde, J. Grant, P. Fejes, R. Liu, D. Roan, M. Ramon, D.
Werho, R. Rai, L. B. La, J. Baker, C. Garza, T. Guenther, J. B. E. White, and P. J.
Tobin, Journal of Vacuum Science & Technology B: Microelectronics and Nanometer
Structures 22, 2121-2127 (2004).
[59] 5 - Y. Senzaki, (U.S. Patent, WO 2005/050715 A2, 2005).
[60] 6 - A. C. Callegari, M. M. Frank, R. Jammy, D. L. Lacey, F. R. McFeely, and S.
Zafar, (U.S. Patent, WO 2006/076087, 2006).
[61] 7 - T. Suntola and J. U. S. P. Antson, in U.S. Patent 4058430 (1977).
[62] 8 - M. Ritala and M. Leskela, in In Handbook of Thin Film Materials, H. S. Nalwa
Ed.; Academic Press: San Diego, CA; Vol. 1 (2002), p. 103-159.
[63] 9 - N. Pinna and E. Rauwel, (U.K. and U.S. patent application, WO 2008/098963 A2,
2008).
[64] 10 - E. Rauwel, G. Clavel, M.-G. Willinger, P. Rauwel, and N. Pinna, Angew. Chem.
Int. Ed. 47, 3592 (2008).
[65] 11 - H. J. Osten, M. Czernohorsky, R. Dargis, A. Laha, D. Kiihne, E. Bugiel, and A. Fissel, Microelectronic Engineering 84, 2222-2225 (2007).
[66] 12 - L. Wang, K. C. Paul, A. Andre, and W. C. Nathan, Journal of Applied Physics
104, 054117 (2008).
[67] 13 - M. T. Ho, Y. Wang, R. T. Brewer, L. S. Wielunski, Y. J. Chabal, N. Moumen, and M. Boleslawski, Applied Physics Letters 87, 133103 (2005).

Claims

Claims
A method for producing a substantially oxide free interface in electronic devices comprising the steps of:
- providing an oxidisable substrate or an oxygen containing substrate;
- depositing a interlayer of metallic magnesium as oxygen diffusion barrier;
- depositing a layer of material in the presence or absence of an oxidant onto the Mg layer.
Method according to claim 1 wherein the Mg layer has a thickness in the range of 0.2 nm to 5 nm.
Method according to claim 2 wherein the deposition of the thin film coating of metallic Mg takes place at temperature ranging from room temperature to 630°C, preferably in the range from 300 to 450°C, and most preferably at 400°C.
Method according to claim 3 wherein the deposition of the thin film coating of metallic Mg occurs at a pressure from 105 to 5x10
1 mbar.
Method according to claim 4 wherein the Mg layer can be deposited by physical methods among them radiofrequency sputtering, DC sputtering, pulse laser deposition (PLD), molecular beam epitaxy (MBE), electron-beam evaporation or standard thermal evaporation.
Method according to claim 5 wherein the deposition process can be a chemical deposition process among them Chemical vapour deposition (CVD), Sol- gel deposition, Metalorganic chemical vapour deposition (MOCVD), Atomic layer deposition (ALD) or all the derived processes.
Method according to claim 6 wherein the deposition of the thin film coating of metallic Mg takes place under an inert atmosphere of Argon.
Method according to any preceding claim wherein the oxidisable substrate is silicon or a metal or a metal oxide.
Method according to any preceding claim wherein the oxidant is oxygen, ozone or air.
Method according to any preceding claim wherein the material deposited onto the Mg layer is a metal, a metal oxide or an alloy. Method according to any preceding claim wherein the metallic Mg could also comprise some impurities of one or more of the following elements: B, N, Si among others.
Method according to the previous claims comprising a further thermal treatment to induce the diffusion of the Mg interlayer into the substrate or into the material layer, or into both.
Method according to claim 12 wherein the thermal treatment is a thermal annealing step at temperatures ranging from 600°C to
1100°C.
Device containing a component produced by the method of claims 1 to 13 wherein said device is:
- an electronic device;
- a catalyst;
- a sensor;
- an OLED;
- display panel.
Device according to claim 14 wherein the electronic device is an electronic component, a CMOS, a transistor, a capacitor or a micro-electromechanical system.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8632745B1 (en) 2012-12-21 2014-01-21 Ut-Battelle, Llc Method and apparatus for controlling stoichiometry in multicomponent materials
CN109950134A (en) * 2019-03-19 2019-06-28 中国科学院上海高等研究院 Structure and preparation method thereof with sull

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4058430A (en) 1974-11-29 1977-11-15 Tuomo Suntola Method for producing compound thin films
US6498093B1 (en) * 2002-01-17 2002-12-24 Advanced Micro Devices, Inc. Formation without vacuum break of sacrificial layer that dissolves in acidic activation solution within interconnect
US20050050715A1 (en) 2003-09-04 2005-03-10 Headway Technologies, Inc. Method of manufacturing thin-film magnetic head
US20060076087A1 (en) 2002-04-29 2006-04-13 Shiqiang Liu Modified sintered RE-Fe-B-type, rare earth permanent magnets with improved toughness
US20060214305A1 (en) * 2005-01-21 2006-09-28 Atsuko Sakata Semiconductor device having oxidized metal film and manufacture method of the same
US7274080B1 (en) * 2003-08-22 2007-09-25 International Business Machines Corporation MgO-based tunnel spin injectors
WO2008098963A2 (en) 2007-02-13 2008-08-21 University Of Aveiro Method of forming an oxide thin film

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4058430A (en) 1974-11-29 1977-11-15 Tuomo Suntola Method for producing compound thin films
US6498093B1 (en) * 2002-01-17 2002-12-24 Advanced Micro Devices, Inc. Formation without vacuum break of sacrificial layer that dissolves in acidic activation solution within interconnect
US20060076087A1 (en) 2002-04-29 2006-04-13 Shiqiang Liu Modified sintered RE-Fe-B-type, rare earth permanent magnets with improved toughness
US7274080B1 (en) * 2003-08-22 2007-09-25 International Business Machines Corporation MgO-based tunnel spin injectors
US20050050715A1 (en) 2003-09-04 2005-03-10 Headway Technologies, Inc. Method of manufacturing thin-film magnetic head
US20060214305A1 (en) * 2005-01-21 2006-09-28 Atsuko Sakata Semiconductor device having oxidized metal film and manufacture method of the same
WO2008098963A2 (en) 2007-02-13 2008-08-21 University Of Aveiro Method of forming an oxide thin film

Non-Patent Citations (9)

* Cited by examiner, † Cited by third party
Title
D. H. TRIYOSO; R. I. HEGDE; J. GRANT; P. FEJES; R. LIU; D. ROAN; M. RAMON; D. WERHO; R. RAI; L. B. LA, JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B: MICROELECTRONICS AND NANOMETER STRUCTURES, vol. 22, 2004, pages 2121 - 2127
E. RAUWEL; G. CLAVEL; M.-G. WILLINGER; P. RAUWEL; N. PINNA, ANGEW. CHEM. INT. ED., vol. 47, 2008, pages 3592
G. D. WILK; R. M. WALLACE; J. M. ANTHONY, J. APPL. PHYS., vol. 87, 2000, pages 484 - 492
H. J. OSTEN; M. CZERNOHORSKY; R. DARGIS; A. LAHA; D. KIIHNE; E. BUGIEL; A. FISSEL, MICROELECTRONIC ENGINEERING, vol. 84, 2007, pages 2222 - 2225
J. ROBERTSON, REPORTS ON PROGRESS IN PHYSICS, vol. 69, 2006, pages 327 - 396
K. HYOUNGSUB; C. M. PAUL; C. CHI ON; C. S. KRISHNA; S. SUSANNE, JOURNAL OF APPLIED PHYSICS, vol. 96, 2004, pages 3467 - 3472
L. WANG; K. C. PAUL; A. ANDRE; W. C. NATHAN, JOURNAL OF APPLIED PHYSICS, vol. 104, 2008, pages 054117
M. RITALA; M. LESKELA: "Handbook of Thin Film Materials", vol. 1, 2002, ACADEMIC PRESS, pages: 103 - 159
M. T. HO; Y. WANG; R. T. BREWER; L. S. WIELUNSKI; Y. J. CHABAL; N. MOUMEN; M. BOLESLAWSKI, APPLIED PHYSICS LETTERS, vol. 87, 2005, pages 133103

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8632745B1 (en) 2012-12-21 2014-01-21 Ut-Battelle, Llc Method and apparatus for controlling stoichiometry in multicomponent materials
CN109950134A (en) * 2019-03-19 2019-06-28 中国科学院上海高等研究院 Structure and preparation method thereof with sull

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