WO2011069277A1 - Procédé de mise en œuvre hautement efficace d'une désadaptation de débit mettant en jeu une combinaison harq appliqué à la norme lte - Google Patents

Procédé de mise en œuvre hautement efficace d'une désadaptation de débit mettant en jeu une combinaison harq appliqué à la norme lte Download PDF

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Publication number
WO2011069277A1
WO2011069277A1 PCT/CN2009/001413 CN2009001413W WO2011069277A1 WO 2011069277 A1 WO2011069277 A1 WO 2011069277A1 CN 2009001413 W CN2009001413 W CN 2009001413W WO 2011069277 A1 WO2011069277 A1 WO 2011069277A1
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WIPO (PCT)
Prior art keywords
buffer
tail
nulls
combining
bytes
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PCT/CN2009/001413
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English (en)
Inventor
Wei Fan
Weifeng Li
Jiajun Zhang
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Texas Instruments Incorporated
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Priority to CN200980119983.8A priority Critical patent/CN102792624B/zh
Priority to PCT/CN2009/001413 priority patent/WO2011069277A1/fr
Priority to US12/869,901 priority patent/US8433987B2/en
Publication of WO2011069277A1 publication Critical patent/WO2011069277A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6525—3GPP LTE including E-UTRA
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0066—Parallel concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]

Definitions

  • Embodiments of the invention are directed, in general, to
  • E-UTRAN LTE long term evolution of UTRAN
  • UE user equipment such as a mobile station or mobile terminal
  • HARQ is a scheme for re-transmitting a packet to compensate for an erroneous packet.
  • HARQ is useful for instances when an error occurs in the reception of an initially transmitted data packet.
  • HARQ functionality helps ensure accurate delivery between peer entities at L1 .
  • HARQ uses multiple stop-and-wait processes operating in parallel. For example, for each transport block received in the UL, an acknowledgment is transmitted from the Node B to the UE after the receiver of the Node B performs a CRC to indicate a successful decoding (ACK) or to request a retransmission of the erroneously received transport block (NACK).
  • ACK successful decoding
  • NACK retransmission of the erroneously received transport block
  • UL signaling includes the one-bit HARQ positive/negative acknowledgement (HARQ-ACK/NACK), and five-bit measurement report (CQI), as non-limiting examples.
  • HARQ-ACK/NACK the one-bit HARQ positive/negative acknowledgement
  • CQI five-bit measurement report
  • the UL signaling information or status report is processed by a MAC sublayer.
  • These ACK/NACK messages are generally transmitted with special physical layer signaling independent of data transmission.
  • HARQ may also be used in the DL in a similar manner.
  • E- UTRAN utilizes HARQ in both the UL and DL.
  • a HARQ message i.e., ACK or NACK
  • An ACK is signaled after the receiver of the UE performs a CRC that indicates a successful decoding while a NACK comprises a request for retransmission of an erroneously received (e.g., erroneously decoded) transport block.
  • FIG. 1 is a block diagram illustrative of a rate matching stage as known in the art.
  • FIG. 2 shows an example of the dual-matrix structure.
  • FIG. 4 shows an example of a Log-Likelihood Ratio LLR combining stage in accordance with embodiments of the invention.
  • FIG. 5 is a flowchart illustrative of Log-Likelihood Ratio LLR combining in accordance with embodiments of the invention.
  • FIG. 6 depicts the group partition in the systematic matrix.
  • FIG. 7 shows that the processing flow of matrix transposing is identical with that for systematic stream.
  • FIG. 8 depicts the group partition in the interlaced parity matrix.
  • FIG. 9 depicts output buffer arrangement.
  • FIG. 10 is flow diagram illustrative of the output buffer arrangement.
  • the de-rate matching stage of the bit processing performed on the uplink is the inverse process of the rate matching stage performed in UE. This rate matching stage must be completed for each code block of each allocation.
  • the rate matching stage as in known in the art is depicted as 100 in FIG. 1.
  • the output from turbo encoder 110 has three streams which are called systematic 113, parityl 111 and parity2 112 respectively. Each stream passes through a sub-block interleaver 120.
  • the interleaver for the systematic stream 123 and the interleaver for parityl stream 21 have the same structure (called sub- block interleaver 01 here) and the interleaver for the parity2 stream 122 is different (called sub-block interleaver 2 here).
  • parityl and parity2 streams are interlaced with each other 130.
  • the resultant stream is then concatenated with the output of the interleaver of the systematic stream.
  • the concatenation 140 starts with the output of the interleaver 123 of the systematic stream and followed by the interlaced stream.
  • the buffer used to hold the concatenation output is called virtual circular buffer 150.
  • There are four permissible starting locations in the virtual circular buffer 150 having starting location selection 160 and output with NULL bypassing 180. The specific starting location for the current transmission is selected by the redundancy version index, denoted by rvidx 170.
  • There are NULL bits in the virtual circular buffer which are dummy bits generated during the code block
  • the rate matching module outputs the bits 190 in the virtual circular buffer bit by bit starting from the location identified by rvidx, skipping NULL bits.
  • NULL bits generated at the transmitter there are two kinds of NULL bits generated at the transmitter, one called filler bits generated during code block segmentation and the other called padding bits generated during sub-block interleaving.
  • Filler bits can only exist in the systematic and parityl streams of the first code block of a transport block and its number is denoted by F per stream.
  • the number of filler bits, F, of the systematic stream and that of parityl stream of one code block are always identical. If there were no restrictions on the transport block size, then the value of F could range from 0 to 63.
  • Padding bits can exist in any code block of a transport block and its number is denoted by ND per stream.
  • the number of padding bits, ND stays the same for all the streams of a code block.
  • the code block size K is always a multiple of 8. After turbo coding, the block size increases to K+4. So, the value range of ND is 4, 12, 20 and 28 which are all of the possible remainder of 8x+4 divided by 32.
  • the bits in the virtual circular buffer 150 have a dual-matrix-like internal structure.
  • this dual-matrix we call this dual-matrix as interleaver dual-matrix.
  • FIG. 2 shows an example of the interleaver dual-matrix structure.
  • the interleaver dual-matrix structure 200 is formed by sequentially taking the bits from the virtual circular buffer 150. Keeping the structure of this dual-matrix in mind clearly is the key to understanding the design.
  • the interleaver dual-matrix structure 200 is a back to back combination of the systematic matrix 210 and the interlaced parity matrix 220, R is the number of rows in the systematic matrix, and ND and F are defined as above.
  • Embodiments of the invention simplify the de-rate matching stage.
  • the improvements provided by the embodiments depend heavily on a new feature introduced in the 8.4.0 specification version.
  • 3GPP TS-36.212 v8.4.0 there are two kinds of NULLs as described above.
  • F is always equals to 0.
  • a future specification could simplify the description related to filler bits.
  • LLR Log-Likelihood Ratio
  • the history buffer doesn't contain NULLs and can be combined with the receiving buffer easily without concern for NULLs, once the starting location in the history buffer for the current transmission (called kO) is known.
  • 0(i)(j) can be calculated easily and the result is summarized in Table 2.
  • the 'tail' comprising input tail 450 and output tail 455 in FIG. 4 denotes index of the last data bit in the circular buffer 430 plus 1 and is useful to determine the summation area 440 and copy area 460.
  • LLR combining module 420 updates and outputs the value of 'tail' for the next retransmission. Tail may be updated to 455 by the LLP combining module 420
  • FIG. 5 depicts a flowchart of the Log-Likelihood Ratio LLR combining which outlines how summation is avoided. Note that sometimes we do summation although it is possible to replace it by copy for simpler code and better execution efficiency for small code blocks.
  • Flowchart 500 starts at 501.
  • initFlag 1
  • the area not to be covered by new data is set to zero 520.
  • buffer is not full nor small enough it is determined if there is an overlap between new and history data 550. If there is an overlap between new and history data and the new data is beyond the overlap region 560, the starting location in the circular buffer for current combining (kO) is subtracted from the index of the last data bit in the circular buffer before combining (tail). The (tail-kO) bytes are summed with no buffer wrap 563. If the new data is not beyond the overlap region, the E bytes are summed with no buffer wrap and the processing continues to 590.
  • the embodiments of the invention split the de-rate matching stage into three stages: NULL insertion, stream separation and de-interleaving. Every stage involves in some kind of data processing and memory moving.
  • the NULL insertion and stream separation stages make the input to the de-interleaver more regular and allow for a simpler de-interleaving operation. However, this functional splitting is not a must.
  • the three stages are merged into a single stage and the execution efficiency is improved greatly.
  • Embodiments of the invention are presented in the following order:
  • the input of the de-interleaver for the systematic streams contains NULLs in the correct locations, so that we can see the data block to be de-interleaved as a complete R*32 matrix (the systematic matrix in FIG. 2).
  • the way to handle NULLs which in fact do not exist in the input buffer of de-interleaver will be given in Bypassing NULLs section below.
  • the soft bits in the systematic matrix are separated into 4 groups based on the input column indices from the viewpoint of de-interleaver:
  • GroupO's input column indices [0, 16, 8, 24, 4, 20, 12, 28]; • Groupl 's input column indices: [2, 18, 10, 26, 6, 22, 14, 30] which are just groupO's indices plus 2;
  • Group2's input column indices [1 , 17, 9, 25, 5, 21 , 13, 29] which are just groupO's indices plus 1 ;
  • Group3's input column indices [3, 19, 1 1 , 27, 7, 23, 15, 31 ] which are just groupO's indices plus 3.
  • Each group's input column indices are ordered such that the
  • the loading address offset to the beginning of the input buffer is R * P'(8 * i+k)+8 * j, where P'(x) is defined in Table 1 .
  • 8 output register pairs are generated as aObOcOdOeOfOgOhO, a1 b1c1d1e1f1g1 h1 , a2b2c2d2e2f2g2h2, a3b3c3d3e3f3g3h3, a4b4c4d4e4f4g4h4, a5b5c5d5e5f5g5h5, a6b6c6d6e6f6g6h6 and a7b7c7d7e7f7g7h7, with each register pair holding one row (8 bytes), which are saved by _mem8 instructions.
  • the saving address offset to the beginning of the output buffer is
  • FIG. 7 is for the big endian platform and the processing flow for the little endian platform is different but with the same principle.
  • transposing can be performed just as the complete matrix, except that the final memory savings are executed conditionally.
  • the soft bits in the interlaced parity matrix are separated into 4 groups based on the input column indices and the rule is identical with systematic streams in the last section.
  • a1 b1 c1 d1 e1f1g1 h1 , a2b2c2d2e2f2g2h2 and a3b3c3d3e3f3g3h3 are saved into parityl stream output buffer, and AOBOCODOEOFOGOHO, A1 B1 C1 D1 E1 F1 G1 H1 , A2B2C2D2E2F2G2H2 and A3B3C3D3E3F3G3H3 are saved into parity2 stream output buffer.
  • the loading address offset for the k-th column of the j-th soft bit matrix in the i-th group is identical with that for the systematic stream,
  • the saving address offset is to the beginning of the parityl output buffer and should be 32 * (4*j+k)+8*i.
  • the saving address offset is to the beginning of the parity2 output buffer and should be 32*(4*j+k)+8 * i+1 , which is explained as below.
  • AOBOCODOEOFOGOHO are the soft bits from the same input locations of parityl stream and parity2 stream respectively, so the saving address offset of
  • AOBOCODOEOFOGOHO is one byte larger than that of aObOcOdOeOfOgOhO.
  • the output buffer of the parity2 stream has one byte spilling and the spilled byte should be wrapped into the first byte of the buffer.
  • this wrapping operation because this byte always holds a NULL bit and the NULLs at the beginning of output buffer are skipped through pointer offsetting before calling turbo decoder, since these NULLs do not involve in turbo decoding.
  • this wrapping operation because this byte always holds a NULL bit and the NULLs at the beginning of output buffer don't involve in turbo decoding.
  • the input buffer of de- interleaver contains NULLs in the correct locations and give the expressions to calcalate the loading address offsets.
  • the LLR combining section there are no NULLs in the input buffer of de-interleaver and the address offsets calculated in the way that the last sections present should be subtracted by a revisional value to take NULLs into account.
  • the revisional value of input address offset for the j-th input column is just the total number of NULLs in column 0 to j and depends on ND and whether we are de-interleaving systematic stream or interlaced parity stream. We denote the revisional value by S(i)(j) for the
  • the output of the de-interleaver described above contains ND NULLs at the head of each stream, while the turbo decoder following the de-rate matching stage doesn't need these NULLs. So, we arrange the three streams in the output buffer of de-rate matching as FIG. 9, where K is the code block size before turbo encoder at the transmitter.
  • FIG. 9 depicts output buffer 900 arrangement.
  • Output buffer of the systematic stream is 920.
  • Output buffer of the parityl stream is 930.
  • Output buffer of the parity2 stream is 940.
  • 950 is the head spilling area of the systematic stream.
  • the interlaced parity stream is de-interleave first and overlapped segment 960 will be overlaid by the output of the following systematic stream de-interleaver.
  • the parityl storing to overlapped segment 970 is always later than the parity2 storing to the same location.
  • 980 is the tail spilling area of parity2 stream.
  • 990 is decoding data segment.
  • FIG. 10 is flow diagram illustrative of the output buffer arrangement.
  • Receiving buffer 1060 receives data without NULLs. Data is input into LLR combining block 1050. History data without NULLs comprises two streams systematic 1071 and parity 1072. History data are buffered in the history buffers 1070 located in a DDR memory. LLR combining is called before de-rate matching.
  • the history buffers 1070 do not contain NULLs and may be combined with the receiving buffer 1060 using direct memory access (DMA) 1075 easily without concern for NULLs.
  • DMA direct memory access
  • the code rate is mostly greater than 1/3 and only the current transmitted part needs to be input into a cache, combined and DMA back to DDR 1047 --reducing processing resources and DDR throughput.
  • LLR output without NULLs is sent to sub-block deinterleaver 1030.
  • LLR output is buffered in buffers 1040 and comprises two streams a systematic stream 1041 and a parity stream 1042.
  • Forge NULLs by offsetting reading pointer to load from LLR combining output buffer 1040.
  • Sub-block de-interleaver output without NULLs is sent to the turbo decoder 1010.
  • Sub-block output is buffered in buffers 1020 and comprises three streams systematic 1021 , parityl 1022 and parity2 1023.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne, selon des modes de réalisation, un procédé de désadaptation de débit sans saut de bits NULS. Selon le procédé, des données sans bits NULS sont reçues et appliquées à un bloc de combinaison à logarithme du rapport de vraisemblance (LLR). Les données historiques sans bits NULS sont mises en mémoire-tampon. La combinaison LLR est mise en œuvre préalablement à la désadaptation de débit. La sortie du bloc de combinaison LLR est désentrelacée. Un pointeur de lecture est décalé pour créer des bits NULS. La sortie désentrelacée sans bits NULS est enfin transmise à un décodeur turbo.
PCT/CN2009/001413 2009-12-10 2009-12-10 Procédé de mise en œuvre hautement efficace d'une désadaptation de débit mettant en jeu une combinaison harq appliqué à la norme lte WO2011069277A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN200980119983.8A CN102792624B (zh) 2009-12-10 2009-12-10 为lte高效实施包括harq结合的解速率匹配的方法
PCT/CN2009/001413 WO2011069277A1 (fr) 2009-12-10 2009-12-10 Procédé de mise en œuvre hautement efficace d'une désadaptation de débit mettant en jeu une combinaison harq appliqué à la norme lte
US12/869,901 US8433987B2 (en) 2009-12-10 2010-08-27 Method for high-efficient implementation of de-rate matching including HARQ combining for LTE

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PCT/CN2009/001413 WO2011069277A1 (fr) 2009-12-10 2009-12-10 Procédé de mise en œuvre hautement efficace d'une désadaptation de débit mettant en jeu une combinaison harq appliqué à la norme lte

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