WO2011063730A1 - 内存镜像处理方法、装置和系统 - Google Patents

内存镜像处理方法、装置和系统 Download PDF

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Publication number
WO2011063730A1
WO2011063730A1 PCT/CN2010/078956 CN2010078956W WO2011063730A1 WO 2011063730 A1 WO2011063730 A1 WO 2011063730A1 CN 2010078956 W CN2010078956 W CN 2010078956W WO 2011063730 A1 WO2011063730 A1 WO 2011063730A1
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Prior art keywords
memory
data
written
module
interface module
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PCT/CN2010/078956
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English (en)
French (fr)
Inventor
罗娇林
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成都市华为赛门铁克科技有限公司
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Publication of WO2011063730A1 publication Critical patent/WO2011063730A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit

Definitions

  • the present invention claims the priority of the Chinese patent application filed on November 27, 2009, the Chinese Patent Application No. 200910225675.5, entitled “Memory Image Processing Method, Apparatus and System,"
  • the present invention relates to the field of storage technologies, and in particular, to a memory mirror processing method, apparatus, and system.
  • a storage controller sets a certain amount of memory as a cache, and after storing data in a Cache, it can feed back a response to the host, thereby reducing the delay of host access.
  • memory is a volatile storage medium that can easily lose data in the event of a power failure or failure of the storage controller.
  • a single storage controller cannot guarantee the reliability of stored data.
  • the prior art storage controller may include two or more controllers, and a mirrored link connection for transmitting mirrored data may be adopted between these controllers.
  • the central processing unit can write data to the cache in the Cache of the local controller. Space, and then copy the data from the buffer storage space to the storage space corresponding to the actual physical address in the Cache, and the CPU can control the local controller to apply for the Cache space to the peer controller connected thereto, and copy the data to In the Cache space of the application, the peer controller then copies the data from the Cache space to the storage space corresponding to the actual physical address for backup.
  • the local controller loses power or fails, data is also stored in the Cache of the peer controller, thereby preventing data loss.
  • the CPU needs to process communication fines in the process of controlling data mirroring.
  • the CPU has a large operation load; moreover, the data needs to be copied multiple times during the process of writing the local controller and mirroring to the peer controller, thereby increasing the delay of data storage.
  • Embodiments of the present invention provide a memory mirror processing method, apparatus, and system, which reduce the number of times a file to be written is copied, and reduce the delay of data storage.
  • An embodiment of the present invention provides a memory mirroring processing apparatus, including:
  • a memory interface module configured to receive data to be written through a standard memory interface, and send an access request to the image processing module
  • the image processing module is configured to receive an access request sent by the memory interface module, and send the data that needs to be backed up in the data to be written to when the access request is an external request to access the peer controller Communication interface module;
  • the communication interface module is configured to receive the data that needs to be backed up sent by the image processing module, and send the data that needs to be backed up to a memory mirror processing device of the peer controller, so that the peer controller
  • the memory mirror processing device performs backup processing on the data that needs to be backed up.
  • the embodiment of the present invention provides a memory mirroring processing system, including at least two controllers connected to each other, each of which includes a central processing unit, a memory mirroring processing device, and a physical memory as a cache.
  • the memory mirroring processing device includes:
  • a memory interface module configured to receive data to be written through a standard memory interface under the control of the central processing unit, and send an access request to the image processing module;
  • the image processing module is configured to receive an access request sent by the memory interface module, and when the access request is an external request for accessing the peer controller, the data to be written needs to be backed up. Data is sent to the communication interface module;
  • the communication interface module is configured to receive the data that needs to be backed up sent by the image processing module, and send the data that needs to be backed up to a memory mirror processing device of the peer controller, so that the peer controller
  • the memory mirror processing device performs backup processing on the data that needs to be backed up;
  • a memory control module configured to receive, by the image processing module, the to-be-written data sent by the image processing module when the access request is an internal request for accessing the local controller, and Writing the data to be written into the physical memory.
  • the embodiment of the invention provides a memory mirroring processing method, including:
  • the backup data is sent to the memory mirror processing device of the peer controller, so that the memory mirror processing device of the peer controller performs backup processing on the data that needs to be backed up.
  • the memory interface module, the communication interface module, and the image processing module capable of providing a standard memory interface are implemented in the process of storing the data to be written, the CPU only needs to perform macro control on the data mirroring process. The specific communication interaction can be completed by the hardware, thereby reducing the operational burden of the CPU.
  • the image processing module can store data in the physical memory of the local controller, or can be controlled at the opposite end. The data is backed up, which reduces the number of times the data to be written is copied, and reduces the delay of data storage.
  • FIG. 1 is a schematic structural diagram of an embodiment of a memory mirroring processing apparatus according to the present invention
  • FIG. 2 is a schematic structural diagram of another embodiment of a memory mirroring processing apparatus according to the present invention
  • FIG. 3 is a schematic structural diagram of an embodiment of a memory mirroring processing system according to the present invention
  • 4 is a schematic structural diagram of another embodiment of the memory mirroring processing system of the present invention
  • FIG. 1 is a schematic structural diagram of an embodiment of a memory mirroring processing apparatus according to the present invention
  • FIG. 2 is a schematic structural diagram of another embodiment of a memory mirroring processing apparatus according to the present invention
  • FIG. 3 is a schematic structural diagram of an embodiment of a memory mirroring processing system according to the present invention
  • 4 is a schematic structural diagram of another embodiment of the memory mirroring processing system of the present invention
  • FIG. 5 is a schematic structural diagram of still another embodiment of the memory mirroring processing system of the present invention
  • FIG. 6 is a schematic structural diagram of still another embodiment of the memory mirroring processing system of the present invention
  • FIG. 7 is a flowchart of an embodiment of a memory mirroring processing method according to the present invention
  • FIG. 8 is a flowchart of another embodiment of a memory mirroring processing method according to the present invention.
  • FIG. 1 is a schematic structural diagram of an embodiment of a memory image processing apparatus according to the present invention. As shown in FIG.
  • the apparatus of this embodiment includes: a memory interface module 1 1 , a communication interface module 13 , and a mirror processing module 14 , wherein the memory interface
  • the module 11 is configured to receive the data to be written through the standard memory interface, and send an access request to the image processing module.
  • the image processing module 14 is configured to receive the access request sent by the memory interface module 11, and the access request is controlled by the access peer.
  • the data to be backed up in the data to be written is sent to the communication interface module 13;
  • the communication interface module 13 is configured to receive the data to be backed up sent by the image processing module 14, and the The data to be backed up is sent to the memory mirror processing device of the peer controller, so that the memory mirror processing device of the peer controller is opposite.
  • the data that needs to be backed up is backed up.
  • the memory interface module 11 can provide a standard memory interface. After being encapsulated by the memory interface module 11, the bridge considers that the memory image processing device of this embodiment is a standard double rate.
  • the image processing module 14 mainly processes the control logic of the image, and receives the access request sent by the memory interface module 11, and then determines whether the access request is an internal request for accessing the local controller or an external request for accessing the peer controller. When the access request is an external request for accessing the peer controller, the image processing module 14 can send the data that needs to be backed up in the data to be written to the memory mirror processing device of the peer controller through the communication interface module 13 , thereby The memory mirroring processing device of the peer controller can perform backup processing on the data that needs to be backed up, and the memory mirroring processing device of the peer controller can be the same as the memory mirroring processing device in this embodiment.
  • the data that needs to be backed up may be all data to be written, or may be part of the data to be written.
  • the memory mirroring device of the embodiment can implement memory virtualization inside the controller by using hardware, and virtualize the memory of the peer controller as local memory. For the CPU, there is no difference between the virtualized memory and the normal memory. , has a separate address space. For data written to the CPU, the memory mirroring device automatically backs up the data through a memory mirroring device in one or more other controllers.
  • the memory image processing device of this embodiment may be a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (IC).
  • the memory image processing device of this embodiment may be an FPGA chip or an AS IC chip, and is connected to a data bus inside the computer system, and the FPGA chip or the ASIC chip may be connected to a mainstream memory chip.
  • the FPGA chip or the AS IC chip appears to be a standard DDR memory, and the FPGA chip or the ASIC chip can intercept and parse the DDR signal, and write the data into the cache of the local controller.
  • the data can also be mirrored to the cache of another controller or controllers via the PCIE data channel.
  • the FPGA chip or the ASIC chip can operate on the entire storage range of the memory chip to which it is connected, it is not necessary to store the data in a fixed space within the memory chip as in the prior art, and then copy the data and then transfer the data. Save to the actual physical storage space.
  • the device of this embodiment can be provided in the process of storing data to be written.
  • the memory interface module of the standard memory interface and the hardware implementation of the communication interface module and the image processing module therefore, the CPU only needs to perform macro control on the data mirroring process, and the specific communication interaction can be completed by the hardware, thereby reducing the operating burden of the CPU; Moreover, in the data mirroring process, the image processing module can back up data in the peer controller, thereby reducing the number of times the data to be backed up is copied during the data mirroring process, and the delay of the data storage is reduced.
  • the apparatus of this embodiment further includes: a memory control module 12, the memory control module, on the basis of the apparatus shown in FIG.
  • the module 12 is connected to the image processing module 14 and the physical memory as a cache.
  • the memory control module 12 is configured to receive the data to be written sent by the image processing module 14 when the access request is an internal request for accessing the local controller. And writing the to-be-written data into the physical memory.
  • the image processing module 14 can send data to the physical memory through the memory control module 12, thereby storing the write data in the local controller.
  • the memory interface module 11 can be connected to a data bus, and the central processing unit can be connected to the data bus through a north bridge. Therefore, the memory interface module 11 can receive the data to be written transmitted by the north bridge connected to the data bus and the central processing unit.
  • the memory interface module 11 can be coupled to a central processing unit. Therefore, the memory interface module 11 can also directly receive the data to be written sent by the central processing unit.
  • the CPU since the memory interface module capable of providing a standard memory interface and the hardware implementation of the communication interface module and the image processing module are used in the process of storing the data to be written, the CPU only needs to macroscopically perform the data mirroring process.
  • the image processing module can store data in the physical memory of the local controller through the memory control module, The data can be backed up in the peer controller, which reduces the number of times the data to be backed up is copied during the data mirroring process, and reduces the delay of the data storage.
  • the system of this embodiment may include: at least two controllers 2 connected to each other, each controller including a central processing unit 21,
  • the memory image processing device 22 and the physical memory 23 as a cache the memory image processing device 22 may include: a memory interface module 221, a memory control module 222, a communication interface module 223, and a mirror processing module 224, wherein the memory interface module 221,
  • the unit 21 receives the data to be written through the standard memory interface, and sends an access request to the image processing module 224.
  • the image processing module 224 is configured to receive the access request sent by the memory interface module 221, and the access request is When the external request of the peer controller is accessed, the data to be backed up in the data to be written is sent to the communication interface module 223; the communication interface module 223 is configured to receive the data to be backed up sent by the image processing module 224, and The data that needs to be backed up is sent to the memory mirror processing device of the peer controller, so that the memory mirror processing device of the peer controller performs backup processing on the data that needs to be backed up; the memory control module 222 and the image processing module The 224 is connected to the physical memory 23, and the memory control module 222 is configured to receive the data to be written sent by the image processing module 224 when the access request is an internal request for accessing the local controller, and the data to be written is Write to the physical memory 23.
  • the memory image processing system of the embodiment may include two controllers 2, and each controller includes: a memory interface module 221, a memory control module 222, a communication interface module 223, and a mirror processing module 224.
  • the communication interface module 223 of the two controllers can be connected through a data channel, and the two controllers can back up each other.
  • the memory interface module 221 can provide a standard memory interface.
  • the bridge After being encapsulated by the memory interface module 221, the bridge will consider the memory mirror processing device 22 to be a standard DDR memory; the memory control module 222 can be the memory.
  • the image processing device 22 provides an external interface through which the physical memory 23, which is externally cached, can be attached to the memory image processing device 22.
  • the image processing module 224 primarily processes the control logic of the image.
  • the memory interface module 221 of the controller 2 on the left in FIG. 3 can receive an access request sent by the CPU 21 or other unit under the control of the CPU 21, and then the memory interface module 221 can forward the access request to the image.
  • the processing module 224, the image processing module 224 can determine that the access request is the local controller, that is, the internal request of the controller 2 on the left in FIG. 3 or the access to the peer controller, that is, the outside of the controller 2 on the right in FIG.
  • the image processing module 224 can send data to the cache of the physical memory 23 through the memory control module 222 for the internal request to access the local controller, and the image processing is performed for the external request to access the peer controller.
  • the module 224 can send the data to the communication interface module 223 of the memory mirror processing device 22 in the peer controller through the communication interface module 223, so that the peer controller performs backup processing on the data, and the memory mirror processing in the peer controller
  • the device may be the same as the memory mirror processing device in this embodiment, and the data is The process of performing backup processing is also the same as the above process, and will not be described again.
  • the memory mirroring processing device 22 of the embodiment can implement memory virtualization inside the controller by using hardware, and virtualize the memory of the peer controller as local memory, and the virtualized memory and the normal memory of the CPU 21 do not have any The difference is that there is a separate address space.
  • the memory image processing device 22 of this embodiment may be an FPGA chip or an AS IC chip, and is connected to a data bus inside the computer system, and the FPGA chip or the AS IC chip may be connected to a mainstream memory chip.
  • the FPGA chip or the AS IC chip appears to be a standard DDR memory.
  • the FPGA chip or the AS IC chip can intercept the DDR signal and parse it, while writing data into the cache of the local controller.
  • the data can also be mirrored to the cache of one or more controllers via the PC Ie data channel.
  • the FPGA chip or the AS IC chip can operate on the entire storage range of the connected memory chip, it is not necessary to store the data in a fixed space within the memory chip as in the prior art, and then copy the data. Transfer to the actual physical storage space.
  • the system in this embodiment only has two controllers backed up from each other. It can be understood by those skilled in the art that when more than two controllers need to be backed up each other, a switch chip can be used. Such techniques are used to connect these controllers to achieve interconnection between these controllers. For each controller, the structure described above can be used, and will not be described again.
  • the memory interface module capable of providing a standard memory interface and the hardware control module, the communication interface module, and the image processing module are implemented in the process of storing the data to be written, the CPU only needs to use the data.
  • the mirroring process performs macro control, and the specific communication interaction can be completed by the hardware, thereby reducing the operational burden of the CPU.
  • the image processing module can store data in the physical memory of the local controller. Data can be backed up in the peer controller, which reduces the number of times the data to be written is copied, and reduces the delay of data storage.
  • FIG. 4 is a schematic structural diagram of another embodiment of a memory mirroring processing system according to the present invention.
  • the system of the embodiment is based on the system shown in FIG. 3.
  • the memory interface module 221 and the data bus 24 are shown.
  • the central processing unit 21 is connected to the data bus 24 via a north bridge 25.
  • more 10 devices can be attached to the data bus 24.
  • the system in this embodiment is a specific implementation of the system shown in FIG. 3, and the implementation principle is the same as that of the system shown in FIG. 3, and details are not described herein again.
  • the memory interface module capable of providing a standard memory interface and the hardware control module, the communication interface module, and the image processing module are implemented in the process of storing the data to be written, the CPU only needs to use the data.
  • the mirroring process performs macro control, and the specific communication interaction can be completed by the hardware, thereby reducing the operational burden of the CPU.
  • the image processing module can store data in the physical memory of the local controller. Data can be backed up in the peer controller, which reduces the number of times the data to be written is copied, and reduces the delay of data storage.
  • FIG. 5 is a schematic structural diagram of still another embodiment of a memory mirroring processing system according to the present invention.
  • the system in this embodiment is based on the system shown in FIG. 3. Further, the memory interface module 221 and the central processing unit are shown. 21 connections.
  • the memory mirror processing device 22 can also be directly connected to the interface of the CPU 21.
  • the system in this embodiment is a specific implementation of the system shown in FIG. 3, and the implementation principle thereof is the same as that of the system shown in FIG. 3, and details are not described herein again.
  • the memory interface module capable of providing a standard memory interface and the hardware control module, the communication interface module, and the image processing module are implemented in the process of storing the data to be written, the CPU only needs to use the data.
  • the mirroring process performs macro control, and the specific communication interaction can be completed by the hardware, thereby reducing the operational burden of the CPU.
  • the image processing module can store data in the physical memory of the local controller. Data can be backed up in the peer controller, which reduces the number of times the data to be written is copied, and reduces the delay of data storage.
  • FIG. 6 is a schematic structural diagram of still another embodiment of a memory image processing system according to the present invention. As shown in FIG. 6, the system of this embodiment may be based on the system described in any of the embodiments of FIG. 3, and further, if the control The number of devices is at least three, and the controllers are interconnected by a switch chip.
  • FIG. 6 shows an example in which four controllers 2 are interconnected by a switch chip 26, wherein each of the four controllers 2 can employ the structure of the controller described in any of the embodiments of FIG.
  • the specific implementation principle is the same and will not be described again.
  • the memory interface module capable of providing a standard memory interface and the hardware control module, the communication interface module, and the image processing module are implemented in the process of storing the data to be written, the CPU only needs to use the data.
  • the mirroring process performs macro control, and the specific communication interaction can be completed by the hardware, thereby reducing the operational burden of the CPU.
  • the image processing module can store data in the physical memory of the local controller. Data can be backed up in the peer controller, which reduces the number of times the data to be written is copied, and reduces the delay of data storage.
  • FIG. 7 is a flowchart of an embodiment of a memory mirroring processing method of the present invention.
  • the method of this embodiment may include: Step 601: Receive a write request command to be written by a standard memory interface provided by a memory interface module.
  • the memory interface module can provide a standard memory interface.
  • the bridge device After being encapsulated by the memory interface module, the bridge device considers that the memory image processing device of this embodiment is a standard DDR memory; the memory control module can The device provides an external interface through which the physical memory that is externally cached can be attached to the device of the embodiment.
  • the image processing module mainly handles the control logic of the image.
  • Step 602 If the write request command is an external request for accessing the peer controller, send the data to be backed up in the data to be written to the memory mirror processing device of the peer controller by using the communication interface module, so that The memory mirror processing device of the peer controller performs backup processing on the data that needs to be backed up.
  • the memory interface module of the local controller can receive an access request sent by the CPU or other unit under the control of the CPU, and then the memory interface module can forward the access request to the image processing module, and the image processing module can determine that the access request is
  • the internal request of the local controller is also an external request for accessing the peer controller.
  • the image processing module can send data to the peer controller through the communication interface module.
  • the communication interface module of the device, so that the peer controller performs backup processing on the data, and the memory mirror processing device in the peer controller may be the same as the memory mirror processing device in this embodiment, and the data is backed up.
  • the process is also the same as the above process, and will not be described again.
  • the number of peer controllers is not limited to one, and any number of peer controllers may be provided as needed.
  • the method in this embodiment can implement memory virtualization inside the controller by using hardware, and virtualize the memory of the peer controller into local memory. There is no difference between the virtualized memory and the normal memory for the CPU, and there is no independent. Address space. For data written to the CPU, the memory mirroring device automatically backs up the data through a memory mirroring device in one or more other controllers.
  • the method of the embodiment can be processed by using the device shown in FIG. 1.
  • the memory image processing device can be an FPGA chip or an AS IC chip, and is connected to a data bus inside the computer system, and the FPGA chip or the AS IC chip. Can be connected to the mainstream memory chip.
  • the FPGA chip or the AS IC chip looks like a standard DDR memory.
  • the FPGA chip or the AS IC chip can intercept the DDR signal and parse it, while writing data into the cache of the local controller.
  • the data can also be mirrored to the cache of one or more controllers via the PCIe data channel. Since the FPGA chip or the AS IC chip can operate on the entire storage range of the connected memory chip, it is not necessary to store the data in a fixed space within the memory chip as in the prior art, and then copy the data. Transfer to the actual physical storage space.
  • the memory interface module capable of providing a standard memory interface and the hardware control module, the communication interface module, and the image processing module are implemented in the process of storing the data to be written, the CPU only needs the data.
  • the mirroring process performs macro control, and the specific communication interaction can be completed by these hardwares, thereby reducing the operational burden of the CPU.
  • the image processing module can back up data in the peer controller, thereby reducing the treatment. The number of times data is written for copying reduces the latency of data storage.
  • FIG. 8 is a flowchart of another embodiment of the memory mirroring processing method of the present invention. As shown in FIG. 8, the method of the present embodiment may be further included in the method of the method shown in FIG.
  • the request command is an internal request for accessing the local controller, and the data to be written is sent to the physical memory through the memory control module.
  • the image processing module can send data to the physical memory through the memory control module.
  • the step 601 may include: receiving, by the memory interface module, a to-be-written write sent by a north bridge connected to the data bus and the central processing unit. Into the data.
  • the method in this embodiment is a specific implementation of the method shown in FIG. 7 or 8.
  • the method can be implemented by using the system shown in FIG. 4, and details are not described herein again.
  • the step 601 may include: receiving, by the memory interface module, data to be written sent by the central processing unit. The method in this embodiment is a specific implementation of the method shown in FIG. 7 or 8.
  • the method can be implemented by using the system shown in FIG. 5, and details are not described herein again.
  • the method of the foregoing embodiment of the present invention in the process of storing data to be written, adopts a hardware interface module capable of providing a standard memory interface, and a hardware implementation of a memory control module, a communication interface module, and a mirror processing module, so the CPU only needs
  • the data mirroring process is macroscopically controlled, and the specific communication interaction can be completed by the hardware, thereby reducing the operational burden of the CPU.
  • the image processing module can store data in the physical memory of the local controller. You can also back up data in the peer controller, which reduces the number of times the data to be written is copied, and reduces the delay of data storage.

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Description

内存镜像处理方法、 装置和系统 本申请要求于 2009 年 11 月 27 日提交中国专利局、 申请号为 200910225675.5、 发明名称为"内存镜像处理方法、 装置和系统，，的中国专利 申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域 本发明涉及存储技术领域，尤其涉及一种内存镜像处理方法、装置和系统。
背景技术 为了优化系统性能， 存储控制器将一定容量的内存设置为緩存（Cache) , 在将数据存储在 Cache中后即可向主机反馈完成响应，从而减小主机访问的延 迟。 但是， 内存是易失性存储介质， 在掉电或者存储控制器出现故障时容易丟 失数据， 单个存储控制器无法保证存储数据的可靠性。 为了解决这一问题，现有技术的存储控制器中可以包括两个或者多个控制 器， 这些控制器之间可以采用用于传输镜像数据的镜像链路连接。 当向该存储 控制器中本端控制器的 Cache 中写入数据时， 中央处理单元 （Centra l Proces s ing Uni t , 以下简称： CPU )可以将数据写入本端控制器的 Cache中的 緩存空间，然后再将数据从该緩存储空间拷贝到 Cache中的实际物理地址所对 应的存储空间， 而且 CPU 可以控制本端控制器向与其连接的对端控制器申请 Cache空间， 并将数据拷贝到申请的 Cache空间中， 然后对端控制器再将数据 从该 Cache空间中拷贝到实际物理地址所对应的存储空间进行备份。当本端控 制器掉电或者发生故障时， 其对端控制器的 Cache内还保存有数据，从而可以 防止数据丟失。 在现有技术中， CPU在控制数据镜像的过程中需要处理通信细 节， CPU操作负荷较大； 而且， 数据在写入本端控制器和镜像到对端控制器的 过程中需要进行多次拷贝操作， 从而增大了数据存储的时延。 发明内容
本发明实施例提供一种内存镜像处理方法、装置和系统， 降低了对待写入 数据进行拷贝的次数， 减小了数据存储的时延。
本发明实施例提供一种内存镜像处理装置， 包括：
内存接口模块， 用于通过标准内存接口接收待写入数据， 并向镜像处理模 块发送访问请求；
所述镜像处理模块， 用于接收所述内存接口模块发送的访问请求， 并在所 述访问请求为访问对端控制器的外部请求时，将所述待写入数据中需要备份的 数据发送给通信接口模块；
所述通信接口模块，用于接收所述镜像处理模块发送的所述需要备份的数 据，将所述需要备份的数据发送给对端控制器的内存镜像处理装置， 以使所述 对端控制器的内存镜像处理装置对所述需要备份的数据进行备份处理。
本发明实施例提供一种内存镜像处理系统，包括相互连接的至少两个控制 器，每个控制器包括中央处理单元、 内存镜像处理装置以及作为緩存的物理内 存， 所述内存镜像处理装置包括：
内存接口模块， 用于在所述中央处理单元控制下，通过标准内存接口接收 待写入数据， 并向镜像处理模块发送访问请求；
所述镜像处理模块， 用于接收所述内存接口模块发送的访问请求， 并在所 述访问请求为访问对端控制器的外部请求时，将所述待写入数据中需要备份的 数据发送给通信接口模块；
所述通信接口模块，用于接收所述镜像处理模块发送的所述需要备份的数 据，将所述需要备份的数据发送给对端控制器的内存镜像处理装置， 以使所述 对端控制器的内存镜像处理装置对所述需要备份的数据进行备份处理；
内存控制模块， 与所述镜像处理模块和所述物理内存连接， 用于接收所述 镜像处理模块在所述访问请求为访问本端控制器的内部请求时发送的所述待 写入数据， 并将所述待写入数据写入所述物理内存中。
本发明实施例提供一种内存镜像处理方法， 包括：
通过内存接口模块提供的标准内存接口接收写请求命令中的待写入数据； 若所述写请求命令是访问对端控制器的外部请求，则通过通信接口模块将 所述待写入数据中需要备份的数据发送给对端控制器的内存镜像处理装置，以 使所述对端控制器的内存镜像处理装置对所述需要备份的数据进行备份处理。
本发明实施例， 由于在对待写入数据进行存储的过程中， 采用能够提供标 准内存接口的内存接口模块、通信接口模块和镜像处理模块这些硬件实现， 因 此 CPU仅需要对数据镜像过程进行宏观控制， 而具体的通信交互可以由这些硬 件完成， 从而降低了 CPU的操作负担； 而且， 在数据镜像过程中， 镜像处理模 块可以在本端控制器的物理内存中存储数据， 也可以在对端控制器中备份数 据， 从而降低了对待写入数据进行拷贝的次数， 减小了数据存储的时延。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施 例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地， 下面描 述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不 付出创造性劳动性的前提下， 还可以根据这些附图获得其他的附图。 图 1为本发明内存镜像处理装置一个实施例的结构示意图； 图 2为本发明内存镜像处理装置另一个实施例的结构示意图； 图 3为本发明内存镜像处理系统一个实施例的结构示意图； 图 4为本发明内存镜像处理系统另一个实施例的结构示意图； 图 5为本发明内存镜像处理系统再一个实施例的结构示意图； 图 6为本发明内存镜像处理系统又一个实施例的结构示意图； 图 7为本发明内存镜像处理方法一个实施例的流程图； 图 8为本发明内存镜像处理方法另一个实施例的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清 楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是 全部的实施例。基于本发明中的实施例， 本领域普通技术人员在没有作出创造 性劳动前提下所获得的所有其他实施例， 都属于本发明保护的范围。 图 1为本发明内存镜像处理装置一个实施例的结构示意图， 如图 1所示， 本实施例的装置包括： 内存接口模块 1 1、 通信接口模块 1 3以及镜像处理模块 14 , 其中， 内存接口模块 11用于通过标准内存接口接收待写入数据， 并向镜 像处理模块发送访问请求；镜像处理模块 14用于接收内存接口模块 11发送的 访问请求， 并在所述访问请求为访问对端控制器的外部请求时，将所述待写入 数据中需要备份的数据发送给通信接口模块 1 3； 通信接口模块 1 3用于接收镜 像处理模块 14发送的所述需要备份的数据， 将所述需要备份的数据发送给对 端控制器的内存镜像处理装置，以使所述对端控制器的内存镜像处理装置对所 述需要备份的数据进行备份处理。 具体地， 内存接口模块 11可以提供标准内存接口， 经过内存接口模块 11 的封装后，桥片会认为本实施例的内存镜像处理装置就是一个标准的双倍速率
( Double Date Rate, 以下简称： DDR ) 内存。 镜像处理模块 14主要处理镜像 的控制逻辑， 它接收内存接口模块 11发送而来的访问请求， 然后可以判断该 访问请求是访问本端控制器的内部请求还是访问对端控制器的外部请求，对于 访问请求为访问对端控制器的外部请求来说， 该镜像处理模块 14可以通过通 信接口模块 13将需要待写入数据中需要进行备份的数据发送给对端控制器的 内存镜像处理装置，从而使得对端控制器的内存镜像处理装置可以对需要备份 的数据进行备份处理，对端控制器的内存镜像处理装置可以为与本实施例中的 内存镜像处理装置相同。 需要备份的数据可以是全部待写入数据，也可以是待 写入数据中的一部分。 本实施例的内存镜像处理装置可以利用硬件实现控制器内部的内存虚拟 化， 将对端控制器的内存虚拟为本地的内存， 对 CPU而言， 虚拟化后的内存和 普通的内存没有任何区别， 有独立的地址空间。 对于 CPU向其中写入的数据， 该内存镜像处理装置会自动将数据通过另外一个或多个控制器中的内存镜像 处理装置进行备份。 本实施例的内存镜像处理装置可以为现场可编程门阵列 ( Field Programmable Gate Array , 以下简称： FPGA ) 或专用集成电路 ( App l icat ion Spec if ic Integra ted Ci rcui t s , 以下简称： ASIC )。 本实施例的内存镜像处理装置可以为 FPGA芯片或者 AS IC芯片，并挂接在 计算机系统内部的数据总线上，而且该 FPGA芯片或者 ASIC芯片上可以接主流 的内存芯片。对于桥片来说， 该 FPGA芯片或者 AS IC芯片看起来就是一个标准 的 DDR内存， 该 FPGA芯片或者 ASIC芯片可以截获 DDR信号并解析，在将数据 写入本端控制器的緩存中的同时， 也可以通过 PCIE数据通道将该数据镜像到 另外一个或多个控制器的緩存中。由于该 FPGA芯片或者 ASIC芯片可以对于其 连接的内存芯片的全部存储范围进行操作， 因此， 不用像现有技术那样先将数 据存储到内存芯片上固定范围内的内存空间 ,再将数据拷贝后转存到实际物理 存储空间。 本实施例的装置， 由于在对待写入数据进行存储的过程中， 采用能够提供 标准内存接口的内存接口模块以及通信接口模块和镜像处理模块这些硬件实 现， 因此 CPU仅需要对数据镜像过程进行宏观控制， 而具体的通信交互可以由 这些硬件完成， 从而降低了 CPU的操作负担； 而且， 在数据镜像过程中， 镜像 处理模块可以在对端控制器中备份数据，从而降低了在数据镜像过程中对需要 备份的数据进行拷贝的次数， 减小了数据存储的时延。
图 2为本发明内存镜像处理装置另一个实施例的结构示意图，如图 2所示， 本实施例的装置在图 1所示的装置的基石出上进一步包括： 内存控制模块 12 , 该内存控制模块 12与镜像处理模块 14和作为緩存的物理内存连接，该内存控 制模块 12用于接收镜像处理模块 14在所述访问请求为访问本端控制器的内部 请求时发送的所述待写入数据， 并将所述待写入数据写入所述物理内存中。对 于访问本端控制器的内部请求来说， 该镜像处理模块 14可以通过内存控制模 块 12将数据发送给物理内存， 从而将带写入数据存储在本端控制器中。 进一步地， 该内存接口模块 11可以与数据总线连接， 中央处理单元可以 通过北桥与所述数据总线连接。 因此， 内存接口模块 11可以接收与数据总线 和中央处理单元连接的北桥发送的待写入数据。 或者该内存接口模块 11可以与中央处理单元连接。 因此， 内存接口模块 11还可以直接接收中央处理单元发送的待写入数据。 本实施例的装置， 由于在对待写入数据进行存储的过程中， 采用能够提供 标准内存接口的内存接口模块以及通信接口模块和镜像处理模块这些硬件实 现， 因此 CPU仅需要对数据镜像过程进行宏观控制， 而具体的通信交互可以由 这些硬件完成， 从而降低了 CPU的操作负担； 而且， 在数据镜像过程中， 镜像 处理模块可以通过内存控制模块在本端控制器的物理内存中存储数据，也可以 在对端控制器中备份数据，从而降低了在数据镜像过程中对需要备份的数据进 行拷贝的次数， 减小了数据存储的时延。
图 3为本发明内存镜像处理系统一个实施例的结构示意图， 如图 3所示， 本实施例的系统可以包括： 相互连接的至少两个控制器 2 , 每个控制器包括中 央处理单元 21、 内存镜像处理装置 22以及作为緩存的物理内存 23 , 所述内存 镜像处理装置 22可以包括： 内存接口模块 221、 内存控制模块 222、 通信接口 模块 223以及镜像处理模块 224 , 其中， 内存接口模块 221 , 用于在中央处理 单元 21控制下， 通过标准内存接口接收待写入数据， 并向镜像处理模块 224 发送访问请求；镜像处理模块 224用于接收所述内存接口模块 221发送的访问 请求， 并在所述访问请求为访问对端控制器的外部请求时，将所述待写入数据 中需要备份的数据发送给通信接口模块 223; 通信接口模块 223用于接收镜像 处理模块 224发送的所述需要备份的数据，将所述需要备份的数据发送给对端 控制器的内存镜像处理装置，以使所述对端控制器的内存镜像处理装置对所述 需要备份的数据进行备份处理；内存控制模块 222与镜像处理模块 224和物理 内存 23连接， 内存控制模块 222用于接收镜像处理模块 224在所述访问请求 为访问本端控制器的内部请求时发送的所述待写入数据，并将所述待写入数据 写入所述物理内存 23中。 具体地， 本实施例的内存镜像处理系统可以包括两个控制器 2 , 在每个控 制器中， 均包括： 内存接口模块 221、 内存控制模块 222、 通信接口模块 223 以及镜像处理模块 224。 这两个控制器的通信接口模块 223可以通过数据通道 连接起来， 两个控制器可以互为备份。 在每一个控制器中， 内存接口模块 221 可以提供标准内存接口， 经过内存接口模块 221的封装后，桥片会认为内存镜 像处理装置 22就是一个标准的 DDR内存； 内存控制模块 222可以为该内存镜 像处理装置 22提供外部接口，外部作为緩存的物理内存 23即可通过该内存控 制模块 222挂接在内存镜像处理装置 22上。 镜像处理模块 224主要处理镜像 的控制逻辑。 举例来说， 图 3中左边的控制器 2的内存接口模块 221可以在 CPU 21的 控制下接收 CPU 21或者其它单元发送而来的访问请求，然后内存接口模块 221 可以将该访问请求转发给镜像处理模块 224 , 镜像处理模块 224可以判断该访 问请求是本端控制器，即图 3中左边的控制器 2的内部请求还是访问对端控制 器， 即图 3中有右边的控制器 2的外部请求，对于访问本端控制器的内部请求 来说，该镜像处理模块 224可以通过内存控制模块 222将数据发送给物理内存 23的緩存， 对于访问对端控制器的外部请求来说， 该镜像处理模块 224 可以 通过通信接口模块 223将数据发送给对端控制器中内存镜像处理装置 22的通 信接口模块 223 , 从而使得对端控制器对该数据进行备份处理， 对端控制器中 的内存镜像处理装置可以为与本实施例中的内存镜像处理装置相同 ,其对数据 进行备份处理的过程也与上述过程相同， 不再贅述。 本实施例的内存镜像处理装置 22 可以利用硬件实现控制器内部的内存虚 拟化， 将对端控制器的内存虚拟为本地的内存， 对 CPU 21而言虚拟化后的内 存和普通的内存没有任何区别，有独立的地址空间。对于 CPU向其中写入的数 据，该内存镜像处理装置会自动将数据通过另外一个或多个控制器中的内存镜 像处理装置 22进行备份。 本实施例的内存镜像处理装置 22可以为 FPGA芯片 或者 AS I C芯片， 并挂接在计算机系统内部的数据总线上， 而且该 FPGA芯片或 者 AS IC芯片上可以接主流的内存芯片。对于桥片来说，该 FPGA芯片或者 AS IC 芯片看起来就是一个标准的 DDR内存， 该 FPGA芯片或者 AS IC芯片可以截获 DDR信号并解析，在将数据写入本端控制器的緩存中的同时，也可以通过 PC Ie 数据通道将该数据镜像到另外一个或多个控制器的緩存中。 由于该 FPGA芯片 或者 AS IC芯片可以对于其连接的内存芯片的全部存储范围进行操作， 因此， 不用像现有技术那样先将数据存储到内存芯片上固定范围内的内存空间，再将 数据拷贝后转存到实际物理存储空间。 需要说明的是， 本实施例的系统仅是出了两个控制器彼此备份的情况， 本 领域技术人员可以理解的是， 当多于两个控制器之间彼此需要备份时， 可以采 用交换芯片等技术手段将这些控制器连接起来，从而实现这些控制器之间的互 联。 对于每一个控制器来说， 均可以采用上述描述的结构， 不再贅述。 本实施例的系统， 由于在对待写入数据进行存储的过程中， 采用能够提供 标准内存接口的内存接口模块以及内存控制模块、通信接口模块和镜像处理模 块这些硬件实现， 因此 CPU仅需要对数据镜像过程进行宏观控制， 而具体的通 信交互可以由这些硬件完成， 从而降低了 CPU的操作负担； 而且， 在数据镜像 过程中，镜像处理模块可以在本端控制器的物理内存中存储数据，也可以在对 端控制器中备份数据，从而降低了对待写入数据进行拷贝的次数， 减小了数据 存储的时延。
图 4为本发明内存镜像处理系统另一个实施例的结构示意图，如图 4所示， 本实施例的系统以图 3所示的系统为基石出， 进一步地， 内存接口模块 221与数 据总线 24连接， 中央处理单元 21通过北桥 25与数据总线 24连接。 另外， 在 该数据总线 24上还可以挂接更多的 10设备。 本实施例的系统为图 3所示的系统的一种具体实现方式，其实现原理与图 3所示的系统的实现原理相同， 不再贅述。 本实施例的系统， 由于在对待写入数据进行存储的过程中， 采用能够提供 标准内存接口的内存接口模块以及内存控制模块、通信接口模块和镜像处理模 块这些硬件实现， 因此 CPU仅需要对数据镜像过程进行宏观控制， 而具体的通 信交互可以由这些硬件完成， 从而降低了 CPU的操作负担； 而且， 在数据镜像 过程中，镜像处理模块可以在本端控制器的物理内存中存储数据，也可以在对 端控制器中备份数据，从而降低了对待写入数据进行拷贝的次数， 减小了数据 存储的时延。
图 5为本发明内存镜像处理系统再一个实施例的结构示意图，如图 5所示， 本实施例的系统以图 3所示的系统为基石出， 进一步地， 内存接口模块 221与中 央处理单元 21连接。 本实施例的系统中， 内存镜像处理装置 22也可以直接与 CPU 21的接口连 接。本实施例的系统为图 3所示的系统的一种具体实现方式， 其实现原理与图 3所示的系统的实现原理相同， 不再贅述。 本实施例的系统， 由于在对待写入数据进行存储的过程中， 采用能够提供 标准内存接口的内存接口模块以及内存控制模块、通信接口模块和镜像处理模 块这些硬件实现， 因此 CPU仅需要对数据镜像过程进行宏观控制， 而具体的通 信交互可以由这些硬件完成， 从而降低了 CPU的操作负担； 而且， 在数据镜像 过程中，镜像处理模块可以在本端控制器的物理内存中存储数据，也可以在对 端控制器中备份数据，从而降低了对待写入数据进行拷贝的次数， 减小了数据 存储的时延。
图 6为本发明内存镜像处理系统又一个实施例的结构示意图，如图 6所示， 本实施例的系统可以基于图 3飞中任一实施例所述的系统， 进一步地， 若所述 控制器的数量为至少三个， 则所述控制器通过交换芯片互联。
图 6示出了将四个控制器 2通过交换芯片 26互联的例子， 其中四个控制 器 2中每一个控制器均可以采用图 3飞中任一实施例所述的控制器的结构。其 具体实现原理相同， 不再贅述。 本实施例的系统， 由于在对待写入数据进行存储的过程中， 采用能够提供 标准内存接口的内存接口模块以及内存控制模块、通信接口模块和镜像处理模 块这些硬件实现， 因此 CPU仅需要对数据镜像过程进行宏观控制， 而具体的通 信交互可以由这些硬件完成， 从而降低了 CPU的操作负担； 而且， 在数据镜像 过程中，镜像处理模块可以在本端控制器的物理内存中存储数据，也可以在对 端控制器中备份数据，从而降低了对待写入数据进行拷贝的次数， 减小了数据 存储的时延。
图 7为本发明内存镜像处理方法一个实施例的流程图，如图 7所示， 本实 施例的方法可以包括： 步骤 601、 通过内存接口模块提供的标准内存接口接收写请求命令中的待 写入数据； 本实施例中， 内存接口模块可以提供标准内存接口， 经过内存接口模块的 封装后， 桥片会认为本实施例的内存镜像处理装置就是一个标准的 DDR内存； 内存控制模块可以为该装置提供外部接口，外部作为緩存的物理内存即可通过 该内存控制模块挂接在本实施例的装置上。镜像处理模块主要处理镜像的控制 逻辑。
步骤 602、 若所述写请求命令是访问对端控制器的外部请求， 则通过通信 接口模块将所述待写入数据中需要备份的数据发送给对端控制器的内存镜像 处理装置，以使所述对端控制器的内存镜像处理装置对所述需要备份的数据进 行备份处理。
本端控制器的内存接口模块可以在 CPU的控制下接收 CPU或者其它单元发 送而来的访问请求， 然后内存接口模块可以将该访问请求转发给镜像处理模 块，镜像处理模块可以判断该访问请求是本端控制器的内部请求还是访问对端 控制器的外部请求，对于访问对端控制器的外部请求来说， 该镜像处理模块可 以通过通信接口模块将数据发送给对端控制器中内存镜像处理装置的通信接 口模块，从而使得对端控制器对该数据进行备份处理，对端控制器中的内存镜 像处理装置可以为与本实施例中的内存镜像处理装置相同，其对数据进行备份 处理的过程也与上述过程相同， 不再贅述。 需要说明的是， 对端控制器的数量 不限于一个， 根据需要可以有任意数量的对端控制器。 本实施例的方法可以利用硬件实现控制器内部的内存虚拟化，将对端控制 器的内存虚拟为本地的内存，对 CPU而言虚拟化后的内存和普通的内存没有任 何区别， 有独立的地址空间。 对于 CPU向其中写入的数据， 该内存镜像处理装 置会自动将数据通过另外一个或多个控制器中的内存镜像处理装置进行备份。
本实施例的方法可以采用图 1所示的装置处理，该内存镜像处理装置可以 为 FPGA芯片或者 AS IC芯片， 并挂接在计算机系统内部的数据总线上， 而且该 FPGA芯片或者 AS IC芯片上可以接主流的内存芯片。 对于桥片来说， 该 FPGA 芯片或者 AS IC芯片看起来就是一个标准的 DDR内存， 该 FPGA芯片或者 AS IC 芯片可以截获 DDR信号并解析，在将数据写入本端控制器的緩存中的同时， 也 可以通过 PCIe数据通道将该数据镜像到另外一个或多个控制器的緩存中。 由 于该 FPGA芯片或者 AS IC芯片可以对于其连接的内存芯片的全部存储范围进行 操作， 因此， 不用像现有技术那样先将数据存储到内存芯片上固定范围内的内 存空间， 再将数据拷贝后转存到实际物理存储空间。
本实施例的方法， 由于在对待写入数据进行存储的过程中， 采用能够提供 标准内存接口的内存接口模块以及内存控制模块、通信接口模块和镜像处理模 块这些硬件实现， 因此 CPU仅需要对数据镜像过程进行宏观控制， 而具体的通 信交互可以由这些硬件完成， 从而降低了 CPU的操作负担； 而且， 在数据镜像 过程中，镜像处理模块可以在对端控制器中备份数据，从而降低了对待写入数 据进行拷贝的次数， 减小了数据存储的时延。
图 8为本发明内存镜像处理方法另一个实施例的流程图，如图 8所示， 本 实施例的方法在图 7所示方法的基石出上， 进一步可以包括： 步骤 603、 若所述写请求命令是访问本端控制器的内部请求， 则通过内存 控制模块将所述待写入数据发送给物理内存。
对于访问本端控制器的内部请求来说，镜像处理模块可以通过内存控制模 块将数据发送给物理内存。
需要说明的是， 本实施例的步骤 602和步骤 603之间可以没有先后顺序。 在本发明内存镜像处理方法另一个实施例中， 上述步骤 601可以包括： 通 过所述内存接口模块接收与数据总线和中央处理单元连接的北桥发送的待写 入数据。 本实施例的方法是图 7或 8所示的方法的一个具体实现，该方法可以通过 图 4所示的系统实现， 不再贅述。 在本发明内存镜像处理方法再一个实施例中， 上述步骤 601可以包括： 通 过所述内存接口模块接收中央处理单元发送的待写入数据。 本实施例的方法是图 7或 8所示的方法的一个具体实现，该方法可以通过 图 5所示的系统实现， 不再贅述。 本发明上述实施例的方法， 由于在对待写入数据进行存储的过程中， 采用 能够提供标准内存接口的内存接口模块以及内存控制模块、通信接口模块和镜 像处理模块这些硬件实现， 因此 CPU仅需要对数据镜像过程进行宏观控制， 而 具体的通信交互可以由这些硬件完成， 从而降低了 CPU的操作负担； 而且， 在 数据镜像过程中，镜像处理模块可以在本端控制器的物理内存中存储数据， 也 可以在对端控制器中备份数据，从而降低了对待写入数据进行拷贝的次数， 减 小了数据存储的时延。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到本发明 可借助软件加必需的硬件平台的方式来实现， 当然也可以全部通过硬件来实 施， 但很多情况下前者是更佳的实施方式。基于这样的理解， 本发明的技术方 案对背景技术做出贡献的全部或者部分可以以软件产品的形式体现出来，该计 算机软件产品可以存储在存储介质中， 如 R0M/RAM、 磁碟、 光盘等， 包括若干 指令用以使得一台计算机设备（可以是个人计算机，服务器，或者网络设备等） 执行本发明各个实施例或者实施例的某些部分所述的方法。 最后应说明的是：以上实施例仅用以说明本发明的技术方案而非对其进行 限制，尽管参照较佳实施例对本发明进行了详细的说明， 本领域的普通技术人 员应当理解： 其依然可以对本发明的技术方案进行修改或者等同替换， 而这些 修改或者等同替换亦不能使修改后的技术方案脱离本发明技术方案的精神和 范围。

Claims

权 利 要 求
1、 一种内存镜像处理装置， 其特征在于， 包括：
内存接口模块， 用于通过标准内存接口接收待写入数据， 并向镜像处理模 块发送访问请求；
所述镜像处理模块， 用于接收所述内存接口模块发送的访问请求， 并在所 述访问请求为访问对端控制器的外部请求时，将所述待写入数据中需要备份的 数据发送给通信接口模块；
所述通信接口模块，用于接收所述镜像处理模块发送的所述需要备份的数 据，将所述需要备份的数据发送给对端控制器的内存镜像处理装置， 以使所述 对端控制器的内存镜像处理装置对所述需要备份的数据进行备份处理。
2、 根据权利要求 1所述的内存镜像处理装置， 其特征在于， 还包括： 内存控制模块， 与所述镜像处理模块和作为緩存的物理内存连接； 所述镜像处理模块，还用于在所述访问请求为访问本端控制器的内部请求 时， 将所述待写入数据发送给所述内存控制模块；
所述内存控制模块，用于接收所述镜像处理模块在所述访问请求为访问本 端控制器的内部请求时发送的待写入数据，并将所述待写入数据写入所述物理 内存中。
3、 根据权利要求 1或 2所述的内存镜像处理装置， 其特征在于， 所述内存 接口模块与数据总线连接。
4、 根据权利要求 1或 2所述的内存镜像处理装置， 其特征在于， 所述内存 接口模块与中央处理单元连接。
5、 一种内存镜像处理系统， 其特征在于， 包括相互连接的至少两个控制 器， 所述控制器包括中央处理单元、 内存镜像处理装置以及作为緩存的物理内 存， 所述内存镜像处理装置包括：
内存接口模块， 用于在所述中央处理单元控制下，通过标准内存接口接收 待写入数据， 并向镜像处理模块发送访问请求；
所述镜像处理模块， 用于接收所述内存接口模块发送的访问请求， 并在所 述访问请求为访问对端控制器的外部请求时，将所述待写入数据中需要备份的 数据发送给通信接口模块；
所述通信接口模块，用于接收所述镜像处理模块发送的所述需要备份的数 据，将所述需要备份的数据发送给对端控制器的内存镜像处理装置， 以使所述 对端控制器的内存镜像处理装置对所述需要备份的数据进行备份处理；
内存控制模块， 与所述镜像处理模块和所述物理内存连接， 用于接收所述 镜像处理模块在所述访问请求为访问本端控制器的内部请求时发送的所述待 写入数据， 并将所述待写入数据写入所述物理内存中。
6、根据权利要求 5所述的内存镜像处理系统， 其特征在于， 若所述控制器 的数量为至少三个， 则所述控制器通过交换芯片互联。
7、 一种内存镜像处理方法， 其特征在于， 包括：
通过内存接口模块提供的标准内存接口接收写请求命令中的待写入数据； 若所述写请求命令是访问对端控制器的外部请求 ,则通过通信接口模块将 所述待写入数据中需要备份的数据发送给对端控制器的内存镜像处理装置，以 使所述对端控制器的内存镜像处理装置对所述需要备份的数据进行备份处理。
8、 根据权利要求 7所述的内存镜像处理方法， 其特征在于， 还包括： 若所述写请求命令是访问本端控制器的内部请求，则通过内存控制模块将 所述待写入数据发送给物理内存。
9、 根据权利要求 7或 8所述的内存镜像处理方法， 其特征在于， 所述通过 内存接口模块提供的标准内存接口接收写请求命令中的待写入数据， 包括： 通过所述内存接口模块接收与数据总线和中央处理单元连接的北桥发送 的待写入数据。
10、 根据权利要求 7或 8所述的内存镜像处理方法， 其特征在于， 所述通过 内存接口模块提供的标准内存接口接收写请求命令中的待写入数据， 包括： 通过所述内存接口模块接收中央处理单元发送的待写入数据。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015036892A1 (en) 2013-09-12 2015-03-19 Pfizer Inc. Use of acetyl-coa carboxylase inhibitors for treating acne vulgaris

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102945288B (zh) * 2012-11-29 2016-01-20 重庆邮电大学 一种物理内存镜像中文本数据文件提取方法
CN103152394B (zh) 2013-02-06 2016-09-28 华为技术有限公司 数据存取系统、内存共享设备及数据读取方法
CN103645996B (zh) * 2013-12-09 2016-07-06 龙芯中科技术有限公司 内存拷贝的方法、装置和片上系统
CN104102881B (zh) * 2014-07-07 2017-01-04 杭州电子科技大学 一种基于内核对象链接关系的内存取证方法
CN104778098A (zh) * 2015-04-09 2015-07-15 浪潮电子信息产业股份有限公司 一种内存镜像的方法及系统、一种内存监控器
CN105843711A (zh) * 2016-06-21 2016-08-10 北京飞杰信息技术有限公司 数据防掉电保护方法及系统
CN106302243B (zh) * 2016-09-23 2019-11-12 新华三技术有限公司 一种报文传输方法、cpu以及网络设备
CN108664362B (zh) * 2017-03-31 2021-06-15 龙芯中科技术股份有限公司 内存镜像的处理方法、内存控制器及用户设备
CN107579936A (zh) * 2017-09-11 2018-01-12 北京腾凌科技有限公司 报文传输方法、控制器及存储系统
CN109343986B (zh) * 2018-08-17 2020-12-22 华为技术有限公司 处理内存故障的方法与计算机系统
CN109254879A (zh) * 2018-09-27 2019-01-22 南方电网科学研究院有限责任公司 一种数据处理方法、系统、装置及可读存储介质
CN109639505B (zh) * 2019-01-07 2021-08-27 南京南瑞继保电气有限公司 一种变电站过程层网络设备及其镜像功能实现方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060106982A1 (en) * 2001-09-28 2006-05-18 Dot Hill Systems Corporation Certified memory-to-memory data transfer between active-active raid controllers
CN101169750A (zh) * 2007-12-10 2008-04-30 杭州华三通信技术有限公司 内存镜像系统、装置和内存镜像方法
US20090031097A1 (en) * 2007-07-29 2009-01-29 Lee Nelson Creating Backups in Storage Systems
CN101458655A (zh) * 2007-12-12 2009-06-17 华为技术有限公司 内存管理方法、系统及内存控制装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060106982A1 (en) * 2001-09-28 2006-05-18 Dot Hill Systems Corporation Certified memory-to-memory data transfer between active-active raid controllers
US20090031097A1 (en) * 2007-07-29 2009-01-29 Lee Nelson Creating Backups in Storage Systems
CN101169750A (zh) * 2007-12-10 2008-04-30 杭州华三通信技术有限公司 内存镜像系统、装置和内存镜像方法
CN101458655A (zh) * 2007-12-12 2009-06-17 华为技术有限公司 内存管理方法、系统及内存控制装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015036892A1 (en) 2013-09-12 2015-03-19 Pfizer Inc. Use of acetyl-coa carboxylase inhibitors for treating acne vulgaris

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