WO2011041140A3 - Procédé de remplissage d'une tranchée profonde dans un substrat - Google Patents
Procédé de remplissage d'une tranchée profonde dans un substrat Download PDFInfo
- Publication number
- WO2011041140A3 WO2011041140A3 PCT/US2010/049354 US2010049354W WO2011041140A3 WO 2011041140 A3 WO2011041140 A3 WO 2011041140A3 US 2010049354 W US2010049354 W US 2010049354W WO 2011041140 A3 WO2011041140 A3 WO 2011041140A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- deep trench
- substrate
- dielectric layer
- filling deep
- filling
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 6
- 239000000758 substrate Substances 0.000 title abstract 4
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
L'invention porte sur des procédés de remplissage de tranchées profondes dans des substrats. Un procédé consiste à se procurer un substrat dans lequel est formée une tranchée profonde. Le procédé comprend également la formation d'une couche diélectrique s'adaptant au substrat et à la tranchée profonde. Le procédé comprend également, avec la partie totale de la couche diélectrique s'adaptant à la tranchée profonde exposée, l'élimination d'au moins une partie, mais non de la totalité, de la couche diélectrique à la partie supérieure de la tranchée profonde avec un procédé d'attaque chimique par plasma à relativement faible polarisation.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US24744709P | 2009-09-30 | 2009-09-30 | |
US61/247,447 | 2009-09-30 | ||
US12/879,924 US20110217832A1 (en) | 2009-09-30 | 2010-09-10 | Method of filling a deep trench in a substrate |
US12/879,924 | 2010-09-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2011041140A2 WO2011041140A2 (fr) | 2011-04-07 |
WO2011041140A3 true WO2011041140A3 (fr) | 2011-06-16 |
Family
ID=43826841
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2010/049354 WO2011041140A2 (fr) | 2009-09-30 | 2010-09-17 | Procédé de remplissage d'une tranchée profonde dans un substrat |
Country Status (2)
Country | Link |
---|---|
US (1) | US20110217832A1 (fr) |
WO (1) | WO2011041140A2 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8564103B2 (en) * | 2009-06-04 | 2013-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing an electronic device |
US8637365B2 (en) | 2012-06-06 | 2014-01-28 | International Business Machines Corporation | Spacer isolation in deep trench |
CN105990310B (zh) * | 2015-01-30 | 2019-04-19 | 联华电子股份有限公司 | 半导体结构及其制造方法 |
US20180323061A1 (en) * | 2017-05-03 | 2018-11-08 | Tokyo Electron Limited | Self-Aligned Triple Patterning Process Utilizing Organic Spacers |
US10740536B2 (en) * | 2018-08-06 | 2020-08-11 | International Business Machines Corporation | Dynamic survey generation and verification |
CN116235283A (zh) | 2020-08-18 | 2023-06-06 | 应用材料公司 | 沉积预蚀刻保护层的方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020009265A (ko) * | 2000-07-25 | 2002-02-01 | 박종섭 | 반도체장치의 플러그 형성방법 |
US20020058409A1 (en) * | 2000-11-16 | 2002-05-16 | Ching-Te Lin | Elimination of overhang in liner/barrier/seed layers using post-deposition sputter etch |
KR100465601B1 (ko) * | 2002-07-18 | 2005-01-13 | 주식회사 하이닉스반도체 | 반도체소자의 형성방법 |
US20060024966A1 (en) * | 2004-07-16 | 2006-02-02 | Sanyo Electric Co., Ltd | Manufacturing method of semiconductor device |
US20070161203A1 (en) * | 2005-12-05 | 2007-07-12 | Semiconductor Manufacturing International (Shanghai) Corporation | Method with high gapfill capability and resulting device structure |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6527968B1 (en) * | 2000-03-27 | 2003-03-04 | Applied Materials Inc. | Two-stage self-cleaning silicon etch process |
US6451705B1 (en) * | 2000-08-31 | 2002-09-17 | Micron Technology, Inc. | Self-aligned PECVD etch mask |
US6624066B2 (en) * | 2001-02-14 | 2003-09-23 | Texas Instruments Incorporated | Reliable interconnects with low via/contact resistance |
US6884736B2 (en) * | 2002-10-07 | 2005-04-26 | Taiwan Semiconductor Manufacturing Co, Ltd. | Method of forming contact plug on silicide structure |
KR20050114784A (ko) * | 2004-06-01 | 2005-12-07 | 동부아남반도체 주식회사 | 반도체 소자의 구리배선 형성방법 |
-
2010
- 2010-09-10 US US12/879,924 patent/US20110217832A1/en not_active Abandoned
- 2010-09-17 WO PCT/US2010/049354 patent/WO2011041140A2/fr active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020009265A (ko) * | 2000-07-25 | 2002-02-01 | 박종섭 | 반도체장치의 플러그 형성방법 |
US20020058409A1 (en) * | 2000-11-16 | 2002-05-16 | Ching-Te Lin | Elimination of overhang in liner/barrier/seed layers using post-deposition sputter etch |
KR100465601B1 (ko) * | 2002-07-18 | 2005-01-13 | 주식회사 하이닉스반도체 | 반도체소자의 형성방법 |
US20060024966A1 (en) * | 2004-07-16 | 2006-02-02 | Sanyo Electric Co., Ltd | Manufacturing method of semiconductor device |
US20070161203A1 (en) * | 2005-12-05 | 2007-07-12 | Semiconductor Manufacturing International (Shanghai) Corporation | Method with high gapfill capability and resulting device structure |
Also Published As
Publication number | Publication date |
---|---|
WO2011041140A2 (fr) | 2011-04-07 |
US20110217832A1 (en) | 2011-09-08 |
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