WO2011037758A1 - Caractérisation et réparation de circuits intégrés - Google Patents

Caractérisation et réparation de circuits intégrés Download PDF

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Publication number
WO2011037758A1
WO2011037758A1 PCT/US2010/048297 US2010048297W WO2011037758A1 WO 2011037758 A1 WO2011037758 A1 WO 2011037758A1 US 2010048297 W US2010048297 W US 2010048297W WO 2011037758 A1 WO2011037758 A1 WO 2011037758A1
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redundant
memory
elements
placement
row
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PCT/US2010/048297
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English (en)
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Erik H. Volkerink
Joseph Milbourn
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Verigy (Singapore) Pte. Ltd.
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Priority to TW099132574A priority Critical patent/TW201133262A/zh
Publication of WO2011037758A1 publication Critical patent/WO2011037758A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme

Definitions

  • DRAMs dynamic random access memories
  • a modern high-capacity DRAM may contain hundreds of millions of memory cells within a silicon chip having a surface area of less than one square inch.
  • Each memory cell consists of one or more components such as transistors and capacitors. If only one of these millions of components does not work, the entire DRAM may be unusable. In practice as many as 95% of newly-manufactured DRAMs fail their initial tests.
  • spare redundant memory cells may be included in the DRAM chip during manufacture. These redundant cells may then be substituted for defective cells during initial testing of the DRAM.
  • the cells in a DRAM are arranged in matrices of rows and columns.
  • One such matrix defines one memory bank.
  • a memory bank may consist of 65,536 memory cells arranged in a matrix of 256 rows by 256 columns.
  • a typical DRAM may contain hundreds of such memory banks, and the banks may be larger than 256 x 256 memory cells.
  • a memory block (also referred to as a memory element) is a rectangular set of memory cells that may encompass an entire memory bank or a subset of a memory bank.
  • redundant cells are provided in the form of redundant rows and columns. Redundant rows and redundant columns are collectively referred to herein as "redundant elements”. For example, if a memory cell in row 25 of memory bank A is defective, a redundant row may be substituted for row 25.
  • Column 6 may contain the 6th memory cell in each of the rows in memory bank A. If the defective memory cell in row 25 is the sixth one, then that cell also lies in column 6, and the defect may be corrected either by substituting a redundant row for row 25 or a redundant column for column 6.
  • the problem of devising a plan for substituting redundant elements consistent with all applicable constraints so as to eliminate all the defective memory cells in a DRAM chip with minimal impact on performance of the chip may be referred to as the "spare allocation problem" (SAP).
  • SAP pare allocation problem
  • Finding a solution to the SAP can be difficult and time- consuming.
  • each DRAM presents a different set of defective memory cells and therefore a different solution must be devised for each DRAM individually.
  • the equipment necessary to test and repair DRAM devices is costly whereas the value of each individual DRAM is very low. Efficient manufacture of production quantities of DRAMs requires that the time required to repair any one DRAM be minimized.
  • NP means "nondeterministic polynomial time”.
  • any set of NP Complete problems has the properties that (a) once a solution has been found to any problem in the set, that solution can be quickly verified in polynomial time, and (b) if any problem in the set can be solved quickly, then so can every other problem in the set.
  • the SAP is an NP Complete problem, as shown by Sy-Yen Kuo et al., "Efficient spare allocation in reconfigurable arrays," DAC '86: Proceedings of the 23rd ACM/IEEE conference on Design automation, pages 385-390, IEEE Press, Piscataway NJ, 1986.
  • a branch-and-bound technique with a cost function dependent on the type of element to arrive at an algorithm for solving the SAP is presented by Kuo et al.
  • the algorithm developed by this technique is a "perfect" algorithm in that it will always lead to an optimum solution to the SAP.
  • An algorithm for solving the SAP represents the SAP as a set of Boolean functions manipulated using a binary decision diagram.
  • Hung-Yau Lin et al "An efficient algorithm for reconfiguring shared spare RRAM," in ICCD '04: Proceedings of the IEEE International Conference on Computer Design, pages 544-546, Washington DC, 2004, IEEE Computer Society.
  • the algorithm developed in this approach is a perfect algorithm; that is, it will always result in an optimum solution to the SAP.
  • a redundancy analysis algorithm must be designed and customized for each type of DRAM individually. Such a manual process of devising repair algorithms is error-prone and time consuming.
  • the SAP must be solved in the critical path of manufacture, and because of the high cost of the equipment that tests and repairs the chips, it is necessary to minimize the time required to analyze and repair any one chip.
  • Many redundancy analysis algorithms provide for trade-offs between the time taken for analysis and the success rate of the analysis. If the algorithm takes less time per chip to solve the SAP, it is likely to achieve a lower percentage yield than an algorithm taking more time, but if it operates quickly enough it may achieve a higher output of usable chips in a given amount of time.
  • the must-repair algorithm has the property that the placement of a redundant element at a specific address in a memory is a "must repair” if the failed cells so repaired cannot be repaired by any combination of placements of any other redundant elements.
  • the must-repair algorithm is applied recursively until there are no redundant elements available to cover remaining faults, or no must-repairs remain, or no failures remain.
  • the algorithm is applied recursively because must-repair conditions change as redundant elements are used to repair faults.
  • a method of characterizing an integrated circuit from data representing physical aspects of the integrated circuit is provided.
  • Each of a plurality of memory blocks in the integrated circuit may be depicted in a graphical format and in a computer-readable text format.
  • the depiction of a memory block indicates rows and columns of memory cells in that memory block.
  • Each of a plurality of redundant elements is depicted in the graphical and computer-readable text formats.
  • the depiction of a redundant element indicates at least one of a row and a column of memory cells in that redundant element.
  • Depictions of the redundant elements are distinct from depictions of the memory blocks. Each of a plurality of possible placements of various ones of the redundant elements is described using the depictions of various ones of the memory blocks and redundant elements. Each redundant element has at least one such possible placement. Each such description may be expressed in prescribed notations in the graphical and computer-readable text formats. Each of a plurality of constraints on placements of the redundant elements may be described using the depictions of various ones of the memory blocks and redundant elements. Each constraint on any given redundant element may be defined by a possible placement of another one of the redundant elements. Each such description may be expressed in prescribed notations in the graphical and computer-readable text formats. Depictions of the memory blocks and the redundant elements, and descriptions of the possible placements and the constraints, may be combined into an overall graphical description and an overall computer- readable textual description of the integrated circuit.
  • a method of generating a repair algorithm for an integrated circuit containing defective components is provided.
  • a list of defects in the integrated circuit and a mathematical model of the integrated circuit are used to identify problems in the integrated circuit.
  • Building block code is generated according to the identified problems.
  • a first potential repair algorithm is generated from the building block code.
  • a simulation of the potential repair algorithm is run. Performance of the potential repair algorithm is measured.
  • a variation of the potential repair algorithm is generated and its performance is simulated and measured. If performances of the potential algorithm and its variation do not converge, more variations are iteratively generated and simulated until there is convergence on an optimal first algorithm.
  • a second potential algorithm is generated and the process is repeated to obtain an optimal second algorithm. If the first and second optimal algorithms do not converge on an optimal overall repair algorithm, the process is repeated until there is convergence on an overall optimal repair algorithm.
  • a method of repairing an integrated circuit is provided.
  • the integrated circuit is tested with an electronic memory tester to identify any defective memory elements.
  • the defective elements are described using a memory description language ("MDL").
  • a model of the integrated circuit is modified according to the described defective memory elements.
  • a plan is prepared for substituting redundant memory elements for defective memory elements. The plan is consistent with any placement and constraint exceptions affecting the redundant memory elements.
  • the plan is tested to determine whether redundant memory blocks have been identified for all defective memory elements. If the plan does not provide a redundant memory block for each defective memory element, the plan is revised and tested again. When redundant memory blocks have been identified for all defective memory elements, the plan is implemented by applying signals to the memory to effect substitution of the redundant elements for the defective elements according to the plan.
  • a system for repairing an integrated circuit containing redundant memory elements includes an electronic memory tester, an electronic processor in communication with the tester, a database in communication with the processor, and instructions stored in the database.
  • the instructions cause the system to test the integrated circuit, generate a description of any defective memory elements using a memory description language (MDL), prepare a plan for substituting redundant memory elements for defective memory elements consistent with any placement exceptions and constraints affecting the redundant memory elements, simulate the plan, and revise the plan until the simulation shows an optimal result has been achieved or no further revisions are possible.
  • MDL memory description language
  • Figure 1 is a graphic representation of an 8x8 memory block with a redundant column
  • Figure 2A is a graphic depiction of a possible placement of a redundant row into a memory block
  • Figure 2B is a graphic depiction of a possible placement of a redundant row into any row in the first half of a memory block
  • Figure 2C is a graphic depiction of a possible placement of a redundant row into any even-numbered row in a memory block
  • Figure 2D is a graphic depiction of an actual placement of a redundant row into a specified row in a memory block
  • Figure 3A is a graphic depiction of a possible placement of two redundant rows with a constraint that their ⁇ -coordinates be equal;
  • Figure 3B is a graphic depiction of a possible placement of two redundant rows with a constraint that both must be placed in the same memory block;
  • Figure 3C is a graphic depiction of a possible placement of two redundant rows with a constraint that both must be placed in the same half of a memory block;
  • Figure 4A is a graphic depiction of orthogonal redundant elements
  • Figure 4B is a graphic depiction of compatible redundant elements
  • Figure 5 is a graphic depiction of intersections of the coverages of three redundant elements
  • Figure 6 A is a layout diagram of a device
  • Figure 6B is a simplified version of Figure 6 A using abstract model elements
  • Figure 7 A is a layout diagram of a memory block with four redundant rows
  • Figure 7B shows placement of the redundant rows of Figure 7A anywhere in the memory block
  • Figure 7C is a simplified version of the placement shown in Figure 7B;
  • Figure 7D is similar to Figure 7C but shows a constraint on the placement of a redundant row;
  • Figure 8 A is a layout diagram of part of a DRAM;
  • Figure 8B shows placement of the redundant rows of Figure 8A in the memory block and with a constraint
  • Figure 8C represents shared fuses between pairs of rows
  • Figure 9 shows a tool for graphical modeling of DRAM devices according to novel principles disclosed herein;
  • Figure 10A shows a memory block with a redundant row and a redundant column
  • Figure 10B is a graphical model of possible placements of the redundant elements of Figure 10A;
  • Figure 11 is a graphical representation of a tree showing possible placements of the redundant elements of Figure 10A;
  • Figure 12A is a graphical representation of a tree similar to that shown in Figure 11 but reduced by a constraint
  • Figure 12B is a graphical model corresponding with the tree of Figure 12A;
  • Figure 13 A is a graphical representation of a tree similar to that shown in Figure 12A but reduced by another constraint
  • Figure 13B is a graphical model corresponding with the tree of Figure 13 A;
  • Figure 14A is a graphical representation of a tree similar to that shown in Figure 13 A but reduced by another constraint
  • Figure 14B is a graphical model corresponding with the tree of Figure 14 A;
  • Figure 15 shows a memory block with repair regions
  • Figure 16A shows two independent memory banks
  • Figure 16B is a graphical model of the memory banks of Figure 16A;
  • Figure 17A shows two adjacent memory banks
  • Figure 17B is a graphical model of the memory banks of Figure 17A;
  • Figure 17C shows the same memory banks as Figure 17A but each with a separate origin
  • Figure 18 shows a memory block with three regions
  • Figure 19 is a block diagram of a region code generator
  • Figure 20 is a flow chart of a procedure for generating a repair algorithm for a
  • Figure 21 shows the code generation library of Figure 20; and [0073]
  • Figure 22 is a block diagram of a testing apparatus in which methods disclosed herein may be practiced.
  • a mathematical model of a complex system such as a large DRAM having many redundant rows and columns is useful in solving the SAP.
  • users can exchange representations of the system, each confident that the other has an identical representation even if the tools used to create the model were different. Indeed, the very creation of tools to manipulate a representation of a complex system may not be feasible without a suitable model of the system.
  • the most common model of a DRAM represents the device as a set of sketches made up of labeled rectangles. Possible uses of redundant elements are typically denoted by local conventions and labeling. This model has no formal basis and therefore is of limited use in developing a solution for the SAP.
  • One such model expresses constraints on redundant elements and defects using Boolean algebra. By this technique a problem may be expressed as an instance of a Boolean satisfiability problem.
  • a model to be used for redundancy analysis need only represent those aspects of a DRAM that are relevant to such analysis. There is no need for such a model to represent the type of package containing the silicon die, the power supply, or other aspects of the DRAM that do not relate to the problem at hand.
  • Such a model might include an incoming memory address bus, combinational logic, a fuse box containing fuses for effecting repairs, and an array of memory cells some of which are redundant and can be used for repair.
  • one bit of storage is referred to as a memory cell.
  • Memory cells are grouped according to their use. A contiguous array of rows and columns of memory cells that cannot be used for repair is referred to as a memory block. A row or column of such cells is referred to as a memory element. Cells that can be used for repair are grouped into
  • each such set which may be a redundant row or a redundant column, is referred to as a redundant element.
  • the fuse box and combinational logic place limits on the use of redundant elements. These limits are referred to as exceptions. There are two kinds of exceptions: those which are independent of all other uses of redundant elements and those which are not.
  • a typical independent exception might be a requirement that a certain redundant element can only be placed in an odd row in a particular memory block.
  • An exception that is not independent might be a requirement that if a first redundant element has been placed in a certain range of addresses, then a second redundant element must also be placed in that range.
  • an "independent" exception can only relate a redundant element to a memory block, whereas a “dependent” exception can only relate one redundant element to another redundant element.
  • An independent exception is described as a "Placement” and a dependent one is described as a "Constraint".
  • Ml POSITION (0, 0). [0083] This memory block would extend from (0, 0) to (7, 7).
  • Rl A redundant element designated as Rl and having one column of 8 cells placed to the right of Ml would be represented as
  • R1 PLACEMENT (M1, 2, 0).
  • placement information In a model such as this, neither the size nor the location of the memory blocks is important. What is needed is placement information.
  • a graphical representation of this placement information makes for a simple, intuitive graphical model in which memory blocks and redundant elements are represented by nodes. Each node is labeled with the name of the device it represents. Placement of a redundant element in a memory block is represented by an edge between their respective nodes. An arrow on the edge denotes the direction of placement.
  • a "placement” shows the use of a redundant element to repair a memory block; a “possible placement” shows the capacity of a redundant element to repair a memory block. If for example a redundant row Rl could be substituted for any row in a memory block Ml, then there would be a possible placement of Rl in Ml at any row. This is depicted graphically in Figure 2A, where a node Rl represents a redundant row that could be placed in any row of a memory block represented by a node Ml. An edge E connects the node Rl to the node Ml and an arrow head on the edge shows the direction of placement as being Rl placed into Ml.
  • An actual placement in a memory block Ml may be represented graphically by an equation.
  • a constraint is made between two redundant elements and can be modeled as a function of those two redundant elements.
  • This constraint function represents a set of inequalities, all of which must be true for placement to be possible.
  • both redundant elements should have specific placements; the constraint function will evaluate as true if this pair of placements is possible.
  • Constraint functions may express many inequalities. These inequalities must all be satisfied for a given pair of placements to be valid. As a result, constraint functions are expressed as the product of a set of Boolean-valued functions. The operators available for the construction of these functions include, in addition to those available for the construction of placements:
  • a constraint is represented by an edge between nodes. Unlike a placement (or a possible placement) a constraint has no direction, so the edge has no arrow. As an additional indicator, the edge may be dashed, or may be marked with a bar (a short line perpendicular to the edge, and placed in the centre).
  • the variables available to the constraint expression include the placement (if any) of both redundant elements, including the memory that each redundant element is placed in.
  • Figure 3A shows two redundant rows Rl and R2, with possible placements into two memories Ml and M2 respectively.
  • Rl and R2 are constrained such that thex coordinate of their placement must be equal. This situation is often called a global spare row, or a tied row, and is expressed as
  • Figure 3B shows two redundant rows Rl and R2 that have possible placements into either memory block Ml or memory block M2, however both Rl and R2 must be placed into the same memory block. This situation is expressed as
  • Figure 3C shows two redundant rows Rl and R2 that have possible placements into a memory block Ml such that both rows must be placed in the same half of Ml .
  • This constraint which can arise from sharing the most significant bit in the fusebox, is expressed as
  • Ml is a 256 x 256 cell array
  • Rl is placed at x ⁇ 128, then R2 must also be placed at x ⁇ 128, and vice versa. This may be expressed as
  • the set of possible placements is a sub-set of the universe defined by the possible placements of the redundant element. Calculating this set requires only the device design information.
  • the possible placements of a redundant element are limited by its constraints with other redundant elements.
  • the set of constrained placements is a sub-set of possible placements, defined by the placements of other redundant elements within the device.
  • the total coverage of a redundant element is the set of cells that could be covered by the redundant element R for all possible placements. This is the set of cells which could be replaced by the redundant element. Total coverage can be defined as the union of all specific coverages of the redundant element R for all possible placements:
  • a possible placement refers to a source redundant element and a target memory
  • coverage can be calculated for a possible placement; however, a possible placement can only represent a set of placements and therefore it can only have a total coverage.
  • the total coverage of a possible placement P with a source redundant element R is given by:
  • DRAM devices are often composed of many very similar parts repeated many times and, as a result, many of the model elements will be identical (in size and, for redundant elements, have the same sets of possible placements). Identifying these replicated elements requires some method of testing if two blocks are equal.
  • Two memory blocks are equal if, and only if, they have the same width and height. The location of the two blocks is not compared - two blocks with the same size and location would overlap, and this would indicate a modeling error. Modeling errors will be discussed presently. Equality of two memory blocks is expressed as:
  • a device may have many (hundreds or even thousands) of redundant rows, all of the same size, and all with possible placements into any of many identical memory blocks.
  • Two redundant elements which are equal should be interchangeable; redundant elements, to be interchangeable, must be not only of the same size but also usable to replace all of the same memory cells and sets of memory cells. That is, if two redundant elements are equal, for each specific coverage of one there must be an identical specific coverage of the other.
  • the total coverage of a redundant element expresses the set of cells which can be replaced.
  • a redundant row and a redundant column with placements in the same memory block often have identical total coverages; however, two redundant elements with the same size and the same total coverage must have matching sets of specific coverages. The conditions for equality of two redundant rows are expressed as:
  • a redundant element is said to be “compatible” with another if they can replace some of the same memory cells. Compatibility is defined in terms of the total coverage of the redundant elements.
  • the compatibility region Comp(Rl,R2) of two redundant elements Rl and R2 is the intersection of their total coverages:
  • Compatibility is associative. In other words, the intersection of the compatibility region of Rl and R2 with the total coverage of R3 is the same as the intersection of the compatibility region of R2 and R3 with the total coverage of Rl.
  • Figure 5 illustrates how the intersections of the total coverage of three redundant elements Rl, R2 and R3 define their compatibility regions.
  • the compatibility region Comp (R1,R2,R3) is the intersection of all total coverages, and is also the intersection of the three two-argument compatibility functions.
  • every bit of storage in the device must be represented by exactly one memory cell; each memory cell must be in a memory block or a redundant element; all memory cells belonging to a given redundant element must be allocated together; and conversely all redundant memory cells allocated together must form one redundant element.
  • FIG. 6A An example of a conventional layout diagram of a device is shown in Figure 6A.
  • the layout diagram shows a first memory block 601 with a redundant row 603 beneath and a redundant column 605 to the right.
  • a second memory block 607 has a redundant row 609 and a redundant column 611
  • a third memory block 613 has a redundant row 615 and a redundant column 617.
  • a redundant row 619 can be placed in all three memory blocks.
  • a graphical model is overlaid on the layout diagram to illustrate the correlation between the graphical model and the layout diagram.
  • the graphical model has a node Ml representing the first memory block 601.
  • a node Rl representing the redundant row 603 is connected to the node Ml by an edge
  • a node R2 representing the redundant column 605 is connected to the node Ml by an edge
  • a node M2 represents the second memory block 607
  • a node R3 representing the redundant row 609 is connected to the node M2 by an edge
  • a node R4 representing the redundant column 61 1 is connected to the node M2 by an edge
  • a node M3 represents the third memory block 613
  • a node R5 representing the redundant row 61 is connected to the node M3 by an edge
  • a node R6 representing the redundant column 617 is connected to the node M3 by an edge
  • a node R7 represents the redundant row 619 and is connected to each of the three memory blocks by edges.
  • a typical DRAM device has many similar memory banks each with a plurality of memory blocks and redundant elements. There are usually no placements of a redundant element outside its memory bank.
  • a model of a DRAM that has a plurality of memory banks, each in turn with a plurality of memory blocks and redundant elements lends itself to abstraction because of its hierarchical, repeating structure.
  • a new model element can hide a sub-graph within a node. Such a node that appears in a graphical model need not be represented in a
  • An abstract model element that can represent only a subgraph can have one connection (possible placement or constraint) with the rest of the model. This limits the use of such an abstract model element in many seemingly obvious situations.
  • An abstract model element that can represent a collection of nodes and edges is not so limited.
  • Figure 6B shows the use of abstract model elements (represented by nodes with a double edged circle) to simplify the example of Figure 6A.
  • An abstract model element represented by a double-edge circle Al represents the three nodes Ml, Rl and R2 and their connecting edges.
  • an abstract model element represented by a double-edge circle A2 represents the three nodes M2, R3 and R4 and their connecting edges
  • an abstract model element represented by a double-edge circle A3 represents the three nodes M3, R5 and R6 and their connecting edges.
  • a plurality of edges may be necessary between nodes representing abstract model elements. Such a plurality of edges may be represented by a single line, in a manner comparable to the representation of a multi-conductor bus in an electrical circuit diagram, with appropriate notations to indicate possible placements and constraints.
  • Figures 7A through 7C are a layout diagram of a memory block 701 and four redundant rows 703, 705, 707 and 709. Any of these rows may be placed anywhere in the memory block 701.
  • FIG. 7B This situation is depicted in a graphical model in Figure 7B, where a node Ml represents the memory block 701 and nodes Rl through R4 represent the redundant rows 703, 705, 707 and 709, respectively. Placements connect each of the nodes Rl through R4 with the node Ml, and constraints, shown as arcuate edges, interconnect the various nodes Rl through R4 with each other.
  • a simplification is shown in Figure 7C, where a single node labeled R includes the numeral "4" to indicate that the node R represents four redundant elements.
  • An edge 71 1 extends from this node to itself, representing a fully interconnected mesh of edges (be they constraints or placements) between all the redundant elements represented by this single node.
  • This single node with the edge 711 may be considered as a type of "atomic abstract model" element that represents a sub-graph.
  • Figure 7D illustrates a situation wherein, if Rl is placed in a 4-bit group, R2 must be placed in the same group. This may be expressed as
  • placements may only differ in the last two bits
  • a text language that can be used for describing a model of a DRAM must include nodes and edges that describe memory blocks, redundant elements, placements, and constraints as set forth above. Such a language must also include all the properties defined in the mathematical model.
  • the syntax of such a language should be familiar to most users. For example, a language similar to that of the C programming language, including named block definitions similar to structures, with blocks defined by pairs of braces and statements separated by semi-colons, would be familiar to most users of the model and would be readable by computers. There should be a facility for user input, for example corrections resulting from user review of syntax and semantics.
  • a memory block has the following properties: origin_row, origin_col.
  • origin_row The origin of the memory block, by convention the top left. Coordinates are expressed in memory cells from the origin of the device, also by convention the top left.
  • width The width of the memory block, in cells.
  • height The height of the memory block, in cells.
  • Redundancy Description of one or more redundant elements. Redundant elements have all the properties of memory blocks, and additionally: count. The number of identical redundant elements represented by this block. Count assumes that the elements are arranged to be adjacent on their longest axes (i.e. a set of rows will be "stacked" vertically). placement. The placement of this redundant element. No placement other than “none” or "0" is possible for a redundant element block with a count of more than one. (Note the distinction between placement and possible placement.)
  • Placement represents a possible placement between one redundant element and one memory block.
  • source The redundant element that has this as a possible placement.
  • target The memory block in which the source redundant element could be placed.
  • expression An expression limiting the possible placement of the source redundant element in the target memory block.
  • Constraint A constraint block represents a constraint between two redundant elements. Like a placement block, it has a defined source and target (though the constraint is bi-directional) and an expression. The set of parameters available in a constraint expression is larger than that available to a placement block.
  • Repeat A repeat construct replicates the same block multiple times ( «).
  • Constraints of some DRAM chips depend on the results of repairing other chips. This feature can be used to create "abort" functions during code generation, or it can be modeled in the MDL. Available data fields are: R.number_fails number of failed cells replaced with a redundant element, fails total number of fails replaced with a redundant element.
  • Placement expressions are a set of Boolean-valued functions all of which must evaluate to true (for a given set of coordinates) if the placement is allowed. Placement expressions may reference the dimensions of the target memory, and the coordinates of the placement under consideration.
  • constraints are also sets of Boolean-valued functions which must evaluate to true for possible placements of both the source and target redundant elements. Constraint expressions are usually more complex than those of possible placements and have access to the possible placement of any redundant element and the dimensions of any memory. Additionally, constraint expressions have extra operators allowing the construction groups of Boolean valued functions.
  • a layout model of part of a DRAM is shown in Figure 8A.
  • a memory block Ml begins at the origin (0,0) in the upper left corner and has 320 rows each of 256 memory cells.
  • the notation (255,0) at the upper right comer shows there are 256 columns, from 0 to 255; in other words, each row has 256 memory cells.
  • the notation (255,319) at the lower right corner of the memory block Ml shows there are 320 rows, from 0 to 319.
  • This model is similar to the model shown in Figure 7 A with the addition of the coordinates of the rows and columns. Not shown in the layout model of Figure 8A is a constraint that was not present in the model of Figures 7A and 7B: if any one of the redundant rows is used to replace an even-numbered row in Ml, then all of the other redundant rows can only be used to replace even-numbered rows in Ml.
  • FIG 8B A graphical model of this same DRAM is shown in Figure 8B. This model is similar to the one shown in Figure 7B, except it includes the constraint that if any one of the redundant rows is used to replace an even-numbered row in Ml, then all of the other redundant rows can only be used to replace even-numbered rows in Ml . This constraint is given by the expression (RS y % 2)(RT>, %2).
  • the number of bad RA rows allowed in a main region may be specified. For certain types of device, such as a NAND device, it is possible to mark or tag the bad blocks/rows. For example, only allow placement if less than 8 faults:
  • MDL Memory Description Language
  • the number of fails allowed in the redundant element may be specified. It may be acceptable to use a redundant column that only has one or two sparse failures to replace a very large failed column in the main. The sparse failure could either be repaired by ECC or by marking out the bad row, particularly for a NAND application.
  • Each R has a priority number used by the code generator to guide a repair algorithm. Redundant elements with a higher priority will be used in preference to those of lower priority. Note that this is not part of describing the repair structure, but rather part of the repair algorithm.
  • Placement (x % 2) [00153] Forced grouping: Placement of 2 adjacent columns in a section of 4 bits:
  • Conditional Odd Even if there are two adjacent redundant columns and one column is placed at an odd location, then the other must also be placed at an odd location. If one column is placed at even location then the other needs to be placed at even location:
  • Root cause last two fuse bits are shared:
  • Odd/Even grouping Two adjacent redundant columns. The difference between the placements must be at least 8.
  • Root cause third fuse bit is shared:
  • the memory is grouped in adjacent 4- bit sections, and if one column is placed in an odd section, then the other one needs to be placed in an odd section.
  • the memory can be represented as: AAAA BBBB CCCC DDDD EEEE FFFF where AAAA, CCCC and EEEE are odd-numbered sections. If one of the two adjacent redundant columns is placed in any column of section AAAA, then the other could be placed in section AAAA or section CCCC but not section BBBB.
  • Root cause third least significant fuse bit is shared:
  • Multi Coloring Two adjacent redundant columns. The memory is grouped in adjacent 4-bit sections. If one redundant column is placed in a given section, then the other redundant column can only be placed four sections further. In the previous memory example, if one redundant column is placed in section AAAA, the other could only be placed in section EEEE.
  • Root cause third and fourth least significant fuse bits are shared:
  • Row column cross reference If there is one redundant column and one redundant row, and if the row is placed in an odd location then the column must also be placed in an odd location, whereas if the row is placed in an even location then the column must also be placed in an even location:
  • Root cause last fuse bit is shared:
  • Graphical tools are commonly used to quickly and accurately create and manipulate models.
  • a graphical tool has been proposed for grid computing work by Andreas Hoheisel, "User tools and languages for graph-based grid workflows: Research articles," Concurr. Comput. : Pract. Exper., 18(10): 1101—1113, 2006.
  • Such a graphical tool presents an interface to complex scientific computing tools, allowing the user to control job execution order and data flow and simplify otherwise complex problems.
  • a graphical tool offered by Advantest and called “mratool” provides a graphical view of a DRAM device. This tool shows memory blocks with local redundant rows and columns. With this tool a user can edit certain properties and manipulate repair structures.
  • a tool embodying principles of inventive aspects disclosed herein provides for graphical modeling of DRAM devices, import and export of models, and generation of repair code and tester configuration specific to those devices.
  • This tool provides three views of the model data: a conventional row and column based layout view, a graphical view as described previously, and a text model also as described previously.
  • the graphical model provided by the tool includes prototype implementations of both abstraction levels, and syntax and semantic checking. The tool can create tester configuration files and repair code.
  • a plug-in environment known as "Eclipse” (E. Foundation. Eclipse. Online at http://www. eclipse, org, Sept 2009) provides a rich set of libraries for creating graphical tools.
  • Eclipse E. Foundation. Eclipse. Online at http://www. eclipse, org, Sept 2009
  • a graphical editing framework provided by Eclipse provides an interface for creating graphical editors.
  • the tool has been developed in Eclipse to take advantage of this cross-platform environment and to allow future interoperability with other tools.
  • Device models can be created using the tool in any of three ways: as a graphical model, a layout model, or a text description. Following is a sequence of actions taken by a user to create a design, and actions the tool performs in response. The actions are similar for creating a design using either the graphical model editor or the layout editor.
  • Tool either presents configuration options partially configured from initial element configuration or presents a "wizard" page providing for automatic replication of elements e.g. at specific positions.
  • Syntax checking may be an iterative process.
  • the tool presents a list of syntax errors in each model element that has any errors.
  • the user may then modify the configuration options and the tool checks syntax again and reports any errors. This process is repeated as needed.
  • the tool can export a design using the text modeling language described above.
  • the text model of a given device is equivalent to the layout or graphical models, and accordingly the tool allows the user to switch between these different model views.
  • the tool can also import a model.
  • the user selects a text model file to import, and in response the tool parses the text model, creates an internal representation, and updates the editor window.
  • the model is then used to create redundancy analysis code or configuration files needed during redundancy analysis.
  • the tool includes a provision for adding new redundancy analysis algorithms, for example by importing them as a package or by saving new algorithms developed by the user; new tester specific configuration can be included by the same mechanism.
  • the components of the tool include elements that interact with the user, such as editors for text models 901, graphical models 903, layout 905, code 907 and library 909 blocks; those that create output such as text model export 91 1 ; and those that manipulate the internal model of a DRAM device, such as bitmap generation 13, plug-in framework 915, simulator 917, algorithm 919 and code 921 generation, and partition algorithms 923. These components are depicted interacting with a central controller 925.
  • the graphical editor manipulates a set of objects representing those drawn on screen and then translates them into objects representing mathematical model elements.
  • a set of hooks are provided to allow the syntax and semantic checker to graphically highlight model elements for which there are syntax or semantic errors. Causes of these errors may be shown in a tooltip of the element.
  • the graphical editor provides a main editor window, a palette of available model elements, a browser displaying all elements in the current model, and a properties window for the selected element.
  • the editor implements an abstract model node as a graphical model node having a filename property. When the user selects this node, the editor opens a new window for editing the corresponding file. When building the mathematical model graph, the editor simply imports nodes from that file.
  • Editors for both generated code and the text model representation are simple text editors and may take advantage of the Eclipse text editor component.
  • Objects generated by the graphical editors and by the text model parser are of two types: those that represent memory cells ("block” objects) and those that represent uses (and restrictions) of memory cells ("connection” objects).
  • Object inheritance is used to create a simple hierarchical representation of the mathematical model.
  • Identification of independent graphs within the model allows improvements to be made during code generation. Identification of independent graphs is implemented as an iterative process, considering each node and collecting nodes with common edges (placements or constraints). Independent trees are stored as a list of names of nodes (memory or redundancy blocks) in the tree.
  • intersection of the sets of their coverage implemented as a fast set operation.
  • Each algorithm may require a number of templates and dedicated code describing the template parameters as described previously.
  • the base class ALGORITHM is provided.
  • Each implemented algorithm must extend this base class.
  • the mathematical model objects and a set of pre- written methods operating on the model are provided to the constructor for each class.
  • a TEMPLATE class provides methods for building an internal representation of a template (which may be supplied from a file or from a string), for populating the template parameters and for combining those parameters with the stored template.
  • One algorithm may require many templates each described by code extending the TEMPLATE class.
  • a BUILDER class is used to translate language and algorithm selections made by the user into the correct algorithm class.
  • the BUILDER class also provides methods to execute the specified algorithm and to collect the generated code.
  • the graphical model editor is automatically invoked, and the user adds nodes representing memory and redundancy in the device and edges representing the uses of those nodes. Selecting a node or edge presents an editable list of the properties of that object. Node names are generated automatically but may be changed by the user. The user manually edits other relevant values.
  • a graphical model may be displayed in a graphical editing window, and properties may be displayed in a separate properties window. [00190] During model creation, mistakes can be corrected with the aid of syntax and semantic checking. The tool may highlight nodes with errors and with a message describing the error.
  • Abstract model elements may be shown as nodes that represent sub-graphs in the graphical model. These abstract model elements reduce the complexity of a displayed graph.
  • the graphical model does not represent physical properties of the model. For example, it does not describe coordinate location of a memory block, nor size of the memory block.
  • the tool can display such information in a layout editor, and it can display a textual model in a text editor.
  • the user may generate a repair algorithm or configuration files.
  • a generator embodying some of the inventive principles disclosed herein generates a repair procedure for a particular type of DRAM chip.
  • the repair procedure in turn generates a repair algorithm for each specific chip that has defective memory cells.
  • the repair algorithm comprises machine code that tells which fuses to burn, and in response the automatic test and repair equipment actually burns the fuses so as to repair the chip.
  • the generator is normally used only once for one specific type of DRAM chip, to generate a repair procedure for that type of chip.
  • the generator starts with a mathematical model of that type of DRAM as expressed in a textual language such as the Memory
  • the generator translates this mathematical model into whatever format is required by the particular automatic test and repair equipment that is to be used to repair the DRAM chips. This translation involves converting a set of data structures that represent the mathematical model of the DRAM into an alternative set of data structures that the test equipment can use with minimal manipulation.
  • the generator is used to generate the repair procedure prior to an actual manufacturing run. Therefore, the generator is not in a critical manufacturing path, and ample time and resources are usually available to it.
  • the repair procedure receives from the automatic test and repair equipment a list of defects in each chip as the chips emerge from the assembly process. This may occur before the silicon wafer is diced into individual chips, or after dicing. From the list of defects in each individual chip, the repair procedure generates a repair algorithm for that chip. Such a repair algorithm must be created for each chip that fails the initial test after manufacture. Thus, it will be seen that the repair procedure is in the critical manufacturing path and therefore it must generate a repair algorithm for each chip in minimal time and with minimal use of system resources.
  • the problem of finding an optimal repair solution for a chip is an NP Complete problem referred to as a SAP (spare allocation problem).
  • Finding a repair algorithm for a specific chip may be thought of as traversing down a tree of placement decisions, backtracking as needed.
  • Optimizing a repair algorithm can be thought of as pruning this decision tree.
  • a language capable of describing primitive functions of a repair algorithm allows the generator to manipulate these primitives, implement existing repair procedures, and develop new repair procedures.
  • a modular generator architecture based on such a language can generate repair algorithms independent of either input language or target platform.
  • FIG. 10 A shows a simple memory block Ml having four rows and four columns, one redundant row Rl, and one redundant column R2.
  • Figure 10B is a graphical model of possible placements of these redundant elements with elements Rl and R2 each connecting to memory block Ml by an edge.
  • Possible placements of these two redundant elements in this memory may also be represented by a tree as shown in Figure 11.
  • the redundant row Rl can be placed in any of the four rows of Ml having starting coordinates 0,0 through 0,3, respectively.
  • the redundant column R2 can be placed in any of the four columns having starting coordinates 0,0 through 3,0.
  • the tree as shown in Figure 1 1 has 16 placement nodes in the leaf (bottom) level, four nodes in the branch (middle) level, and one node at the root (top) level.
  • the tree would instead have 25 leaf nodes, representing all possible uses of the two redundant elements including the possibility of not using the elements at all.
  • the tree as drawn actually represents a simplification from 25 leaf nodes to 16, in that the possibility of not using the redundant elements has been excluded.
  • any subtrees not permitted by the restrictions may be removed, reducing the size of the tree.
  • the size of the tree is reduced by half, as shown in Figure 12A.
  • Figure 14A shows the effect on the tree of a constraint that the most significant bit of the placement address of Rl must be the same as the most significant bit of the placement address of R2.
  • This constraint reduces the number of leaf nodes to two.
  • This type of constraint is often imposed by sharing of a bit in the fusebox.
  • the repair decision tree can be further pruned by using failure data to select only those branches that actually replace failed cells. This may be done by pre-computing a set of look-up tables based on the functions described above.
  • the total coverage of a redundant element was previously defined as the union of all the cells covered by the possible placements of that redundant element. Each possible placement is independent of all other possible placements. Therefore, this union of cells can be calculated by iteratively evaluating each cell in each memory block in which the redundant element can be placed and testing the coordinates of each cell against the possible placement expressions.
  • compatibility tables simplify the selection of other redundant elements capable of partially covering those faults. But a search through all redundant elements may be required to identify this initial one redundant element.
  • Compiling a table of which redundant elements can replace particular regions of the device allows a simple coordinate lookup of those redundant elements that can replace a failed air a failure, without a costly search during repair algorithm execution. Boundaries of these regions can be identified by analyzing compatibility regions already calculated. Such analysis does not require failure data.
  • a "region" is defined as each non-empty intersection of compatibility for each unique permutation of all redundant elements. Regions can be identified by tagging each cell with the name of all redundant elements covering that cell, and then computing regions with contiguous tags, according to the following procedure:
  • a 8x8 memory block having six repair regions is shown in Figure 15.
  • a first repair region RR1 extends from coordinates (0,0) to coordinates (3,3).
  • a second repair region RR2 extends from (4,0) to (5,3).
  • a third repair region RR3 extends from (6,0) to (7,3).
  • a fourth repair region RR4 extends from (0,4) to (3,7).
  • a fifth repair region RR5 extends from (4,4) to (5,7).
  • a sixth repair region RR2 extends from (6,4) to (7,7).
  • a first redundant element Rl is a 6-cell row element that can be placed in any row between columns 0 and 5.
  • a second redundant element R2 is a 4-cell row element that can be placed in any row between columns 4 and 7.
  • a third redundant element R3 is a 4-cell column element that can be placed in any column between rows 0 and 3.
  • a fourth redundant element R4 is a 4-cell column element that can be placed in any column between rows 4 and 7.
  • a fifth redundant element R5 is an 8-cell row element that can be placed in any row.
  • a fast region lookup function can be implemented as an if-then-else tree, a lookup table, or however is most suited to the target platform.
  • a final optimization that can be implemented without any actual failure data is partitioning the repair problem into smaller independent problems. If a spare allocation problem of complexity 0(N!) can be split into two independent smaller problems of complexity 0(P!) and O(Q!) where P > Q then the complexity of the overall problem has been reduced to 0(P!).
  • a spare allocation problem of complexity 0(N!) can be split into two independent smaller problems of complexity 0(P!) and O(Q!) where P > Q then the complexity of the overall problem has been reduced to 0(P!).
  • Within a large DRAM device there may be a number of banks where none of the redundant elements place outside the bank, nor are there constraints with elements not included in the bank. See, for example, T.
  • Independent memory banks can easily be identified as they form independent graphs in the mathematical model.
  • Two independent memory banks Ml and M2 are shown in layout view in Figure 16A.
  • the memory bank Ml has a redundant row element Rl and a redundant column element CI
  • the memory bank M2 has a redundant row element R2 and a redundant column element C2.
  • the graphical model for these memory banks is shown in Figure 16B, where the redundant elements Rl and CI are shown connecting to Ml, and the redundant elements R2 and C2 are shown connecting to M2.
  • the repair procedure can solve the simplified SAP using, for example, a must-repair heuristic followed by a branch-and-bound algorithm to generate the repair algorithm.
  • the tool developed may be compared to a compiler.
  • a compiler receives a representation of a procedure in source code and translates it into a representation of the procedure in machine code.
  • the generator is more complex in that it receives a model of a device and must generate a repair procedure.
  • Templates are written directly in the target language. Therefore, the use of templates to describe repair procedures removes the need for a generic language to describe repair procedures.
  • the generator replaces template parameters with data derived from the model of the DRAM.
  • a relatively simple repair procedure and platform configuration can be implemented as templates with parameters derived from the model, e.g. the number of redundant rows and columns available, or the size of a memory array. More complex repair procedures require more flexibility; such procedures can be implemented as nested templates, where a parameter in one template may be substituted with the output of another template.
  • the DRAM model is partitioned into sub-problems. Generating a repair procedure for a specific defective DRAM is accomplished separately for each sub-problem by providing appropriate pre-written fixed code and using templates with parameter substitution to generate additional code. The code generated for the sub-problems is integrated to provide the repair procedure.
  • the templates applied to the sub-problems are selected according to the user's preference for yield, throughput, or any other factor.
  • Each template or set of templates may be labeled with an indication of expected performance so that templates matching the user's choice may be selected.
  • a tool including a simulation framework such as "Raisin" as described above may be used to benchmark possible repair algorithms for the specified device and present the results to the user, who may then select a desired repair algorithm.
  • the user may be given a list of algorithms that can be generated and the user may select based on pre-existing knowledge.
  • FIG 17A For example, a layout model of a device with two 16x16 memory banks is shown Figure 17A.
  • a corresponding graphical model is shown in Figure 17B.
  • a first memory bank Ml begins at coordinates (0,0) and has a redundant row Rl and a redundant column R2, either of which can be placed anywhere in Ml.
  • a second memory bank M2 begins at coordinates (16,0) and has a redundant column R3 that can be placed anywhere in M2 and a redundant row R4 that can be placed in any row between columns 24 and 31.
  • a redundant row R5 covers both memory banks and can be placed in any row.
  • templating the region identification can be split into only two templates, a framework template providing function definition and a template building the //clause and redundant element list for each region.
  • repair procedures are constructed.
  • One way to construct a repair procedure is to start with a "must- repair” procedure.
  • a "must-repair" for a single independent problem can be expressed as a fixed code template.
  • a generated template can be used to package the "must- repair” problems together.
  • the "must-repair" procedure can be followed with a “branch-and-bound” procedure as performed by the following function.
  • the GET RED BY REGION function (described previously) returns a list of redundant elements capable of replacing a failure at the specified coordinates; typically this is implemented by region lookup tables.
  • the function GET NEXT FAULT ( ) is not defined here. It returns the coordinates of the next faulty, un-replaced cell in the device.
  • a simple implementation of the CONSTRAINT ALLOWED () function can iterate over all constraints in the independent graph, or model, checking the constraint expression for only those constraints for which both source and target redundant elements have been placed.
  • EVALUATE CONSTRAINT 0 evaluates a constraint expression with the placement of both source and target redundant elements.
  • Figure 18 shows a 256x256 memory block having three regions.
  • a first region Rl extends across all rows from column 0 to column 127.
  • a second region R2 extends across rows 0 to 127 from column 128 to column 255 and a third region R3 extends across rows 128 to 255 from column 128 to column 255.
  • C++ code representing these three regions is generated in a region code generator shown in Figure 19.
  • the region code generator receives the following template construct:
  • the region code generator uses a description of a specific device written in MDL to provide the following device-specific C++ code returning the appropriate region id:
  • a method of creating a repair algorithm for a specific DRAM chip having defective memory cells is depicted in Figure 20.
  • the chip is referred to herein as a DUT (device under test).
  • a defects list 2001 is provided by a tester that tested the DUT after assembly.
  • This defects list, and a mathematical model 2003 of the chip, and computer code in a code generation library 2005 are used to identify problems 2007. From there a building block is generated 2009.
  • the computer code in the library 2005 which may be C++ code, was previously developed as described above.
  • the code may be stored in the library in the form of a plurality of software blades. As the building block is generated, the resulting code is stored in a redundancy analysis (RA) library 2011.
  • the library 2011 is used for DUT- specific code.
  • the building block, and as needed code from the library 2011, are used to generate a potential repair algorithm 2013.
  • a simulation of the potential repair algorithm is run 2015.
  • the result of this simulation is compared against a desired yield model 2017, such as maximum throughput or maximum number of chips repaired.
  • the comparison may refer to a process parameters library 2019.
  • Performance metrics are measured 2021 and compared with performance results from previously-run simulations as stored in a performance database 2023. Also, the performance metrics may be stored in the database 2023 for future comparisons with performance metrics from other possible algorithms.
  • the organization of the code generation library 2005 is depicted in Figure 21.
  • the library includes fixed code blocks 2101, template blocks 2103, and generated template blocks 2105. Also included is integration freedom C++ code 2107.
  • the template blocks 2103 include C++ templates 2109, C++ code 21 1 1, and C++ debug routines 21 13.
  • the generated template blocks 2105 include text template constructs 2115, C++ code 2117, and C++ debug routines 2119. Test Apparatus
  • a processing unit 2201 typically includes such components as (not shown) a microprocessor, random-access memory, disk drives, and the like.
  • a user may communicate with the processing unit 2201, for example through a keyboard 2203 and a monitor 2205.
  • other input devices such as a mouse or other output devices that may be used as desired.
  • a printer 2207 may give any desired hard-copy output of text and of graphics.
  • Memory such as a hard disk 2209 may contain instructions that control the processing unit 2201 and any peripheral devices.
  • the hard disk 2209 may also contain any of the databases described previously.
  • the various devices shown in Figure 22 may be located adjacent one another or even in a common cabinet, or they may be remotely located in which event they may communicate through dedicated lines, wireless connections, the Internet, or in other ways as may be convenient.
  • a test hub 2211 communicates with the processing unit 2201.
  • a DUT device under test
  • an integrated circuit 2213 is connected to the test hub through a plurality of leads 2215. Although only three leads are shown, it will be apparent that any number of leads may be used according to the configuration of the particular DUT.
  • a socket or test probe or other connecting apparatus may be used to establish electrical connections between the DUT and the test hub, or direcdy between the DUT and the processing unit as desired. Electrical power and mechanical cooling connections may also be provided through the test hub or the processing unit as necessary.
  • a rapid connect and disconnect probe or socket may be used to achieve high throughput.
  • Test signals from the processing unit 2201 are applied to the DUT to test its various elements. Responses are communicated back to the processing unit 2201. If a repair is to be effected, instruction signals from the processor 2201 are applied to the DUT, for example to burn fuses in the DUT or otherwise repair the DUT according to the methods set forth above.
  • the test head responsive to the processing unit, may generate power signals needed to burn fuses in the DUT.
  • inventive principles disclosed herein have been described with reference to certain embodiments, but the described embodiments do not limit the scope of the below claims. Many variations will be apparent. For example, although the embodiments speak mainly of DRAM chips, the inventive principles disclosed herein may be applied to the repair of other kinds of integrated circuits. The scope of the inventive principles disclosed herein is to be limited only by the claims.

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé de caractérisation de circuits intégrés dans lequel des blocs de mémoire sont représentés en formats graphiques et en formats textuels lisibles par un ordinateur. Des éléments redondants sont représentés dans ces formats. Les positionnements éventuels des éléments redondants sont décrits dans les formats graphiques et les formats textuels lisibles par un ordinateur. Les contraintes de positionnement sur les éléments redondants sont également décrites. Les représentations des blocs mémoire et des éléments redondants, et les descriptions des positionnements éventuels et des contraintes, sont combinés en descriptions globales graphiques et textuelles lisibles par l'ordinateur du circuit intégré. L'invention concerne également un procédé de génération d'algorithme de réparation de circuit intégré, et un procédé et un système de réparation de circuit intégré.
PCT/US2010/048297 2009-09-28 2010-09-09 Caractérisation et réparation de circuits intégrés WO2011037758A1 (fr)

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