WO2011036088A3 - Carrier for electrically connecting a plurality of contacts of at least one chip applied to the carrier and method for producing the carrier - Google Patents
Carrier for electrically connecting a plurality of contacts of at least one chip applied to the carrier and method for producing the carrier Download PDFInfo
- Publication number
- WO2011036088A3 WO2011036088A3 PCT/EP2010/063618 EP2010063618W WO2011036088A3 WO 2011036088 A3 WO2011036088 A3 WO 2011036088A3 EP 2010063618 W EP2010063618 W EP 2010063618W WO 2011036088 A3 WO2011036088 A3 WO 2011036088A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- carrier
- contacts
- solder
- electrically connecting
- metal
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000002184 metal Substances 0.000 abstract 4
- 229910000679 solder Inorganic materials 0.000 abstract 3
- 239000004020 conductor Substances 0.000 abstract 1
- 238000001816 cooling Methods 0.000 abstract 1
- 239000012530 fluid Substances 0.000 abstract 1
- 230000008023 solidification Effects 0.000 abstract 1
- 238000007711 solidification Methods 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/101—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by casting or moulding of conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L24/92—Specific sequence of method steps
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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- H01L2225/06503—Stacked arrangements of devices
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2924/014—Solder alloys
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/12—Using specific substances
- H05K2203/128—Molten metals, e.g. casting thereof, or melting by heating and excluding molten solder
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention relates to a carrier (1) for electrically connecting a plurality of contacts of at least one chip (70-1) applied to the carrier (1) of a plurality of chips (7, 70) to each other, comprising holes (2) closed on one side by metal contacts (5) and/or metal contacts of chips, so that blind holes open toward the top side of the carrier are produced. The carrier (1) is immersed in a fluid bath having electrically conductive solder or metal under vacuum. In the immersed state, the environment of the carrier (1) is placed under negative pressure so that the holes (2) of the carrier (1) including the lower surface of the carrier are completely filled with metal conductive material after cooling and solidification of the solder (10), whereby the complete wiring of the carrier (1) is completed by the solder (10).
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102009042558.6 | 2009-09-22 | ||
DE102009042558 | 2009-09-22 | ||
DE102010009452A DE102010009452A1 (en) | 2009-09-22 | 2010-02-26 | Carrier for electrically connecting a plurality of contacts of at least one chip applied to the carrier and method for producing the carrier |
DE102010009452.8 | 2010-02-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2011036088A2 WO2011036088A2 (en) | 2011-03-31 |
WO2011036088A3 true WO2011036088A3 (en) | 2013-04-18 |
Family
ID=43705766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2010/063618 WO2011036088A2 (en) | 2009-09-22 | 2010-09-16 | Carrier for electrically connecting a plurality of contacts of at least one chip applied to the carrier and method for producing the carrier |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE102010009452A1 (en) |
WO (1) | WO2011036088A2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102012218561A1 (en) * | 2012-10-11 | 2014-04-17 | Siemens Aktiengesellschaft | Electronic module of multiple modules for use in tetrahedral coolant container, has metal layer that comprises edge region which is directly connected to support |
DE102013201479A1 (en) * | 2013-01-30 | 2014-08-14 | Siemens Aktiengesellschaft | Method for through-contacting a semiconductor substrate and semiconductor substrate |
JP6138026B2 (en) * | 2013-11-12 | 2017-05-31 | 日本メクトロン株式会社 | Method for filling conductive paste and method for producing multilayer printed wiring board |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1321545A (en) * | 1971-12-08 | 1973-06-27 | Ibm | Method of fabricating multilayer circuits |
US6426241B1 (en) * | 1999-11-12 | 2002-07-30 | International Business Machines Corporation | Method for forming three-dimensional circuitization and circuits formed |
JP2002237468A (en) * | 2001-02-09 | 2002-08-23 | Fujikura Ltd | Method of forming electrode passed through substrate, and substrate having through electrode |
JP2002368082A (en) * | 2001-06-08 | 2002-12-20 | Fujikura Ltd | Method and device for filling metal into fine space |
DE102006060533A1 (en) * | 2006-12-21 | 2008-06-26 | Qimonda Ag | Method for producing a first layer with an electrical line and arrangement with a contact layer |
-
2010
- 2010-02-26 DE DE102010009452A patent/DE102010009452A1/en not_active Withdrawn
- 2010-09-16 WO PCT/EP2010/063618 patent/WO2011036088A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1321545A (en) * | 1971-12-08 | 1973-06-27 | Ibm | Method of fabricating multilayer circuits |
US6426241B1 (en) * | 1999-11-12 | 2002-07-30 | International Business Machines Corporation | Method for forming three-dimensional circuitization and circuits formed |
JP2002237468A (en) * | 2001-02-09 | 2002-08-23 | Fujikura Ltd | Method of forming electrode passed through substrate, and substrate having through electrode |
JP2002368082A (en) * | 2001-06-08 | 2002-12-20 | Fujikura Ltd | Method and device for filling metal into fine space |
DE102006060533A1 (en) * | 2006-12-21 | 2008-06-26 | Qimonda Ag | Method for producing a first layer with an electrical line and arrangement with a contact layer |
Also Published As
Publication number | Publication date |
---|---|
WO2011036088A2 (en) | 2011-03-31 |
DE102010009452A1 (en) | 2011-04-07 |
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