WO2011021276A1 - Temperature detection device, information processing equipment and method for controlling temperature detection device - Google Patents

Temperature detection device, information processing equipment and method for controlling temperature detection device Download PDF

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Publication number
WO2011021276A1
WO2011021276A1 PCT/JP2009/064464 JP2009064464W WO2011021276A1 WO 2011021276 A1 WO2011021276 A1 WO 2011021276A1 JP 2009064464 W JP2009064464 W JP 2009064464W WO 2011021276 A1 WO2011021276 A1 WO 2011021276A1
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Prior art keywords
clock
temperature
voltage
temperature detection
unit
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PCT/JP2009/064464
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French (fr)
Japanese (ja)
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隆広 米澤
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富士通株式会社
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Priority to PCT/JP2009/064464 priority Critical patent/WO2011021276A1/en
Publication of WO2011021276A1 publication Critical patent/WO2011021276A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01KMEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K7/00Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements
    • G01K7/16Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements
    • G01K7/18Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a linear resistance, e.g. platinum resistance thermometer
    • G01K7/20Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a linear resistance, e.g. platinum resistance thermometer in a specially-adapted circuit, e.g. bridge circuit
    • G01K7/203Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat ; Power supply therefor, e.g. using thermoelectric elements using resistive elements the element being a linear resistance, e.g. platinum resistance thermometer in a specially-adapted circuit, e.g. bridge circuit in an oscillator circuit
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16Constructional details or arrangements
    • G06F1/20Cooling means
    • G06F1/206Cooling means comprising thermal management
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234Power saving characterised by the action undertaken
    • G06F1/324Power saving characterised by the action undertaken by lowering clock frequency
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to a temperature detection device, an information processing device, and a temperature detection device control method.
  • a temperature detection device for measuring the temperature of an integrated circuit
  • a device that compares a reference clock independent of temperature with the number of pulses of a VCO (Voltage Controlled Oscillator) controlled by a temperature-dependent control voltage has been known. Yes.
  • an apparatus using a pair of VCOs can relatively cancel process variations and fluctuations in power supply voltage and reduce measurement errors.
  • the input range of the VCO control voltage is limited, it is difficult to adjust the resolution.
  • the present invention has been made in view of the above, and provides a temperature detection device, an information processing device, and a temperature detection device control method capable of suppressing the influence of process variations and power supply voltage fluctuations and changing the resolution.
  • the purpose is to do.
  • the disclosed temperature detection apparatus, information processing apparatus, and temperature detection apparatus control method are configured such that the first oscillation unit uses the first voltage corresponding to the temperature to change the temperature.
  • a first clock having a frequency corresponding to the output frequency is output, the second oscillation unit outputs a second clock using a second voltage as a reference voltage, and the frequency dividing unit divides the first clock.
  • the third clock is output, and the counting unit counts the number of pulses of the third clock in the period of the pulse width of the second clock.
  • the disclosed temperature detection apparatus, information processing apparatus, and control method for the temperature detection apparatus are capable of suppressing the influence of process variations and power supply voltage fluctuations and changing the resolution, and controlling the temperature detection apparatus, information processing apparatus, and temperature detection apparatus There is an effect that a method can be obtained.
  • FIG. 1 is a schematic configuration diagram of a temperature detection apparatus according to a first embodiment.
  • FIG. 2 is a schematic configuration diagram of a first comparative example of the temperature detection device.
  • FIG. 3 is a schematic configuration diagram of a second comparative example of the temperature detection device.
  • FIG. 4 is an explanatory diagram illustrating an example of the configuration of the temperature detection unit 11.
  • FIG. 5 is a schematic configuration diagram of the temperature detection apparatus according to the second embodiment.
  • FIG. 6 is a circuit diagram of the VCO 23_1 shown in FIG.
  • FIG. 7 is a circuit diagram of the SELECTOR 24 shown in FIG.
  • FIG. 8 is a circuit diagram of the DECODER 24a.
  • FIG. 9 is a truth table of the DECODER 24a.
  • FIG. 1 is a schematic configuration diagram of a temperature detection apparatus according to a first embodiment.
  • FIG. 2 is a schematic configuration diagram of a first comparative example of the temperature detection device.
  • FIG. 3 is a schematic configuration diagram of
  • FIG. 10 is a circuit diagram of the DATPROC 25 shown in FIG.
  • FIG. 11 is a time chart regarding the trigger pulse and the output VJUD of the temperature detection device 2.
  • FIG. 12 is a circuit diagram of the COUNTER_TEMP 24b and the COUNTER_PROC 25b.
  • FIG. 13 is a circuit diagram of the REGISTER 25c shown in FIG.
  • FIG. 14 is a circuit diagram of the SUBTRACTOR 26 shown in FIG.
  • FIG. 15 is an explanatory diagram of the input / output relationship between the DATPROC 25 and the SUBTRACTOR 26.
  • FIG. 16 is an explanatory diagram of a scan chain included in the temperature detection device 2.
  • FIG. 17 is an explanatory diagram of the boundary scan for the scan chain shown in FIG.
  • FIG. 18 is a schematic configuration diagram of the information processing apparatus according to the third embodiment.
  • FIG. 1 is a schematic configuration diagram of a temperature detection apparatus according to the first embodiment.
  • the temperature detection device 1 illustrated in FIG. 1 includes a temperature detection unit 11, a power supply unit 12, a first oscillation unit 13_1, a second oscillation unit 13_2, a frequency division unit 14, and a counting unit 15.
  • the temperature detector 11 detects the temperature and outputs a first voltage VREF1 corresponding to the detected temperature.
  • the power supply unit 12 outputs a second voltage VREF2 serving as a reference voltage for the first voltage.
  • the first oscillation unit 13_1 receives the voltage VREF1 and outputs a first clock VOSCTEMP having a frequency corresponding to the voltage VREF1.
  • the frequency divider 14 divides the first clock and outputs a third clock VCOUNT.
  • the second oscillator 13_2 receives the voltage VREF2, and outputs a second clock VOSCREF having a frequency corresponding to the voltage VREF2.
  • the counting unit 15 receives the second clock VOSCREF and the third clock VCOUNT, counts the number of pulses of the clock VCOUNT during the pulse width period of the clock VOSCREF, and outputs the counting result.
  • the first oscillator 13_1 and the second oscillator 13_2 are, for example, VCO (Voltage Controlled Oscillator).
  • the first oscillator 13_1 and the second oscillator 13_2 are connected to the same power source and the same ground so as to have the same circuit characteristics, and have the same circuit configuration.
  • the first oscillation unit 13_1 and the second oscillation unit 13_2 are disposed close to each other.
  • the clock VCOUNT Since the clock VCOUNT is obtained by dividing the clock VOSCTEMP, the clock VCOUNT has a temperature-dependent difference and a division ratio difference with respect to the clock VOSCTEMP.
  • the resolution can be adjusted without changing the voltage VREF1 or the voltage VREF2.
  • VOSCREF and VOSCTEMP also change due to process variations or voltage fluctuations due to noise or the like, but since the relative difference does not change, the difference between VOSCREF and VOSCTEMP depends only on temperature.
  • VCOUNT A ⁇ VOSCTEMP Represented as:
  • VCOUNT1-VCOUNT2 A ⁇ (VOSCTEMP1-VOSCTEMP2) It becomes. From this equation, it can be seen that the temperature difference can be increased by increasing A even when the difference between VOSCTEM1 and VOSCTEMP2 is small, that is, when the temperature change is small. Therefore, the resolution can be varied by selecting A.
  • FIG. 2 is a schematic configuration diagram of a first comparative example of the temperature detection device.
  • the reference clock Vck independent of temperature is input to the CK terminal of the counting unit 15_1, and the pulse of the oscillation unit 13_3 controlled by the control voltage Vt depending on temperature is counted in the counting unit 15_1.
  • the counter 15_1 counts the number of pulses input to the EN terminal during the High or Low of the reference clock Vck.
  • FIG. 3 is a schematic configuration diagram of a second comparative example of the temperature detection device.
  • the first oscillation unit 13_1 is operated using the temperature-dependent reference voltage output from the temperature detection unit 11 as a control voltage, and the number of pulses is counted by the counting unit 15_2.
  • the second oscillating unit 13_2 is operated with a reference voltage that does not depend on the temperature output from the power supply unit 12 as a control voltage, and the counting unit 15_3 counts the number of pulses.
  • the control unit 16 performs temperature measurement using the fact that the difference between the count numbers of the counting unit 15_2 and the counting unit 15_3 depends only on the temperature.
  • the oscillation frequency is changed by changing the voltage supplied to the oscillation unit. Since there is a limit to the range of voltage that can be supplied to the oscillation unit, it is difficult to adjust the resolution in the second comparative example. Further, when the oscillation frequency is increased in order to increase the resolution, there is a problem that the power consumption increases.
  • the temperature detection device disclosed in FIG. 1 can cancel out process variations in the oscillation unit and fluctuations in the power supply voltage, reduce measurement errors, and set the division ratio.
  • the resolution can be changed easily.
  • the resolution since it is not necessary to increase the voltage supplied to the oscillation unit in order to increase the resolution, the resolution can be improved without increasing the power consumption.
  • FIG. 4 is an explanatory diagram illustrating an example of the configuration of the temperature detection unit 11.
  • the temperature detector 11 is configured by connecting a power source 11a, a resistor 11b, and a diode 11c in series, and obtains a voltage VREF1 from between the power source 11a and the resistor 11b. Since the diode 11c has temperature dependency, the voltage VREF1 becomes a DC voltage having temperature dependency due to the output voltage of the diode.
  • a voltage having temperature dependency and a voltage not having temperature dependency are supplied to the oscillation unit.
  • the clock signal oscillated based on the voltage having temperature dependency is divided, and the temperature information is obtained by comparing with the clock signal oscillated based on the voltage not having temperature dependency.
  • the temperature detection device, the information processing device, and the temperature detection device that can suppress the influence of process variations and power supply voltage fluctuations and can change the resolution.
  • a control method can be obtained.
  • FIG. 5 is a schematic configuration diagram of the temperature detection apparatus according to the second embodiment. 5 includes a VGEN 21 that functions as a temperature detection unit 11, a VGEN 22 that functions as a constant pressure power supply having no temperature dependency, VCOs 23_1 and 23_2 that function as oscillation units, and a SELECTOR 24 that functions as a frequency division unit. Have.
  • the VGEN 21 generates the DC voltage VREF1 depending on the temperature.
  • the VGEN 22 generates a DC voltage VREF2 that does not depend on temperature.
  • These VREF1 and VREF2 are supplied as control voltages for the VCOs 23_1 and 23_2.
  • the temperature detection device 2 includes a DATPROC 25 that functions as a counting unit, a SUBTRACTOR 26 that functions as a comparison unit that compares the counting result with a predetermined value, and a D-FF 27 that is a flip-flop circuit.
  • the VCO 23_1 is controlled by a temperature-dependent voltage VREF1.
  • the VCO 23_2 is controlled by a voltage VREF2 that does not depend on temperature.
  • the output VOSCTEMP of the VCO 23_1 is input to the SELECTOR 24, and the output of the SELECTOR 24 is obtained as VCOUNT.
  • VCO1 and VCO2 are connected to the same power source and the same ground so as to have the same circuit characteristics, and have the same circuit configuration. In consideration of variations in the chip, VCO1 and VCO2 are arranged close to each other on the layout. As a result, variations in VCO 23_1 and VCO 23_2 and power supply noise are offset, and the difference between VOSCREF and VOSCTEMP depends only on temperature.
  • VCOUNT is obtained by dividing VOSCTEMP, as a result, the difference between VOSCREF and VCOUNT depends only on temperature. Therefore, when adjusting the resolution of the temperature detecting device 2, it can be adjusted by the SELECTOR 24 without raising or lowering the control voltage of the VCOs 23_1 and V_2.
  • FIG. 6 is a circuit diagram of the VCO 23_1 shown in FIG.
  • the VCO 23_1 is a ring oscillator in which three differential amplifiers 23a to 23c are connected, and is strong against power supply noise.
  • a DC bias is applied to VIN_RING, which is an input to the VCO 23_1, and an output VOUT_RING having a frequency controlled by VIN_RING can be obtained.
  • the VCO 23_2 has the same configuration as the VCO 23_1.
  • FIG. 7 is a circuit diagram of the SELECTOR 24 shown in FIG.
  • the SELECTOR 24 includes a COUNTER_TEMP 24b that receives the VOSCTEMP output from the VCO 23_1 as an input.
  • the COUNTER_TEMP 24b creates and outputs eight clock signals VT0 to VT7 in which the VOSCTEMP cycle is 1 time, 2 times, 4 times, 8 times, 16 times, 32 times, 64 times, and 128 times.
  • VT0 to VT7 are input to PASSSTR_p0 to PASSSTR_p7, respectively.
  • the SELECTOR 24 has a DECODER 24a inside thereof.
  • the DECODER 24a receives VSEL 0 to 2 indicating the frequency division ratio setting value for setting the frequency division ratio from the outside. Since each of VSEL0 to VSEL2 is a 1-bit signal, one of PASSSTR_p0 to PASSSTR_p7 can be specified by 3 bits of VSEL0 to VSEL2.
  • FIG. 8 is a circuit diagram of the DECODER 24a.
  • FIG. 9 is a truth table of DECODER 24a.
  • the SELECTOR 24 can selectively output one of VT0 to VT7 by selecting PASSSTR based on the designation of VSEL0 to 2.
  • FIG. 10 is a circuit diagram of the DATPROC 25 shown in FIG.
  • the inputs to DATPROC 25 are the output VOSCREF of VCO 23_2 and the output VCOUNT of SELECTOR 24.
  • the outputs of DATPROC 25 are VJTRG and VB.
  • VDTRG is used as a trigger pulse used when the data of the output VD of the COUNTER is taken into the REGISTER 25c, and is generated by using three D-FFs 25a_1 to 3, an AND circuit and a NOR circuit. This VDTRG is generated after detecting the down edge of VCOUNT and counting is completed. Further, the count data taken into the REGISTER 25c is output as VQ.
  • VJTRG is generated using VDTRG, and is used as a trigger pulse when using final determination as to whether or not the temperature determination value is exceeded, and as a reset pulse for COUNTER_PROC 25b.
  • VJTRG is generated by the AND circuit and D-FF 25a_4 using the output of VDTRG.
  • FIG. 11 is a time chart regarding the trigger pulse and the output VJUD of the temperature detection device 2.
  • VDTRG generates a one-shot trigger pulse at the second up-edge of VOSCREF when VCOUNT is at a low level.
  • VJTRG generates a one-shot trigger pulse at the third up-edge of VOSCREF when VCOUNT is at low level. Then, in consideration of the delay until the SUBTRACTOR 26 performs arithmetic processing and outputs the result, the delay from the VDTRG generation timing to the generation of VJTRG is intentionally given.
  • FIG. 12 is a circuit diagram of COUNTER_TEMP 24b and COUNTER_PROC 25b.
  • COUNTER_TEMP 24b uses VOSCTEMP as VCK.
  • COUNTER_PROC 25b uses VCOUNTIN shown in FIG. 10 as VCK.
  • COUNTER_TEMP 24b and COUNTER_PROC 25b have 8 JK-FFs, and obtain 8 bits of outputs VCQ0 to VCQ7 of each JK-FF.
  • FIG. 13 is a circuit diagram of the REGISTER 25c shown in FIG.
  • the REGISTER 25c has 8 D-FFs, and the 8-bit output of the COUNTER_PROC 25b becomes the 8-bit input of the REGISTER 25c.
  • the D-FF CK is input as a trigger pulse used when VDTRG captures data into the D-FF.
  • the 8-bit data taken in by VDTRG becomes an 8-bit output of VQ0 to VQ7.
  • the 8-bit outputs VQ0 to VQ7 become the 8-bit inputs VB0 to VB7 to the SUBTRACTOR 26.
  • FIG. 14 is a circuit diagram of the SUBTRACTOR 26 shown in FIG.
  • the SUBTRACTOR 26 receives VSUBREF from an external input terminal, and compares the output VSUBTEMP and VSUBREF of the DATPROC 25 to obtain an output VSUB.
  • VSUBREF is a temperature judgment value indicated by 8 bits of VA0 to VA7.
  • the value of VSUBREF can be obtained in advance, for example, by simulation.
  • the SUBTRACTOR 26 has eight full adders FA0 to FA7, and subtracts 8 bits of VA0 to VA7 and 8 bits of VB0 to VB7.
  • VSUBREF is larger than the output VSUBTEMP of the DATPROC 25, indicating that the object to be measured is below the temperature determination value.
  • VSUBREF is a smaller value than VSUBTEMP, indicating that the temperature measurement object exceeds the temperature determination value.
  • the data of the signal VSUB indicating whether or not the judgment value is exceeded is taken into the D-FF 27 shown in FIG. 5 by the VJTRG and output as VJUD.
  • FIG. 15 is an explanatory diagram of the input / output relationship between the DATPROC 25 and the SUBTRACTOR 26.
  • DATPROC 25 has an 8-bit output from VB0 to VB7 and becomes an 8-bit input of SUBTRACTOR26.
  • SUBTRACTOR26 has an 8-bit input terminal from VA0 to VA7, and VA0 to VA7 correspond to each bit of VSUBREF.
  • FIG. 16 is an explanatory diagram of a scan chain that the temperature detection device 2 has.
  • the temperature detection device 2 has 11 LATCH_L1 to L10.
  • LATCH_L1 to L10 LATCH_L1 to L7 correspond to VA0 to VA7.
  • LATCH_L8 to L10 correspond to VSEL0 to VSEL2.
  • FIG. 17 is an explanatory diagram of the boundary scan for the scan chain shown in FIG. As shown in FIG. 17, the 11 flip-flops BSC0 to BSC10 of the boundary scan are connected in correspondence with LATCH_L1 to L10. Then, the value is shifted from TDI to TDO, that is, from flip-flops BSC0 to BSC10, and taken into LATCH_L0 to LATCH_L10.
  • the temperature detection method and the temperature detection method disclosed in the second embodiment can suppress the influence of process variations and power supply voltage variations and change the resolution in the same manner as the first embodiment.
  • the resolution is changed by receiving the inputs of VSEL 0 to 2 from the external system, storing them in LATCH_L 8 to L 10, and changing the division ratio based on the values of VSEL 0 to 2.
  • the temperature determination value VSUBREF is received from an external system, stored in LATCH_L0 to L7, and a comparison result VJUD between the detected temperature and the temperature determination value is output to the outside.
  • this external result for example, by the arithmetic processing unit, it is possible to stop or start the calculation based on whether or not the circuit temperature has reached or exceeded the determination value.
  • the case where there is one type of temperature determination value is illustrated.
  • a storage unit that stores a plurality of temperature determination values in the temperature detection device 2 and any one of the stored plurality of temperature determination values. You may comprise so that the selection part to select may be given.
  • FIG. 18 is a schematic configuration diagram of the information processing apparatus according to the third embodiment.
  • the LSI 3 that is the information processing apparatus shown in FIG. 18 is a large-scale integrated circuit in which the temperature detection apparatus 2 disclosed in the second embodiment and four CPU cores 31 to 34 that operate as arithmetic processing apparatuses are connected. is there.
  • the temperature inside the LSI 3 changes according to the operation status. Since the heat generated by the operation of the CPU cores 31 to 34 is dominant to the temperature of the LSI 3, it is effective to control the temperature by controlling the operation of the CPU cores 31 to 34.
  • the internal temperature of the LSI 3 can be kept optimal. .
  • the information processing device disclosed in the third embodiment controls the temperature of the LSI 3 by controlling the arithmetic processing device using the highly accurate temperature information obtained from the temperature detection device 2 capable of changing the resolution. Therefore, the reliability of the information processing apparatus can be improved.

Abstract

A clock signal (VOSCTEMP) is generated by controlling a first oscillation unit (13_1) at a temperature-dependent voltage (VREF1), and a clock signal (VOSCREF) is generated by controlling a second oscillation unit (13_2) at a temperature-independent voltage (VREF2).  A frequency division unit (14) frequency-divides the clock signal (VOSCTEMP) to obtain a clock signal (VCOUNT).  A counting unit (15) compares the clock signal (VCOUNT) and the clock signal (VOSCREF) to obtain temperature information.  The temperature detection resolution can be changed by changing the radio of frequency division by the frequency division unit (14).

Description

温度検出装置、情報処理装置および温度検出装置の制御方法Temperature detection apparatus, information processing apparatus, and control method for temperature detection apparatus
 本発明は、温度検出装置、情報処理装置および温度検出装置の制御方法に関する。 The present invention relates to a temperature detection device, an information processing device, and a temperature detection device control method.
 CPU(Central Processing Unit)などの集積回路では、集積回路自身の発熱によって生じる温度変化により、集積回路の動作に変化が生じる。そのため、集積回路の温度を測る技術が工夫されてきた。集積回路の温度を測定する温度検出装置として、従来、温度に依存しない基準クロックと、温度に依存するコントロール電圧で制御されたVCO(Voltage Controlled Oscillator)のパルス数とを比較する装置が知られている。また、他の温度検出装置として、温度に依存しない基準電圧と温度に依存する基準電圧とでそれぞれVCOを動作させ、パルスの数の差を温度の情報として得る装置が知られている。 In an integrated circuit such as a CPU (Central Processing Unit), the operation of the integrated circuit changes due to a temperature change caused by heat generation of the integrated circuit itself. Therefore, techniques for measuring the temperature of integrated circuits have been devised. As a temperature detection device for measuring the temperature of an integrated circuit, a device that compares a reference clock independent of temperature with the number of pulses of a VCO (Voltage Controlled Oscillator) controlled by a temperature-dependent control voltage has been known. Yes. As another temperature detection device, there is known a device that operates a VCO with a reference voltage that does not depend on temperature and a reference voltage that depends on temperature, and obtains a difference in the number of pulses as temperature information.
特開昭63-304499号公報JP-A 63-304499 特開平1-058124号公報Japanese Unexamined Patent Publication No. 1-058124
 しかしながら、温度に依存しない基準クロックと、温度に依存するコントロール電圧で制御されたVCOのパルス数とを比較する装置では、半導体製造プロセスによるバラツキや電源電圧の変動によってVCOの特性が温度に関係なく変動しまうという問題があった。 However, in a device that compares a reference clock that does not depend on temperature and the number of pulses of a VCO that is controlled by a control voltage that depends on temperature, the characteristics of the VCO do not depend on temperature due to variations in the semiconductor manufacturing process or fluctuations in power supply voltage. There was a problem of fluctuation.
 これに対し、1対のVCOを用いる装置では、プロセスバラツキや電源電圧の変動を相対的に相殺し、測定誤差を減らすことができる。しかし、測定精度を上げるためには少なくとも一方のVCOの発振周波数を上げるか、もしくは片方のVCOの発振周波数を下げる必要があった。ところがVCOのコントロール電圧の入力範囲には制限があるので、分解能を調整することが困難だった。 In contrast, an apparatus using a pair of VCOs can relatively cancel process variations and fluctuations in power supply voltage and reduce measurement errors. However, in order to increase the measurement accuracy, it is necessary to increase the oscillation frequency of at least one VCO or decrease the oscillation frequency of one VCO. However, since the input range of the VCO control voltage is limited, it is difficult to adjust the resolution.
 本発明は、上記に鑑みてなされたものであって、プロセスバラツキや電源電圧変動の影響を抑制し、分解能を変更することができる温度検出装置、情報処理装置および温度検出装置の制御方法を提供することを目的とする。 The present invention has been made in view of the above, and provides a temperature detection device, an information processing device, and a temperature detection device control method capable of suppressing the influence of process variations and power supply voltage fluctuations and changing the resolution. The purpose is to do.
 上述した課題を解決し、目的を達成するために、開示の温度検出装置、情報処理装置および温度検出装置の制御方法は、第1の発振部が温度に応じた第1の電圧を用いて温度に応じた周波数の第1のクロックを出力し、第2の発振部が基準電圧となる第2の電圧を用いて第2のクロックを出力し、分周部が第1のクロックを分周して第3のクロックを出力し、計数部が第2のクロックのパルス幅の期間における第3のクロックのパルス数を計数する。 In order to solve the above-described problems and achieve the object, the disclosed temperature detection apparatus, information processing apparatus, and temperature detection apparatus control method are configured such that the first oscillation unit uses the first voltage corresponding to the temperature to change the temperature. A first clock having a frequency corresponding to the output frequency is output, the second oscillation unit outputs a second clock using a second voltage as a reference voltage, and the frequency dividing unit divides the first clock. The third clock is output, and the counting unit counts the number of pulses of the third clock in the period of the pulse width of the second clock.
 開示の温度検出装置、情報処理装置および温度検出装置の制御方法は、プロセスバラツキや電源電圧変動の影響を抑制し、分解能を変更することができる温度検出装置、情報処理装置および温度検出装置の制御方法を得ることができるという効果を奏する。 The disclosed temperature detection apparatus, information processing apparatus, and control method for the temperature detection apparatus are capable of suppressing the influence of process variations and power supply voltage fluctuations and changing the resolution, and controlling the temperature detection apparatus, information processing apparatus, and temperature detection apparatus There is an effect that a method can be obtained.
図1は、実施例1にかかる温度検出装置の概要構成図である。FIG. 1 is a schematic configuration diagram of a temperature detection apparatus according to a first embodiment. 図2は、温度検出装置の第1の比較例の概要構成図である。FIG. 2 is a schematic configuration diagram of a first comparative example of the temperature detection device. 図3は、温度検出装置の第2の比較例の概要構成図である。FIG. 3 is a schematic configuration diagram of a second comparative example of the temperature detection device. 図4は、温度検出部11の構成の一例について説明する説明図である。FIG. 4 is an explanatory diagram illustrating an example of the configuration of the temperature detection unit 11. 図5は、実施例2にかかる温度検出装置の概要構成図である。FIG. 5 is a schematic configuration diagram of the temperature detection apparatus according to the second embodiment. 図6は、図5に示したVCO23_1の回路図である。FIG. 6 is a circuit diagram of the VCO 23_1 shown in FIG. 図7は、図5に示したSELECTOR24の回路図である。FIG. 7 is a circuit diagram of the SELECTOR 24 shown in FIG. 図8は、DECODER24aの回路図である。FIG. 8 is a circuit diagram of the DECODER 24a. 図9はDECODER24aの真理値表である。FIG. 9 is a truth table of the DECODER 24a. 図10は、図5に示したDATPROC25の回路図である。FIG. 10 is a circuit diagram of the DATPROC 25 shown in FIG. 図11は、トリガーパルスと温度検出装置2の出力VJUDに関するタイムチャートである。FIG. 11 is a time chart regarding the trigger pulse and the output VJUD of the temperature detection device 2. 図12は、COUNTER_TEMP24bおよびCOUNTER_PROC25bの回路図である。FIG. 12 is a circuit diagram of the COUNTER_TEMP 24b and the COUNTER_PROC 25b. 図13は、図10に示したREGISTER25cの回路図である。FIG. 13 is a circuit diagram of the REGISTER 25c shown in FIG. 図14は、図5に示したSUBTRACTOR26の回路図である。FIG. 14 is a circuit diagram of the SUBTRACTOR 26 shown in FIG. 図15は、DATPROC25とSUBTRACTOR26との間の入出力関係の説明図である。FIG. 15 is an explanatory diagram of the input / output relationship between the DATPROC 25 and the SUBTRACTOR 26. 図16は、温度検出装置2が有するスキャンチェーンの説明図である。FIG. 16 is an explanatory diagram of a scan chain included in the temperature detection device 2. 図17は、図16に示したスキャンチェーンに対するバウンダリスキャンについての説明図である。FIG. 17 is an explanatory diagram of the boundary scan for the scan chain shown in FIG. 図18は、実施例3にかかる情報処理装置の概要構成図である。FIG. 18 is a schematic configuration diagram of the information processing apparatus according to the third embodiment.
 以下に、温度検出装置、情報処理装置および温度検出装置の制御方法の実施例を図面に基づいて詳細に説明する。なお、この実施例は開示の技術を限定するものではない。 Hereinafter, embodiments of a temperature detection device, an information processing device, and a control method for the temperature detection device will be described in detail with reference to the drawings. Note that this embodiment does not limit the disclosed technology.
 図1は、実施例1にかかる温度検出装置の概要構成図である。図1に示した温度検出装置1は、温度検出部11、電源部12、第1発振部13_1、第2発振部13_2、分周部14、計数部15を有する。 FIG. 1 is a schematic configuration diagram of a temperature detection apparatus according to the first embodiment. The temperature detection device 1 illustrated in FIG. 1 includes a temperature detection unit 11, a power supply unit 12, a first oscillation unit 13_1, a second oscillation unit 13_2, a frequency division unit 14, and a counting unit 15.
 温度検出部11は、温度を検出し、検出した温度に応じた第1の電圧VREF1を出力する。電源部12は、第1の電圧の基準電圧となる第2の電圧VREF2を出力する。第1発振部13_1は、電圧VREF1を入力され、電圧VREF1に応じた周波数の第1のクロックVOSCTEMPを出力する。分周部14は、第1のクロックを分周し、第3のクロックVCOUNTを出力する。 The temperature detector 11 detects the temperature and outputs a first voltage VREF1 corresponding to the detected temperature. The power supply unit 12 outputs a second voltage VREF2 serving as a reference voltage for the first voltage. The first oscillation unit 13_1 receives the voltage VREF1 and outputs a first clock VOSCTEMP having a frequency corresponding to the voltage VREF1. The frequency divider 14 divides the first clock and outputs a third clock VCOUNT.
 第2発振部13_2は、電圧VREF2を入力され、電圧VREF2に応じた周波数の第2のクロックVOSCREFを出力する。計数部15は、第2のクロックVOSCREFと第3のクロックVCOUNTを入力され、クロックVOSCREFのパルス幅の期間におけるクロックVCOUNTのパルス数を計数し、計数結果を出力する。 The second oscillator 13_2 receives the voltage VREF2, and outputs a second clock VOSCREF having a frequency corresponding to the voltage VREF2. The counting unit 15 receives the second clock VOSCREF and the third clock VCOUNT, counts the number of pulses of the clock VCOUNT during the pulse width period of the clock VOSCREF, and outputs the counting result.
 第1発振部13_1と第2発振部13_2は、例えばVCO(Voltage Controlled Oscillator)である。この第1発振部13_1と第2発振部13_2は同じ回路特性を持たせるように同一の電源と同一のグランドに接続し、同一の回路構成とする。またチップ内でのバラツキを考慮し、第1発振部13_1と第2発振部13_2とは近接配置する。 The first oscillator 13_1 and the second oscillator 13_2 are, for example, VCO (Voltage Controlled Oscillator). The first oscillator 13_1 and the second oscillator 13_2 are connected to the same power source and the same ground so as to have the same circuit characteristics, and have the same circuit configuration. In consideration of variations in the chip, the first oscillation unit 13_1 and the second oscillation unit 13_2 are disposed close to each other.
 このため、第1発振部13_1と第2発振部13_2のバラツキや電源ノイズは相殺され、クロックVOSCREFとクロックVOSCTEMPの出力の違いは温度だけに依存する。 For this reason, variations and power supply noise between the first oscillating unit 13_1 and the second oscillating unit 13_2 are canceled out, and the difference between the outputs of the clock VOSCREF and the clock VOSCTEMP depends only on the temperature.
 またクロックVCOUNTはクロックVOSCTEMPを分周したものであるので、クロックVCOUNTはクロックVOSCTEMPに対して温度依存分と分周比分の差を有することとなる。 Since the clock VCOUNT is obtained by dividing the clock VOSCTEMP, the clock VCOUNT has a temperature-dependent difference and a division ratio difference with respect to the clock VOSCTEMP.
 そして、分周部14の分周比を変化させれば、電圧VREF1や電圧VREF2を変化させることなく分解能を調整することができる。 If the frequency division ratio of the frequency divider 14 is changed, the resolution can be adjusted without changing the voltage VREF1 or the voltage VREF2.
 具体的には、プロセスがばらついたりノイズ等で電圧が変動したりすることでVOSCREFとVOSCTEMPも変化するが、相対的な差は変わらないことから、VOSCREFとVOSCTEMPの差は温度だけに依存する。 Specifically, VOSCREF and VOSCTEMP also change due to process variations or voltage fluctuations due to noise or the like, but since the relative difference does not change, the difference between VOSCREF and VOSCTEMP depends only on temperature.
 分周部14の内部でVOSCTEMPの周波数をA倍したとすると、VCOUNTとVOSCTEMPは、
  VCOUNT=A×VOSCTEMP
として表される。
Assuming that the frequency of VOSCTEMP is multiplied by A inside the frequency divider 14, VCOUNT and VOSCTEMP are
VCOUNT = A × VOSCTEMP
Represented as:
 したがって、温度Temp1におけるVCOUNTをVCOUNT1、温度Temp2におけるVCOUNTをVCOUNT2としたときの温度差は、
  VCOUNT1-VCOUNT2=A×(VOSCTEMP1-VOSCTEMP2)
となる。この式より、VOSCTEM1とVOSCTEMP2の差が小さい場合でも、すなわち温度変化が小さい場合でもAを大きくすることで温度差を大きくすることができることがわかる。よってAを選択できることで分解能を可変させることができる。
Therefore, the temperature difference when VCOUNT at temperature Temp1 is VCOUNT1 and VCOUNT at temperature Temp2 is VCOUNT2 is:
VCOUNT1-VCOUNT2 = A × (VOSCTEMP1-VOSCTEMP2)
It becomes. From this equation, it can be seen that the temperature difference can be increased by increasing A even when the difference between VOSCTEM1 and VOSCTEMP2 is small, that is, when the temperature change is small. Therefore, the resolution can be varied by selecting A.
 図2は、温度検出装置の第1の比較例の概要構成図である。図2に示した第1の比較例では、温度に依存しない基準クロックVckを計数部15_1のCK端子に入力し、温度に依存するコントロール電圧Vtで制御された発振部13_3のパルスを計数部15_1のEN端子に入力する。計数部15_1は、基準クロックVckのHighまたはLowの間にEN端子に入力されたパルス数をカウントする。 FIG. 2 is a schematic configuration diagram of a first comparative example of the temperature detection device. In the first comparative example shown in FIG. 2, the reference clock Vck independent of temperature is input to the CK terminal of the counting unit 15_1, and the pulse of the oscillation unit 13_3 controlled by the control voltage Vt depending on temperature is counted in the counting unit 15_1. Input to the EN terminal. The counter 15_1 counts the number of pulses input to the EN terminal during the High or Low of the reference clock Vck.
 この第1の比較例では、温度検出の分解能を変化させるためには基準クロックVckとコントロール電圧Vtのいずれかを変化させることとなり、分解能の変更が困難である。また、発振部13_3のプロセスバラツキや電源電圧の変動によって発振部13_3の特性が温度に関係なく変動しまうという問題があった。 In the first comparative example, in order to change the resolution of temperature detection, either the reference clock Vck or the control voltage Vt is changed, and it is difficult to change the resolution. In addition, there is a problem that the characteristics of the oscillation unit 13_3 fluctuate regardless of temperature due to process variations of the oscillation unit 13_3 and fluctuations in the power supply voltage.
 図3は、温度検出装置の第2の比較例の概要構成図である。図3に示した第2の比較例では、温度検出部11が出力する温度依存の基準電圧をコントロール電圧として第1発振部13_1を動作させ、計数部15_2でそのパルス数をカウントする。また、電源部12が出力する温度に依存しない基準電圧をコントロール電圧として第2発振部13_2を動作させて、計数部15_3でそのパルス数をカウントする。制御部16は、計数部15_2と計数部15_3のカウント数の差が温度だけに依存することを利用して温度測定を行なう。 FIG. 3 is a schematic configuration diagram of a second comparative example of the temperature detection device. In the second comparative example shown in FIG. 3, the first oscillation unit 13_1 is operated using the temperature-dependent reference voltage output from the temperature detection unit 11 as a control voltage, and the number of pulses is counted by the counting unit 15_2. Further, the second oscillating unit 13_2 is operated with a reference voltage that does not depend on the temperature output from the power supply unit 12 as a control voltage, and the counting unit 15_3 counts the number of pulses. The control unit 16 performs temperature measurement using the fact that the difference between the count numbers of the counting unit 15_2 and the counting unit 15_3 depends only on the temperature.
 第2の比較例では、2つの発振部を用いることでプロセスバラツキや電源電圧の変動を相殺し、測定誤差を減らすことができる。しかし、測定の分解能を変化させるためには、発振部に供給する電圧を変化させることで発振周波数を変化させることとなる。発振部に供給可能な電圧の囲には制限があるので、第2の比較例では分解能を調整することが困難であった。また、分解能をあげるために発振周波数を大きくすると、消費電力が大きくなるという問題があった。 In the second comparative example, by using two oscillating units, process variations and power supply voltage fluctuations can be offset and measurement errors can be reduced. However, in order to change the measurement resolution, the oscillation frequency is changed by changing the voltage supplied to the oscillation unit. Since there is a limit to the range of voltage that can be supplied to the oscillation unit, it is difficult to adjust the resolution in the second comparative example. Further, when the oscillation frequency is increased in order to increase the resolution, there is a problem that the power consumption increases.
 第1,第2の比較例に対し、図1に開示した温度検出装置では、発振部のプロセスバラツキや電源電圧の変動を相殺し、測定誤差を減らすことができるとともに、分周比の設定によって簡易に分解能を変更することができる。また、分解能をあげるために発振部に供給する電圧を上げる必要がないので、消費電力を上げることなく分解能を向上することができる。 In contrast to the first and second comparative examples, the temperature detection device disclosed in FIG. 1 can cancel out process variations in the oscillation unit and fluctuations in the power supply voltage, reduce measurement errors, and set the division ratio. The resolution can be changed easily. In addition, since it is not necessary to increase the voltage supplied to the oscillation unit in order to increase the resolution, the resolution can be improved without increasing the power consumption.
 図4は、温度検出部11の構成の一例について説明する説明図である。図4に示した例では、温度検出部11は、電源11a、抵抗11b、ダイオード11cを直列に接続して構成し、電源11aと抵抗11bの間から電圧VREF1を得ている。ダイオード11cが温度依存性を有するので、ダイオードの出力電圧によって電圧VREF1が温度依存を持った直流電圧になる。 FIG. 4 is an explanatory diagram illustrating an example of the configuration of the temperature detection unit 11. In the example shown in FIG. 4, the temperature detector 11 is configured by connecting a power source 11a, a resistor 11b, and a diode 11c in series, and obtains a voltage VREF1 from between the power source 11a and the resistor 11b. Since the diode 11c has temperature dependency, the voltage VREF1 becomes a DC voltage having temperature dependency due to the output voltage of the diode.
 以上説明してきたように、本実施例1に開示した温度検出装置およびその制御方法では、温度依存性を有する電圧と温度依存性を持たない電圧とをそれぞれ発振部に供給する。そして温度検出装置およびその制御方法では、温度依存性を有する電圧に基づいて発振したクロック信号を分周し、温度依存性を持たない電圧に基づいて発振したクロック信号と比較して温度情報を得る。 As described above, in the temperature detection device and the control method disclosed in the first embodiment, a voltage having temperature dependency and a voltage not having temperature dependency are supplied to the oscillation unit. In the temperature detection device and its control method, the clock signal oscillated based on the voltage having temperature dependency is divided, and the temperature information is obtained by comparing with the clock signal oscillated based on the voltage not having temperature dependency. .
 そのため、本実施例1に開示した温度検出方法およびその温度検出方法では、プロセスバラツキや電源電圧変動の影響を抑制し、分解能を変更することができる温度検出装置、情報処理装置および温度検出装置の制御方法を得ることができる。 Therefore, in the temperature detection method and the temperature detection method disclosed in the first embodiment, the temperature detection device, the information processing device, and the temperature detection device that can suppress the influence of process variations and power supply voltage fluctuations and can change the resolution. A control method can be obtained.
 図5は、実施例2にかかる温度検出装置の概要構成図である。図5に示した温度検出装置2は、温度検出部11として機能するVGEN21、温度依存性を持たない定圧電源として機能するVGEN22、発振部として機能するVCO23_1,23_2、分周部として機能するSELECTOR24を有する。 FIG. 5 is a schematic configuration diagram of the temperature detection apparatus according to the second embodiment. 5 includes a VGEN 21 that functions as a temperature detection unit 11, a VGEN 22 that functions as a constant pressure power supply having no temperature dependency, VCOs 23_1 and 23_2 that function as oscillation units, and a SELECTOR 24 that functions as a frequency division unit. Have.
 したがって、VGEN21は、温度に依存する直流電圧VREF1を生成することとなる。また、VGEN22は、温度に依存しない直流電圧VREF2を生成する。このVREF1,VREF2がVCO23_1,23_2のコントロール電圧として供給される。 Therefore, the VGEN 21 generates the DC voltage VREF1 depending on the temperature. The VGEN 22 generates a DC voltage VREF2 that does not depend on temperature. These VREF1 and VREF2 are supplied as control voltages for the VCOs 23_1 and 23_2.
 さらに、温度検出装置2は、計数部として機能するDATPROC25、計数結果と所定値とを比較する比較部として機能するSUBTRACTOR26、フリップフロップ回路であるD-FF27を有する。 Furthermore, the temperature detection device 2 includes a DATPROC 25 that functions as a counting unit, a SUBTRACTOR 26 that functions as a comparison unit that compares the counting result with a predetermined value, and a D-FF 27 that is a flip-flop circuit.
 VCO23_1は温度に依存する電圧VREF1で制御される。VCO23_2は温度に依存しない電圧VREF2で制御される。また、VCO23_1の出力VOSCTEMPをSELECTOR24の入力とし、SELECTOR24の出力をVCOUNTとして得る。VCO1とVCO2は同じ回路特性を持たせるように同一の電源と同一のグランドに接続し、同一の回路構成とする。またチップ内でのバラツキを考慮し、VCO1とVCO2はレイウト上で近接に配置する。その結果、VCO23_1とVCO23_2のバラツキや電源ノイズを相殺し、VOSCREFとVOSCTEMPの違いは温度だけに依存する。 The VCO 23_1 is controlled by a temperature-dependent voltage VREF1. The VCO 23_2 is controlled by a voltage VREF2 that does not depend on temperature. Further, the output VOSCTEMP of the VCO 23_1 is input to the SELECTOR 24, and the output of the SELECTOR 24 is obtained as VCOUNT. VCO1 and VCO2 are connected to the same power source and the same ground so as to have the same circuit characteristics, and have the same circuit configuration. In consideration of variations in the chip, VCO1 and VCO2 are arranged close to each other on the layout. As a result, variations in VCO 23_1 and VCO 23_2 and power supply noise are offset, and the difference between VOSCREF and VOSCTEMP depends only on temperature.
 VCOUNTはVOSCTEMPを分周したものであるので、結果的にVOSCREFとVCOUNTの違いは温度だけに依存することとなる。したがって、温度検出装置2の分解能を調整する際はVCO23_1,2のコントロール電圧を上下することなく、SELECTOR24で調整できる。 Since VCOUNT is obtained by dividing VOSCTEMP, as a result, the difference between VOSCREF and VCOUNT depends only on temperature. Therefore, when adjusting the resolution of the temperature detecting device 2, it can be adjusted by the SELECTOR 24 without raising or lowering the control voltage of the VCOs 23_1 and V_2.
 図6は、図5に示したVCO23_1の回路図である。VCO23_1は、3つの差動アンプ23a~23cを接続したリング発振器であり、電源ノイズに強い。VCO23_1に対する入力であるVIN_RINGには直流バイアスが印加され、VIN_RINGによって周波数が制御された出力VOUT_RINGを得ることができる。なお、VCO23_2もVCO23_1と同様の構成を有する。 FIG. 6 is a circuit diagram of the VCO 23_1 shown in FIG. The VCO 23_1 is a ring oscillator in which three differential amplifiers 23a to 23c are connected, and is strong against power supply noise. A DC bias is applied to VIN_RING, which is an input to the VCO 23_1, and an output VOUT_RING having a frequency controlled by VIN_RING can be obtained. Note that the VCO 23_2 has the same configuration as the VCO 23_1.
 図7は、図5に示したSELECTOR24の回路図である。SELECTOR24は、その内部にVCO23_1から出力されたVOSCTEMPを入力として受け取るCOUNTER_TEMP24bを有する。COUNTER_TEMP24bは、VOSCTEMPの周期を1倍、2倍、4倍、8倍、16倍、32倍、64倍、128倍した8つのクロック信号VT0~VT7を作成して出力する。VT0~VT7はそれぞれPASSTR_p0~PASSTR_p7に入力される。 FIG. 7 is a circuit diagram of the SELECTOR 24 shown in FIG. The SELECTOR 24 includes a COUNTER_TEMP 24b that receives the VOSCTEMP output from the VCO 23_1 as an input. The COUNTER_TEMP 24b creates and outputs eight clock signals VT0 to VT7 in which the VOSCTEMP cycle is 1 time, 2 times, 4 times, 8 times, 16 times, 32 times, 64 times, and 128 times. VT0 to VT7 are input to PASSSTR_p0 to PASSSTR_p7, respectively.
 また、SELECTOR24は、その内部にDECODER24aを有する。DECODER24aは分周比を設定する分周比設定値を示すVSEL0~2を外部から入力される。VSEL0~2はそれぞれ1ビットの信号であるので、VSEL0~2の3ビットでPASSTR_p0~PASSTR_p7のいずれかを指定することができる。図8は、DECODER24aの回路図である。また、図9はDECODER24aの真理値表である。 Further, the SELECTOR 24 has a DECODER 24a inside thereof. The DECODER 24a receives VSEL 0 to 2 indicating the frequency division ratio setting value for setting the frequency division ratio from the outside. Since each of VSEL0 to VSEL2 is a 1-bit signal, one of PASSSTR_p0 to PASSSTR_p7 can be specified by 3 bits of VSEL0 to VSEL2. FIG. 8 is a circuit diagram of the DECODER 24a. FIG. 9 is a truth table of DECODER 24a.
 このようにSELECTOR24は、VSEL0~2の指定に基づいてPASSTRを選択することで、VT0~7のいずれかを一つを選択的に出力することができる。 Thus, the SELECTOR 24 can selectively output one of VT0 to VT7 by selecting PASSSTR based on the designation of VSEL0 to 2.
 図10は、図5に示したDATPROC25の回路図である。DATPROC25に対する入力は、VCO23_2の出力VOSCREFとSELECTOR24の出力VCOUNTである。DATPROC25の出力はVJTRGとVBである。 FIG. 10 is a circuit diagram of the DATPROC 25 shown in FIG. The inputs to DATPROC 25 are the output VOSCREF of VCO 23_2 and the output VCOUNT of SELECTOR 24. The outputs of DATPROC 25 are VJTRG and VB.
 VDTRGはCOUNTERの出力VDのデータをREGISTER25cに取り込む際に用いられるトリガーパルスとして用いられ、3つのD-FF25a_1~3とAND回路とNOR回路を用いることで生成される。このVDTRGはVCOUNTのダウンエッジを検出し、カウントが確実に終わってから生成されるものである。また、REGISTER25cに取り込まれたカウントデータはVQとして出力される。 VDTRG is used as a trigger pulse used when the data of the output VD of the COUNTER is taken into the REGISTER 25c, and is generated by using three D-FFs 25a_1 to 3, an AND circuit and a NOR circuit. This VDTRG is generated after detecting the down edge of VCOUNT and counting is completed. Further, the count data taken into the REGISTER 25c is output as VQ.
 VJTRGはVDTRGを用いて生成され、温度判定値を超えているか否かの最終判定を用いる際のトリガーパルス、COUNTER_PROC25bのリセットパルスとして用いられる。VJTRGはVDTRGの出力を用いてAND回路とD-FF25a_4で生成される。 VJTRG is generated using VDTRG, and is used as a trigger pulse when using final determination as to whether or not the temperature determination value is exceeded, and as a reset pulse for COUNTER_PROC 25b. VJTRG is generated by the AND circuit and D-FF 25a_4 using the output of VDTRG.
 図11は、トリガーパルスと温度検出装置2の出力VJUDに関するタイムチャートである。VDTRGはVCOUNTがLowレベルかつVOSCREFの2回目のアップエッジでワンショットのトリガーパルスが生成する。VJTRGはVCOUNTがLowレベルかつVOSCREFの3回目のアップエッジでワンショットのトリガーパルスを生成する。そして、SUBTRACTOR26で演算処理を行って結果を出力するまでのディレイを考慮し、VDTRG生成タイミングからVJTRGが生成されるまでのタイミングに故意にディレイを持たせている。 FIG. 11 is a time chart regarding the trigger pulse and the output VJUD of the temperature detection device 2. VDTRG generates a one-shot trigger pulse at the second up-edge of VOSCREF when VCOUNT is at a low level. VJTRG generates a one-shot trigger pulse at the third up-edge of VOSCREF when VCOUNT is at low level. Then, in consideration of the delay until the SUBTRACTOR 26 performs arithmetic processing and outputs the result, the delay from the VDTRG generation timing to the generation of VJTRG is intentionally given.
 図12は、COUNTER_TEMP24bおよびCOUNTER_PROC25bの回路図である。COUNTER_TEMP24bは、VCKとしてVOSCTEMPを用いる。COUNTER_PROC25bはVCKとして図10に示したVCOUNTINを用いる。図12に示したようにCOUNTER_TEMP24bおよびCOUNTER_PROC25bは、8個のJK-FFを有し、各JK-FFの出力VCQ0~VCQ7の8ビットを得る。 FIG. 12 is a circuit diagram of COUNTER_TEMP 24b and COUNTER_PROC 25b. COUNTER_TEMP 24b uses VOSCTEMP as VCK. COUNTER_PROC 25b uses VCOUNTIN shown in FIG. 10 as VCK. As shown in FIG. 12, COUNTER_TEMP 24b and COUNTER_PROC 25b have 8 JK-FFs, and obtain 8 bits of outputs VCQ0 to VCQ7 of each JK-FF.
 図13は、図10に示したREGISTER25cの回路図である。REGISTER25cは8個のD-FFを有し、COUNTER_PROC25bの8ビット出力がREGISTER25cの8ビット入力となる。D-FFのCKにはVDTRGがD-FFにデータを取り込む際に用いられるトリガーパルスとして入力される。VDTRGで取り込まれた8ビットのデータはVQ0~VQ7の8ビット出力となる。VQ0~VQ7の8ビットの出力は、SUBTRACTOR26に対する8ビットの入力VB0~VB7となる。 FIG. 13 is a circuit diagram of the REGISTER 25c shown in FIG. The REGISTER 25c has 8 D-FFs, and the 8-bit output of the COUNTER_PROC 25b becomes the 8-bit input of the REGISTER 25c. The D-FF CK is input as a trigger pulse used when VDTRG captures data into the D-FF. The 8-bit data taken in by VDTRG becomes an 8-bit output of VQ0 to VQ7. The 8-bit outputs VQ0 to VQ7 become the 8-bit inputs VB0 to VB7 to the SUBTRACTOR 26.
 図14は、図5に示したSUBTRACTOR26の回路図である。SUBTRACTOR26は、外部入力端子からVSUBREFを入力され、DATPROC25の出力VSUBTEMPとVSUBREFとを比較して、出力VSUBを得る。 FIG. 14 is a circuit diagram of the SUBTRACTOR 26 shown in FIG. The SUBTRACTOR 26 receives VSUBREF from an external input terminal, and compares the output VSUBTEMP and VSUBREF of the DATPROC 25 to obtain an output VSUB.
 VSUBREFは、VA0~VA7の8ビットで示される温度判定値である。VSUBREFの値は例えばシミュレーションなどによって予め求めることができる。SUBTRACTOR26は8個の全加算器FA0~FA7を有し、VA0~VA7の8ビットとVB0~VB7の8ビットの減算を行う。 VSUBREF is a temperature judgment value indicated by 8 bits of VA0 to VA7. The value of VSUBREF can be obtained in advance, for example, by simulation. The SUBTRACTOR 26 has eight full adders FA0 to FA7, and subtracts 8 bits of VA0 to VA7 and 8 bits of VB0 to VB7.
 SUBTRACTOR26の出力VSUBが0のときはVSUBREFがDATPROC25の出力VSUBTEMPよりも大きい値であり、被温度測定物が温度判定値以下であることを示している。そして、VSUBが1のときはVSUBREFがVSUBTEMPよりも小さい値であり、被温度測定物が温度判定値を超えていることを示している。 When the output VSUB of the SUBTRACTOR 26 is 0, VSUBREF is larger than the output VSUBTEMP of the DATPROC 25, indicating that the object to be measured is below the temperature determination value. When VSUB is 1, VSUBREF is a smaller value than VSUBTEMP, indicating that the temperature measurement object exceeds the temperature determination value.
 判定値を超えているか否かの示す信号VSUBのデータは、VJTRGによって図5に示したD-FF27に取り込まれ、VJUDとして出力される。 The data of the signal VSUB indicating whether or not the judgment value is exceeded is taken into the D-FF 27 shown in FIG. 5 by the VJTRG and output as VJUD.
 図15は、DATPROC25とSUBTRACTOR26との間の入出力関係の説明図である。DATPROC25はVB0~VB7までの8ビットの出力を持ち、SUBTRACTOR26の8ビット入力になる。SUBTRACTOR26はVB0~VB7以外にVA0~VA7までの8ビット入力端子を持っており、VA0~VA7はVSUBREFの各ビットに対応する。 FIG. 15 is an explanatory diagram of the input / output relationship between the DATPROC 25 and the SUBTRACTOR 26. DATPROC 25 has an 8-bit output from VB0 to VB7 and becomes an 8-bit input of SUBTRACTOR26. In addition to VB0 to VB7, SUBTRACTOR26 has an 8-bit input terminal from VA0 to VA7, and VA0 to VA7 correspond to each bit of VSUBREF.
 図16は、温度検出装置2が有するスキャンチェーンの説明図である。温度検出装置2は、11個のLATCH_L1~L10を有する。LATCH_L1~L10のうち、LATCH_L1~L7は、VA0~VA7に対応する。また、LATCH_L1~L10のうち、LATCH_L8~L10は、VSEL0~VSEL2に対応する。 FIG. 16 is an explanatory diagram of a scan chain that the temperature detection device 2 has. The temperature detection device 2 has 11 LATCH_L1 to L10. Of LATCH_L1 to L10, LATCH_L1 to L7 correspond to VA0 to VA7. Of LATCH_L1 to L10, LATCH_L8 to L10 correspond to VSEL0 to VSEL2.
 図17は、図16に示したスキャンチェーンに対するバウンダリスキャンについての説明図である。図17に示したようにバウンダリスキャンの11個のフリップフロップBSC0~BSC10はLATCH_L1~L10に対応させて接続される。そして、TDIからTDOへ、すなわちフリップフロップBSC0からBSC10へ値をシフトさせていき、LATCH_L0~LATCH_L10に取り込む。 FIG. 17 is an explanatory diagram of the boundary scan for the scan chain shown in FIG. As shown in FIG. 17, the 11 flip-flops BSC0 to BSC10 of the boundary scan are connected in correspondence with LATCH_L1 to L10. Then, the value is shifted from TDI to TDO, that is, from flip-flops BSC0 to BSC10, and taken into LATCH_L0 to LATCH_L10.
 以上説明してきたように本実施例2に開示した温度検出方法およびその温度検出方法は、実施例1と同様にプロセスバラツキや電源電圧変動の影響を抑制し、分解能を変更することができる。 As described above, the temperature detection method and the temperature detection method disclosed in the second embodiment can suppress the influence of process variations and power supply voltage variations and change the resolution in the same manner as the first embodiment.
 加えて本実施例2では、外部システムからVSEL0~2の入力を受けてLATCH_L8~L10に記憶し、VSEL0~2の値に基づいて分周比を変更することで分解能を変更している。 In addition, in the second embodiment, the resolution is changed by receiving the inputs of VSEL 0 to 2 from the external system, storing them in LATCH_L 8 to L 10, and changing the division ratio based on the values of VSEL 0 to 2.
 また、本実施例2では、外部システムから温度判定値VSUBREFの入力を受けてLATCH_L0~L7に記憶し、検出した温度と温度判定値との比較結果VJUDを外部に出力している。この外部結果を例えば演算処理装置が使用することで、回路の温度が判定値以上になったか否かに基づいて演算の停止や開始を行なうことができる。 In the second embodiment, the temperature determination value VSUBREF is received from an external system, stored in LATCH_L0 to L7, and a comparison result VJUD between the detected temperature and the temperature determination value is output to the outside. By using this external result, for example, by the arithmetic processing unit, it is possible to stop or start the calculation based on whether or not the circuit temperature has reached or exceeded the determination value.
 なお、本実施例2では、温度判定値が1種類の場合を例示したが、例えば温度検出装置2に複数の温度判定値を記憶する記憶部と、記憶した複数の温度判定値のいずれかを選択する選択部とを持たせるように構成してもよい。 In the second embodiment, the case where there is one type of temperature determination value is illustrated. However, for example, a storage unit that stores a plurality of temperature determination values in the temperature detection device 2 and any one of the stored plurality of temperature determination values. You may comprise so that the selection part to select may be given.
 図18は、実施例3にかかる情報処理装置の概要構成図である。図18に示した情報処理装置であるLSI3は、実施例2に開示した温度検出装置2と、演算処理装置として動作するである4個のCPUコア31~34とを接続した大規模集積回路である。 FIG. 18 is a schematic configuration diagram of the information processing apparatus according to the third embodiment. The LSI 3 that is the information processing apparatus shown in FIG. 18 is a large-scale integrated circuit in which the temperature detection apparatus 2 disclosed in the second embodiment and four CPU cores 31 to 34 that operate as arithmetic processing apparatuses are connected. is there.
 CPUコア31~34は適正に動作する温度範囲が存在するので、LSI3の温度を温度検出装置2から得ることで、温度異状による誤動作を防止することができる。 Since there is a temperature range in which the CPU cores 31 to 34 operate properly, by obtaining the temperature of the LSI 3 from the temperature detection device 2, it is possible to prevent malfunction due to temperature abnormality.
 また、CPUコア31~34が演算処理を行なうと、その動作状況に応じてLSI3内部の温度は変化する。CPUコア31~34の動作による発熱がLSI3の温度に対しては支配的であるので、CPUコア31~34の動作制御を行って温度調整をすることが有効である。 Further, when the CPU cores 31 to 34 perform arithmetic processing, the temperature inside the LSI 3 changes according to the operation status. Since the heat generated by the operation of the CPU cores 31 to 34 is dominant to the temperature of the LSI 3, it is effective to control the temperature by controlling the operation of the CPU cores 31 to 34.
 温度検出装置2の出力であるVJUDのアップエッジあるいはHighレベルの情報を各CPUコア31~34のクロック制御や電源電圧制御用の信号として用いることで、LSI3内部の温度を最適に保つことができる。 By using the VJUD up-edge or high-level information that is the output of the temperature detection device 2 as a signal for clock control and power supply voltage control of each of the CPU cores 31 to 34, the internal temperature of the LSI 3 can be kept optimal. .
 以上説明してきたように本実施例3に開示した情報処理装置は、分解能を変更可能な温度検出装置2から得た高精度の温度情報を用いて演算処理装置を制御することで、LSI3の温度を管理し、もって情報処理装置の信頼性向上に寄与することができる。 As described above, the information processing device disclosed in the third embodiment controls the temperature of the LSI 3 by controlling the arithmetic processing device using the highly accurate temperature information obtained from the temperature detection device 2 capable of changing the resolution. Therefore, the reliability of the information processing apparatus can be improved.
  1,2 温度検出装置
  3  LSI
 11  温度検出部
 11a 電源
 11b 抵抗
 11c ダイオード
 12  電源部
 13_1 第1発振部
 13_2 第2発振部
 13_3 発振部
 14  分周部
 15,15_1~15_3  計数部
 16  制御部
 21,22 VGEN
 23_1,23_2 VCO
 23a,23b,23c 差動アンプ
 24  SELECTOR
 24a DECODER
 24b COUNTER_TEMP
 25  DATPROC
 25a_1~4,27  D-FF
 25b COUNTER_PROC
 25c REGISTER
 26  SUBTRACTOR
 31~34 CPUコア
1, 2 Temperature detector 3 LSI
DESCRIPTION OF SYMBOLS 11 Temperature detection part 11a Power supply 11b Resistance 11c Diode 12 Power supply part 13_1 1st oscillation part 13_2 2nd oscillation part 13_3 Oscillation part 14 Dividing part 15,15_1-15_3 Counting part 16 Control part 21,22 VGEN
23_1, 23_2 VCO
23a, 23b, 23c Differential amplifier 24 SELECTOR
24a DECODER
24b COUNTER_TEMP
25 DATPROC
25a_1 ~ 4,27 D-FF
25b COUNTER_PROC
25c REGISTER
26 SUBTRACTOR
31-34 CPU core

Claims (10)

  1.  温度を検出し、前記検出した温度に応じた第1の電圧を出力する温度検出部と、
     前記第1の電圧の基準電圧となる第2の電圧を出力する電源部と、
     入力する前記第1の電圧に応じた周波数の第1のクロックを出力する第1の発振部と、
     入力する前記第2の電圧に応じた周波数の第2のクロックを出力する第2の発振部と、
     入力する前記第1のクロックを分周して第3のクロックを出力する分周部と、
     前記第2のクロックと前記第3のクロックを入力し、前記第2のクロックのパルス幅の期間における前記第3のクロックのパルス数を計数し、計数結果を出力する計数部とを有することを特徴とする温度検出装置。
    A temperature detector that detects a temperature and outputs a first voltage corresponding to the detected temperature;
    A power supply unit that outputs a second voltage serving as a reference voltage of the first voltage;
    A first oscillation unit that outputs a first clock having a frequency corresponding to the first voltage to be input;
    A second oscillation unit that outputs a second clock having a frequency corresponding to the second voltage to be input;
    A frequency divider that divides the input first clock and outputs a third clock;
    A counting unit that inputs the second clock and the third clock, counts the number of pulses of the third clock in a period of the pulse width of the second clock, and outputs a counting result; A featured temperature detection device.
  2.  前記温度検出装置は、電子装置に接続されるとともに、前記温度検出装置はさらに、
     所定値を記憶する記憶部と、
     前記計数結果と前記所定値との比較結果に基づいて、前記電子装置に通知信号を出力する比較部とを有することを特徴とする請求項1に記載の温度検出装置。
    The temperature detection device is connected to an electronic device, and the temperature detection device further includes:
    A storage unit for storing a predetermined value;
    The temperature detection device according to claim 1, further comprising: a comparison unit that outputs a notification signal to the electronic device based on a comparison result between the counting result and the predetermined value.
  3.  前記温度検出装置は、演算を行う演算処理装置に接続されるとともに、
     前記温度検出装置はさらに、
     所定値を記憶する記憶部と、
     前記計数結果と、前記所定値とを比較し、前記選択部が出力する所定値と前記計数結果との比較結果に基づいて、前記演算処理装置に通知信号を出力する比較部とを有することを特徴とする請求項1に記載の温度検出装置。
    The temperature detection device is connected to an arithmetic processing device that performs an operation,
    The temperature detecting device further includes
    A storage unit for storing a predetermined value;
    A comparison unit that compares the count result with the predetermined value and outputs a notification signal to the arithmetic processing unit based on a comparison result between the predetermined value output by the selection unit and the count result; The temperature detection device according to claim 1, wherein
  4.  前記演算処理装置は、前記比較部からの通知信号を入力した場合、演算を停止又は開始することを特徴とする請求項2又は3に記載の温度検出装置。 The temperature detection device according to claim 2 or 3, wherein the arithmetic processing device stops or starts the arithmetic operation when a notification signal from the comparison unit is input.
  5.  前記電源部は、前記第2の電圧を定電圧として出力する定電圧回路を有することを特徴とする請求項1に記載の温度検出装置。 The temperature detection device according to claim 1, wherein the power supply unit includes a constant voltage circuit that outputs the second voltage as a constant voltage.
  6.  温度を検出し、前記検出した温度に応じた第1の電圧を出力する温度検出部と、
     第2の電圧を出力する電源部と、
     前記第1の電圧を入力し、前記第1の電圧に応じた周波数の第1のクロックを出力する第1の発振部と、
     前記第2の電圧を入力し、前記第2の電圧に応じた周波数の第2のクロックを出力する第2の発振部と、
     前記第1のクロックを入力し、前記第1のクロックを分周して第3のクロックを出力する分周部と、
     前記第2のクロックと前記第3のクロックを入力し、前記第2のクロックのパルス幅の期間における前記第3のクロックのパルス数を計数し、計数結果を出力する計数部と、
     所定値を記憶する記憶部と、
     前記計数結果と前記所定値を比較し、前記所定値と前記計数結果との比較結果に基づいて、通知信号を出力する比較部と、
     演算を行うとともに、前記通知信号を入力した場合、演算を停止又は開始する演算処理装置とを有することを特徴とする情報処理装置。
    A temperature detector that detects a temperature and outputs a first voltage corresponding to the detected temperature;
    A power supply for outputting a second voltage;
    A first oscillating unit that inputs the first voltage and outputs a first clock having a frequency corresponding to the first voltage;
    A second oscillator that inputs the second voltage and outputs a second clock having a frequency corresponding to the second voltage;
    A frequency divider that inputs the first clock, divides the first clock, and outputs a third clock;
    A counting unit that inputs the second clock and the third clock, counts the number of pulses of the third clock in a period of the pulse width of the second clock, and outputs a counting result;
    A storage unit for storing a predetermined value;
    A comparison unit that compares the count result with the predetermined value and outputs a notification signal based on a comparison result between the predetermined value and the count result;
    An information processing apparatus comprising: an arithmetic processing device that performs an arithmetic operation and stops or starts the arithmetic operation when the notification signal is input.
  7.  前記情報処理装置はさらに、
     前記分周部の分周比を設定する分周比設定値を記憶する分周比記憶部と、
     前記分周比記憶部に対する前記分周比設定値の設定を制御するシステム制御装置とを有することを特徴とする請求項6に記載の情報処理装置。
    The information processing apparatus further includes:
    A frequency division ratio storage unit for storing a frequency division ratio setting value for setting a frequency division ratio of the frequency division unit;
    The information processing apparatus according to claim 6, further comprising: a system control device that controls setting of the division ratio setting value for the division ratio storage unit.
  8.  温度検出装置の制御方法において、
     第1の発振部が、温度に応じた値を有する第1の電圧に応じた周波数の第1のクロックを出力するステップと、
     第2の発振部が、電源部から入力する第2の電圧に応じた周波数の第2のクロックを出力するステップと、
     分周部が、前記第1のクロックを分周して第3のクロックを出力するステップと、
     前記温度制御装置が有する計数部が、前記第2のクロックのパルス幅の期間における前記第3のクロックのパルス数を計数し、計数結果を出力するステップを有することを特徴とする温度検出装置の制御方法。
    In the control method of the temperature detection device,
    A first oscillator that outputs a first clock having a frequency corresponding to a first voltage having a value corresponding to a temperature;
    A step of outputting a second clock having a frequency according to a second voltage input from the power supply unit by the second oscillation unit;
    A frequency divider that divides the first clock and outputs a third clock;
    The temperature detecting device includes a step of counting a number of pulses of the third clock in a period of a pulse width of the second clock, and outputting a counting result, the counting unit included in the temperature control device. Control method.
  9.  前記温度検出装置は、演算を行う演算処理装置に接続されるとともに、
     前記温度検出装置の制御方法はさらに、
     前記温度制御装置が有する比較部が、前記計数結果と記憶部に記憶された所定値を比較し、
     前記所定値と前記計数結果との比較結果に基づいて、通知信号を出力することを特徴とする請求項8に記載の温度検出装置の制御方法。
    The temperature detection device is connected to an arithmetic processing device that performs an operation,
    The method for controlling the temperature detection device further includes:
    The comparison unit included in the temperature control device compares the count result with a predetermined value stored in the storage unit,
    The temperature detection device control method according to claim 8, wherein a notification signal is output based on a comparison result between the predetermined value and the counting result.
  10.  前記演算処理装置は、前記比較部からの通知信号を入力した場合、演算を停止することを特徴とする請求項9に記載の温度検出装置の制御方法。 10. The temperature detection device control method according to claim 9, wherein the arithmetic processing device stops the arithmetic operation when a notification signal from the comparison unit is input.
PCT/JP2009/064464 2009-08-18 2009-08-18 Temperature detection device, information processing equipment and method for controlling temperature detection device WO2011021276A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022235215A1 (en) * 2021-05-07 2022-11-10 脸萌有限公司 Temperature measurement circuit and method
WO2023022022A1 (en) * 2021-08-16 2023-02-23 ローム株式会社 Semiconductor device and vehicle-mounted device
TWI841958B (en) 2022-05-04 2024-05-11 開曼群島商臉萌有限公司 Temperature measurement circuit and method

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JPH01114728A (en) * 1987-10-28 1989-05-08 Nec Corp Temperature monitoring device
JP2005215794A (en) * 2004-01-27 2005-08-11 Nec Computertechno Ltd Temperature abnormality processing method, and data processor with temperature abnormality processing function
JP2009175032A (en) * 2008-01-25 2009-08-06 Sharp Corp Temperature detection circuit and video device incorporating same

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JPH01114728A (en) * 1987-10-28 1989-05-08 Nec Corp Temperature monitoring device
JP2005215794A (en) * 2004-01-27 2005-08-11 Nec Computertechno Ltd Temperature abnormality processing method, and data processor with temperature abnormality processing function
JP2009175032A (en) * 2008-01-25 2009-08-06 Sharp Corp Temperature detection circuit and video device incorporating same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022235215A1 (en) * 2021-05-07 2022-11-10 脸萌有限公司 Temperature measurement circuit and method
WO2023022022A1 (en) * 2021-08-16 2023-02-23 ローム株式会社 Semiconductor device and vehicle-mounted device
TWI841958B (en) 2022-05-04 2024-05-11 開曼群島商臉萌有限公司 Temperature measurement circuit and method

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