WO2011014328A2 - Light-up prevention in electrostatic chucks - Google Patents

Light-up prevention in electrostatic chucks Download PDF

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Publication number
WO2011014328A2
WO2011014328A2 PCT/US2010/040284 US2010040284W WO2011014328A2 WO 2011014328 A2 WO2011014328 A2 WO 2011014328A2 US 2010040284 W US2010040284 W US 2010040284W WO 2011014328 A2 WO2011014328 A2 WO 2011014328A2
Authority
WO
WIPO (PCT)
Prior art keywords
electrostatic chuck
chuck assembly
gas distribution
layer
subterranean
Prior art date
Application number
PCT/US2010/040284
Other languages
French (fr)
Other versions
WO2011014328A3 (en
Inventor
Tom Stevenson
Daniel Byun
Saurabh Ullal
Babak Kadkhodayan
Rajinder Dhindsa
Original Assignee
Lam Research Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corporation filed Critical Lam Research Corporation
Priority to EP10804865A priority Critical patent/EP2460179A2/en
Priority to JP2012522844A priority patent/JP2013500605A/en
Priority to CN2010800327935A priority patent/CN102473672A/en
Priority to SG2012001616A priority patent/SG177584A1/en
Publication of WO2011014328A2 publication Critical patent/WO2011014328A2/en
Publication of WO2011014328A3 publication Critical patent/WO2011014328A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23Q—DETAILS, COMPONENTS, OR ACCESSORIES FOR MACHINE TOOLS, e.g. ARRANGEMENTS FOR COPYING OR CONTROLLING; MACHINE TOOLS IN GENERAL CHARACTERISED BY THE CONSTRUCTION OF PARTICULAR DETAILS OR COMPONENTS; COMBINATIONS OR ASSOCIATIONS OF METAL-WORKING MACHINES, NOT DIRECTED TO A PARTICULAR RESULT
    • B23Q3/00—Devices holding, supporting, or positioning work or tools, of a kind normally removable from the machine
    • B23Q3/15—Devices for holding work using magnetic or electric force acting directly on the work
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32532—Electrodes
    • H01J37/32541—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32532—Electrodes
    • H01J37/3255—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67109—Apparatus for thermal treatment mainly by convection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833—Details of electrostatic chucks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02N—ELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
    • H02N13/00—Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect

Definitions

  • the present disclosure relates to electrostatic chucks and, more particularly, to an electrostatic chuck designs including features that help prevent electrical arcing between the chuck assembly and the wafer being processed or plasma ignition in backside gas distribution channels.
  • Electrostatic chucks can be used to fix, clamp or otherwise handle a silicon wafer for semiconductor processing. Many electrostatic chucks are also configured to help regulate the temperature of the wafer during processing. For example, as is well documented in the art, a high thermal conductivity gas such as helium gas can circulated in an electrostatic chuck to help regulate the temperature of the wafer. More specifically, a relatively thin layer of gas at relatively low pressure can be used to sink heat from a silicon wafer during plasma-etch fabrication or other semiconductor processing steps. The relatively low pressure of the gas, which typically exerts only a few pounds of force on the wafer, permits the use of electrostatic attraction to oppose it and seal the wafer to a face of the chuck.
  • a high thermal conductivity gas such as helium gas
  • a relatively thin layer of gas at relatively low pressure can be used to sink heat from a silicon wafer during plasma-etch fabrication or other semiconductor processing steps.
  • the relatively low pressure of the gas which typically exerts only a few pounds of force on the wafer, permits the use of
  • the concepts of the present disclosure are applicable to a wide variety of electrostatic chuck configurations that would otherwise be prone to plasma arcing and backside gas ionization including, but not limited to, those illustrated in U.S. Patent Nos. 5,583,736, 5,715,132, 5,729,423, 5,742,331, 6,422,775, 6,606,234, and others.
  • the concepts of the present disclosure have been illustrated with reference to the relatively simple chuck configurations of Figs. 1 and 2 for clarity but the scope of the present disclosure should not be limited to these relatively simple configurations.
  • an electrostatic chuck assembly comprising a ceramic contact layer, a patterned bonding layer, an electrically conductive base plate, and a subterranean arc mitigation layer.
  • the ceramic contact layer and the electrically conductive base plate cooperate to define a plurality of hybrid gas distribution channels formed in a subterranean portion of the electrostatic chuck assembly.
  • Individual ones of the hybrid gas distribution channels comprise surfaces of relatively high electrical conductivity presented by the electrically conductive base plate and relatively low electrical conductivity presented by the ceramic contact layer.
  • the subterranean arc mitigation layer comprises a layer of relatively low electrical
  • a semiconductor wafer processing chamber comprising an electrostatic chuck assembly having one or more of the novel features disclosed herein.
  • Fig. 1 is a schematic illustration of an electrostatic chuck assembly according to embodiments of the present disclosure where gas distribution channel surfaces are presented by counter-bored grooves formed in a surface of an electrically conductive base plate;
  • Fig. 2 is a schematic illustration of an electrostatic chuck assembly according to embodiments of the present disclosure where gas distribution channel surfaces are presented by counter-bored grooves formed in a ceramic contact layer;
  • Fig. 3 is a schematic illustrations of an electrostatic chuck assemblies where a subterranean arc mitigation layer is limited to the hybrid gas distribution channels or regions disposed relatively adjacent thereto;
  • Fig. 4 is a schematic illustration of an electrostatic chuck assembly according to embodiments of the present disclosure where gas distribution channel surfaces of relatively low electrical conductivity are presented by one or more sidewall faces of a ceramic contact layer.
  • an electrostatic chuck assembly 10 is illustrated in the context of a non-specific semiconductor wafer processing chamber 100 comprising a processing chamber 60, a voltage source 70, and a supply of coolant gas 80.
  • the electrostatic chuck assembly 10 is positioned in the processing chamber to secure a wafer 15 for processing and comprises a ceramic contact layer 20, a patterned bonding layer 30, an electrically conductive base plate 40, and a subterranean arc mitigation layer 50.
  • the semiconductor wafer processing chamber 100 is described herein as being non-specific because it is contemplated that the concepts of the present disclosure will be applicable to a variety of types of semiconductor wafer processing chambers and should not be limited to chambers similar to that illustrated generally in Figs. 1-4.
  • the ceramic contact layer 20 and the electrically conductive base plate 40 cooperate to define a plurality of hybrid gas distribution channels 35 formed in a subterranean portion of the electrostatic chuck assembly 10.
  • the ceramic contact layer 20 also comprises a plurality of coolant ports 22 formed in the contact face 25 of the contact layer 20.
  • coolant ports 22 formed in the contact face 25 of the contact layer 20.
  • "subterranean" portions of the electrostatic chuck assembly 10 lie below the contact face 25 of the ceramic contact layer 20, between the contact face 25 and a distal portion 42 of the electrically conductive base plate 40.
  • the wafer 15 is shown to be slightly displaced from the contact face 25 but in operation, the wafer 15 will be electrostatically secured to the contact face 25.
  • the patterned bonding layer 30 is configured to secure the ceramic contact layer 20 to the electrically conductive base plate 40 and may comprise, for example, silicone, acrylic or a conventional or yet to be developed adhesive suitable for use in semiconductor wafer processing chambers. To prevent obstruction of coolant flow in the hybrid gas distribution channels 35, the patterned bonding layer 30 can be configured to comprise a pattern of voids that are aligned with the hybrid gas distribution channels 35.
  • the coolant ports 22 are in fluid communication with the hybrid gas distribution channels 35 of the electrostatic chuck assembly 10 and the hybrid gas distribution channels 35 are coupled fluidly to the coolant gas supply 80.
  • the thermally conductive coolant gas can be directed from the coolant gas supply 80 to the coolant ports 22 via the hybrid gas distribution channels 35, which may be configured to communicate with a common coolant inlet 24 and can be distributed across a coolant plane in the subterranean portion of the electrostatic chuck assembly 10.
  • Each of the hybrid gas distribution channels 35 comprise surfaces of relatively high and relatively low electrical conductivity.
  • the highly conductive channel surfaces are those presented by the electrically conductive base plate 40, which is typically aluminum or another metal suitable for use in a wafer processing chamber 100.
  • the less conductive channel surfaces are presented by the ceramic contact layer 20, which -A- is typically a ceramic dielectric like alumina, aluminum nitride or another electrically insulating dielectric suitable for use in a wafer processing chamber 100.
  • the hybrid gas distribution channels 35 can be formed in the subterranean portion of the electrostatic chuck assembly 10 by providing counter-bored grooves in a surface of the electrically conductive base plate 40, a surface of the ceramic contact layer 20, or both.
  • gas distribution channel surfaces of relatively high electrical conductivity are presented by forming counter-bored grooves in the electrically conductive base plate 40.
  • the counter-bored grooves in the base plate 40 cooperate with low conductivity gas distribution channel surfaces presented by the backside face 27 of the ceramic contact layer 20 to collectively form each hybrid gas distribution channel 35.
  • gas distribution channel surfaces of relatively low electrical conductivity are presented by forming counter-bored grooves formed in the ceramic contact layer 20.
  • the counter-bored grooves in the ceramic contact layer 20 cooperate with high conductivity gas distribution channel surfaces presented by the frontside face 45 of the electrically conductive base plate 40.
  • the coolant ports 22 are expanded in size and the gas distribution channel surfaces of relatively low electrical conductivity are presented by the sidewall faces 29 of the ceramic contact layer 20.
  • the subterranean arc mitigation layer 50 which comprises a layer of relatively low electrical conductivity, should be formed over the relatively high conductivity surfaces of the hybrid gas distribution channels 35 to help mitigate destructive arcing that can occur when electric fields in the gas distribution channels 35 reach a point where plasma is ignited in the channels 35 or when process plasma works its way into the channels 35 during wafer processing. In either case, the gas distribution channels 35 can begin to
  • the subterranean arc mitigation layer 50 which may comprise a spray-on coating of alumina or another dielectric, performs optimally if it comprises a dielectric layer that characterized by a thickness that is at least approximately 75 ⁇ m but less than
  • the subterranean arc mitigation layer 50 comprises a dielectric layer characterized by a thickness that is less than approximately 35 % of a thickness of the ceramic contact layer 20.
  • the subterranean arc mitigation layer 50 may comprise a continuous or discontinuous anodized layer or a layer of alumina, yttria, yttrium aluminum garnet, or combinations thereof. It is also contemplated that the subterranean arc mitigation layer 50 may comprise a discontinuous layer that is limited to the hybrid gas distribution channels or regions disposed relatively adjacent thereto, as is illustrated in Fig. 3.
  • the ceramic contact layer 20, which typically comprises a substantially planar contact face 25, may comprise any suitable ceramic for use in a wafer processing chamber including, for example, an alumina dielectric, an alumina and titanium dioxide dielectric, aluminum nitride, silicon nitride, silicon carbide, boron nitride, yttria, yttrium aluminate, or any combination thereof, with or without trace impurities. It is contemplated that the ceramic contact layer may further comprise a sintering aid, a bonding agent, a corrosion resistant coating, a mechanically conformal coating, or combinations thereof.
  • the electrically conductive base plate may comprise any suitable electrically conductive material for use in a wafer processing chamber including, for example, an electrically conductive aluminum pedestal of substantially uniform composition.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
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Abstract

An electrostatic chuck assembly is provided comprising a ceramic contact layer, a patterned bonding layer, an electrically conductive base plate, and a subterranean arc mitigation layer. The ceramic contact layer and the electrically conductive base plate cooperate to define a plurality of hybrid gas distribution channels formed in a subterranean portion of the electrostatic chuck assembly. Individual ones of the hybrid gas distribution channels comprise surfaces of relatively high electrical conductivity presented by the electrically conductive base plate and relatively low electrical conductivity presented by the ceramic contact layer. The subterranean arc mitigation layer comprises a layer of relatively low electrical conductivity and is formed over the relatively high conductivity surfaces of the hybrid gas distribution channels in the subterranean portion of the electrostatic chuck assembly. Semiconductor wafer processing chambers are also provided.

Description

LIGHT-UP PREVENTION IN ELECTROSTATIC CHUCKS
The present disclosure relates to electrostatic chucks and, more particularly, to an electrostatic chuck designs including features that help prevent electrical arcing between the chuck assembly and the wafer being processed or plasma ignition in backside gas distribution channels.
Electrostatic chucks can be used to fix, clamp or otherwise handle a silicon wafer for semiconductor processing. Many electrostatic chucks are also configured to help regulate the temperature of the wafer during processing. For example, as is well documented in the art, a high thermal conductivity gas such as helium gas can circulated in an electrostatic chuck to help regulate the temperature of the wafer. More specifically, a relatively thin layer of gas at relatively low pressure can be used to sink heat from a silicon wafer during plasma-etch fabrication or other semiconductor processing steps. The relatively low pressure of the gas, which typically exerts only a few pounds of force on the wafer, permits the use of electrostatic attraction to oppose it and seal the wafer to a face of the chuck.
As will be appreciated by those practicing the present invention, the concepts of the present disclosure are applicable to a wide variety of electrostatic chuck configurations that would otherwise be prone to plasma arcing and backside gas ionization including, but not limited to, those illustrated in U.S. Patent Nos. 5,583,736, 5,715,132, 5,729,423, 5,742,331, 6,422,775, 6,606,234, and others. The concepts of the present disclosure have been illustrated with reference to the relatively simple chuck configurations of Figs. 1 and 2 for clarity but the scope of the present disclosure should not be limited to these relatively simple configurations.
In accordance with one embodiment of the present disclosure, an electrostatic chuck assembly is provided comprising a ceramic contact layer, a patterned bonding layer, an electrically conductive base plate, and a subterranean arc mitigation layer. The ceramic contact layer and the electrically conductive base plate cooperate to define a plurality of hybrid gas distribution channels formed in a subterranean portion of the electrostatic chuck assembly. Individual ones of the hybrid gas distribution channels comprise surfaces of relatively high electrical conductivity presented by the electrically conductive base plate and relatively low electrical conductivity presented by the ceramic contact layer. The subterranean arc mitigation layer comprises a layer of relatively low electrical
conductivity and is formed over the relatively high conductivity surfaces of the hybrid gas distribution channels in the subterranean portion of the electrostatic chuck assembly.
In accordance with another embodiment of the present disclosure, a semiconductor wafer processing chamber is provided comprising an electrostatic chuck assembly having one or more of the novel features disclosed herein.
The following detailed description of specific embodiments of the present disclosure can be best understood when read in conjunction with the following drawings, where like structure is indicated with like reference numerals and in which:
Fig. 1 is a schematic illustration of an electrostatic chuck assembly according to embodiments of the present disclosure where gas distribution channel surfaces are presented by counter-bored grooves formed in a surface of an electrically conductive base plate;
Fig. 2 is a schematic illustration of an electrostatic chuck assembly according to embodiments of the present disclosure where gas distribution channel surfaces are presented by counter-bored grooves formed in a ceramic contact layer;
Fig. 3 is a schematic illustrations of an electrostatic chuck assemblies where a subterranean arc mitigation layer is limited to the hybrid gas distribution channels or regions disposed relatively adjacent thereto; and
Fig. 4 is a schematic illustration of an electrostatic chuck assembly according to embodiments of the present disclosure where gas distribution channel surfaces of relatively low electrical conductivity are presented by one or more sidewall faces of a ceramic contact layer.
Referring initially to Fig. 1, an electrostatic chuck assembly 10 is illustrated in the context of a non-specific semiconductor wafer processing chamber 100 comprising a processing chamber 60, a voltage source 70, and a supply of coolant gas 80. The electrostatic chuck assembly 10 is positioned in the processing chamber to secure a wafer 15 for processing and comprises a ceramic contact layer 20, a patterned bonding layer 30, an electrically conductive base plate 40, and a subterranean arc mitigation layer 50. The semiconductor wafer processing chamber 100 is described herein as being non-specific because it is contemplated that the concepts of the present disclosure will be applicable to a variety of types of semiconductor wafer processing chambers and should not be limited to chambers similar to that illustrated generally in Figs. 1-4.
The ceramic contact layer 20 and the electrically conductive base plate 40 cooperate to define a plurality of hybrid gas distribution channels 35 formed in a subterranean portion of the electrostatic chuck assembly 10. The ceramic contact layer 20 also comprises a plurality of coolant ports 22 formed in the contact face 25 of the contact layer 20. For the purposes of describing and defining the present invention, it is noted that "subterranean" portions of the electrostatic chuck assembly 10 lie below the contact face 25 of the ceramic contact layer 20, between the contact face 25 and a distal portion 42 of the electrically conductive base plate 40. For illustrative purposes, the wafer 15 is shown to be slightly displaced from the contact face 25 but in operation, the wafer 15 will be electrostatically secured to the contact face 25.
The patterned bonding layer 30 is configured to secure the ceramic contact layer 20 to the electrically conductive base plate 40 and may comprise, for example, silicone, acrylic or a conventional or yet to be developed adhesive suitable for use in semiconductor wafer processing chambers. To prevent obstruction of coolant flow in the hybrid gas distribution channels 35, the patterned bonding layer 30 can be configured to comprise a pattern of voids that are aligned with the hybrid gas distribution channels 35.
The coolant ports 22 are in fluid communication with the hybrid gas distribution channels 35 of the electrostatic chuck assembly 10 and the hybrid gas distribution channels 35 are coupled fluidly to the coolant gas supply 80. As such, the thermally conductive coolant gas can be directed from the coolant gas supply 80 to the coolant ports 22 via the hybrid gas distribution channels 35, which may be configured to communicate with a common coolant inlet 24 and can be distributed across a coolant plane in the subterranean portion of the electrostatic chuck assembly 10.
Each of the hybrid gas distribution channels 35 comprise surfaces of relatively high and relatively low electrical conductivity. Specifically, the highly conductive channel surfaces are those presented by the electrically conductive base plate 40, which is typically aluminum or another metal suitable for use in a wafer processing chamber 100. The less conductive channel surfaces are presented by the ceramic contact layer 20, which -A- is typically a ceramic dielectric like alumina, aluminum nitride or another electrically insulating dielectric suitable for use in a wafer processing chamber 100.
It is contemplated that the hybrid gas distribution channels 35 can be formed in the subterranean portion of the electrostatic chuck assembly 10 by providing counter-bored grooves in a surface of the electrically conductive base plate 40, a surface of the ceramic contact layer 20, or both. For example, in Fig. 1, gas distribution channel surfaces of relatively high electrical conductivity are presented by forming counter-bored grooves in the electrically conductive base plate 40. The counter-bored grooves in the base plate 40 cooperate with low conductivity gas distribution channel surfaces presented by the backside face 27 of the ceramic contact layer 20 to collectively form each hybrid gas distribution channel 35. In Fig. 2, gas distribution channel surfaces of relatively low electrical conductivity are presented by forming counter-bored grooves formed in the ceramic contact layer 20. The counter-bored grooves in the ceramic contact layer 20 cooperate with high conductivity gas distribution channel surfaces presented by the frontside face 45 of the electrically conductive base plate 40. In Fig. 4, the coolant ports 22 are expanded in size and the gas distribution channel surfaces of relatively low electrical conductivity are presented by the sidewall faces 29 of the ceramic contact layer 20.
Regardless of the manner in which the hybrid gas distribution channels 35 are formed, the subterranean arc mitigation layer 50, which comprises a layer of relatively low electrical conductivity, should be formed over the relatively high conductivity surfaces of the hybrid gas distribution channels 35 to help mitigate destructive arcing that can occur when electric fields in the gas distribution channels 35 reach a point where plasma is ignited in the channels 35 or when process plasma works its way into the channels 35 during wafer processing. In either case, the gas distribution channels 35 can begin to
"glow," creating a low impedance path for electrical arcing between the conductive base plate 40 and the wafer 15. In the context of plasma etch chambers utilizing He cooling gas, this phenomenon is generally referred to as He hole light-up.
The subterranean arc mitigation layer 50, which may comprise a spray-on coating of alumina or another dielectric, performs optimally if it comprises a dielectric layer that characterized by a thickness that is at least approximately 75 μm but less than
approximately 350 μm, although a variety of workable thicknesses are contemplated outside of this range. Typically, the subterranean arc mitigation layer 50 comprises a dielectric layer characterized by a thickness that is less than approximately 35 % of a thickness of the ceramic contact layer 20. In addition to alumina, it is contemplated that the subterranean arc mitigation layer 50 may comprise a continuous or discontinuous anodized layer or a layer of alumina, yttria, yttrium aluminum garnet, or combinations thereof. It is also contemplated that the subterranean arc mitigation layer 50 may comprise a discontinuous layer that is limited to the hybrid gas distribution channels or regions disposed relatively adjacent thereto, as is illustrated in Fig. 3.
The ceramic contact layer 20, which typically comprises a substantially planar contact face 25, may comprise any suitable ceramic for use in a wafer processing chamber including, for example, an alumina dielectric, an alumina and titanium dioxide dielectric, aluminum nitride, silicon nitride, silicon carbide, boron nitride, yttria, yttrium aluminate, or any combination thereof, with or without trace impurities. It is contemplated that the ceramic contact layer may further comprise a sintering aid, a bonding agent, a corrosion resistant coating, a mechanically conformal coating, or combinations thereof. Similarly, the electrically conductive base plate may comprise any suitable electrically conductive material for use in a wafer processing chamber including, for example, an electrically conductive aluminum pedestal of substantially uniform composition.
It is noted that recitations herein of a component of the present disclosure being "configured" in a particular way, to embody a particular property, or function in a particular manner, are structural recitations, as opposed to recitations of intended use. More specifically, the references herein to the manner in which a component is
"configured" denotes an existing physical condition of the component and, as such, is to be taken as a definite recitation of the structural characteristics of the component.
It is noted that terms like "preferably," "commonly," and "typically," when utilized herein, are not utilized to limit the scope of the claimed invention or to imply that certain features are critical, essential, or even important to the structure or function of the claimed invention. Rather, these terms are merely intended to identify particular aspects of an embodiment of the present disclosure or to emphasize alternative or additional features that may or may not be utilized in a particular embodiment of the present disclosure.
For the purposes of describing and defining the present invention it is noted that the terms "substantially" and "approximately" are utilized herein to represent the inherent degree of uncertainty that may be attributed to any quantitative comparison, value, measurement, or other representation. The terms "substantially" and "approximately" are also utilized herein to represent the degree by which a quantitative representation may vary from a stated reference without resulting in a change in the basic function of the subject matter at issue.
Having described the subject matter of the present disclosure in detail and by reference to specific embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims. More specifically, although some aspects of the present disclosure are identified herein as preferred or particularly advantageous, it is contemplated that the present disclosure is not necessarily limited to these aspects.
It is noted that one or more of the following claims utilize the term "wherein" as a transitional phrase. For the purposes of defining the present invention, it is noted that this term is introduced in the claims as an open-ended transitional phrase that is used to introduce a recitation of a series of characteristics of the structure and should be interpreted in like manner as the more commonly used open-ended preamble term
"comprising."

Claims

1. An electrostatic chuck assembly comprising a ceramic contact layer, a patterned bonding layer, an electrically conductive base plate, and a subterranean arc mitigation layer, wherein:
the patterned bonding layer is configured to secure the ceramic contact layer to the electrically conductive base plate;
the ceramic contact layer and the electrically conductive base plate cooperate to define a plurality of hybrid gas distribution channels formed in a subterranean portion of the electrostatic chuck assembly;
the ceramic contact layer comprises a contact face and a plurality of coolant ports formed in the contact face of the ceramic contact layer;
the coolant ports are in fluid communication with the hybrid gas distribution channels of the electrostatic chuck assembly;
individual ones of the hybrid gas distribution channels comprise surfaces of relatively high electrical conductivity presented by the electrically conductive base plate and relatively low electrical conductivity presented by the ceramic contact layer; and the subterranean arc mitigation layer comprises a layer of relatively low electrical conductivity and is formed over the relatively high conductivity surfaces of the hybrid gas distribution channels in the subterranean portion of the electrostatic chuck assembly.
2. An electrostatic chuck assembly as claimed in claim 1 wherein the subterranean arc mitigation layer comprises a dielectric layer characterized by a thickness that is at least approximately 75 μm but less than approximately 350 μm.
3. An electrostatic chuck assembly as claimed in claim 1 wherein the subterranean arc mitigation layer comprises a dielectric layer characterized by a thickness that is less than approximately 35 % of a thickness of the ceramic contact layer.
4. An electrostatic chuck assembly as claimed in claim 1 wherein the subterranean arc mitigation layer comprises a spray-on dielectric coating.
5. An electrostatic chuck assembly as claimed in claim 1 wherein the subterranean arc mitigation layer comprises a spray-on alumina coating.
6. An electrostatic chuck assembly as claimed in claim 1 wherein the subterranean arc mitigation layer comprises a spray-on alumina dielectric layer characterized by a thickness less than approximately 350 μm.
7. An electrostatic chuck assembly as claimed in claim 1 wherein the subterranean arc mitigation layer comprises a continuous or discontinuous anodized layer or a layer of alumina, Yttria, YAG, or combinations thereof.
8. An electrostatic chuck assembly as claimed in claim 1 wherein the subterranean arc mitigation layer comprises a discontinuous layer comprising portions of relatively low conductivity material limited to the hybrid gas distribution channels or regions disposed relatively adjacent thereto.
9. An electrostatic chuck assembly as claimed in claim 1 wherein the hybrid gas distribution channels formed in the subterranean portion of the electrostatic chuck assembly comprise counter-bored grooves formed in a surface of the electrically conductive base plate, a surface of the ceramic contact layer, or both.
10. An electrostatic chuck assembly as claimed in claim 1 wherein gas distribution channel surfaces of relatively high electrical conductivity are presented by counter-bored grooves formed in a surface of the electrically conductive base plate.
11. An electrostatic chuck assembly as claimed in claim 10 wherein gas distribution channel surfaces of relatively low electrical conductivity are presented by a backside face of the ceramic contact layer.
12. An electrostatic chuck assembly as claimed in claim 10 wherein gas distribution channel surfaces of relatively low electrical conductivity are presented by one or more sidewall faces of the ceramic contact layer.
13. An electrostatic chuck assembly as claimed in claim 1 wherein gas distribution channel surfaces of relatively low electrical conductivity are presented by counter-bored grooves formed in the ceramic contact layer.
14. An electrostatic chuck assembly as claimed in claim 13 wherein gas distribution channel surfaces of relatively high electrical conductivity are presented by a frontside face of the electrically conductive base plate.
15. An electrostatic chuck assembly as claimed in claim 1 wherein the ceramic contact layer comprises an alumina dielectric, an alumina and titanium dioxide dielectric, aluminum nitride, silicon nitride, silicon carbide, boron nitride, yttria, yttrium aluminate, or any combination thereof, with or without trace impurities.
16. An electrostatic chuck assembly as claimed in claim 1 wherein the patterned bonding layer comprises a pattern of voids aligned with the hybrid gas distribution channels.
17. An electrostatic chuck assembly as claimed in claim 1 wherein the patterned bonding layer comprises silicone.
18. An electrostatic chuck assembly as claimed in claim 1 wherein the patterned bonding layer comprises an adhesive.
19. An electrostatic chuck assembly comprising a ceramic contact layer, a silicone patterned bonding layer, an electrically conductive base plate, and a subterranean arc mitigation layer, wherein:
the patterned bonding layer is configured to secure the ceramic contact layer to the electrically conductive base plate;
the ceramic contact layer and the electrically conductive base plate cooperate to define a plurality of hybrid gas distribution channels formed in a subterranean portion of the electrostatic chuck assembly; the hybrid gas distribution channels comprise counter-bored grooves formed in a surface of the electrically conductive base plate, a surface of the ceramic contact layer, or both;
the ceramic contact layer comprises a contact face and a plurality of coolant ports formed in the contact face of the ceramic contact layer;
the coolant ports are in fluid communication with the hybrid gas distribution channels of the electrostatic chuck assembly;
individual ones of the hybrid gas distribution channels comprise surfaces of relatively high electrical conductivity presented by the electrically conductive base plate and relatively low electrical conductivity presented by the ceramic contact layer;
the subterranean arc mitigation layer comprises a spray-on alumina dielectric layer characterized by a thickness less than approximately 350 μm formed over the relatively high conductivity surfaces of the hybrid gas distribution channels in the subterranean portion of the electrostatic chuck assembly.
20. A semiconductor wafer processing chamber comprising an electrostatic chuck assembly, a processing chamber, a voltage source, and a supply of coolant gas, wherein: the electrostatic chuck assembly is positioned in the processing chamber and comprises a ceramic contact layer, a patterned bonding layer, an electrically conductive base plate, and a subterranean arc mitigation layer;
the voltage source is coupled electrically to the electrically conductive base plate; the patterned bonding layer is configured to secure the ceramic contact layer to the electrically conductive base plate;
the ceramic contact layer and the electrically conductive base plate cooperate to define a plurality of hybrid gas distribution channels formed in a subterranean portion of the electrostatic chuck assembly;
the supply of coolant gas is coupled fluidly to the hybrid gas distribution channels; the ceramic contact layer comprises a contact face and a plurality of coolant ports formed in the contact face of the ceramic contact layer;
the coolant ports are in fluid communication with the hybrid gas distribution channels of the electrostatic chuck assembly; individual ones of the hybrid gas distribution channels comprise surfaces of relatively high electrical conductivity presented by the electrically conductive base plate and relatively low electrical conductivity presented by the ceramic contact layer; and the subterranean arc mitigation layer comprises a layer of relatively low electrical conductivity and is formed over the relatively high conductivity surfaces of the hybrid gas distribution channels in the subterranean portion of the electrostatic chuck assembly.
PCT/US2010/040284 2009-07-30 2010-06-29 Light-up prevention in electrostatic chucks WO2011014328A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP10804865A EP2460179A2 (en) 2009-07-30 2010-06-29 Light-up prevention in electrostatic chucks
JP2012522844A JP2013500605A (en) 2009-07-30 2010-06-29 Ignition prevention in electrostatic chuck
CN2010800327935A CN102473672A (en) 2009-07-30 2010-06-29 Light-up prevention in electrostatic chucks
SG2012001616A SG177584A1 (en) 2009-07-30 2010-06-29 Light-up prevention in electrostatic chucks

Applications Claiming Priority (2)

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US12/512,520 2009-07-30
US12/512,520 US20110024049A1 (en) 2009-07-30 2009-07-30 Light-up prevention in electrostatic chucks

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WO2011014328A2 true WO2011014328A2 (en) 2011-02-03
WO2011014328A3 WO2011014328A3 (en) 2011-05-05

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EP (1) EP2460179A2 (en)
JP (1) JP2013500605A (en)
KR (1) KR20120048578A (en)
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SG (2) SG10201404264RA (en)
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Publication number Publication date
WO2011014328A3 (en) 2011-05-05
EP2460179A4 (en) 2012-06-06
TW201118979A (en) 2011-06-01
CN102473672A (en) 2012-05-23
SG177584A1 (en) 2012-02-28
EP2460179A2 (en) 2012-06-06
SG10201404264RA (en) 2014-10-30
US20110024049A1 (en) 2011-02-03
JP2013500605A (en) 2013-01-07
KR20120048578A (en) 2012-05-15

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