WO2011013407A1 - Matrix substrate, method for manufacturing same, and display device - Google Patents

Matrix substrate, method for manufacturing same, and display device Download PDF

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Publication number
WO2011013407A1
WO2011013407A1 PCT/JP2010/055868 JP2010055868W WO2011013407A1 WO 2011013407 A1 WO2011013407 A1 WO 2011013407A1 JP 2010055868 W JP2010055868 W JP 2010055868W WO 2011013407 A1 WO2011013407 A1 WO 2011013407A1
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Prior art keywords
conductive film
film
insulating film
contact region
resist
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PCT/JP2010/055868
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French (fr)
Japanese (ja)
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沖　一郎
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シャープ株式会社
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Publication of WO2011013407A1 publication Critical patent/WO2011013407A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present invention relates to a matrix substrate, a display device using the matrix substrate, and a method for manufacturing the matrix substrate, and more particularly to a matrix substrate suitably used for a display device such as a liquid crystal display device and a method for manufacturing the matrix substrate.
  • a liquid crystal display device that performs display by sandwiching a liquid crystal between a pair of opposing substrates and applying a voltage between electrodes of the substrate is known.
  • an active matrix liquid crystal display device configured to drive a plurality of liquid crystal cells using a matrix substrate provided with a thin film transistor (TFT) as a switching element on one substrate is widely used.
  • a matrix substrate of an active matrix liquid crystal display device has a plurality of signal lines and scanning lines arranged in a lattice pattern on the surface of a transparent insulating substrate such as a glass plate, and amorphous silicon is provided for each pixel serving as a display unit.
  • a TFT active matrix circuit including a TFT made of a semiconductor thin film such as the above is formed.
  • a TFT active matrix circuit includes a plurality of steps of forming a thin film layer on the entire surface of the substrate, forming a resist pattern on the thin film layer using a photomask, and then patterning the thin film layer by etching or the like. It is formed by a so-called photolithography method that is repeated several times.
  • the manufacturing method of the matrix substrate described in Patent Document 1 is as follows. First, as shown in FIG. 20A, a gate electrode film 102 is formed on the entire surface of the glass substrate 101. Next, a resist layer is applied over the gate electrode film 102, and exposure and development are performed using a photomask (first mask: not shown) to form a resist pattern 103. Etching is performed using the resist pattern 103 to form a patterned gate electrode film 102 [see FIG.
  • a gate insulating film 104, an amorphous silicon (a-Si) layer 105, and an n + a-Si layer 106 are continuously formed on the entire surface, and a source / drain electrode film 107 is further laminated.
  • a resist layer is applied to the surface of the laminated film, and the exposure amount is adjusted using a halftone mask (second mask: not shown), and exposure and development are performed. And a portion of the source / drain electrode, a-Si layer, and n + a-Si layer that are not covered with the resist pattern 108 are removed (see FIG. 4C).
  • the resist pattern 108 is not formed in the pixel portion and the terminal portion, the channel portion of the TFT element portion is formed as the thin portion 108a, and the other portions are formed thick.
  • the thickness of the remaining resist pattern 108 is reduced by ashing, and the surface of the source / drain electrode film is exposed at the position of the channel portion 105a corresponding to the thin portion 108a.
  • source / drain electrode separation and channel etching are performed, and then the resist pattern 108 is removed [see FIG. In the channel portion 105a, the n + a-Si layer 106 and the source / drain electrode film 107 are removed, and the thickness of the a-Si layer 105 is adjusted.
  • a passivation film 109 and a photosensitive acrylic resin film 110 with a flattened surface are sequentially formed on the entire surface of the substrate 1.
  • a photoresist is applied to the entire surface of the acrylic resin film 110, exposed and developed using a slit mask or the like as the third photomask, and two kinds of thicknesses are obtained.
  • a resist layer 111 made of a resist pattern having the above is formed. In the resist layer 111, a portion corresponding to a region where the pixel electrode is formed becomes a thin portion 111a, a contact hole position 111b becomes an unformed portion, and the other portion is formed as a thick portion.
  • the photosensitive acrylic resin film 110 when the photosensitive acrylic resin film 110 is exposed, the exposed portion of the photosensitive acrylic resin film 110 not masked by the resist layer 111 is decomposed, and the source / drain electrode film 107 or the gate electrode A contact hole 114 that penetrates to the film 102 is formed.
  • the overall thickness of the resist layer 111 is reduced by ashing. Ashing is performed until the resist layer in the thin-walled portion 111a is removed.
  • a transparent conductive film 112 is formed on the entire surface as shown in FIG.
  • the transparent conductive film 112 on the resist layer 111 is removed together with the resist layer 111, and the pixel portion 112a and the contact hole portion 112b.
  • the transparent conductive film remains.
  • the method described in Patent Document 1 is a method of patterning a transparent conductive film, and forming a pixel electrode by utilizing the fact that a transparent conductive film is not formed in a portion where a resist layer is lifted off. It is a method of forming.
  • the manufacturing method of the matrix substrate described in Patent Document 2 is as follows. As in the above-mentioned Patent Document 1, first, the steps shown in FIGS. 20A to 20E are performed to form a photosensitive acrylic resin film 110 on the surface of the substrate 1 provided with each layer. Next, as shown in FIG. 22 (k), a photoresist is applied to the entire surface of the acrylic resin film 110, and exposed and developed using a halftone mask (third mask: not shown). A resist layer 111 patterned to a stepped thickness is formed. In the resist layer 111, pixel portions and terminal portions where contact holes are formed are not formed, other pixel portion regions are formed as thick portions 111c, and other portions where no contact holes or pixel electrodes are formed are formed as thin portions 111d. To do.
  • the exposed acrylic resin film as a contact hole is removed and a through hole 114 is formed.
  • the through hole 114 is formed as a contact hole reaching the source / drain electrode film.
  • a coating-type transparent conductive film is applied to the surface by spin coating, the surface of the acrylic resin film 110 in a portion where water repellency is not imparted (portion other than the plasma treatment region) as shown in FIG.
  • the inside of the contact hole 114 is covered with the coating type transparent conductive film 115, and the pixel electrode is formed in a predetermined pattern.
  • the method of Patent Document 2 is a method of patterning a transparent conductive film, and forming a pixel electrode by utilizing the fact that the transparent conductive film 115 is not formed in the water-repellent portion 113. It is a method of forming.
  • a method for patterning the transparent conductive film using a phase shift mask is known (for example, see Patent Document 3).
  • a transparent conductive film is patterned on the surface of the acrylic resin film 110 from the state where the acrylic resin film 110 is formed on the surface of the substrate 101 shown in FIG.
  • the photosensitive acrylic resin film 120 on the surface is exposed using a phase shift mask (not shown).
  • a portion corresponding to the contact hole formation region is a transmission portion, so that a pattern of the contact hole 121 is formed.
  • the groove 120a that is perpendicular to the photosensitive acrylic resin film of the corresponding portion is patterned when exposure is performed. .
  • a transparent conductive film 122 is formed on the entire surface of the photosensitive acrylic resin film 120 by sputtering or the like, the transparent conductive film 122a in a portion where the groove 120a near vertical is patterned.
  • the transparent conductive film 122 is electrically separated by the groove 120a.
  • a transparent conductive film may be formed even in a water-repellent region when the pixel electrode is formed in a predetermined pattern. There is a problem in that it is not easy to reliably form the pattern of the pixel electrode, and the process controllability is poor.
  • Patent Document 3 has a problem in that since the width of the groove serving as a pattern boundary is narrow, the conductive film may not be completely divided at the groove portion, and there is a possibility of short-circuiting at that portion. there were. If the transparent conductive film is short-circuited at the groove portion, the transparent conductive film cannot be formed in a predetermined pixel pattern, and there is a problem that process controllability is poor.
  • An object of the present invention is to provide a matrix substrate, a display element, and a method for manufacturing a matrix substrate that can be formed, reduce generation of particles in the manufacturing process, improve product yield, and have excellent process controllability.
  • the matrix substrate of the present invention is A substrate; a matrix circuit having a plurality of switching elements provided on the substrate; an insulating film formed on a surface of the matrix circuit; a conductive film formed on the surface of the insulating film; In a matrix substrate comprising a film and a contact hole formed to electrically connect the matrix circuit,
  • the surface of the insulating film includes a contact region in which the conductive film is electrically connected to the matrix circuit and a non-contact region in which the conductive film is not electrically connected to the matrix circuit.
  • the non-contact area is divided by the partition,
  • the partition is configured as a step difference in height between the contact region and the non-contact region, and the contact region and the non-contact region of the conductive film are electrically separated using the step of the partition.
  • the gist of the display device of the present invention is that it includes the matrix substrate.
  • the method for manufacturing the matrix substrate of the present invention includes: A substrate; a matrix circuit having a plurality of switching elements provided on the substrate; an insulating film formed on a surface of the matrix circuit; a conductive film formed on the surface of the insulating film; In a method of manufacturing a matrix substrate comprising a film and a contact hole formed to electrically connect the matrix circuit, When forming the insulating film, there is a partition section that partitions a contact region in which the conductive film is electrically connected to the matrix circuit and a non-contact region in which the conductive film is not electrically connected to the matrix circuit.
  • the matrix substrate of the present invention has the following effects.
  • the surface of the insulating film includes a contact region in which the conductive film is electrically connected to the matrix circuit and a non-contact region in which the conductive film is not electrically connected to the matrix circuit.
  • the non-contact region is divided by a partition portion, and the partition portion is configured as a step difference in height between the contact region and the non-contact region, and the contact region of the conductive film is not contacted with the step portion of the partition portion.
  • the matrix substrate of the present invention has a non-contact region having water repellency, and the conductive region is not formed in the contact region. Since the boundary between and can be reliably divided by using a step, the conductive film can be reliably formed in a predetermined pattern, and the process controllability of manufacturing is good.
  • the matrix substrate of the present invention electrically separates the contact area and the non-contact area of the conductive film by using a step, the entire conductive film in the non-contact area is completely separated as in the conventional lift-off method. Since it is not necessary to remove the conductive film in the non-contact region, there is no possibility that a large amount of particles are generated unlike when the conductive film in the non-contact region is removed by the lift-off method. Therefore, the generated particles do not adhere to the substrate and the yield does not decrease, and the productivity of the matrix substrate is excellent.
  • the method for manufacturing a matrix substrate of the present invention when forming the insulating film, a contact region in which the conductive film is electrically connected to the matrix circuit and the conductive film are not electrically connected to the matrix circuit.
  • the insulating film is formed such that a partition portion that divides the non-contact region is a step, and an insulating film forming step of providing a contact hole in the insulating film, and when forming the conductive film, A conductive film forming step of forming a conductive film so that the contact region and the non-contact region are electrically separated using a step of the partition portion, whereby the predetermined conductive film pattern is formed.
  • the matrix substrate can be manufactured easily and reliably.
  • the method for manufacturing a matrix substrate of the present invention can reduce the generation of particles in the manufacturing process and has excellent process controllability.
  • FIG. 1 is a sectional view in the thickness direction showing a part of a matrix substrate.
  • FIG. 2 is a plan view of FIG. 3A to 3C are cross-sectional views showing the TFT manufacturing process of the embodiment.
  • 4D to 4F are cross-sectional views showing the TFT manufacturing process of the example.
  • FIGS. 5G to 5I are cross-sectional views showing the TFT manufacturing process of the example.
  • FIG. 6J is a cross-sectional view showing the TFT manufacturing process of the example.
  • 7A to 7C are cross-sectional views showing the manufacturing process of the first embodiment.
  • 8D to 8F are cross-sectional views showing the manufacturing process of the first embodiment.
  • FIG. 9G is a cross-sectional view showing the manufacturing process of the first embodiment.
  • FIGS. 1 is a sectional view in the thickness direction showing a part of a matrix substrate.
  • FIGS. 10A to 10C are cross-sectional views showing the manufacturing process of the second embodiment.
  • FIGS. 11D to 11F are cross-sectional views showing the manufacturing process of the second embodiment.
  • FIG. 12G is a cross-sectional view showing the manufacturing process of the second embodiment.
  • FIGS. 13A to 13D are cross-sectional views showing manufacturing steps of a modification of the second embodiment.
  • 14D to 14F are cross-sectional views showing the manufacturing process of the third embodiment.
  • FIGS. 15G and 15H are cross-sectional views showing the manufacturing process of the third embodiment.
  • FIGS. 16A, 16B, and 16C are enlarged views of FIGS. 14E, 14F, and 15H, respectively.
  • FIG. 17 is an exploded perspective view showing a schematic configuration of a liquid crystal display device which is an example of the display device of the present invention.
  • 18 is a cross-sectional view showing a schematic configuration of the liquid crystal display device of FIG.
  • FIG. 19 is a cross-sectional view showing a part of the liquid crystal display panel of the liquid crystal display device of FIG. 20 (a) to 20 (e) are cross-sectional views showing manufacturing steps of the prior art.
  • 21 (f) to 21 (j) are cross-sectional views showing the manufacturing steps of the prior art.
  • 22 (k) to 22 (o) are cross-sectional views showing the manufacturing steps of the prior art.
  • 22 (a) to 22 (b) are cross-sectional views showing manufacturing steps of the prior art.
  • the first embodiment of the matrix substrate of the present invention is an example of an active matrix substrate (also referred to as a matrix substrate) used in an active matrix liquid crystal display device using thin film transistors (TFTs).
  • FIG. 1 is a sectional view in the thickness direction showing a part of the matrix substrate
  • FIG. 2 is a plan view.
  • FIG. 1 shows a cross section taken along line AA of the plan view of FIG.
  • the active matrix substrate 10 is provided with a plurality of pixels P in a matrix (only one pixel portion is shown in FIGS. 1 and 2).
  • the matrix substrate 10 includes a thin film transistor (TFT) 12 as a switching element for driving each pixel P on the surface of a transparent substrate 11 such as a glass plate as a substrate, and wiring such as gate wiring 24 and source wiring 25.
  • TFT thin film transistor
  • a plurality of gate wirings (sometimes referred to as scanning lines) 24 are provided substantially in parallel with a predetermined interval.
  • a plurality of source wirings (sometimes referred to as data lines) 25 are provided on the matrix substrate 10 in a direction orthogonal to the gate wirings 24 at a predetermined interval.
  • TFTs 12 are provided in the vicinity of the intersections between the gate lines 24 and the source lines 25 of the matrix substrate 10.
  • the matrix substrate 10 is provided with an interlayer insulating film 13 as an insulating film on the surface of the matrix circuit.
  • a transparent conductive film L made of ITO (Indium Tin Oxide) constituting the pixel electrode 14 or the like is provided as a conductive film on substantially the entire surface.
  • the interlayer insulating film 13 is formed with contact holes 15, 16, and 17 that are holes that penetrate the insulating film 13 in the thickness direction.
  • the transparent conductive film L is partitioned by the partition portion D as the pixel electrode 14 and the terminal portions 26 and 27.
  • the partition portion D is formed as a step.
  • the pixel electrode 14 and the terminal portions 26 and 27 are electrically separated by the partition portion D.
  • the contact holes 15, 16, and 17 electrically connect the transparent conductive film L of the pixel electrode 14 and the terminal portions 26 and 27 and the matrix circuit below the insulating layer 13.
  • the TFT 12 of the matrix circuit includes a gate electrode 12c formed on the surface of the transparent substrate 11, a gate insulating film 21 formed on the gate electrode 12c, and the gate insulating film 21.
  • a source wiring 25 for supplying an image signal is connected to the source electrode 12a.
  • An interlayer insulating film 13 is provided on the source electrode 12a and the drain electrode 12b.
  • the interlayer insulating film 13 includes an inorganic insulating film made of silicon nitride (SiNx) or the like formed immediately above the TFT 12, and an organic insulating film made of an acrylic resin or the like formed on the upper layer. It is formed as a two-layer laminated film.
  • the pixel electrode 14 is connected to the drain electrode 12 b of the TFT 12 through the contact hole 15. By turning on the TFT 12 for a certain period, the image signal supplied from the source wiring 25 is written to each pixel P at a predetermined timing.
  • the source electrode 12a, the drain electrode 12b, and the source wiring 25 connected to the source electrode 12a are composed of a stacked body in which a doping semiconductor film 18 and a second conductive film 19 are stacked.
  • the doped semiconductor film 18 is made of amorphous silicon (n + Si) doped with n-type impurities such as phosphorus (P) at a high concentration
  • the second conductive film 19 is made of, for example, aluminum (Al), chromium (Cr), tantalum. It can be formed from a single metal film such as (Ta) or titanium (Ti), or a laminate of these metal nitrides.
  • the source wiring 25 is connected to a wiring connected to a source signal supply circuit (not shown) for supplying an image signal using the contact hole 16 in which the transparent conductive film L is formed as a terminal portion 26.
  • a gate wiring 24 for applying a scanning signal line-sequentially at a predetermined timing is connected to the gate electrode 12c of the TFT 12.
  • the gate wiring 24 is connected to a wiring connected to a scanning signal supply circuit (not shown) using the contact hole 17 in which the transparent conductive film L is formed as a terminal portion 27.
  • the transparent conductive film L includes a contact area CA that is electrically connected to the matrix circuit and a non-contact area NA that is not electrically connected to the matrix circuit in a region other than the contact area CA.
  • the contact area CA includes the pixel electrode 14 and terminal portions 26 and 27.
  • the transparent conductive film L is divided into regions by a partition portion D provided at the boundary between the contact region CA and the non-contact region NA.
  • a partition portion D of the interlayer insulating film 13 is formed as a step difference in height between the contact area CA and the non-contact area NA. There is a portion where the transparent conductive film L is not formed on the side wall surface of the interlayer insulating film 13 formed as a step of the partition portion D.
  • the contact area CA and the non-contact area NA are electrically separated. Since the contact area CA and the non-contact area NA are electrically separated, the transparent conductive film L may remain on the surface of the non-contact area CA. That is, after forming the transparent conductive film L on the entire surface of the interlayer insulating film 13, it is not necessary to remove the transparent conductive film L in the non-contact region NA on the surface of the interlayer insulating film 13.
  • the surface of the interlayer insulating film 13 except for the contact holes 15, 16, and 17 has a contact area CA and a non-contact area NA on the surface. It is formed as a flat surface without irregularities and grooves.
  • the interlayer insulating film 13 is formed so that the height of the contact area CA formed as a flat surface is different from the height of the non-contact area NA. That is, the thickness of the contact area CA of the interlayer insulating film 13 is different from the thickness of the non-contact area NA.
  • the surface of the contact area CA and the surface of the non-contact NA are not formed on the same plane. Either the height of the contact area CA or the height of the non-contact area NA may be high, but in the embodiment of FIG. 2, the height of the surface of the interlayer insulating film 13 in the contact area CA is the interlayer insulation of the non-contact area NA. It is formed so as to be higher than the height of the surface of the film 13.
  • the transparent conductive film L is formed over the entire surface of the interlayer insulating film 13 except for the partition portion D.
  • the contact region CA and the non-contact region NA are electrically separated from each other on the surface of the side wall that becomes the step portion of the partition portion D of the interlayer insulating film 13. Even if the transparent conductive film L is formed on the side wall of the partition part, it may be formed so as not to be conductive between the upper and lower steps.
  • the transparent conductive film L is not formed on the entire side wall of the interlayer insulating film 13 in the partition portion D.
  • the transparent conductive film L is not formed on the entire side wall, when particles or the like adhere to the partition portion D between the contact area CA and the non-contact region NA, there is a possibility of short-circuiting between adjacent regions in the partition portion D. Becomes lower. There is an advantage that the transparent conductive film can be divided more reliably.
  • the manufacturing method of the matrix substrate of the present invention can be broadly divided into (1) a TFT forming step in which a TFT is formed on a glass substrate to form an interlayer insulating film, and (2) a contact hole is formed in the interlayer insulating film and a step is formed on the surface.
  • the (1) TFT forming step can be formed by a method similar to the conventional method. This process is a process common to the second and third embodiments described later.
  • the present invention is greatly characterized in the following (2) insulating film forming step and (3) conductive film forming step. Hereinafter, each process is demonstrated one by one.
  • FIG. 3A a first conductive film 20 made of a metal film or the like is formed on the entire surface of the transparent substrate 11 having transparent insulation.
  • the transparent substrate 11 can be made of glass, plastic, or the like having a thickness of 0.5 mm, 0.7 mm, 1.1 mm, or the like.
  • the first conductive film 20 can be usually formed to a thickness of 1000 to 3000 mm by a sputtering method.
  • the first conductive film 20 is made of, for example, a metal film such as titanium (Ti), chromium (Cr), aluminum (Al), molybdenum (Mo), tantalum (Ta), tungsten (W), copper (Cu), molybdenum tantalum ( An alloy film such as MoTa) or molybdenum tungsten (MoW), or a stacked film of these can be used.
  • a metal film such as titanium (Ti), chromium (Cr), aluminum (Al), molybdenum (Mo), tantalum (Ta), tungsten (W), copper (Cu), molybdenum tantalum (
  • An alloy film such as MoTa) or molybdenum tungsten (MoW), or a stacked film of these can be used.
  • a photoresist is applied on the first conductive film 20, and exposure and development are performed using a first photomask (not shown), and the gate electrode and A resist 40 is formed in a pattern of a region to be a gate wiring.
  • the first conductive film 20 in the region not covered with the resist 40 is removed by dry etching or wet etching, and the gate electrode 12c, the gate wiring 24, and the like are formed. Then, the resist 40 is removed by plasma ashing using oxygen.
  • the gate insulating film 21, the semiconductor film 22, the doping semiconductor film 18, and the second conductive film 19 are successively formed on the gate electrode 12 c and the gate wiring 24.
  • the gate insulating film 21, the semiconductor film 22, and the doping semiconductor film 18 are formed using a plasma CVD method. Usually, this three-layer film is formed continuously in the same apparatus.
  • the gate insulating film 21 is formed of silicon nitride (SiNx), silicon oxide film (SiOx), or the like.
  • the semiconductor film 22 is formed of, for example, an amorphous silicon (a-Si) film.
  • the doped semiconductor film 18 is formed of an amorphous silicon (n + Si) film doped with an n-type impurity such as phosphorus (P) at a high concentration.
  • the second conductive film 19 is usually formed of a metal film such as aluminum (Al), chromium (Cr), tantalum (Ta), titanium (Ti) or a laminated film of these metal nitrides using a sputtering method. Formed with.
  • a photoresist is applied on the second conductive film 19, and exposure and development are performed using a second photomask (not shown) to activate the TFT 12.
  • a resist 40 is formed in a pattern to be the formation region, the channel region Q of the TFT 12, the source electrode 12a, the source wiring 25, and the drain electrode 12b.
  • the resist 40 uses a multi-tone mask such as a halftone mask or a gray tone mask as the second photomask, and the TFT activation region, the source electrode, the source wiring, and the region on the region Q serving as the channel of the TFT 12.
  • a thin film portion 41 having a thickness smaller than that on the region to be the drain electrode is formed.
  • a portion other than the thin film portion of the resist 40 is formed as a thick film portion 42.
  • the resist material may be either a negative photosensitive resist material or a positive photosensitive resist material.
  • a multi-tone photomask (sometimes referred to simply as a multi-tone mask) has a pattern composed of two gradations, a light-shielding portion (black) that blocks light and a transmitted light portion (white) that transmits light.
  • the binary mask is configured as a photomask having three or more gradations including a light-shielding portion (black) and a transmitted light portion (white), and a semi-transmitted light portion (gray) that semi-transmits light.
  • the multi-tone photomask includes a gray tone mask and a halftone mask.
  • the halftone mask is a semi-transparent light portion configured to reduce the amount of light transmitted by forming the light-shielding film of the semi-transmissive light portion thinner than the thickness of the light shielding portion by means such as etching. .
  • the gray tone mask uses a light diffraction effect by providing a fine pattern below the exposure machine resolution limit as a semi-transmissive light portion.
  • a resist pattern with a film thickness difference can be formed by a single exposure and development when a resist layer with a film thickness difference is formed compared to when a binary mask is used. Therefore, the process can be shortened.
  • the formation of the resist 40 is not limited to a method using a multi-tone photomask as long as it can form a film thickness difference, and any method may be used.
  • a resist 40 having a film thickness difference using a method using a plurality of binary masks by changing the exposure amount using a binary mask or performing a plurality of exposures. May be formed.
  • the second conductive film 19 the doped semiconductor film 18 and the semiconductor film 22 in a region not covered with the resist 40 are removed by dry etching or wet etching, so that the thin film transistor is activated.
  • the thin film portion 41 formed thinly on the region Q to be a TFT channel is removed by ashing using oxygen plasma. Only the thick film portion 42 remains in the resist 40.
  • the portion where the resist 40 is removed is etched again by dry etching or wet etching, and the second conductive film and the doped semiconductor film are removed to form the channel region Q of the TFT 12. To do.
  • the remaining resist thick film portion 42 is removed by ashing using oxygen plasma.
  • an inorganic insulating film made of a silicon nitride film (SiNx) and a planarizing film (organic insulating film) made of acrylic resin are sequentially formed on the entire surface of the substrate on which the TFT 12 is formed. Then, an unprocessed interlayer insulating film 13a is formed. In this way, the entire upper surface of the matrix circuit provided with the TFT is covered with the interlayer insulating film 13a.
  • the silicon nitride film is formed so as to follow the shape of the TFT 12, the surface of the planarizing film is formed flat, and the surface of the unprocessed interlayer insulating film 13a is formed flat.
  • the inorganic insulating film is formed to a thickness of about 0.2 to 0.3 ⁇ m, and the planarizing film is formed to a thickness of about 1.8 to 2.2 ⁇ m.
  • the inorganic insulating film contributes to the stable operation of the TFT by providing the insulating film mainly with a passivation function. Yes.
  • the planarizing film is formed as a layer for planarizing the surface of the unprocessed interlayer insulating film 13a.
  • FIGS. 7A to 7C and FIGS. 8D to 8E show the insulating film forming steps of the first embodiment, and FIGS. 7A to 7E are cross-sectional views of the respective steps.
  • the insulating film forming step is a step of forming steps in the contact holes 15, 16, and 17 and the partition portion D in the interlayer insulating film 13a as shown in FIG.
  • the partition portion D is a portion that partitions a contact area CA in which the transparent conductive film L is electrically connected to the matrix circuit and a non-contact area NA in which the transparent conductive film L is not electrically connected to the matrix circuit.
  • a photoresist is applied to the surface of the interlayer insulating film 13a to form a resist 40, and a multi-tone is formed as a third photomask for the resist 40. Exposure and development are performed using a mask (not shown).
  • the resist 40 is formed as a multistage resist film in which the contact hole forming portion is removed, the resist in the contact region CA becomes the thick film portion 42, and the resist in the non-contact region becomes the thin film portion 41.
  • the interlayer insulating film 13a is dry-etched. In the dry etching, the contact hole portions 15a, 16a, and 17a are etched halfway.
  • the resist 40 is ashed using oxygen plasma or the like. Ashing is performed until the thin film portion 41 of the resist is removed. Only the thick film portion 42 remains on the resist 50 on the interlayer insulating film 13a.
  • the interlayer insulating film 13a is dry-etched.
  • the contact hole portions 15a, 16a, and 17a are continuously etched by dry etching, and the portion from which the thin film portion 41 is removed (non-contact region NA) is etched.
  • the resist 40 is ashed with oxygen plasma or the like to remove the thick film portion 42, and the resist is completely removed.
  • the interlayer insulating film 13 in which the partition portion D is formed as a step and the contact holes 15, 16, and 17 are formed at predetermined positions is obtained.
  • the etching depth of the non-contact area NA that is, the height of the step of the partition portion D is formed to be about 0.3 to 0.4 ⁇ m.
  • etching is performed in the depth direction, such as etching of the contact holes 15, 16, 17 and the non-contact area NA
  • an anisotropic etching method such as reactive ion etching (RIE) is used.
  • RIE reactive ion etching
  • RIE reactive ion etching
  • the conductive film forming step when forming the transparent conductive film, the contact area CA and the non-contact area NA of the transparent conductive film L are formed so as to be electrically separated using the step of the partition portion D. It is.
  • the conductive film forming step will be described.
  • a transparent conductive material such as an ITO film is formed on the entire surface of the interlayer insulating film 13 in which the step of the partition portion D and the contact holes 15, 16, and 17 are formed.
  • the film L is formed by sputtering.
  • the transparent conductive film L adjusts sputtering conditions, and forms the thickness of the side wall part of the partition part D thinner than the thickness of a plane part.
  • sputtering is performed so that ITO atoms are incident on the plane portion substantially perpendicularly. Therefore, usually, when the transparent conductive film L is formed by a sputtering method, the side wall portion is formed thinner than the planar portion.
  • a transparent conductive material such as IZO (indium-zinc oxide), zinc oxide, tin oxide, etc. can be used in addition to ITO.
  • the transparent conductive film L is usually formed to a thickness of 1000 to 2000 mm.
  • the surface of the transparent conductive film L is etched by plasma etching to remove the transparent conductive film on the side wall of the partition portion D. Since the transparent conductive film on the side wall portion is formed by the ITO sputtering method, it is formed thinner than the flat portion. Therefore, it is easy to remove only the transparent conductive film on the side wall part and leave the transparent conductive film on the flat part.
  • the etching conditions are set so that the transparent conductive film on the inner walls of the contact holes 15, 16, and 17 is not removed.
  • the etching rate is set to be a condition that determines the supply rate of the reactive gas.
  • the reactive gas is unlikely to be supplied to the side wall inside the contact hole having a small opening surface with respect to the side wall portion of the step D having a large opening surface.
  • the etching rate of the side wall inside the contact hole to which the reactive gas is difficult to be supplied is lower than the side wall of the step.
  • the rate of supply of the reactive gas means such as increasing the supply amount of the reactive gas or increasing the pressure of the reactive gas can be used.
  • the transparent conductive film L is removed by etching to remove the transparent conductive film on the side wall portion of the step of the partition portion D, so that the transparent conductive film L becomes the pixel electrode 14 and the terminal portion.
  • a matrix substrate 10 having a predetermined pattern of 26 and 27 and having a contact area CA formed in the interlayer insulating film 13 is obtained.
  • the interlayer insulating film 13 is formed as a non-contact region NA in the TFT element 12, the source wiring 25, and the gate wiring 24 other than the contact area CA.
  • the transparent conductive film L is also formed in the non-contact region NA and remains, but the stepped portion becomes a partition portion D and is electrically separated from the contact region CA.
  • the transparent conductive film removing step is unnecessary, the removing step is unnecessary as compared with the method of removing the remaining transparent conductive film as in the conventional lift-off method. There is no problem (for example, short-circuiting due to adhesion of particles) caused by the generation of particles.
  • FIGS. 10 (a) to 10 (c), 11 (d) and 11 (e) show a second embodiment of the method for manufacturing a matrix substrate of the present invention, and FIGS. It is sectional drawing of a process.
  • the TFT forming process is the same as that in the first embodiment, and the description thereof is omitted.
  • the insulating film forming step of the second embodiment as shown in FIG. 10A, first, a photoresist is applied to the surface of the interlayer insulating film 13a to form a resist film, and a third photo is applied to the resist film. Exposure and development are performed using a multi-tone mask (not shown) as a mask.
  • the resist 40 is formed as a multistage resist film.
  • portions where the contact holes 15, 16, and 17 are formed are removed, the resist 40 in the contact area CA becomes the thick film part 42, and the resist 40 in the non-contact area becomes the thin film part 41, and the thick film part 42 is partitioned.
  • the resist film of the portion D is formed as a resist pillar portion 53 that is a convex portion upward.
  • the interlayer insulating film 13a is dry-etched. In the dry etching, the contact hole portions 15a, 16a, and 17a are etched halfway.
  • the resist 40 is ashed using oxygen plasma or the like. Ashing is performed until the thin film portion 41 of the resist 40 is removed. The thick film portion 42 and the resist pillar portion 53 remain in the resist 40 on the interlayer insulating film 13a.
  • the interlayer insulating film 13a is dry-etched.
  • the contact hole portions 15a, 16a, and 17a are continuously etched by dry etching, and the portion from which the thin film portion 41 is removed (non-contact region NA) is etched.
  • Contact holes 15, 16, and 17 are formed to a predetermined depth, and non-contact region NA is formed as a recess.
  • the resist is ashed with oxygen plasma or the like to leave the resist pillar portion 53 and remove the thick film portion.
  • the partition portion D is formed as a step, the contact holes 15, 16, and 17 are formed at predetermined positions, and the interlayer insulating film 13 with the resist pillar portion 53 remaining at the periphery of the contact region CA is obtained.
  • the etching depth of the non-contact area NA that is, the height of the step of the partition portion D is formed to be about 0.3 to 0.4 ⁇ m.
  • the remaining resist pillar portion 53 has a height of about 1.2 to 1.5 ⁇ m.
  • the remaining resist pillar portion 53 is formed to have a width of about 0.3 to 0.5 ⁇ m.
  • a transparent conductive film L is formed by sputtering on the surface of the interlayer insulating film 13 where the step and the resist pillar portion 53 are formed in the partition portion D and on the surface of the resist pillar portion 53.
  • the transparent conductive film L is formed such that the side wall portion of the partition portion D and the side surface of the resist pillar portion 53 are thinner than the planar portion.
  • the transparent conductive film L can be formed to have a thickness of about 0.05 to 0.1 ⁇ m at the side wall and about 0.1 to 0.2 ⁇ m at the flat surface.
  • the transparent conductive film L on the surface is also removed together with the resist pillar portion 53.
  • the contact area CA and the non-contact area NA of the transparent conductive film L are electrically separated.
  • the removal of the resist pillar portion 53 by the lift-off method can use a known wet process or the like.
  • the matrix substrate 10 in which the transparent conductive film L is formed in a predetermined shape such as the pixel electrode 14 and the terminal portions 26 and 27 is obtained.
  • the transparent conductive film L may remain on the side wall portion of the partition portion D, but the side wall portion of the partition portion D may be further removed by reactive ion etching or the like.
  • the transparent conductive film L may be removed.
  • the transparent conductive film of the resist pillar portion 53 is removed by lift-off, but the transparent conductive film L remains in other portions, and a so-called local lift-off method is used.
  • This method has the following advantages over the conventional method using the so-called full surface lift-off method in which the transparent conductive film in the non-contact region is completely removed. In the whole surface lift-off method, all the transparent conductive film other than the pixel region is brought into the wet processing tank. On the other hand, in the local lift-off method, the transparent conductive film of the resist pillar portion 53 is merely brought into the wet processing tank.
  • the amount of the transparent conductive film brought into the wet treatment tank is 1 / 1,000 or less that of the whole surface lift-off method, and is extremely small. For this reason, the load on the wet treatment tank is significantly reduced. For example, when the load on the wet treatment tank is reduced, clogging of the circulation filter and the like is reduced, and the replacement frequency is increased.
  • the processing amount of the transparent conductive film since the processing amount of the transparent conductive film is small, the wet processing time may be short and the wet processing temperature may be low. Further, the local lift-off method has an advantage that the concentration of the chemical solution in the wet treatment may be low.
  • a resist pillar portion 53 is provided at the step of the partition portion D, and the contact area CA and the non-contact region NA are partitioned by the step. Further, in this embodiment, the contact area CA and the non-contact area NA are not on the same plane, and each area is formed as a surface having a different height. In the case of a matrix substrate in which the contact region and the non-contact region are on the same plane as in the prior art and the boundary is defined by a groove, the contact region and the non-contact region when particles adhere to the groove, etc. Is easily shorted by particles. On the other hand, if a step is formed in the partition portion D of both regions, the possibility that particles adhere to the step and short-circuit between both regions is reduced.
  • FIGS. 13 (a) to 13 (d) show modified examples of the second embodiment and are enlarged cross-sectional views of the step portions of the respective steps.
  • the transparent conductive film L remains on the surface of the side wall of the partition portion D.
  • the matrix substrate 10 from which the transparent conductive film L on the side wall of the partition portion D is removed is provided. can get.
  • a method for manufacturing a matrix substrate according to a modification of the second embodiment will be described.
  • the resist pillar portion 53 is reflowed from the state in which the resist pillar portion 53 is formed on the surface of the interlayer insulating film 13 in the second embodiment.
  • the resist pillar portion 53 is reflowed so that the side wall portion of the step is covered with the reflowed resist 54.
  • a transparent conductive film L is formed on the entire surface of the interlayer insulating film 13 as shown in FIG.
  • the reflowed resist 54 is removed as shown in FIG. 4D, the reflowed resist 54 and the transparent conductive film L on the surface thereof are removed by the lift-off method.
  • the resist can be reflowed by a known reflow method such as a method of exposing to a reflow solvent vapor or a method of reflow solvent and heating.
  • FIGS. 14 (d) to 14 (f) and FIG. 15 (g) show the insulating film forming steps of the third embodiment of the method for manufacturing a matrix substrate of the present invention
  • FIGS. 14 (d) to (g) are sectional views of the respective steps. It is.
  • the TFT forming process is the same as that in the first and second embodiments, and the description thereof is omitted.
  • the steps up to the step of forming the recess in the non-contact region in the insulating film forming step of the third embodiment by etching are the same steps as in FIGS. 7A to 7C of the first embodiment, and thus description thereof is omitted. To do.
  • the interlayer insulating film 13a includes contact hole portions 15a, 16a, 17a and non-contact regions NA as in the first embodiment.
  • the part is etched. In this state, the thick film portion 42 of the resist 40 remains.
  • the remaining resist is reflowed, and the reflowed resist 54 is the surface of the side wall of the partition portion D and the side walls of the contact holes 15, 16, and 17. And cover the bottom.
  • the reflowed resist 54 covers the surface of the contact area CA and the side wall of the partition portion D, but does not cover the surface of the non-contact area NA.
  • FIGS. 16 (a) and 16 (b) are enlarged views of the side walls of the partition portions of FIGS. 14 (e) and 14 (f), respectively.
  • the interlayer insulating film 13a provided with the reflowed resist 54 is etched.
  • the non-contact region NA is etched in the depth direction to form a recess.
  • the side wall of the non-contact region formed as a recess of the interlayer insulating film 13a by etching also proceeds to the inside of the wall surface, and the corner portion is etched to form the undercut portion 13b. In this case, it is preferable to use isotropic etching.
  • plasma etching can be used as isotropic etching.
  • the etching in the side surface direction can surely proceed.
  • the undercut portion 13b can be reliably formed in a shape in which the conductive film is difficult to be formed.
  • the reflowed resist 54 is ashed with oxygen plasma to remove the resist 54.
  • contact holes 15, 16, 17, steps in the partition part D and undercut part 13 b are formed in the interlayer insulating film 13.
  • FIG. 15 (h) is a cross-sectional view showing the conductive film forming step
  • FIG. 16 (c) is an enlarged view of the step in FIG. 15 (h).
  • a transparent conductive film L is formed by sputtering on the surface of the interlayer insulating film 13 on which the undercut portion 13b is formed. Since the ITO atoms forming the transparent conductive film L are incident on the substrate substantially perpendicularly, the bottom of the undercut portion 13b is shaded and the transparent conductive film L is not formed.
  • the transparent conductive film L in the contact area CA and the non-contact area NA is electrically separated by the undercut portion 13b.
  • the pixel electrode 14 and the terminal portions 26 and 27 are formed in a predetermined shape.
  • the matrix substrate 10 in which the pixel electrode 14 and the terminal portions 26 and 27 of the transparent conductive film L are formed in a predetermined shape is obtained.
  • the matrix substrate 10 has been described with an example in which only one step is provided in the partition portion D. However, a plurality of steps may be provided. Further, when providing the undercut portion as shown in the third embodiment, when a plurality of steps are provided in the partition portion of the matrix substrate, the undercut portion may be formed at any step.
  • the transparent conductive film in the non-contact region is left without being removed in the conductive film forming step. Therefore, there is no need for a photolithography process in which resist coating for removing the non-contact region of the transparent conductive film and exposure using a photomask are performed. Since a photolithography process is not required to form the transparent conductive film, the productivity of the matrix substrate is excellent.
  • Examples 1 to 3 when manufacturing an active matrix substrate using a TFT as a switching element, a manufacturing process including formation of a matrix circuit, formation of an insulating film, and formation of a conductive film is performed on three sheets. It is possible to manufacture by a three-mask process using a photomask. In this case, as shown in the above embodiment, the transparent conductive film can be reliably formed in a predetermined pattern, and the disadvantages of the three-mask process in the production of the conventional active matrix substrate can be eliminated.
  • the display device of the present invention includes the matrix substrate described above.
  • the display device of the present invention will be described below.
  • 17 is an exploded perspective view showing a schematic configuration of a liquid crystal display device which is an example of the display device of the present invention
  • FIG. 18 is a cross-sectional view showing a schematic configuration of the liquid crystal display device of FIG.
  • the liquid crystal display device 1 includes a rectangular liquid crystal display panel 2 and a backlight device 3 as an external light source, which are formed so as to be integrally held by a bezel 4 or the like. Has been.
  • the backlight device 3 shown in FIG. 17 and FIG. 18 is a so-called direct-type backlight device, and a plurality of cold cathodes are provided directly below the back surface of the panel surface (display surface) of the liquid crystal display panel 2 along the panel surface.
  • a tube 301 is arranged as a light source.
  • the backlight device 3 includes a rectangular metal base 302 having an open top surface, an optical member 303 attached to cover the opening of the base 302, and the optical member 303 held by the base 302. And a cold cathode tube 301 accommodated in the base 302, a holder 305 for holding both ends of the cold cathode tube 301, a lamp holder 306 and a clip 307 that collectively cover these.
  • the optical member 303 is formed by laminating a diffusion plate, a diffusion sheet, a lens sheet, and the like.
  • FIG. 19 is a cross-sectional view showing a part of the liquid crystal display panel of the liquid crystal display device of FIG.
  • the pair of substrates of the matrix substrate 10 and the counter substrate 70 of the present invention are bonded together with a gap therebetween, and liquid crystal is sealed between the substrates.
  • a liquid crystal layer 80 is provided.
  • the matrix substrate 10 is an active matrix substrate, and includes a TFT 12 as a semiconductor element and a pixel electrode 14 connected to the TFT on the liquid crystal layer 80 side of the transparent substrate 11.
  • An alignment film 30 and the like are provided on the liquid crystal side of the pixel electrode 14 of the matrix substrate 10. For example, a polyimide rubbing film or the like is used as the alignment film 30.
  • a polarizing plate 31 is disposed on the opposite side of the liquid crystal layer 80 of the matrix substrate 10.
  • a stretched film obtained by stretching a transparent film soaked with iodine or a dye in one direction can be used.
  • the counter substrate 70 is a color having a colored portion or the like that can selectively transmit R (red), G (green), and blue (B) light on the liquid crystal layer 80 side of a transparent substrate 71 such as a glass plate.
  • the color filter substrate includes a filter 72, a counter electrode 73, an alignment film 74, and the like.
  • a polarizing plate 75 is disposed on the opposite side of the counter substrate 70 from the liquid crystal layer 80.
  • the color filter 72 includes a black matrix 72b arranged at the boundary of the colored portions (72R, 72G, 72B), and the black matrix 72b is provided at a position covering a non-pixel portion (region where TFTs are formed) of the panel. It has been.
  • the counter electrode 73 is made of a transparent conductive film such as ITO, and is formed on the entire surface of the counter substrate 70 on the liquid crystal layer 80 side. As the alignment film 74, the polarizing plate 75, and the like, the same materials as those of the matrix substrate 10 can be used.
  • the counter substrate 70 and the matrix substrate 10 are manufactured, the surfaces of the alignment films are opposed to each other, and are bonded via a sealing material (not shown), and liquid crystal is injected between the substrates. Then, the liquid crystal layer 80 is formed, and a drive circuit or the like can be connected. Furthermore, the liquid crystal display device 1 can be obtained by mounting the above-described backlight device 3 and various control circuits and substrates on the liquid crystal display panel 2.
  • the control circuit and the substrate are, for example, a control circuit that controls the liquid crystal display panel 2 and the matrix substrate 10, a substrate such as a drive circuit and a power supply circuit, a circuit that controls the backlight device 3, and the like.
  • the matrix substrate of the present invention can be suitably used particularly for various display elements such as liquid crystal display elements, organic EL display elements, and plasma display elements.
  • the display device of the present invention can be suitably used for large televisions and the like.

Abstract

Provided is a matrix substrate, which has a conductive film easily and surely formed in a predetermined pattern on a matrix circuit with an insulating film therebetween, has reduced particles generated in the manufacture steps, and has an improved product yield with excellent process controllability. In a transparent conductive film (L), a contact region (CA), which is electrically connected to the matrix circuit, and a non-contact region (NA), which is not electrically connected to matrix circuits in regions other than the contact region (CA), are partitioned by means of partitioning sections (D) provided on the boundaries. Each of the partitioning sections (D) is formed as a step formed by the difference between the height of the contact region (CA) and that of the non-contact region (NA), the contact region (CA) and the non-contact region (NA) are electrically separated by means of the step, and the pixel electrode (14) and the terminal sections (26, 27) in the contact region are formed in predetermined patterns, thereby configuring the matrix substrate (10).

Description

マトリクス基板、その製造方法及び表示装置Matrix substrate, manufacturing method thereof, and display device
　本発明は、マトリクス基板、該マトリクス基板を用いた表示装置、及びマトリクス基板の製造方法に関し、特に液晶表示装置等の表示装置に好適に用いられるマトリクス基板及びマトリクス基板の製造方法に関するものである。 The present invention relates to a matrix substrate, a display device using the matrix substrate, and a method for manufacturing the matrix substrate, and more particularly to a matrix substrate suitably used for a display device such as a liquid crystal display device and a method for manufacturing the matrix substrate.
　従来、表示装置として例えば対向する一対の基板の間に液晶を挟持し、基板の電極間に電圧を印加して表示を行う液晶表示装置が公知である。 Conventionally, as a display device, for example, a liquid crystal display device that performs display by sandwiching a liquid crystal between a pair of opposing substrates and applying a voltage between electrodes of the substrate is known.
　液晶表示装置として、一方の基板にスイッチング素子として薄膜トランジスタ（Thin Film Transistor:TFT）を設けたマトリクス基板を用いて、複数の液晶セルを駆動するように構成したアクティブマトリクス型液晶表示装置が広く用いられている。アクティブマトリクス型液晶表示装置のマトリクス基板には、ガラス板等の透明絶縁性の基板の表面に、複数本の信号線と走査線が格子状に設けられ、表示単位となる絵素毎にアモルファスシリコン等の半導体薄膜からなるＴＦＴを備えるＴＦＴアクティブマトリクス回路が形成されている。 As a liquid crystal display device, an active matrix liquid crystal display device configured to drive a plurality of liquid crystal cells using a matrix substrate provided with a thin film transistor (TFT) as a switching element on one substrate is widely used. ing. A matrix substrate of an active matrix liquid crystal display device has a plurality of signal lines and scanning lines arranged in a lattice pattern on the surface of a transparent insulating substrate such as a glass plate, and amorphous silicon is provided for each pixel serving as a display unit. A TFT active matrix circuit including a TFT made of a semiconductor thin film such as the above is formed.
　マトリクス基板において、ＴＦＴアクティブマトリクス回路は、基板の表面の全面に薄膜層を形成し、該薄膜層上にフォトマスクを用いてレジストパターンを形成した後、エッチング等により薄膜層をパターニングする工程を複数回繰り返す、所謂フォトリソグラフィ法により形成されている。 In a matrix substrate, a TFT active matrix circuit includes a plurality of steps of forming a thin film layer on the entire surface of the substrate, forming a resist pattern on the thin film layer using a photomask, and then patterning the thin film layer by etching or the like. It is formed by a so-called photolithography method that is repeated several times.
　従来の露光に使用するフォトマスクを５枚用いてフォトリソグラフィ法によりマトリクス基板を製造する方法に対し、例えばハーフトーンマスクと多層膜の一括エッチングを組み合わせる方法により、フォトマスクの使用を５枚から３枚に減らすことで、マトリクス基板の生産性を向上させる方法が公知である（例えば特許文献１～２参照）。 Compared to the conventional method of manufacturing a matrix substrate by photolithography using five photomasks used for exposure, the use of a photomask is reduced from 5 to 3 by combining a halftone mask and a multi-layer etching of a multilayer film, for example. A method for improving the productivity of the matrix substrate by reducing the number of the substrates is known (see, for example, Patent Documents 1 and 2).
　特許文献１に記載のマトリクス基板の製造方法は、以下の通りである。図２０（ａ）に示すように先ずガラス基板１０１の表面全体にゲート電極膜１０２を成膜する。次にゲート電極膜１０２上にレジスト層を塗布し、フォトマスク（第１のマスク：図示せず）を用いて露光、現像を行い、レジストパターン１０３を形成する。このレジストパターン１０３を利用してエッチングしてパターン状のゲート電極膜１０２を形成する〔同図（ｂ）参照〕。 The manufacturing method of the matrix substrate described in Patent Document 1 is as follows. First, as shown in FIG. 20A, a gate electrode film 102 is formed on the entire surface of the glass substrate 101. Next, a resist layer is applied over the gate electrode film 102, and exposure and development are performed using a photomask (first mask: not shown) to form a resist pattern 103. Etching is performed using the resist pattern 103 to form a patterned gate electrode film 102 [see FIG.
　次に表面全体に、ゲート絶縁膜１０４、アモルファスシリコン（ａ－Ｓｉ）層１０５、ｎ＋ａ－Ｓｉ層１０６、を三層連続成膜し、更にソース・ドレイン電極膜１０７を積層する。次に積層膜の表面にレジスト層を塗布し、ハーフトーンマスク（第２のマスク：図示せず）を用いて露光量等を調節して、露光、現像を行い、複数段階の厚みのレジスト層を有するレジストパターン１０８を形成し、エッチングを行い、レジストパターン１０８に覆われていない部分のソース・ドレイン電極、ａ－Ｓｉ層、ｎ＋ａ－Ｓｉ層を除去する〔同図（ｃ）参照〕。尚、レジストパターン１０８は、画素部と端子部に形成せず、ＴＦＴ素子部のチャネル部を薄肉部１０８ａとして形成し、その他の部分が厚く形成されている。 Next, a gate insulating film 104, an amorphous silicon (a-Si) layer 105, and an n + a-Si layer 106 are continuously formed on the entire surface, and a source / drain electrode film 107 is further laminated. Next, a resist layer is applied to the surface of the laminated film, and the exposure amount is adjusted using a halftone mask (second mask: not shown), and exposure and development are performed. And a portion of the source / drain electrode, a-Si layer, and n + a-Si layer that are not covered with the resist pattern 108 are removed (see FIG. 4C). The resist pattern 108 is not formed in the pixel portion and the terminal portion, the channel portion of the TFT element portion is formed as the thin portion 108a, and the other portions are formed thick.
　次にアッシングにより残存しているレジストパターン１０８の厚みを減少させ、薄肉部１０８ａに対応するチャネル部１０５ａの位置でソース・ドレイン電極膜の表面を露出させる。次に、残存するレジストパターン１０８を利用して、ソース・ドレイン電極分離及びチャネルエッチングを行った後、レジストパターン１０８を除去する〔同図（ｄ）参照〕。チャネル部１０５ａではｎ＋ａ－Ｓｉ層１０６、ソース・ドレイン電極膜１０７が除去され、ａ－Ｓｉ層１０５の厚みが調整される。 Next, the thickness of the remaining resist pattern 108 is reduced by ashing, and the surface of the source / drain electrode film is exposed at the position of the channel portion 105a corresponding to the thin portion 108a. Next, using the remaining resist pattern 108, source / drain electrode separation and channel etching are performed, and then the resist pattern 108 is removed [see FIG. In the channel portion 105a, the n + a-Si layer 106 and the source / drain electrode film 107 are removed, and the thickness of the a-Si layer 105 is adjusted.
　次に同図（ｅ）に示すように基板１の全面にパッシベーション膜１０９、表面を平坦化した感光性のアクリル系樹脂膜１１０を順次形成する。次に、図２１（ｆ）に示すように、アクリル系樹脂膜１１０の表面全面にフォトレジストを塗布し、３枚目のフォトマスクとしてスリットマスク等を用いて露光、現像し、２種類の厚みを有するレジストパターンからなるレジスト層１１１を形成する。レジスト層１１１は、画素電極が形成される領域に対応する部分が薄肉部１１１ａとなり、コンタクトホール位置１１１ｂが未形成部分となり、その他の部分が厚肉部として形成される。 Next, as shown in FIG. 5E, a passivation film 109 and a photosensitive acrylic resin film 110 with a flattened surface are sequentially formed on the entire surface of the substrate 1. Next, as shown in FIG. 21 (f), a photoresist is applied to the entire surface of the acrylic resin film 110, exposed and developed using a slit mask or the like as the third photomask, and two kinds of thicknesses are obtained. A resist layer 111 made of a resist pattern having the above is formed. In the resist layer 111, a portion corresponding to a region where the pixel electrode is formed becomes a thin portion 111a, a contact hole position 111b becomes an unformed portion, and the other portion is formed as a thick portion.
　次に同図（ｇ）に示すように、感光性アクリル樹脂膜１１０に露光すると、レジスト層１１１にマスクされない露光部分の感光性アクリル樹脂膜１１０が分解し、ソース・ドレイン電極膜１０７又はゲート電極膜１０２まで貫通するコンタクトホール１１４が形成される。次に同図（ｈ）に示すように、アッシングによってレジスト層１１１の全体的な厚みを減少させる。アッシングは、薄肉部１１１ａの部分のレジスト層が除去されるまで行う。次に同図（ｉ）に示すように、全面に透明導電膜１１２を形成する。 Next, as shown in FIG. 5G, when the photosensitive acrylic resin film 110 is exposed, the exposed portion of the photosensitive acrylic resin film 110 not masked by the resist layer 111 is decomposed, and the source / drain electrode film 107 or the gate electrode A contact hole 114 that penetrates to the film 102 is formed. Next, as shown in FIG. 5H, the overall thickness of the resist layer 111 is reduced by ashing. Ashing is performed until the resist layer in the thin-walled portion 111a is removed. Next, a transparent conductive film 112 is formed on the entire surface as shown in FIG.
　次に同図（ｊ）に示すように、リフトオフ法によりレジスト層１１１を除去すると、レジスト層１１１の上の透明導電膜１１２が、レジスト層１１１と共に除去されて、画素部分１１２ａ及びコンタクトホール部分１１２ｂの透明導電膜が残存する。このように特許文献１に記載の方法は、透明導電膜をパターニングして画素電極を形成する方法として、レジスト層をリフトオフする部分に透明導電膜が形成されないことを利用して、画素電極のパターンを形成する方法である。 Next, as shown in FIG. 6J, when the resist layer 111 is removed by the lift-off method, the transparent conductive film 112 on the resist layer 111 is removed together with the resist layer 111, and the pixel portion 112a and the contact hole portion 112b. The transparent conductive film remains. As described above, the method described in Patent Document 1 is a method of patterning a transparent conductive film, and forming a pixel electrode by utilizing the fact that a transparent conductive film is not formed in a portion where a resist layer is lifted off. It is a method of forming.
　特許文献２に記載のマトリクス基板の製造方法は、以下の通りである。上記特許文献１と同様に、まず図２０（ａ）～（ｅ）に示す工程を行い、各層を設けた基板１の表面に感光性のアクリル系樹脂膜１１０を形成する。次に図２２（ｋ）に示すように、アクリル系樹脂膜１１０の表面にフォトレジストを全面に塗布し、ハーフトーンマスク（第３のマスク：図示せず）を用いて露光、現像し、複数段階の厚みにパターンニングされたレジスト層１１１を形成する。レジスト層１１１は、コンタクトホールを形成する画素部や端子部は未形成部分とし、その他の画素部領域を厚肉部１１１ｃとし、その他のコンタクトホールや画素電極を形成しない部分を薄肉部１１１ｄとして形成する。 The manufacturing method of the matrix substrate described in Patent Document 2 is as follows. As in the above-mentioned Patent Document 1, first, the steps shown in FIGS. 20A to 20E are performed to form a photosensitive acrylic resin film 110 on the surface of the substrate 1 provided with each layer. Next, as shown in FIG. 22 (k), a photoresist is applied to the entire surface of the acrylic resin film 110, and exposed and developed using a halftone mask (third mask: not shown). A resist layer 111 patterned to a stepped thickness is formed. In the resist layer 111, pixel portions and terminal portions where contact holes are formed are not formed, other pixel portion regions are formed as thick portions 111c, and other portions where no contact holes or pixel electrodes are formed are formed as thin portions 111d. To do.
　次にレジスト層１１１の上から感光性アクリル樹脂膜１１０に露光すると、レジスト層１１１がマスクとなってアクリル系樹脂膜１１０のないコンタクトホールとする部分のみに光が照射される。次に同図（ｌ）に示すように、全面にアッシングを行い、レジスト層１１１ｃ、１１１ｄの厚みを均一に薄くする。アッシングは、画素部領域のレジスト層１１１ｃ以外のレジスト層が除去されて、アクリル系樹脂膜１１０が露出するまで行う。次にフッ素系ガスを用いてプラズマ処理を施す。レジスト層１１１ｃが存在せずアクリル系樹脂膜１１０が表面に露出しているプラズマ処理領域１１３に、撥水性が生じる。次に、画素部領域に残存していたレジスト層１１１ｃを剥離する［同図（ｍ）参照］。 Next, when the photosensitive acrylic resin film 110 is exposed from the top of the resist layer 111, light is irradiated only to a portion where a contact hole without the acrylic resin film 110 is formed using the resist layer 111 as a mask. Next, as shown in FIG. 1L, ashing is performed on the entire surface to uniformly reduce the thickness of the resist layers 111c and 111d. Ashing is performed until the resist layer other than the resist layer 111c in the pixel portion region is removed and the acrylic resin film 110 is exposed. Next, plasma treatment is performed using a fluorine-based gas. Water repellency occurs in the plasma treatment region 113 where the resist layer 111c does not exist and the acrylic resin film 110 is exposed on the surface. Next, the resist layer 111c remaining in the pixel portion region is peeled [see FIG.
　次に同図（ｎ）に示すように、現像を行うと、露光されているコンタクトホールとする部分のアクリル系樹脂膜が除去されて貫通孔１１４が形成される。更にエッチングを行うと貫通孔１１４はソース・ドレイン電極膜に達するコンタクトホールとして形成される。最後に表面に塗布型透明導電膜をスピンコートにより塗布すると、同図（ｏ）に示すように、撥水性が付与されていない部分（プラズマ処理領域以外の部分）のアクリル系樹脂膜１１０の表面、及びコンタクトホール１１４の内側が塗布型透明導電膜１１５で覆われ、画素電極が所定のパターンに形成される。このように特許文献２の方法は、透明導電膜をパターンニングして画素電極を形成する方法として、撥水処理した部分１１３に透明導電膜１１５が形成されないことを利用して、画素電極のパターンを形成する方法である。 Next, as shown in FIG. 9 (n), when development is performed, the exposed acrylic resin film as a contact hole is removed and a through hole 114 is formed. When the etching is further performed, the through hole 114 is formed as a contact hole reaching the source / drain electrode film. Finally, when a coating-type transparent conductive film is applied to the surface by spin coating, the surface of the acrylic resin film 110 in a portion where water repellency is not imparted (portion other than the plasma treatment region) as shown in FIG. The inside of the contact hole 114 is covered with the coating type transparent conductive film 115, and the pixel electrode is formed in a predetermined pattern. As described above, the method of Patent Document 2 is a method of patterning a transparent conductive film, and forming a pixel electrode by utilizing the fact that the transparent conductive film 115 is not formed in the water-repellent portion 113. It is a method of forming.
　また透明導電膜をパターン状に形成する方法として、位相シフトマスクを用いて透明導電膜のパターニングを行う方法が公知である（例えば、特許文献３参照）。特許文献３に記載の方法は、上記の図２０（ｅ）に示す基板１０１の表面にアクリル系樹脂膜１１０を形成した状態から、該アクリル系樹脂膜１１０の表面に透明導電膜をパターニングする。具体的には、図２３（ａ）に示すように、位相シフトマスクを用いて（図示せず）表面の感光性アクリル系樹脂膜１２０に露光を行う。位相シフトマスクは、コンタクトホール形成領域に該当する部分が透過部分とされているので、コンタクトホール１２１のパターンが形成される。また位相シフトマスクの導電膜を形成しない部分に該当する領域は、位相シフト部分として形成されているので、露光を行うと、該当部分の感光性アクリル樹脂膜に垂直に近い溝１２０ａがパターニングされる。 Also, as a method for forming the transparent conductive film in a pattern, a method for patterning the transparent conductive film using a phase shift mask is known (for example, see Patent Document 3). In the method described in Patent Document 3, a transparent conductive film is patterned on the surface of the acrylic resin film 110 from the state where the acrylic resin film 110 is formed on the surface of the substrate 101 shown in FIG. Specifically, as shown in FIG. 23A, the photosensitive acrylic resin film 120 on the surface is exposed using a phase shift mask (not shown). In the phase shift mask, a portion corresponding to the contact hole formation region is a transmission portion, so that a pattern of the contact hole 121 is formed. In addition, since the region corresponding to the portion where the conductive film of the phase shift mask is not formed is formed as a phase shift portion, the groove 120a that is perpendicular to the photosensitive acrylic resin film of the corresponding portion is patterned when exposure is performed. .
　その後、図２３（ｂ）に示すように、スパッタリング法等で感光性アクリル樹脂膜１２０の表面に透明導電膜１２２を全面に形成すると、垂直に近い溝１２０ａがパターニングされた部分の透明導電膜１２２aは、溝１２０ａにより、透明導電膜１２２が電気的に分断される。その結果、絵素電極（画素電極）の形成工程では、フォトマスクを使用せずに液晶表示装置用ＴＦＴアレイ基板（マトリクス基板）を製造可能であるとされている。 Thereafter, as shown in FIG. 23 (b), when a transparent conductive film 122 is formed on the entire surface of the photosensitive acrylic resin film 120 by sputtering or the like, the transparent conductive film 122a in a portion where the groove 120a near vertical is patterned. The transparent conductive film 122 is electrically separated by the groove 120a. As a result, in the pixel electrode (pixel electrode) formation process, it is said that a TFT array substrate (matrix substrate) for a liquid crystal display device can be manufactured without using a photomask.
特開２００２－９８９９５号公報Japanese Patent Laid-Open No. 2002-98995 特開２００２－２５０９３４号公報JP 2002-250934 A 特開２００６－２３５１３４号公報JP 2006-235134 A
　上記特許文献１に記載の方法は、画素電極を所定のパターンに形成する際に、リフトオフ法により画素電極の部分以外の透明導電膜を全て除去するものであるから、除去された透明導電膜等による大量のパーティクルが発生して不良品が増加し易く、歩留まりが悪くなってしまうという問題があった。 In the method described in Patent Document 1, when the pixel electrode is formed in a predetermined pattern, the transparent conductive film other than the part of the pixel electrode is removed by the lift-off method. As a result, a large number of particles are generated, and the number of defective products tends to increase, resulting in a poor yield.
　また上記特許文献２に記載の方法は、画素電極を所定のパターンに形成する際に、撥水処理した領域であっても透明導電膜が形成されてしまうことがあり、透明導電膜を所定の画素電極のパターンに確実に形成するのが容易ではなく、プロセスの制御性が悪いという問題があった。 In the method described in Patent Document 2, a transparent conductive film may be formed even in a water-repellent region when the pixel electrode is formed in a predetermined pattern. There is a problem in that it is not easy to reliably form the pattern of the pixel electrode, and the process controllability is poor.
　また上記特許文献３に記載の方法は、パターンの境界となる溝の幅が狭いため、溝の部分で導電膜が完全に分断されない虞があり、その部分でショートする可能性があるという問題があった。透明導電膜が溝の部分でショートしてしまうと、透明導電膜を所定の画素のパターンに形成することができなくなってしまい、プロセスの制御性が悪いという問題があった。 In addition, the method described in Patent Document 3 has a problem in that since the width of the groove serving as a pattern boundary is narrow, the conductive film may not be completely divided at the groove portion, and there is a possibility of short-circuiting at that portion. there were. If the transparent conductive film is short-circuited at the groove portion, the transparent conductive film cannot be formed in a predetermined pixel pattern, and there is a problem that process controllability is poor.
　上記実状に鑑み、本発明が解決しようとする課題は、マトリクス回路の上に絶縁膜を介して設けられる導電膜を所定のパターンに形成することが容易であり、更に導電膜のパターンを確実に形成可能であり、また製造工程においてパーティクルの発生を少なくし、製品の歩留まりを向上させてプロセスの制御性に優れたマトリクス基板、表示素子、及びマトリクス基板の製造方法を提供することにある。 In view of the above situation, the problem to be solved by the present invention is that it is easy to form the conductive film provided on the matrix circuit via the insulating film in a predetermined pattern, and further, the pattern of the conductive film can be surely formed. An object of the present invention is to provide a matrix substrate, a display element, and a method for manufacturing a matrix substrate that can be formed, reduce generation of particles in the manufacturing process, improve product yield, and have excellent process controllability.
　このような課題を解決するために、本発明のマトリクス基板は、
　基板と、前記基板上に複数のスイッチング素子が設けられてなるマトリクス回路と、前記マトリクス回路の表面に形成されている絶縁膜と、前記絶縁膜の表面に形成されている導電膜と、前記導電膜と前記マトリクス回路を電気的に接続するために形成されているコンタクトホールとを備えるマトリクス基板において、
　前記絶縁膜の表面は、前記導電膜が前記マトリクス回路と電気的に接続されるコンタクト領域と、前記導電膜が前記マトリクス回路と電気的に接続されない非コンタクト領域とからなり、前記コンタクト領域と前記非コンタクト領域は区画部によって分割されており、
　前記区画部は、前記コンタクト領域と前記非コンタクト領域の高低差となる段差として構成され、前記区画部の段差を利用して導電膜のコンタクト領域と非コンタクト領域が電気的に分断されていることを要旨とするものである。 In order to solve such a problem, the matrix substrate of the present invention is
A substrate; a matrix circuit having a plurality of switching elements provided on the substrate; an insulating film formed on a surface of the matrix circuit; a conductive film formed on the surface of the insulating film; In a matrix substrate comprising a film and a contact hole formed to electrically connect the matrix circuit,
The surface of the insulating film includes a contact region in which the conductive film is electrically connected to the matrix circuit and a non-contact region in which the conductive film is not electrically connected to the matrix circuit. The non-contact area is divided by the partition,
The partition is configured as a step difference in height between the contact region and the non-contact region, and the contact region and the non-contact region of the conductive film are electrically separated using the step of the partition. Is a summary.
　また本発明の表示装置は、上記マトリクス基板を備えることを要旨とするものである。 The gist of the display device of the present invention is that it includes the matrix substrate.
　また本発明のマトリクス基板の製造方法は、
　基板と、前記基板上に複数のスイッチング素子が設けられてなるマトリクス回路と、前記マトリクス回路の表面に形成されている絶縁膜と、前記絶縁膜の表面に形成されている導電膜と、前記導電膜と前記マトリクス回路を電気的に接続するために形成されているコンタクトホールとを備えるマトリクス基板の製造方法において、
　前記絶縁膜を形成する際に、前記導電膜が前記マトリクス回路と電気的に接続されるコンタクト領域と、前記導電膜が前記マトリクス回路と電気的に接続されない非コンタクト領域とを区画する区画部が段差となるように前記絶縁膜を形成すると共に、前記絶縁膜にコンタクトホールを設ける絶縁膜形成工程と、
　前記導電膜を形成する際に、前記導電膜のコンタクト領域と非コンタクト領域が前記区画部の段差を利用して電気的に分断されるように導電膜を形成する導電膜形成工程とを備えることを要旨とするものである。 In addition, the method for manufacturing the matrix substrate of the present invention includes:
A substrate; a matrix circuit having a plurality of switching elements provided on the substrate; an insulating film formed on a surface of the matrix circuit; a conductive film formed on the surface of the insulating film; In a method of manufacturing a matrix substrate comprising a film and a contact hole formed to electrically connect the matrix circuit,
When forming the insulating film, there is a partition section that partitions a contact region in which the conductive film is electrically connected to the matrix circuit and a non-contact region in which the conductive film is not electrically connected to the matrix circuit. Forming the insulating film so as to be a step, and forming an insulating film in which a contact hole is provided in the insulating film;
A conductive film forming step of forming the conductive film so that the contact region and the non-contact region of the conductive film are electrically separated using the step of the partition when forming the conductive film. Is a summary.
　本発明のマトリクス基板は、下記の効果を奏する。前記絶縁膜の表面は、前記導電膜が前記マトリクス回路と電気的に接続されるコンタクト領域と、前記導電膜が前記マトリクス回路と電気的に接続されない非コンタクト領域とからなり、前記コンタクト領域と前記非コンタクト領域は区画部によって分割され、前記区画部は、前記コンタクト領域と前記非コンタクト領域の高低差となる段差として構成され、前記区画部の段差を利用して導電膜のコンタクト領域と非コンタクト領域が電気的に分断されている構成を採用したことにより、導電膜のコンタクト領域と非コンタクト領域は段差を利用して両者を電気的に分離することができるので、従来の、同一平面において単なる溝等で両者を電気的に分離する構成のもの等と比較して、両領域間でショートする虞が小さくなって、導電膜を所定のパターンを確実に形成することができる。 The matrix substrate of the present invention has the following effects. The surface of the insulating film includes a contact region in which the conductive film is electrically connected to the matrix circuit and a non-contact region in which the conductive film is not electrically connected to the matrix circuit. The non-contact region is divided by a partition portion, and the partition portion is configured as a step difference in height between the contact region and the non-contact region, and the contact region of the conductive film is not contacted with the step portion of the partition portion. By adopting a configuration in which the region is electrically separated, the contact region and the non-contact region of the conductive film can be electrically separated using a step, so that the conventional method can be used in the same plane. Compared with a structure in which the two are electrically separated by a groove or the like, there is less risk of short-circuiting between the two regions, and the conductive film is placed. It can be a pattern formed reliably.
　また本発明のマトリクス基板は、従来の、非コンタクト領域を撥水性として、当該部分に導電膜が形成されないようにしたものと比較して、非コンタクト領域に導電膜が残っていても、コンタクト領域との境界は段差を利用することで確実に分断させることができるので、導電膜を所定のパターンに確実に形成することができ、製造のプロセス制御性が良い。 In addition, the matrix substrate of the present invention has a non-contact region having water repellency, and the conductive region is not formed in the contact region. Since the boundary between and can be reliably divided by using a step, the conductive film can be reliably formed in a predetermined pattern, and the process controllability of manufacturing is good.
　また本発明のマトリクス基板は、導電膜のコンタクト領域と非コンタクト領域との間が段差を利用して電気的に分断されているから、従来のリフトオフ法のように非コンタクト領域の導電膜を全て除去する必要はないので、非コンタクト領域の導電膜をリフトオフ法により除去する際のように大量のパーティクルが発生する虞はない。そのため、発生したパーティクルが基板に付着して歩留まりが低下することがなく、マトリクス基板の生産性が優れている。 In addition, since the matrix substrate of the present invention electrically separates the contact area and the non-contact area of the conductive film by using a step, the entire conductive film in the non-contact area is completely separated as in the conventional lift-off method. Since it is not necessary to remove the conductive film in the non-contact region, there is no possibility that a large amount of particles are generated unlike when the conductive film in the non-contact region is removed by the lift-off method. Therefore, the generated particles do not adhere to the substrate and the yield does not decrease, and the productivity of the matrix substrate is excellent.
　本発明のマトリクス基板の製造方法は、前記絶縁膜を形成する際に、前記導電膜が前記マトリクス回路と電気的に接続されるコンタクト領域と、前記導電膜が前記マトリクス回路と電気的に接続されない非コンタクト領域とを区画する区画部が段差となるように前記絶縁膜を形成すると共に、前記絶縁膜にコンタクトホールを設ける絶縁膜形成工程と、前記導電膜を形成する際に、前記導電膜のコンタクト領域と非コンタクト領域が前記区画部の段差を利用して電気的に分断されるように導電膜を形成する導電膜形成工程とを備えることにより、上記の所定の導電膜のパターンが形成されたマトリクス基板を容易に製造することができると共に、確実に製造することができる。また本発明のマトリクス基板の製造方法は、製造工程においてパーティクルの発生を少なくすることができ、プロセスの制御性に優れたものである。 In the method for manufacturing a matrix substrate of the present invention, when forming the insulating film, a contact region in which the conductive film is electrically connected to the matrix circuit and the conductive film are not electrically connected to the matrix circuit. The insulating film is formed such that a partition portion that divides the non-contact region is a step, and an insulating film forming step of providing a contact hole in the insulating film, and when forming the conductive film, A conductive film forming step of forming a conductive film so that the contact region and the non-contact region are electrically separated using a step of the partition portion, whereby the predetermined conductive film pattern is formed. In addition, the matrix substrate can be manufactured easily and reliably. In addition, the method for manufacturing a matrix substrate of the present invention can reduce the generation of particles in the manufacturing process and has excellent process controllability.
図１はマトリクス基板の一部を示す厚み方向の断面図である。FIG. 1 is a sectional view in the thickness direction showing a part of a matrix substrate. 図２は図１の平面図である。FIG. 2 is a plan view of FIG. 図３（ａ）～（ｃ）は実施例のＴＦＴ製造工程を示す断面図である。3A to 3C are cross-sectional views showing the TFT manufacturing process of the embodiment. 図４（ｄ）～（ｆ）は実施例のＴＦＴ製造工程を示す断面図である。4D to 4F are cross-sectional views showing the TFT manufacturing process of the example. 図５（ｇ）～（ｉ）は実施例のＴＦＴ製造工程を示す断面図である。FIGS. 5G to 5I are cross-sectional views showing the TFT manufacturing process of the example. 図６（ｊ）は実施例のＴＦＴ製造工程を示す断面図である。FIG. 6J is a cross-sectional view showing the TFT manufacturing process of the example. 図７（ａ）～（ｃ）は第１実施例の製造工程を示す断面図である。7A to 7C are cross-sectional views showing the manufacturing process of the first embodiment. 図８（ｄ）～（ｆ）は第１実施例の製造工程を示す断面図である。8D to 8F are cross-sectional views showing the manufacturing process of the first embodiment. 図９（ｇ）は第１実施例の製造工程を示す断面図である。FIG. 9G is a cross-sectional view showing the manufacturing process of the first embodiment. 図１０（ａ）～（ｃ）は第２実施例の製造工程を示す断面図である。FIGS. 10A to 10C are cross-sectional views showing the manufacturing process of the second embodiment. 図１１（ｄ）～（ｆ）は第２実施例の製造工程を示す断面図である。FIGS. 11D to 11F are cross-sectional views showing the manufacturing process of the second embodiment. 図１２（ｇ）は第２実施例の製造工程を示す断面図である。FIG. 12G is a cross-sectional view showing the manufacturing process of the second embodiment. 図１３（ａ）～（ｄ）は第２実施例の変形例の製造工程を示す断面図である。FIGS. 13A to 13D are cross-sectional views showing manufacturing steps of a modification of the second embodiment. 図１４（ｄ）～（ｆ）は第３実施例の製造工程を示す断面図である。14D to 14F are cross-sectional views showing the manufacturing process of the third embodiment. 図１５（ｇ）、（ｈ）は第３実施例の製造工程を示す断面図であるFIGS. 15G and 15H are cross-sectional views showing the manufacturing process of the third embodiment. 図１６（ａ）、（ｂ）、（ｃ）は、それぞれ、図１４（ｅ）、（ｆ）、図１５（ｈ）の拡大図である。FIGS. 16A, 16B, and 16C are enlarged views of FIGS. 14E, 14F, and 15H, respectively. 図１７は本発明の表示装置の一例である液晶表示装置の概略構成を示す分解斜視図である。FIG. 17 is an exploded perspective view showing a schematic configuration of a liquid crystal display device which is an example of the display device of the present invention. 図１８は図１７の液晶表示装置の概略構成を示す断面図である。18 is a cross-sectional view showing a schematic configuration of the liquid crystal display device of FIG. 図１９は図１７の液晶表示装置の液晶表示パネルの一部を示す断面図である。FIG. 19 is a cross-sectional view showing a part of the liquid crystal display panel of the liquid crystal display device of FIG. 図２０（ａ）～（ｅ）は従来技術の製造工程を示す断面図である。20 (a) to 20 (e) are cross-sectional views showing manufacturing steps of the prior art. 図２１（ｆ）～（ｊ）は従来技術の製造工程を示す断面図である。21 (f) to 21 (j) are cross-sectional views showing the manufacturing steps of the prior art. 図２２（ｋ）～（ｏ）は従来技術の製造工程を示す断面図である。22 (k) to 22 (o) are cross-sectional views showing the manufacturing steps of the prior art. 図２２（ａ）～（ｂ）は従来技術の製造工程を示す断面図である。22 (a) to 22 (b) are cross-sectional views showing manufacturing steps of the prior art.
　以下、本発明の実施例について図面を参照して詳細に説明する。本発明のマトリクス基板の第１実施例は、薄膜トランジスタ（Thin Film Transistor：ＴＦＴ）を用いたアクティブマトリクス型液晶表示装置に用いられるアクティブマトリクス基板（マトリクス基板ということもある）の例である。図１はマトリクス基板の一部を示す厚み方向の断面図であり、図２は平面図である。図１は図２の平面図のＡ－Ａ線断面を示している。図１及び図２に示すように、アクティブマトリクス基板１０には、複数の画素Ｐがマトリクス状に設けられている（図１及び図２では１つの画素の部分のみ示した）。マトリクス基板１０には、基板としてのガラス板等の透明基板１１の表面に、各画素Ｐを駆動するためのスイッチング素子としての薄膜トランジスタ（ＴＦＴ）１２と、ゲート配線２４及びソース配線２５等の配線等からなるマトリクス回路が設けられている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The first embodiment of the matrix substrate of the present invention is an example of an active matrix substrate (also referred to as a matrix substrate) used in an active matrix liquid crystal display device using thin film transistors (TFTs). FIG. 1 is a sectional view in the thickness direction showing a part of the matrix substrate, and FIG. 2 is a plan view. FIG. 1 shows a cross section taken along line AA of the plan view of FIG. As shown in FIGS. 1 and 2, the active matrix substrate 10 is provided with a plurality of pixels P in a matrix (only one pixel portion is shown in FIGS. 1 and 2). The matrix substrate 10 includes a thin film transistor (TFT) 12 as a switching element for driving each pixel P on the surface of a transparent substrate 11 such as a glass plate as a substrate, and wiring such as gate wiring 24 and source wiring 25. A matrix circuit is provided.
　マトリクス基板１０に設けられているマトリクス回路は、複数のゲート配線（走査線とも称されることもある）２４が、所定の間隔をおいて略平行に設けられている。更にマトリクス基板１０には、前記ゲート配線２４と直交する方向に、複数のソース配線（データ線と称されることもある）２５が、所定の間隔をおいて略平行に設けられている。マトリクス基板１０の各ゲート配線２４と各ソース配線２５との交差点近傍に、ＴＦＴ１２が設けられている。 In the matrix circuit provided on the matrix substrate 10, a plurality of gate wirings (sometimes referred to as scanning lines) 24 are provided substantially in parallel with a predetermined interval. In addition, a plurality of source wirings (sometimes referred to as data lines) 25 are provided on the matrix substrate 10 in a direction orthogonal to the gate wirings 24 at a predetermined interval. TFTs 12 are provided in the vicinity of the intersections between the gate lines 24 and the source lines 25 of the matrix substrate 10.
　更にマトリクス基板１０は、図１に示すように、マトリクス回路の表面に絶縁膜として層間絶縁膜１３が設けられている。層間絶縁膜１３の表面には、導電膜として、画素電極１４等を構成するＩＴＯ（Indium Tin Oxide：インジウム酸化スズ）等からなる透明導電膜Ｌが略全面に設けられている。また層間絶縁膜１３には、該絶縁膜１３を厚み方向に貫通する孔からなるコンタクトホール１５、１６、１７が形成されている。透明導電膜Ｌは、画素電極１４及び端子部２６、２７として区画部Ｄにより区画されている。区画部Ｄは段差として形成されている。画素電極１４及び端子部２６、２７は、区画部Ｄにより電気的に分断されている。コンタクトホール１５、１６、１７は、画素電極１４及び端子部２６、２７の透明導電膜Ｌと絶縁層１３の下層のマトリクス回路とを電気的に接続している。 Further, as shown in FIG. 1, the matrix substrate 10 is provided with an interlayer insulating film 13 as an insulating film on the surface of the matrix circuit. On the surface of the interlayer insulating film 13, a transparent conductive film L made of ITO (Indium Tin Oxide) constituting the pixel electrode 14 or the like is provided as a conductive film on substantially the entire surface. The interlayer insulating film 13 is formed with contact holes 15, 16, and 17 that are holes that penetrate the insulating film 13 in the thickness direction. The transparent conductive film L is partitioned by the partition portion D as the pixel electrode 14 and the terminal portions 26 and 27. The partition portion D is formed as a step. The pixel electrode 14 and the terminal portions 26 and 27 are electrically separated by the partition portion D. The contact holes 15, 16, and 17 electrically connect the transparent conductive film L of the pixel electrode 14 and the terminal portions 26 and 27 and the matrix circuit below the insulating layer 13.
　マトリクス回路のＴＦＴ１２は、図１及び図２に示すように、透明基板１１の表面に形成されたゲート電極１２ｃと、該ゲート電極１２ｃ上に形成されたゲート絶縁膜２１と、該ゲート絶縁膜２１上に形成されチャネル領域Ｑを備える半導体膜２２と、半導体膜２２の一端に接続されたソース電極１２ａと、半導体膜２２の他端に接続され、ソース電極１２ａに対してチャネル領域Ｑを介して接続されるドレイン電極１２ｂとを備えている。ソース電極１２ａには、画像信号を供給するためのソース配線２５が接続されている。ソース電極１２ａ及びドレイン電極１２ｂの上に、層間絶縁膜１３が設けられている。 As shown in FIGS. 1 and 2, the TFT 12 of the matrix circuit includes a gate electrode 12c formed on the surface of the transparent substrate 11, a gate insulating film 21 formed on the gate electrode 12c, and the gate insulating film 21. A semiconductor film 22 having a channel region Q formed thereon, a source electrode 12a connected to one end of the semiconductor film 22, and a second electrode connected to the other end of the semiconductor film 22 via the channel region Q. And a drain electrode 12b to be connected. A source wiring 25 for supplying an image signal is connected to the source electrode 12a. An interlayer insulating film 13 is provided on the source electrode 12a and the drain electrode 12b.
　層間絶縁膜１３は、特に図示しないが、ＴＦＴ１２のすぐ上に形成される窒化シリコン（ＳｉＮｘ）等からなる無機系絶縁膜と、その上層に形成されるアクリル系樹脂等からなる有機系絶縁膜との２層の積層膜として形成されている。 Although not specifically shown, the interlayer insulating film 13 includes an inorganic insulating film made of silicon nitride (SiNx) or the like formed immediately above the TFT 12, and an organic insulating film made of an acrylic resin or the like formed on the upper layer. It is formed as a two-layer laminated film.
　画素電極１４は、ＴＦＴ１２のドレイン電極１２ｂに、コンタクトホール１５を介して接続されている。ＴＦＴ１２を一定期間だけオン状態とすることで、ソース配線２５から供給される画像信号が各画素Ｐに所定のタイミングで書き込まれる。 The pixel electrode 14 is connected to the drain electrode 12 b of the TFT 12 through the contact hole 15. By turning on the TFT 12 for a certain period, the image signal supplied from the source wiring 25 is written to each pixel P at a predetermined timing.
　ソース電極１２ａ及びドレイン電極１２ｂ並びにソース電極１２ａに接続されたソース配線２５は、ドーピング半導体膜１８、第２導電膜１９が積層された積層体から構成されている。ドーピング半導体膜１８は、例えばリン（Ｐ）等のｎ型不純物を高濃度にドーピングしたアモルファスシリコン（ｎ＋Ｓｉ）等からなり、第２導電膜１９は、例えばアルミニウム（Ａｌ）、クロム（Ｃｒ）、タンタル（Ｔａ）、チタン（Ｔｉ）等の金属膜単体、これらの金属窒化物等との積層体等から形成することができる。ソース配線２５は、透明導電膜Ｌが形成されたコンタクトホール１６を端子部２６として画像信号を供給するためのソース信号供給回路（図示せず）に繋がる配線に接続される。 The source electrode 12a, the drain electrode 12b, and the source wiring 25 connected to the source electrode 12a are composed of a stacked body in which a doping semiconductor film 18 and a second conductive film 19 are stacked. The doped semiconductor film 18 is made of amorphous silicon (n + Si) doped with n-type impurities such as phosphorus (P) at a high concentration, and the second conductive film 19 is made of, for example, aluminum (Al), chromium (Cr), tantalum. It can be formed from a single metal film such as (Ta) or titanium (Ti), or a laminate of these metal nitrides. The source wiring 25 is connected to a wiring connected to a source signal supply circuit (not shown) for supplying an image signal using the contact hole 16 in which the transparent conductive film L is formed as a terminal portion 26.
　またＴＦＴ１２のゲート電極１２ｃには、所定のタイミングで走査信号を線順次に印加するためのゲート配線２４が接続されている。ゲート配線２４は、透明導電膜Ｌが形成されたコンタクトホール１７を端子部２７として走査信号供給回路（図示せず）に繋がる配線に接続される。 Further, a gate wiring 24 for applying a scanning signal line-sequentially at a predetermined timing is connected to the gate electrode 12c of the TFT 12. The gate wiring 24 is connected to a wiring connected to a scanning signal supply circuit (not shown) using the contact hole 17 in which the transparent conductive film L is formed as a terminal portion 27.
　図１に示すように、透明導電膜Ｌは、マトリクス回路と電気的に接続されるコンタクト領域ＣＡと、該コンタクト領域ＣＡ以外の領域のマトリクス回路と電気的に接続されない非コンタクト領域ＮＡとから構成されている。コンタクト領域ＣＡは、画素電極１４と端子部２６、２７等から構成されている。透明導電膜Ｌは、コンタクト領域ＣＡと非コンタクト領域ＮＡの境界に設けられた区画部Ｄによって領域が分割されている。そして、層間絶縁膜１３の区画部Ｄが、コンタクト領域ＣＡと非コンタクト領域ＮＡの高低差となる段差として形成されている。この区画部Ｄの段差として形成されている層間絶縁膜１３の側壁表面には、透明導電膜Ｌが形成されていない部分がある。そのため、コンタクト領域ＣＡと非コンタクト領域ＮＡは、電気的に分断されることになる。コンタクト領域ＣＡと非コンタクト領域ＮＡは電気的に分断されているので、非コンタクト領域ＣＡの表面に透明導電膜Ｌが残っていてもよい。すなわち、層間絶縁膜１３の表面の全面に透明導電膜Ｌを形成した後、層間絶縁膜１３表面の非コンタクト領域ＮＡの透明導電膜Ｌを除去しなくてもよい。 As shown in FIG. 1, the transparent conductive film L includes a contact area CA that is electrically connected to the matrix circuit and a non-contact area NA that is not electrically connected to the matrix circuit in a region other than the contact area CA. Has been. The contact area CA includes the pixel electrode 14 and terminal portions 26 and 27. The transparent conductive film L is divided into regions by a partition portion D provided at the boundary between the contact region CA and the non-contact region NA. A partition portion D of the interlayer insulating film 13 is formed as a step difference in height between the contact area CA and the non-contact area NA. There is a portion where the transparent conductive film L is not formed on the side wall surface of the interlayer insulating film 13 formed as a step of the partition portion D. Therefore, the contact area CA and the non-contact area NA are electrically separated. Since the contact area CA and the non-contact area NA are electrically separated, the transparent conductive film L may remain on the surface of the non-contact area CA. That is, after forming the transparent conductive film L on the entire surface of the interlayer insulating film 13, it is not necessary to remove the transparent conductive film L in the non-contact region NA on the surface of the interlayer insulating film 13.
　図１に示すように、マトリクス基板１０は、層間絶縁膜１３の表面が、コンタクトホール１５、１６、１７の部分を除く各領域は、コンタクト領域ＣＡ及び非コンタクト領域ＮＡのいずれも、それぞれ表面に凹凸や溝のない平坦面として形成されている。 As shown in FIG. 1, in the matrix substrate 10, the surface of the interlayer insulating film 13 except for the contact holes 15, 16, and 17 has a contact area CA and a non-contact area NA on the surface. It is formed as a flat surface without irregularities and grooves.
　層間絶縁膜１３は、平坦面として形成されているコンタクト領域ＣＡの高さと、非コンタクト領域ＮＡの高さが、異なるように形成されている。すなわち、層間絶縁膜１３のコンタクト領域ＣＡの厚みと非コンタクト領域ＮＡの厚みとが相違する。コンタクト領域ＣＡの表面と非コンタクトＮＡの表面は同一平面に形成されていない。コンタクト領域ＣＡの高さと、非コンタクト領域ＮＡの高さはどちらが高くてもよいが、図２の態様では、コンタクト領域ＣＡの層間絶縁膜１３の表面の高さが、非コンタクト領域ＮＡの層間絶縁膜１３の表面の高さよりも高くなるように形成されている。 The interlayer insulating film 13 is formed so that the height of the contact area CA formed as a flat surface is different from the height of the non-contact area NA. That is, the thickness of the contact area CA of the interlayer insulating film 13 is different from the thickness of the non-contact area NA. The surface of the contact area CA and the surface of the non-contact NA are not formed on the same plane. Either the height of the contact area CA or the height of the non-contact area NA may be high, but in the embodiment of FIG. 2, the height of the surface of the interlayer insulating film 13 in the contact area CA is the interlayer insulation of the non-contact area NA. It is formed so as to be higher than the height of the surface of the film 13.
　透明導電膜Ｌは、区画部Ｄの部分を除いて、層間絶縁膜１３の表面に略全面に亘り形成されている。層間絶縁膜１３の区画部Ｄの段差の部分となる側壁の表面は、コンタクト領域ＣＡと非コンタクト領域ＮＡが電気的に分断されている。区画部の側壁に透明導電膜Ｌが形成されていても段差の上と下とで導通しないように形成されていれば良い。好ましくは、図１に示すように、区画部Ｄの層間絶縁膜１３の側壁全体に透明導電膜Ｌが形成されていないことである。側壁全体に透明導電膜Ｌが形成されていないと、コンタクト領域ＣＡと非コンタクト領域ＮＡの間の区画部Ｄにパーティクル等が付着した際に、区画部Ｄにおいて隣接する領域間でショートする可能性が低くなる。より確実に透明導電膜を分断することができるという利点がある。 The transparent conductive film L is formed over the entire surface of the interlayer insulating film 13 except for the partition portion D. The contact region CA and the non-contact region NA are electrically separated from each other on the surface of the side wall that becomes the step portion of the partition portion D of the interlayer insulating film 13. Even if the transparent conductive film L is formed on the side wall of the partition part, it may be formed so as not to be conductive between the upper and lower steps. Preferably, as shown in FIG. 1, the transparent conductive film L is not formed on the entire side wall of the interlayer insulating film 13 in the partition portion D. If the transparent conductive film L is not formed on the entire side wall, when particles or the like adhere to the partition portion D between the contact area CA and the non-contact region NA, there is a possibility of short-circuiting between adjacent regions in the partition portion D. Becomes lower. There is an advantage that the transparent conductive film can be divided more reliably.
　以下、上記第１実施例のマトリクス基板の製造方法について説明する。本発明のマトリクス基板の製造方法は、大きく分けて（１）ガラス基板上にＴＦＴを形成し層間絶縁膜を形成するＴＦＴ形成工程、（２）層間絶縁膜にコンタクトホールを形成し表面に段差を形成する絶縁膜形成工程、（３）層間絶縁膜の表面に透明導電膜を形成する導電膜形成工程から構成される。本発明の製造方法において上記（１）ＴＦＴ形成工程は、従来と同様の方法により形成することができる。この工程は、後述する第２実施例及び第３実施例においても共通する工程である。本発明は次の（２）絶縁膜形成工程及び（３）導電膜形成工程に大きな特徴がある。以下、各工程を順次説明する。 Hereinafter, a method for manufacturing the matrix substrate of the first embodiment will be described. The manufacturing method of the matrix substrate of the present invention can be broadly divided into (1) a TFT forming step in which a TFT is formed on a glass substrate to form an interlayer insulating film, and (2) a contact hole is formed in the interlayer insulating film and a step is formed on the surface. An insulating film forming step to be formed; and (3) a conductive film forming step of forming a transparent conductive film on the surface of the interlayer insulating film. In the manufacturing method of the present invention, the (1) TFT forming step can be formed by a method similar to the conventional method. This process is a process common to the second and third embodiments described later. The present invention is greatly characterized in the following (2) insulating film forming step and (3) conductive film forming step. Hereinafter, each process is demonstrated one by one.
図３（ａ）～（ｃ）、図４（ｄ）～（ｆ）、図５（ｇ）～（ｉ）、図６（ｊ）はＴＦＴ形成工程を示し、（ａ）～（ｊ）は各工程の断面図である。まず図３（ａ）に示すように、透明絶縁性を有する透明基板１１の表面全面に、金属膜等からなる第１導電膜２０を形成する。透明基板１１は、厚み０．５ｍｍ、０．７ｍｍ、１．１ｍｍ等のガラス、プラスチック等を用いることができる。第１導電膜２０は、通常、スパッタリング法により１０００Å～３０００Åの厚みに形成することができる。第１導電膜２０は、例えばチタン（Ｔｉ）、クロム（Ｃｒ）、アルミニウム（Ａｌ）、モリブデン（Ｍｏ）、タンタル（Ｔａ）、タングステン（Ｗ）、銅（Ｃｕ）等の金属膜、モリブデンタンタル（ＭｏＴａ）、モリブデンタングステン（ＭｏＷ）等の合金膜、又は、これらの積層膜等を用いることができる。 3 (a) to (c), FIGS. 4 (d) to (f), FIGS. 5 (g) to (i), and FIG. 6 (j) show the TFT forming process, and FIGS. It is sectional drawing of each process. First, as shown in FIG. 3A, a first conductive film 20 made of a metal film or the like is formed on the entire surface of the transparent substrate 11 having transparent insulation. The transparent substrate 11 can be made of glass, plastic, or the like having a thickness of 0.5 mm, 0.7 mm, 1.1 mm, or the like. The first conductive film 20 can be usually formed to a thickness of 1000 to 3000 mm by a sputtering method. The first conductive film 20 is made of, for example, a metal film such as titanium (Ti), chromium (Cr), aluminum (Al), molybdenum (Mo), tantalum (Ta), tungsten (W), copper (Cu), molybdenum tantalum ( An alloy film such as MoTa) or molybdenum tungsten (MoW), or a stacked film of these can be used.
　次に同図（ｂ）に示すように、第１導電膜２０の上に、フォトレジストを塗布し、第１のフォトマスク（図示せず）を用いて、露光、現像を行い、ゲート電極及びゲート配線となる領域のパターン状にレジスト４０を形成する。 Next, as shown in FIG. 4B, a photoresist is applied on the first conductive film 20, and exposure and development are performed using a first photomask (not shown), and the gate electrode and A resist 40 is formed in a pattern of a region to be a gate wiring.
　次に同図（ｃ）に示すように、ドライエッチング又はウェットエッチングによって、レジスト４０に覆われていない領域の第１導電膜２０を除去して、ゲート電極１２ｃ及びゲート配線２４等を形成する。そして酸素を使用したプラズマアッシングによって、レジスト４０を除去する。 Next, as shown in FIG. 5C, the first conductive film 20 in the region not covered with the resist 40 is removed by dry etching or wet etching, and the gate electrode 12c, the gate wiring 24, and the like are formed. Then, the resist 40 is removed by plasma ashing using oxygen.
　次に図４（ｄ）に示すように、ゲート電極１２ｃ及びゲート配線２４の上に、ゲート絶縁膜２１、半導体膜２２、ドーピング半導体膜１８、第２導電膜１９を続けて形成する。ゲート絶縁膜２１、半導体膜２２、ドーピング半導体膜１８はプラズマＣＶＤ法を使用して形成する。通常、この３層膜は、同一装置内で連続的に形成される。ゲート絶縁膜２１は、窒化シリコン（ＳｉＮｘ）、酸化シリコン膜（ＳｉＯｘ）等で形成される。半導体膜２２は、例えばアモルファスシリコン（ａ－Ｓｉ）膜で形成される。ドーピング半導体膜１８は、リン（Ｐ）等のｎ型不純物を高濃度にドーピングしたアモルファスシリコン（ｎ＋Ｓｉ）膜で形成される。第２導電膜１９は、通常、スパッタリング法を使用して、アルミニウム（Ａｌ）、クロム（Ｃｒ）、タンタル（Ｔａ）、チタン（Ｔｉ）等の金属膜単体又はこれらの金属窒化物との積層膜で形成される。 Next, as shown in FIG. 4D, the gate insulating film 21, the semiconductor film 22, the doping semiconductor film 18, and the second conductive film 19 are successively formed on the gate electrode 12 c and the gate wiring 24. The gate insulating film 21, the semiconductor film 22, and the doping semiconductor film 18 are formed using a plasma CVD method. Usually, this three-layer film is formed continuously in the same apparatus. The gate insulating film 21 is formed of silicon nitride (SiNx), silicon oxide film (SiOx), or the like. The semiconductor film 22 is formed of, for example, an amorphous silicon (a-Si) film. The doped semiconductor film 18 is formed of an amorphous silicon (n + Si) film doped with an n-type impurity such as phosphorus (P) at a high concentration. The second conductive film 19 is usually formed of a metal film such as aluminum (Al), chromium (Cr), tantalum (Ta), titanium (Ti) or a laminated film of these metal nitrides using a sputtering method. Formed with.
　次に同図（ｅ）に示すように、第２導電膜１９の上に、フォトレジストを塗布し、第２のフォトマスク（図示せず）を用いて、露光、現像を行い、ＴＦＴ１２の活性化領域、ＴＦＴ１２のチャネル領域Ｑ、ソース電極１２ａ、ソース配線２５、及びドレイン電極１２ｂとなる領域のパターンのレジスト４０を形成する。レジスト４０は、第２のフォトマスクとしてハーフトーンマスク又はグレイトーンマスク等の多階調マスクを使用して、ＴＦＴ１２のチャネルとなる領域Ｑ上に、ＴＦＴの活性化領域、ソース電極、ソース配線及びドレイン電極となる領域上よりも薄い膜厚の薄膜部４１を形成する。レジスト４０の薄膜部以外の部分は厚膜部４２として形成される。 Next, as shown in FIG. 4E, a photoresist is applied on the second conductive film 19, and exposure and development are performed using a second photomask (not shown) to activate the TFT 12. A resist 40 is formed in a pattern to be the formation region, the channel region Q of the TFT 12, the source electrode 12a, the source wiring 25, and the drain electrode 12b. The resist 40 uses a multi-tone mask such as a halftone mask or a gray tone mask as the second photomask, and the TFT activation region, the source electrode, the source wiring, and the region on the region Q serving as the channel of the TFT 12. A thin film portion 41 having a thickness smaller than that on the region to be the drain electrode is formed. A portion other than the thin film portion of the resist 40 is formed as a thick film portion 42.
　レジスト材料は、ネガ型、ポジ型の感光性レジスト材料のいずれを用いても良い。多階調フォトマスク（単に多階調マスクと言うこともある）は、光を遮光する遮光部（黒）と光を透過する透過光部（白）の２階調でパターンが構成されているバイナリマスクに対し、遮光部（黒）と透過光部（白）に加え光を半透過させる半透過光部（グレイ）からなる３階調以上のフォトマスクとして構成されている。多階調フォトマスクには、グレイトーンマスクとハーフトーンマスクがある。ハーフトーンマスクは、半透過光部の遮光膜をエッチング等の手段により、遮光部の厚さよりも薄く形成することにより、光の透過量を減少させるように半透過光部を構成したものである。グレイトーンマスクは、半透過光部として露光機解像限界以下の微細パターンを設けることで、光の回折効果を利用するものである。多階調フォトマスクを用いた場合、バイナリマスクを用いた場合と比較して、膜厚差のあるレジスト層を形成する場合に、一度の露光と現像で膜厚差のあるレジストパターンを形成可能であるから、工程を短縮することができる。 The resist material may be either a negative photosensitive resist material or a positive photosensitive resist material. A multi-tone photomask (sometimes referred to simply as a multi-tone mask) has a pattern composed of two gradations, a light-shielding portion (black) that blocks light and a transmitted light portion (white) that transmits light. The binary mask is configured as a photomask having three or more gradations including a light-shielding portion (black) and a transmitted light portion (white), and a semi-transmitted light portion (gray) that semi-transmits light. The multi-tone photomask includes a gray tone mask and a halftone mask. The halftone mask is a semi-transparent light portion configured to reduce the amount of light transmitted by forming the light-shielding film of the semi-transmissive light portion thinner than the thickness of the light shielding portion by means such as etching. . The gray tone mask uses a light diffraction effect by providing a fine pattern below the exposure machine resolution limit as a semi-transmissive light portion. When a multi-tone photomask is used, a resist pattern with a film thickness difference can be formed by a single exposure and development when a resist layer with a film thickness difference is formed compared to when a binary mask is used. Therefore, the process can be shortened.
　このようにレジスト４０の形成は、膜厚差を形成可能な方法であれば、多階調フォトマスクを使用する方法に限定されずどのような方法を用いてもよい。例えば多階調フォトマスクを使用する代わりに、バイナリマスクを用いて露光量を変えたり、複数の露光を行ったりして、複数のバイナリマスクを用いる方法等を用いて膜厚差のあるレジスト４０を形成してもよい。 Thus, the formation of the resist 40 is not limited to a method using a multi-tone photomask as long as it can form a film thickness difference, and any method may be used. For example, instead of using a multi-tone photomask, a resist 40 having a film thickness difference using a method using a plurality of binary masks by changing the exposure amount using a binary mask or performing a plurality of exposures. May be formed.
　次に同図（ｆ）に示すように、ドライエッチング又はウェットエッチングによって、まずレジスト４０に覆われていない領域の第２導電膜１９、ドーピング半導体膜１８、半導体膜２２を除去して、薄膜トランジスタ活性領域、ソース電極１２ａ、ソース配線２５及びドレイン電極１２ｂを形成する。 Next, as shown in FIG. 5F, first, the second conductive film 19, the doped semiconductor film 18 and the semiconductor film 22 in a region not covered with the resist 40 are removed by dry etching or wet etching, so that the thin film transistor is activated. A region, a source electrode 12a, a source wiring 25, and a drain electrode 12b are formed.
　次に図５（ｇ）に示すように、酸素プラズマを使用したアッシングによって、ＴＦＴのチャネルとなる領域Ｑ上に薄く形成した薄膜部４１を除去する。レジスト４０は厚膜部４２だけが残る。 Next, as shown in FIG. 5G, the thin film portion 41 formed thinly on the region Q to be a TFT channel is removed by ashing using oxygen plasma. Only the thick film portion 42 remains in the resist 40.
　次に同図（ｈ）に示すように、再度ドライエッチング又はウェットエッチングによって、レジスト４０を除去した部分をエッチングして、第２導電膜、ドーピング半導体膜を除去してＴＦＴ１２のチャネル領域Ｑを形成する。 Next, as shown in FIG. 5H, the portion where the resist 40 is removed is etched again by dry etching or wet etching, and the second conductive film and the doped semiconductor film are removed to form the channel region Q of the TFT 12. To do.
　次に同図（ｉ）に示すように、酸素プラズマを使用したアッシングによって残りのレジストの厚膜部４２を除去する。 Next, as shown in FIG. 5I, the remaining resist thick film portion 42 is removed by ashing using oxygen plasma.
　次に、図６（ｊ）に示すように、ＴＦＴ１２を形成した基板表面の全面に窒化シリコン膜（ＳｉＮｘ）からなる無機系絶縁膜、アクリル樹脂からなる平坦化膜(有機系絶縁膜)を順次形成して、未処理の状態の層間絶縁膜１３ａを形成する。このようにして、ＴＦＴが設けられたマトリクス回路の上の全面が層間絶縁膜１３ａで覆われた状態になる。 Next, as shown in FIG. 6J, an inorganic insulating film made of a silicon nitride film (SiNx) and a planarizing film (organic insulating film) made of acrylic resin are sequentially formed on the entire surface of the substrate on which the TFT 12 is formed. Then, an unprocessed interlayer insulating film 13a is formed. In this way, the entire upper surface of the matrix circuit provided with the TFT is covered with the interlayer insulating film 13a.
　上記窒化シリコン膜は、ＴＦＴ１２の形状に追従するように形成され、上記平坦化膜は表面が平坦に形成され、未処理の層間絶縁膜１３ａの表面は平坦に形成されている。上記無機系絶縁膜は０．２～０．３μｍ程度の厚みに形成され、平坦化膜は１．８～２．２μｍ程度の厚みに形成される。特に図示しないが、無機系絶縁膜は、絶縁膜に主としてパッシベーションの機能を持たせてＴＦＴの安定動作に寄与している。いる。また平坦化膜は未処理の状態の層間絶縁膜１３ａの表面を平坦化する層として形成されている。 The silicon nitride film is formed so as to follow the shape of the TFT 12, the surface of the planarizing film is formed flat, and the surface of the unprocessed interlayer insulating film 13a is formed flat. The inorganic insulating film is formed to a thickness of about 0.2 to 0.3 μm, and the planarizing film is formed to a thickness of about 1.8 to 2.2 μm. Although not particularly shown, the inorganic insulating film contributes to the stable operation of the TFT by providing the insulating film mainly with a passivation function. Yes. The planarizing film is formed as a layer for planarizing the surface of the unprocessed interlayer insulating film 13a.
　図７（ａ）～（ｃ）、図８（ｄ）～（ｅ）は第１実施例の絶縁膜形成工程を示し、（ａ）～（ｅ）は各工程の断面図である。絶縁膜形成工程は、層間絶縁膜１３ａに、図１に示すように、コンタクトホール１５、１６、１７と、区画部Ｄの段差を形成する工程である。区画部Ｄは、透明導電膜Ｌがマトリクス回路と電気的に接続されるコンタクト領域ＣＡと、透明導電膜Ｌが前記マトリクス回路と電気的に接続されない非コンタクト領域ＮＡとを区画する部分である。 FIGS. 7A to 7C and FIGS. 8D to 8E show the insulating film forming steps of the first embodiment, and FIGS. 7A to 7E are cross-sectional views of the respective steps. The insulating film forming step is a step of forming steps in the contact holes 15, 16, and 17 and the partition portion D in the interlayer insulating film 13a as shown in FIG. The partition portion D is a portion that partitions a contact area CA in which the transparent conductive film L is electrically connected to the matrix circuit and a non-contact area NA in which the transparent conductive film L is not electrically connected to the matrix circuit.
　絶縁膜形成工程では、先ず図７（ａ）に示すように、層間絶縁膜１３ａの表面に、フォトレジストを塗布しレジスト４０を形成し、該レジスト４０に対し第３のフォトマスクとして多階調マスク（特に図示せず）を用いて、露光と現像を行う。レジスト４０は、コンタクトホールを形成する部分が除去され、コンタクト領域ＣＡのレジストが厚膜部４２となり、非コンタクト領域のレジストが薄膜部４１となる多段レジスト膜として形成される。 In the insulating film forming step, first, as shown in FIG. 7A, a photoresist is applied to the surface of the interlayer insulating film 13a to form a resist 40, and a multi-tone is formed as a third photomask for the resist 40. Exposure and development are performed using a mask (not shown). The resist 40 is formed as a multistage resist film in which the contact hole forming portion is removed, the resist in the contact region CA becomes the thick film portion 42, and the resist in the non-contact region becomes the thin film portion 41.
　次に同図（ｂ）に示すように、層間絶縁膜１３ａのドライエッチングを行う。ドライエッチングは、コンタクトホールの部分１５ａ、１６ａ、１７ａを途中までエッチングする。次に同図（ｃ）に示すように、レジスト４０を酸素プラズマ等を用いてアッシングする。アッシングは、レジストの薄膜部４１が除去されるまで行う。層間絶縁膜１３ａの上のレジスト５０は、厚膜部４２のみが残存する。 Next, as shown in FIG. 4B, the interlayer insulating film 13a is dry-etched. In the dry etching, the contact hole portions 15a, 16a, and 17a are etched halfway. Next, as shown in FIG. 2C, the resist 40 is ashed using oxygen plasma or the like. Ashing is performed until the thin film portion 41 of the resist is removed. Only the thick film portion 42 remains on the resist 50 on the interlayer insulating film 13a.
　次に図８（ｄ）に示すように、層間絶縁膜１３ａのドライエッチングを行う。層間絶縁膜１３ａは、ドライエッチングにより、コンタクトホールの部分１５ａ、１６ａ、１７ａが引き続きエッチングされると共に、薄膜部４１が除去された部分（非コンタクト領域ＮＡ）がエッチングされる。 Next, as shown in FIG. 8D, the interlayer insulating film 13a is dry-etched. In the interlayer insulating film 13a, the contact hole portions 15a, 16a, and 17a are continuously etched by dry etching, and the portion from which the thin film portion 41 is removed (non-contact region NA) is etched.
　次にレジスト４０を酸素プラズマ等でアッシングして、厚膜部４２を除去して、レジストを全部除去する。同図（ｅ）に示すように、区画部Ｄが段差として形成され、コンタクトホール１５、１６、１７が所定の位置に形成された層間絶縁膜１３が得られる。非コンタクト領域ＮＡのエッチングの深さ、すなわち区画部Ｄの段差の高さは、０．３～０．４μｍ程度に形成される。 Next, the resist 40 is ashed with oxygen plasma or the like to remove the thick film portion 42, and the resist is completely removed. As shown in FIG. 5E, the interlayer insulating film 13 in which the partition portion D is formed as a step and the contact holes 15, 16, and 17 are formed at predetermined positions is obtained. The etching depth of the non-contact area NA, that is, the height of the step of the partition portion D is formed to be about 0.3 to 0.4 μm.
　このようなコンタクトホール１５、１６、１７や非コンタクト領域ＮＡのエッチングのように、深さ方向にエッチングを行う場合、反応性イオンエッチング（ＲＩＥ）等のような異方性エッチング法を用いることが好ましい。ＲＩＥは例えばコンタクトホールのエッチング等では、側面に反応物が析出しエッチングが側面方向に進行しにくくなるので、深さ方向にエッチングが選択的に進行し易く、比較的壁面が垂直に近く形成される。 When etching is performed in the depth direction, such as etching of the contact holes 15, 16, 17 and the non-contact area NA, an anisotropic etching method such as reactive ion etching (RIE) is used. preferable. In RIE, for example, when a contact hole is etched, a reaction product is deposited on the side surface and the etching does not easily proceed in the direction of the side surface. Therefore, the etching is likely to proceed selectively in the depth direction, and the wall surface is formed relatively vertically. The
　図８（ｆ）及び図９（ｇ）は、第１実施例の導電膜形成工程を示し、（ｆ）、（ｇ）はそれぞれ各工程の断面図である。導電膜形成工程は、透明導電膜を形成する際に、透明導電膜Ｌのコンタクト領域ＣＡと非コンタクト領域ＮＡが前記区画部Ｄの段差を利用して電気的に分断されるように形成するものである。以下、導電膜形成工程について説明する。 8 (f) and 9 (g) show the conductive film forming process of the first embodiment, and (f) and (g) are sectional views of the respective processes. In the conductive film forming step, when forming the transparent conductive film, the contact area CA and the non-contact area NA of the transparent conductive film L are formed so as to be electrically separated using the step of the partition portion D. It is. Hereinafter, the conductive film forming step will be described.
　先ず図８（ｆ）に示すように、導電膜形成工程は、先ず区画部Ｄの段差とコンタクトホール１５、１６、１７が形成された層間絶縁膜１３の表面全体に、ＩＴＯ膜等の透明導電膜Ｌをスパッタ法で形成する。透明導電膜Ｌは、スパッタ条件を調整し、区画部Ｄの側壁部の厚みを平面部の厚みよりも薄く形成する。一般にスパッタ法では、ＩＴＯ原子が平面部にほぼ垂直に入射するように行う。そのため、通常、スパッタ法で透明導電膜Ｌを形成すると、側壁部は平面部よりも薄く形成される。透明導電膜Ｌは、ＩＴＯ以外に、ＩＺＯ（indium-zinc oxide）、酸化亜鉛、酸化スズ等の透明導電性材料を用いることができる。透明導電膜Ｌは、通常、１０００Å～２０００Åの厚みに製膜する。 First, as shown in FIG. 8F, in the conductive film forming step, first, a transparent conductive material such as an ITO film is formed on the entire surface of the interlayer insulating film 13 in which the step of the partition portion D and the contact holes 15, 16, and 17 are formed. The film L is formed by sputtering. The transparent conductive film L adjusts sputtering conditions, and forms the thickness of the side wall part of the partition part D thinner than the thickness of a plane part. In general, sputtering is performed so that ITO atoms are incident on the plane portion substantially perpendicularly. Therefore, usually, when the transparent conductive film L is formed by a sputtering method, the side wall portion is formed thinner than the planar portion. For the transparent conductive film L, a transparent conductive material such as IZO (indium-zinc oxide), zinc oxide, tin oxide, etc. can be used in addition to ITO. The transparent conductive film L is usually formed to a thickness of 1000 to 2000 mm.
　次に図９（ｇ）に示すように、透明導電膜Ｌの表面をプラズマエッチングによりエッチングして、区画部Ｄの側壁の透明導電膜を除去する。側壁部の透明導電膜はＩＴＯのスパッタ法で形成されているので、平面部よりも薄く形成されている。そのため、側壁部の透明導電膜のみを除去し平面部の透明導電膜を残すことは容易である。また、このエッチングの際に、コンタクトホール１５、１６、１７の内壁の透明導電膜が除去されないようにエッチング条件を設定する。具体的には、エッチングレートが反応性ガスの供給律速となる条件とすることである。一般的に反応性ガスは、大きな開口面を持つ段差Ｄの側壁部に対し、開口面の小さいコンタクトホールの内部の側壁に供給されにくい。反応性ガスが供給されにくいコンタクトホールの内部の側壁は、段差の側壁よりもエッチングレートが低下する。エッチングレートが反応性ガスの供給律速となるようにするには、反応性ガスの供給量を増加させるか、又は反応性ガスの圧力を増加させるといった手段を用いることができる。 Next, as shown in FIG. 9G, the surface of the transparent conductive film L is etched by plasma etching to remove the transparent conductive film on the side wall of the partition portion D. Since the transparent conductive film on the side wall portion is formed by the ITO sputtering method, it is formed thinner than the flat portion. Therefore, it is easy to remove only the transparent conductive film on the side wall part and leave the transparent conductive film on the flat part. In this etching, the etching conditions are set so that the transparent conductive film on the inner walls of the contact holes 15, 16, and 17 is not removed. Specifically, the etching rate is set to be a condition that determines the supply rate of the reactive gas. In general, the reactive gas is unlikely to be supplied to the side wall inside the contact hole having a small opening surface with respect to the side wall portion of the step D having a large opening surface. The etching rate of the side wall inside the contact hole to which the reactive gas is difficult to be supplied is lower than the side wall of the step. In order to make the etching rate the rate of supply of the reactive gas, means such as increasing the supply amount of the reactive gas or increasing the pressure of the reactive gas can be used.
　上記の通り層間絶縁膜１３の上に透明導電膜Ｌを形成した後、区画部Ｄの段差の側壁部の透明導電膜をエッチングにより除去することで、透明導電膜Ｌが画素電極１４、端子部２６、２７の所定のパターンに形成され、コンタクト領域ＣＡが層間絶縁膜１３に形成されたマトリクス基板１０が得られる。また層間絶縁膜１３は、コンタクト領域ＣＡ以外のＴＦＴ素子１２、ソース配線２５、ゲート配線２４の部分が非コンタクト領域ＮＡとして形成される。透明導電膜Ｌは非コンタクト領域ＮＡにも形成されていて残存しているが、段差の部分が区画部Ｄとなって上記コンタクト領域ＣＡと電気的に分断されている。そのため非コンタクト領域ＮＡの部分の透明導電膜Ｌは特に除去する必要はない。透明導電膜除去工程が不要であるから、従来のリフトオフ法のように残存している透明導電膜を除去する方法と比較して、除去工程が不要であり、透明導電膜除去の際に大量のパーティクルが発生することに起因する不具合（例えば、パーティクルが付着してショートすること）等がない。 After forming the transparent conductive film L on the interlayer insulating film 13 as described above, the transparent conductive film L is removed by etching to remove the transparent conductive film on the side wall portion of the step of the partition portion D, so that the transparent conductive film L becomes the pixel electrode 14 and the terminal portion. A matrix substrate 10 having a predetermined pattern of 26 and 27 and having a contact area CA formed in the interlayer insulating film 13 is obtained. Further, the interlayer insulating film 13 is formed as a non-contact region NA in the TFT element 12, the source wiring 25, and the gate wiring 24 other than the contact area CA. The transparent conductive film L is also formed in the non-contact region NA and remains, but the stepped portion becomes a partition portion D and is electrically separated from the contact region CA. Therefore, it is not necessary to remove the transparent conductive film L in the non-contact area NA. Since the transparent conductive film removing step is unnecessary, the removing step is unnecessary as compared with the method of removing the remaining transparent conductive film as in the conventional lift-off method. There is no problem (for example, short-circuiting due to adhesion of particles) caused by the generation of particles.
　以下、本発明の第２実施例について説明する。図１０（ａ）～（ｃ）、図１１（ｄ）、（ｅ）は本発明のマトリクス基板の製造方法の第２実施例を示し、（ａ）～（ｅ）は絶縁膜形成工程の各工程の断面図である。尚、第２実施例においてＴＦＴ形成工程は第１実施例と共通であるので、説明を省略する。第２実施例の絶縁膜形成工程は、先ず図１０（ａ）に示すように、層間絶縁膜１３ａの表面に、フォトレジストを塗布しレジスト膜を形成し、該レジスト膜に対し第３のフォトマスクとして多階調マスク（特に図示せず）を用いて、露光と現像を行う。レジスト４０は、多段レジスト膜として形成される。レジスト４０は、コンタクトホール１５、１６、１７を形成する部分が除去され、コンタクト領域ＣＡのレジスト４０が厚膜部４２となり、非コンタクト領域のレジスト４０が薄膜部４１となり、厚膜部４２の区画部Ｄのレジスト膜が上方に凸部となるレジストピラー部５３として形成されている。 Hereinafter, a second embodiment of the present invention will be described. FIGS. 10 (a) to 10 (c), 11 (d) and 11 (e) show a second embodiment of the method for manufacturing a matrix substrate of the present invention, and FIGS. It is sectional drawing of a process. In the second embodiment, the TFT forming process is the same as that in the first embodiment, and the description thereof is omitted. In the insulating film forming step of the second embodiment, as shown in FIG. 10A, first, a photoresist is applied to the surface of the interlayer insulating film 13a to form a resist film, and a third photo is applied to the resist film. Exposure and development are performed using a multi-tone mask (not shown) as a mask. The resist 40 is formed as a multistage resist film. In the resist 40, portions where the contact holes 15, 16, and 17 are formed are removed, the resist 40 in the contact area CA becomes the thick film part 42, and the resist 40 in the non-contact area becomes the thin film part 41, and the thick film part 42 is partitioned. The resist film of the portion D is formed as a resist pillar portion 53 that is a convex portion upward.
　次に同図（ｂ）に示すように、層間絶縁膜１３ａのドライエッチングを行う。ドライエッチングは、コンタクトホールの部分１５ａ、１６ａ、１７ａを途中までエッチングする。 Next, as shown in FIG. 4B, the interlayer insulating film 13a is dry-etched. In the dry etching, the contact hole portions 15a, 16a, and 17a are etched halfway.
　次に同図（ｃ）に示すように、レジスト４０を酸素プラズマ等を用いてアッシングする。アッシングは、レジスト４０の薄膜部４１が除去されるまで行う。層間絶縁膜１３ａの上のレジスト４０は、厚膜部４２とレジストピラー部５３が残存する。 Next, as shown in FIG. 5C, the resist 40 is ashed using oxygen plasma or the like. Ashing is performed until the thin film portion 41 of the resist 40 is removed. The thick film portion 42 and the resist pillar portion 53 remain in the resist 40 on the interlayer insulating film 13a.
　次に図１１（ｄ）に示すように、層間絶縁膜１３ａのドライエッチングを行う。層間絶縁膜１３ａは、ドライエッチングにより、コンタクトホールの部分１５ａ、１６ａ、１７ａが引き続きエッチングされると共に、薄膜部４１が除去された部分（非コンタクト領域ＮＡ）がエッチングされる。コンタクトホール１５、１６、１７が所定の深さに形成され、非コンタクト領域ＮＡが凹部として形成される。 Next, as shown in FIG. 11D, the interlayer insulating film 13a is dry-etched. In the interlayer insulating film 13a, the contact hole portions 15a, 16a, and 17a are continuously etched by dry etching, and the portion from which the thin film portion 41 is removed (non-contact region NA) is etched. Contact holes 15, 16, and 17 are formed to a predetermined depth, and non-contact region NA is formed as a recess.
　次に同図（ｅ）に示すように、レジストを酸素プラズマ等でアッシングして、レジストピラー部５３を残存させ厚膜部４２を除去する。区画部Ｄが段差として形成され、コンタクトホール１５、１６、１７が所定の位置に形成され、コンタクト領域ＣＡの周縁にレジストピラー部５３が残存した状態の層間絶縁膜１３が得られる。非コンタクト領域ＮＡのエッチングの深さ、すなわち区画部Ｄの段差の高さは、０．３～０．４μｍ程度に形成される。残存したレジストピラー部５３の高さは、１．２～１．５μｍ程度に形成されている。また残存したレジストピラー部５３の幅は、０．３～０．５μｍ程度に形成されている。 Next, as shown in FIG. 5E, the resist is ashed with oxygen plasma or the like to leave the resist pillar portion 53 and remove the thick film portion. The partition portion D is formed as a step, the contact holes 15, 16, and 17 are formed at predetermined positions, and the interlayer insulating film 13 with the resist pillar portion 53 remaining at the periphery of the contact region CA is obtained. The etching depth of the non-contact area NA, that is, the height of the step of the partition portion D is formed to be about 0.3 to 0.4 μm. The remaining resist pillar portion 53 has a height of about 1.2 to 1.5 μm. The remaining resist pillar portion 53 is formed to have a width of about 0.3 to 0.5 μm.
　図１１（ｆ）、図１２（ｇ）は導電膜形成工程を示し、（ｆ）、（ｇ）は各工程の断面図である。図１１（ｆ）に示すように、区画部Ｄに段差とレジストピラー部５３が形成された層間絶縁膜１３の表面及びレジストピラー部５３の表面に透明導電膜Ｌをスパッタ法で形成する。透明導電膜Ｌは、区画部Ｄの側壁部及びレジストピラー部５３の側面の厚みが、平面部の厚みよりも薄く形成される。例えば透明導電膜Ｌの厚みは、側壁部で０．０５～０．１μｍ、平面部で０．１～０．２μｍ程度に形成することができる。 11 (f) and 12 (g) show a conductive film forming process, and (f) and (g) are cross-sectional views of each process. As shown in FIG. 11 (f), a transparent conductive film L is formed by sputtering on the surface of the interlayer insulating film 13 where the step and the resist pillar portion 53 are formed in the partition portion D and on the surface of the resist pillar portion 53. The transparent conductive film L is formed such that the side wall portion of the partition portion D and the side surface of the resist pillar portion 53 are thinner than the planar portion. For example, the transparent conductive film L can be formed to have a thickness of about 0.05 to 0.1 μm at the side wall and about 0.1 to 0.2 μm at the flat surface.
　次に図１２（ｇ）に示すように、リフトオフ法によりレジストピラー部５３を除去すると、表面の透明導電膜Ｌもレジストピラー部５３と一緒に除去される。区画部Ｄのレジストピラー部５３の透明導電膜Ｌが除去されると、透明導電膜Ｌのコンタクト領域ＣＡと非コンタクト領域ＮＡが、電気的に分断される。リフトオフ法によるレジストピラー部５３の除去は、公知のウエット処理等を用いることができる。このように透明導電膜Ｌが、画素電極１４、端子部２６、２７等の所定の形状に形成されたマトリクス基板１０が得られる。第２実施例の製造方法により得られるマトリクス基板１０は、区画部Ｄの側壁部は透明導電膜Ｌが残存している状態でもよいが、更に反応性イオンエッチング等により、区画部Ｄの側壁の透明導電膜Ｌを除去してもよい。 Next, as shown in FIG. 12G, when the resist pillar portion 53 is removed by the lift-off method, the transparent conductive film L on the surface is also removed together with the resist pillar portion 53. When the transparent conductive film L of the resist pillar portion 53 of the partition portion D is removed, the contact area CA and the non-contact area NA of the transparent conductive film L are electrically separated. The removal of the resist pillar portion 53 by the lift-off method can use a known wet process or the like. Thus, the matrix substrate 10 in which the transparent conductive film L is formed in a predetermined shape such as the pixel electrode 14 and the terminal portions 26 and 27 is obtained. In the matrix substrate 10 obtained by the manufacturing method of the second embodiment, the transparent conductive film L may remain on the side wall portion of the partition portion D, but the side wall portion of the partition portion D may be further removed by reactive ion etching or the like. The transparent conductive film L may be removed.
　第２実施例は、レジストピラー部５３の透明導電膜をリフトオフで除去するが、他の部分には透明導電膜Ｌが残っていて、所謂局所リフトオフ法を用いるものである。この方法は、非コンタクト領域の透明導電膜を全部除去する所謂全面リフトオフ法を用いる従来の方法と比較して、以下の利点がある。全面リフトオフ法では、画素領域以外の透明導電膜が全てウエット処理槽に持ち込まれる。これに対し局所リフトオフ法ではレジストピラー部５３の部分の透明導電膜がウエット処理槽に持ち込まれるのにすぎない。局所リフトオフ法ではウエット処理槽に持ち込まれる透明導電膜の量は、全面リフトオフ法の千分の一以下であり、著しく少ない。このため、ウエット処理槽への負荷が著しく軽減される。例えば、ウエット処理槽の負荷が小さくなると、循環フィルタ等の詰まりが少なくなって、交換頻度が伸びることになる。また局所リフトオフ法は、透明導電膜の処理量が少なくて済むことから、ウエット処理時間が短時間で済むことや、ウエット処理温度が低くても良い。また局所リフトオフ法は、ウエット処理の薬液の濃度が低くても良い等の利点がある。 In the second embodiment, the transparent conductive film of the resist pillar portion 53 is removed by lift-off, but the transparent conductive film L remains in other portions, and a so-called local lift-off method is used. This method has the following advantages over the conventional method using the so-called full surface lift-off method in which the transparent conductive film in the non-contact region is completely removed. In the whole surface lift-off method, all the transparent conductive film other than the pixel region is brought into the wet processing tank. On the other hand, in the local lift-off method, the transparent conductive film of the resist pillar portion 53 is merely brought into the wet processing tank. In the local lift-off method, the amount of the transparent conductive film brought into the wet treatment tank is 1 / 1,000 or less that of the whole surface lift-off method, and is extremely small. For this reason, the load on the wet treatment tank is significantly reduced. For example, when the load on the wet treatment tank is reduced, clogging of the circulation filter and the like is reduced, and the replacement frequency is increased. In the local lift-off method, since the processing amount of the transparent conductive film is small, the wet processing time may be short and the wet processing temperature may be low. Further, the local lift-off method has an advantage that the concentration of the chemical solution in the wet treatment may be low.
　この実施例では、区画部Ｄの段差のところにレジストピラー部５３を設け、段差によってコンタクト領域ＣＡと非コンタクト領域ＮＡが区画されている。更にこの実施例では、コンタクト領域ＣＡと非コンタクト領域ＮＡは同一平面上にはなく、各領域が異なる高さの面として形成されている。従来のようにコンタクト領域と非コンタクト領域とが同一平面にあって、その境界が溝により区画されているマトリクス基板の場合、パーティクルが溝の上に付着した場合などに、コンタクト領域と非コンタクト領域がパーティクルによってショートし易い。これに対し、両領域の区画部Ｄに段差が形成されていると、パーティクルが段差に付着して両領域の間でショートする虞が小さくなる。 In this embodiment, a resist pillar portion 53 is provided at the step of the partition portion D, and the contact area CA and the non-contact region NA are partitioned by the step. Further, in this embodiment, the contact area CA and the non-contact area NA are not on the same plane, and each area is formed as a surface having a different height. In the case of a matrix substrate in which the contact region and the non-contact region are on the same plane as in the prior art and the boundary is defined by a groove, the contact region and the non-contact region when particles adhere to the groove, etc. Is easily shorted by particles. On the other hand, if a step is formed in the partition portion D of both regions, the possibility that particles adhere to the step and short-circuit between both regions is reduced.
　図１３（ａ）～（ｄ）は第２実施例の変形例を示すものであり、各工程の段差部分を拡大した断面図である。第２実施例のマトリクス基板は、区画部Ｄの側壁表面に透明導電膜Ｌが残っているものであるが、この変形例では区画部Ｄの側壁の透明導電膜Ｌを除去したマトリクス基板１０が得られる。以下、第２実施例の変形例のマトリクス基板の製造方法について説明する。 FIGS. 13 (a) to 13 (d) show modified examples of the second embodiment and are enlarged cross-sectional views of the step portions of the respective steps. In the matrix substrate of the second embodiment, the transparent conductive film L remains on the surface of the side wall of the partition portion D. In this modification, the matrix substrate 10 from which the transparent conductive film L on the side wall of the partition portion D is removed is provided. can get. Hereinafter, a method for manufacturing a matrix substrate according to a modification of the second embodiment will be described.
　先ず図１３（ａ）に示すように、第２実施例において層間絶縁膜１３の表面にレジストピラー部５３を形成した状態から、レジストピラー部５３をリフローさせる。同図（ｂ）に示すように、レジストピラー部５３のリフローは、段差の側壁部がリフローしたレジスト５４で覆われるようにする。次に、同図（ｃ）に示すように透明導電膜Ｌを層間絶縁膜１３の表面全面に形成する。次に、同図（ｄ）に示すようにリフローしたレジスト５４を除去すると、リフトオフ法によりリフローしたレジスト５４とその表面の透明導電膜Ｌが除去される。区画部Ｄの側壁の透明導電膜Ｌも除去されるので、より確実にコンタクト領域ＣＡと非コンタクト領域ＮＡを電気的に分離することができる。レジストのリフローは、リフロー溶剤の蒸気に暴露する方法、リフロー溶剤と加熱による方法等の公知のリフロー方法を用いることができる。 First, as shown in FIG. 13A, the resist pillar portion 53 is reflowed from the state in which the resist pillar portion 53 is formed on the surface of the interlayer insulating film 13 in the second embodiment. As shown in FIG. 2B, the resist pillar portion 53 is reflowed so that the side wall portion of the step is covered with the reflowed resist 54. Next, a transparent conductive film L is formed on the entire surface of the interlayer insulating film 13 as shown in FIG. Next, when the reflowed resist 54 is removed as shown in FIG. 4D, the reflowed resist 54 and the transparent conductive film L on the surface thereof are removed by the lift-off method. Since the transparent conductive film L on the side wall of the partition portion D is also removed, the contact area CA and the non-contact area NA can be electrically separated more reliably. The resist can be reflowed by a known reflow method such as a method of exposing to a reflow solvent vapor or a method of reflow solvent and heating.
　以下、第３実施例について説明する。図１４（ｄ）～（ｆ）、図１５（ｇ）は本発明のマトリクス基板の製造方法の第３実施例の絶縁膜形成工程を示し、（ｄ）～（ｇ）は各工程の断面図である。尚、第３実施例において、ＴＦＴ形成工程は第１実施例及び第２実施例と共通であるので、説明を省略する。また、第３実施例の絶縁膜形成工程の非コンタクト領域をエッチングにより凹部とするところまでは、第１実施例の図７（ａ）～（ｃ）と共通の工程であるので、説明を省略する。 Hereinafter, the third embodiment will be described. FIGS. 14 (d) to 14 (f) and FIG. 15 (g) show the insulating film forming steps of the third embodiment of the method for manufacturing a matrix substrate of the present invention, and FIGS. 14 (d) to (g) are sectional views of the respective steps. It is. In the third embodiment, the TFT forming process is the same as that in the first and second embodiments, and the description thereof is omitted. Further, the steps up to the step of forming the recess in the non-contact region in the insulating film forming step of the third embodiment by etching are the same steps as in FIGS. 7A to 7C of the first embodiment, and thus description thereof is omitted. To do.
　第３実施例の絶縁膜形成工程は、第１実施例と同様に図１４（ｄ）に示すように、層間絶縁膜１３ａは、コンタクトホールの部分１５ａ、１６ａ、１７ａと、非コンタクト領域ＮＡの部分がエッチングされる。この状態では、レジスト４０の厚膜部４２が残存している。 In the insulating film forming process of the third embodiment, as shown in FIG. 14 (d), the interlayer insulating film 13a includes contact hole portions 15a, 16a, 17a and non-contact regions NA as in the first embodiment. The part is etched. In this state, the thick film portion 42 of the resist 40 remains.
　次に同図（ｅ）に示すように、残存しているレジスト（厚膜部４２）をリフローして、リフローしたレジスト５４が区画部Ｄの側壁の表面、コンタクトホール１５、１６、１７の側壁及び底面を覆うようにする。リフローしたレジスト５４は、コンタクト領域ＣＡの表面と区画部Ｄの側壁を覆っているが、非コンタクト領域ＮＡの表面は覆わないようになっている。 Next, as shown in FIG. 5E, the remaining resist (thick film portion 42) is reflowed, and the reflowed resist 54 is the surface of the side wall of the partition portion D and the side walls of the contact holes 15, 16, and 17. And cover the bottom. The reflowed resist 54 covers the surface of the contact area CA and the side wall of the partition portion D, but does not cover the surface of the non-contact area NA.
　図１６（ａ）、（ｂ）は、それぞれ、図１４（ｅ）、（ｆ）の区画部の側壁の拡大図である。次に図１４（ｅ）、図１６（ａ）に示すように、リフローしたレジスト５４が設けられた層間絶縁膜１３ａのエッチングを行う。図１４（ｆ）、図１６（ｂ）に示すように、非コンタクト領域ＮＡが深さ方向にエッチングされ凹所として形成される。更に、エッチングにより層間絶縁膜１３ａの凹所として形成された非コンタクト領域の側壁も、壁面内方にエッチングが進行して、隅の部分がエッチングされた状態となりアンダーカット部１３ｂが形成される。この場合のエッチングは、等方性エッチングを用いることが好ましい。例えば等方性エッチングとしては、プラズマエッチングを用いることができる。等方性エッチングを用いてアンダーカット部１３ｂを形成することで、側面方向へのエッチングを確実に進行させることができる。その結果、アンダーカット部１３ｂを、導電膜が形成され難い形状に確実に形成することができる。 FIGS. 16 (a) and 16 (b) are enlarged views of the side walls of the partition portions of FIGS. 14 (e) and 14 (f), respectively. Next, as shown in FIGS. 14E and 16A, the interlayer insulating film 13a provided with the reflowed resist 54 is etched. As shown in FIGS. 14 (f) and 16 (b), the non-contact region NA is etched in the depth direction to form a recess. Further, the side wall of the non-contact region formed as a recess of the interlayer insulating film 13a by etching also proceeds to the inside of the wall surface, and the corner portion is etched to form the undercut portion 13b. In this case, it is preferable to use isotropic etching. For example, plasma etching can be used as isotropic etching. By forming the undercut portion 13b using isotropic etching, the etching in the side surface direction can surely proceed. As a result, the undercut portion 13b can be reliably formed in a shape in which the conductive film is difficult to be formed.
　次にリフローしたレジスト５４を酸素プラズマでアッシングして、レジスト５４を除去する。図１５（ｇ）に示すように、層間絶縁膜１３に、コンタクトホール１５、１６、１７、区画部Ｄの段差及びアンダーカット部１３ｂが形成される Next, the reflowed resist 54 is ashed with oxygen plasma to remove the resist 54. As shown in FIG. 15G, contact holes 15, 16, 17, steps in the partition part D and undercut part 13 b are formed in the interlayer insulating film 13.
　図１５（ｈ）は導電膜形成工程を示す断面図であり、図１６（ｃ）は、図１５（ｈ）の段差の拡大図である。図１５（ｈ）、図１６（ｃ）に示すように、導電膜形成工程では、上記のアンダーカット部１３ｂが形成された層間絶縁膜１３の表面にスパッタ法により透明導電膜Ｌを形成する。透明導電膜Ｌを形成するＩＴＯ原子は、基板にほぼ垂直に入射するので、アンダーカット部１３ｂの底は陰になり透明導電膜Ｌが形成されない。アンダーカット部１３ｂにより、コンタクト領域ＣＡと非コンタクト領域ＮＡの透明導電膜Ｌが電気的に分断される。コンタクト領域ＣＡでは画素電極１４及び端子部２６、２７が所定の形状に形成される。このようにして透明導電膜Ｌの画素電極１４、端子部２６、２７が所定の形状に形成されたマトリクス基板１０が得られる。 FIG. 15 (h) is a cross-sectional view showing the conductive film forming step, and FIG. 16 (c) is an enlarged view of the step in FIG. 15 (h). As shown in FIGS. 15 (h) and 16 (c), in the conductive film forming step, a transparent conductive film L is formed by sputtering on the surface of the interlayer insulating film 13 on which the undercut portion 13b is formed. Since the ITO atoms forming the transparent conductive film L are incident on the substrate substantially perpendicularly, the bottom of the undercut portion 13b is shaded and the transparent conductive film L is not formed. The transparent conductive film L in the contact area CA and the non-contact area NA is electrically separated by the undercut portion 13b. In the contact area CA, the pixel electrode 14 and the terminal portions 26 and 27 are formed in a predetermined shape. Thus, the matrix substrate 10 in which the pixel electrode 14 and the terminal portions 26 and 27 of the transparent conductive film L are formed in a predetermined shape is obtained.
　上記実施例１～３では、マトリクス基板１０は、区画部Ｄに段差を１つだけ設けた例を示したが、段差は複数設けても良い。また上記第３実施例に示すようにアンダーカット部を設ける際、マトリクス基板の区画部に段差を複数設けた場合、アンダーカット部を、どの段差のところに形成しても良い。 In the first to third embodiments, the matrix substrate 10 has been described with an example in which only one step is provided in the partition portion D. However, a plurality of steps may be provided. Further, when providing the undercut portion as shown in the third embodiment, when a plurality of steps are provided in the partition portion of the matrix substrate, the undercut portion may be formed at any step.
　上記実施例１～３は、導電膜形成工程では非コンタクト領域の透明導電膜を除去せずに残した状態としている。そのため透明導電膜の非コンタクト領域を除去するためのレジスト塗布とフォトマスクを使用した露光を行なうフォトリソグラフィの工程が不要である。透明導電膜を形成するのにフォトリソグラフィの工程が不要であるから、マトリクス基板の生産性に優れる。 In Examples 1 to 3, the transparent conductive film in the non-contact region is left without being removed in the conductive film forming step. Therefore, there is no need for a photolithography process in which resist coating for removing the non-contact region of the transparent conductive film and exposure using a photomask are performed. Since a photolithography process is not required to form the transparent conductive film, the productivity of the matrix substrate is excellent.
　また実施例１～３に示すように、スイッチング素子としてＴＦＴを用いたアクティブマトリクス基板の製造に際し、マトリクス回路の形成と、絶縁膜の形成と、導電膜の形成とからなる製造工程を３枚のフォトマスクを使用する３枚マスクプロセスで製造することが可能である。この場合、上記実施例に示すように、透明導電膜を所定のパターンに確実に形成することができ、従来のアクティブマトリクス基板の製造における３枚マスクプロセスの欠点を解消できるものである。 Further, as shown in Examples 1 to 3, when manufacturing an active matrix substrate using a TFT as a switching element, a manufacturing process including formation of a matrix circuit, formation of an insulating film, and formation of a conductive film is performed on three sheets. It is possible to manufacture by a three-mask process using a photomask. In this case, as shown in the above embodiment, the transparent conductive film can be reliably formed in a predetermined pattern, and the disadvantages of the three-mask process in the production of the conventional active matrix substrate can be eliminated.
　本発明の表示装置は、上記のマトリクス基板を備えるものである。以下、本発明の表示装置について説明する。図１７は本発明の表示装置の一例である液晶表示装置の概略構成を示す分解斜視図であり、図１８は図１７の液晶表示装置の概略構成を示す断面図である。図１７及び図１８に示すように液晶表示装置１は、矩形をなす液晶表示パネル２と外部光源であるバックライト装置３とを備え、これらがベゼル４などにより一体的に保持されるように形成されている。 The display device of the present invention includes the matrix substrate described above. The display device of the present invention will be described below. 17 is an exploded perspective view showing a schematic configuration of a liquid crystal display device which is an example of the display device of the present invention, and FIG. 18 is a cross-sectional view showing a schematic configuration of the liquid crystal display device of FIG. As shown in FIGS. 17 and 18, the liquid crystal display device 1 includes a rectangular liquid crystal display panel 2 and a backlight device 3 as an external light source, which are formed so as to be integrally held by a bezel 4 or the like. Has been.
　図１７及び図１８に示すバックライト装置３は、所謂直下型のバックライト装置であって、液晶表示パネル２のパネル面（表示面）の背面直下に、当該パネル面に沿って複数の冷陰極管３０１が光源として配置されている。バックライト装置３は、上面側が開口した矩形の略箱型をなす金属製のベース３０２と、該ベース３０２の開口部を覆うように取り付けられる光学部材３０３と、該光学部材３０３をベース３０２に保持するためのフレーム３０４と、ベース３０２内に収容される冷陰極管３０１と該冷陰極管３０１の両端を保持するホルダ３０５とこれらを一括で覆うランプホルダ３０６とクリップ３０７等を備えている。上記光学部材３０３は、拡散板、拡散シート、レンズシート等が積層されている。 The backlight device 3 shown in FIG. 17 and FIG. 18 is a so-called direct-type backlight device, and a plurality of cold cathodes are provided directly below the back surface of the panel surface (display surface) of the liquid crystal display panel 2 along the panel surface. A tube 301 is arranged as a light source. The backlight device 3 includes a rectangular metal base 302 having an open top surface, an optical member 303 attached to cover the opening of the base 302, and the optical member 303 held by the base 302. And a cold cathode tube 301 accommodated in the base 302, a holder 305 for holding both ends of the cold cathode tube 301, a lamp holder 306 and a clip 307 that collectively cover these. The optical member 303 is formed by laminating a diffusion plate, a diffusion sheet, a lens sheet, and the like.
　図１９は図１７の液晶表示装置の液晶表示パネルの一部を示す断面図である。図１９に示すように、液晶表示パネル２は、上記の本発明のマトリクス基板１０と対向基板７０との一対の基板が、ギャップを開けた状態で貼り合わせられると共に、両基板間に液晶が封入され液晶層８０が設けられている。マトリクス基板１０はアクティブマトリクス基板であり透明基板１１の液晶層８０側に半導体素子としてＴＦＴ１２と該ＴＦＴに接続された画素電極１４とを備えている。尚、マトリクス基板１０の画素電極１４の液晶側には配向膜３０等が設けられている。配向膜３０は、例えばポリイミドのラビング膜等が用いられる。マトリクス基板１０の液晶層８０の反対側には、偏光板３１が配設されている。偏光板３１は、例えば透明フィルムにヨウ素や染料を染み込ませたものを一方向に延伸した延伸フィルムなどを用いることができる。 FIG. 19 is a cross-sectional view showing a part of the liquid crystal display panel of the liquid crystal display device of FIG. As shown in FIG. 19, in the liquid crystal display panel 2, the pair of substrates of the matrix substrate 10 and the counter substrate 70 of the present invention are bonded together with a gap therebetween, and liquid crystal is sealed between the substrates. A liquid crystal layer 80 is provided. The matrix substrate 10 is an active matrix substrate, and includes a TFT 12 as a semiconductor element and a pixel electrode 14 connected to the TFT on the liquid crystal layer 80 side of the transparent substrate 11. An alignment film 30 and the like are provided on the liquid crystal side of the pixel electrode 14 of the matrix substrate 10. For example, a polyimide rubbing film or the like is used as the alignment film 30. A polarizing plate 31 is disposed on the opposite side of the liquid crystal layer 80 of the matrix substrate 10. As the polarizing plate 31, for example, a stretched film obtained by stretching a transparent film soaked with iodine or a dye in one direction can be used.
　対向基板７０は、ガラス板等の透明基板７１の液晶層８０側に、Ｒ（赤）、Ｇ（緑）、青（Ｂ）の各色光を選択的に透過可能な着色部等を備えたカラーフィルタ７２と、対向電極７３と、配向膜７４等を備えているカラーフィルタ基板である。尚、対向基板７０の液晶層８０の反対側には、偏光板７５が配設されている。 The counter substrate 70 is a color having a colored portion or the like that can selectively transmit R (red), G (green), and blue (B) light on the liquid crystal layer 80 side of a transparent substrate 71 such as a glass plate. The color filter substrate includes a filter 72, a counter electrode 73, an alignment film 74, and the like. A polarizing plate 75 is disposed on the opposite side of the counter substrate 70 from the liquid crystal layer 80.
　カラーフィルタ７２は、着色部（７２Ｒ、７２Ｇ、７２Ｂ）の境界に配されたブラックマトリクス７２ｂを備え、該ブラックマトリクス７２ｂはパネルの非画素部（ＴＦＴ等の形成された領域）を覆う位置に設けられている。対向電極７３は、ＩＴＯ等の透明導電膜からなり、対向基板７０の液晶層８０側の全面に形成されている。配向膜７４、偏光板７５等はマトリクス基板１０と同様のものを用いることができる。 The color filter 72 includes a black matrix 72b arranged at the boundary of the colored portions (72R, 72G, 72B), and the black matrix 72b is provided at a position covering a non-pixel portion (region where TFTs are formed) of the panel. It has been. The counter electrode 73 is made of a transparent conductive film such as ITO, and is formed on the entire surface of the counter substrate 70 on the liquid crystal layer 80 side. As the alignment film 74, the polarizing plate 75, and the like, the same materials as those of the matrix substrate 10 can be used.
　液晶表示パネル２は、上記対向基板７０とマトリクス基板１０をそれぞれ製造し、それぞれ配向膜の面を対向させてシール材(図示せず)を介して貼り合わせ、両基板の間に液晶を注入して液晶層８０を形成し、駆動回路等を接続させることで製造することができる。更に液晶表示パネル２に、上記したバックライト装置３や、各種の制御回路や基板等を装着することで、液晶表示装置１が得られる。上記制御回路や基板は、例えば液晶表示パネル２やマトリクス基板１０を制御する制御回路、駆動回路、電源回路等の基板や、バックライト装置３を制御する回路等である。 In the liquid crystal display panel 2, the counter substrate 70 and the matrix substrate 10 are manufactured, the surfaces of the alignment films are opposed to each other, and are bonded via a sealing material (not shown), and liquid crystal is injected between the substrates. Then, the liquid crystal layer 80 is formed, and a drive circuit or the like can be connected. Furthermore, the liquid crystal display device 1 can be obtained by mounting the above-described backlight device 3 and various control circuits and substrates on the liquid crystal display panel 2. The control circuit and the substrate are, for example, a control circuit that controls the liquid crystal display panel 2 and the matrix substrate 10, a substrate such as a drive circuit and a power supply circuit, a circuit that controls the backlight device 3, and the like.
　本発明のマトリクス基板は、特に液晶表示素子、有機ＥＬ表示素子、プラズマ表示素子のような各種の表示素子に好適に用いることができる。本発明の表示装置は、大型テレビジョン等に好適に利用することができる。 The matrix substrate of the present invention can be suitably used particularly for various display elements such as liquid crystal display elements, organic EL display elements, and plasma display elements. The display device of the present invention can be suitably used for large televisions and the like.

Claims (21)

  1. 　基板と、前記基板上に複数のスイッチング素子が設けられてなるマトリクス回路と、前記マトリクス回路の表面に形成されている絶縁膜と、前記絶縁膜の表面に形成されている導電膜と、前記導電膜と前記マトリクス回路を電気的に接続するために形成されているコンタクトホールとを備えるマトリクス基板において、
    　前記絶縁膜の表面が、前記導電膜が前記マトリクス回路と電気的に接続されるコンタクト領域と、前記導電膜が前記マトリクス回路と電気的に接続されない非コンタクト領域とからなり、前記コンタクト領域と前記非コンタクト領域は区画部によって分割されており、
    　前記区画部が前記コンタクト領域と前記非コンタクト領域の高低差となる段差として構成され、前記区画部の段差を利用して導電膜のコンタクト領域と非コンタクト領域が電気的に分断されていることを特徴とするマトリクス基板。     A substrate; a matrix circuit having a plurality of switching elements provided on the substrate; an insulating film formed on a surface of the matrix circuit; a conductive film formed on the surface of the insulating film; In a matrix substrate comprising a film and a contact hole formed to electrically connect the matrix circuit,
    The surface of the insulating film includes a contact region where the conductive film is electrically connected to the matrix circuit, and a non-contact region where the conductive film is not electrically connected to the matrix circuit, and the contact region and the The non-contact area is divided by the partition,
    The partition is configured as a step difference in height between the contact region and the non-contact region, and the contact region and the non-contact region of the conductive film are electrically separated using the step of the partition. A characteristic matrix substrate.
  2. 　前記絶縁膜の表面の高さが、前記コンタクト領域と前記非コンタクト領域とで異なるように形成されていることを特徴とする請求項１記載のマトリクス基板。 2. The matrix substrate according to claim 1, wherein the surface height of the insulating film is different between the contact region and the non-contact region.
  3. 　前記絶縁膜のコンタクト領域の表面の高さが、前記絶縁膜の非コンタクト領域の高さよりも高く形成されていることを特徴とする請求項１又は２記載のマトリクス基板。 3. The matrix substrate according to claim 1, wherein the surface height of the contact region of the insulating film is formed higher than the height of the non-contact region of the insulating film.
  4. 　前記絶縁膜の非コンタクト領域の表面が平坦に形成されていることを特徴とする請求項１～３のいずれか１項に記載のマトリクス基板。 The matrix substrate according to any one of claims 1 to 3, wherein a surface of the non-contact region of the insulating film is formed flat.
  5. 　前記区画部の段差の側壁部分に、導電膜が形成されていないことを特徴とする請求項１～４のいずれか１項に記載のマトリクス基板。 The matrix substrate according to any one of claims 1 to 4, wherein a conductive film is not formed on a side wall portion of the step of the partition portion.
  6. 　前記スイッチング素子が、薄膜トランジスタであることを特徴とする請求項１～５のいずれか１項に記載のマトリクス基板。 The matrix substrate according to any one of claims 1 to 5, wherein the switching element is a thin film transistor.
  7. 　前記導電膜のコンタクト領域が、画素電極部であることを特徴とする請求項１～６のいずれか１項に記載のマトリクス基板。 7. The matrix substrate according to claim 1, wherein the contact region of the conductive film is a pixel electrode portion.
  8. 　前記導電膜のコンタクト領域が、端子部であることを特徴とする請求項１～７のいずれか１項に記載のマトリクス基板。 The matrix substrate according to any one of claims 1 to 7, wherein the contact region of the conductive film is a terminal portion.
  9. 　請求項１～８のいずれか１項に記載のマトリクス基板を備えることを特徴とする表示装置。 A display device comprising the matrix substrate according to any one of claims 1 to 8.
  10. 　基板と、前記基板上に複数のスイッチング素子が設けられてなるマトリクス回路と、前記マトリクス回路の表面に形成されている絶縁膜と、前記絶縁膜の表面に形成されている導電膜と、前記導電膜と前記マトリクス回路を電気的に接続するために形成されているコンタクトホールとを備えるマトリクス基板の製造方法において、
    　前記絶縁膜を形成する際に、前記導電膜が前記マトリクス回路と電気的に接続されるコンタクト領域と、前記導電膜が前記マトリクス回路と電気的に接続されない非コンタクト領域とを区画する区画部が段差となるように前記絶縁膜を形成すると共に、前記絶縁膜にコンタクトホールを設ける絶縁膜形成工程と、
    　前記導電膜を形成する際に、前記導電膜のコンタクト領域と非コンタクト領域が前記区画部の段差を利用して電気的に分断されるように導電膜を形成する導電膜形成工程とを備えることを特徴とするマトリクス基板の製造方法。     A substrate; a matrix circuit having a plurality of switching elements provided on the substrate; an insulating film formed on a surface of the matrix circuit; a conductive film formed on the surface of the insulating film; In a method of manufacturing a matrix substrate comprising a film and a contact hole formed to electrically connect the matrix circuit,
    When forming the insulating film, there is a partition section that partitions a contact region in which the conductive film is electrically connected to the matrix circuit and a non-contact region in which the conductive film is not electrically connected to the matrix circuit. Forming the insulating film so as to be a step, and forming an insulating film in which a contact hole is provided in the insulating film;
    A conductive film forming step of forming the conductive film so that the contact region and the non-contact region of the conductive film are electrically separated using the step of the partition when forming the conductive film. A method of manufacturing a matrix substrate characterized by the above.
  11. 　前記絶縁膜形成工程が、前記マトリクス回路の上に所定の厚さに絶縁膜を成膜した後、該絶縁膜の上にレジスト膜を形成し、該レジスト膜に対し多階調マスクを用いて露光と現像を行い、厚さが段階的に異なる多段レジスト膜を形成し、該多段レジスト膜を利用して前記絶縁膜のエッチングを行い、前記段差とコンタクトホールが形成された絶縁膜を得ることを特徴とする請求項１０記載のマトリクス基板の製造方法。 The insulating film forming step forms an insulating film with a predetermined thickness on the matrix circuit, forms a resist film on the insulating film, and uses a multi-tone mask for the resist film. Exposure and development are performed to form a multi-stage resist film having different thicknesses, and the insulating film is etched using the multi-stage resist film to obtain an insulating film in which the step and the contact hole are formed. The method of manufacturing a matrix substrate according to claim 10.
  12. 　前記導電膜形成工程が、絶縁膜の上に導電膜を形成した後、段差の側壁部の導電膜をエッチングにより除去することを特徴とする請求項１０又は１１に記載のマトリクス基板の製造方法。 12. The method for manufacturing a matrix substrate according to claim 10, wherein the conductive film forming step forms a conductive film on the insulating film, and then removes the conductive film on the side wall of the step by etching.
  13. 　前記段差の側壁部の導電膜の除去に、プラズマエッチング法を用いるものであることを特徴とする請求項１２に記載のマトリクス基板の製造方法。 13. The method of manufacturing a matrix substrate according to claim 12, wherein a plasma etching method is used to remove the conductive film on the side wall of the step.
  14. 　前記導電膜形成工程が、絶縁膜の上にスパッタリング法で導電膜を形成し、側壁部の導電膜を平面部の導電膜よりも薄く形成することを特徴とする請求項１０～１３のいずれか１項に記載のマトリクス基板の製造方法。 The conductive film forming step includes forming a conductive film on the insulating film by a sputtering method, and forming the conductive film on the side wall portion thinner than the conductive film on the planar portion. 2. A method for manufacturing a matrix substrate according to item 1.
  15. 　前記絶縁膜形成工程が、前記絶縁膜の前記区画部のレジスト膜が凸部となるように残存させたレジストピラー部を設けるものであり、
    　前記導電膜形成工程が、前記レジストピラー部を設けた絶縁膜の上に導電膜を形成した後、リフトオフ法により前記レジストピラー部とその上の導電膜を除去することを特徴とする請求項１０～１４のいずれか１項に記載のマトリクス基板の製造方法。     The insulating film forming step is to provide a resist pillar portion left so that the resist film of the partition portion of the insulating film becomes a convex portion;
    11. The conductive film forming step of forming a conductive film on an insulating film provided with the resist pillar portion, and then removing the resist pillar portion and the conductive film thereon by a lift-off method. 15. The method for manufacturing a matrix substrate according to any one of items 14 to 14.
  16. 　前記絶縁膜形成工程で、前記レジストピラー部を形成した後、レジストピラー部をリフローさせて区画部の段差の側壁を覆うレジスト側壁部を設け、前記導電膜形成工程で、リフトオフ法によりレジストピラー部とレジスト側壁部とその上の導電膜を除去することを特徴とする請求項１５記載のマトリクス基板の製造方法。 After forming the resist pillar portion in the insulating film forming step, a resist sidewall portion is provided to reflow the resist pillar portion to cover the side wall of the stepped portion of the partition portion. In the conductive film forming step, the resist pillar portion is formed by a lift-off method. 16. The method of manufacturing a matrix substrate according to claim 15, wherein the resist side wall portion and the conductive film thereon are removed.
  17. 　前記絶縁膜形成工程が、絶縁膜のコンタクト領域又は非コンタクト領域のいずれか一方のレジスト膜を除去した状態とした後、レジスト膜をリフローさせて、前記区画部の段差の側壁を覆うレジスト側壁部を形成した後、絶縁膜のエッチングを行い、前記段差のレジスト側壁部の下端から側面方向に凹所となるアンダーカット部を形成するものであり、
    　前記導電膜形成工程が、スパッタリング法により導電膜を形成し、前記アンダーカット部に導電膜が形成されないようにすることを特徴とする請求項１０記載のマトリクス基板の製造方法。     In the insulating film forming step, after the resist film in either the contact region or the non-contact region of the insulating film is removed, the resist film is reflowed to cover the side wall of the step of the partition portion. After that, the insulating film is etched to form an undercut portion that becomes a recess in the side surface direction from the lower end of the resist side wall portion of the step,
    11. The method of manufacturing a matrix substrate according to claim 10, wherein the conductive film forming step forms a conductive film by a sputtering method so that the conductive film is not formed in the undercut portion.
  18. 　前記絶縁膜形成工程のアンダーカット部の形成が、等方性エッチング法を用いるものであることを特徴とする請求項１７に記載のマトリクス基板の製造方法。 18. The method of manufacturing a matrix substrate according to claim 17, wherein the formation of the undercut portion in the insulating film forming step uses an isotropic etching method.
  19. 　前記絶縁膜形成工程で、前記アンダーカット部を形成した後、絶縁膜の上のレジスト膜を全て除去することを特徴とする請求項１７又は１８に記載のマトリクス基板の製造方法。 19. The method of manufacturing a matrix substrate according to claim 17, wherein after the undercut portion is formed in the insulating film forming step, the entire resist film on the insulating film is removed.
  20. 　前記導電膜形成工程で、フォトマスクを使用した露光を行わないことを特徴とする請求項１０～１９のいずれか１項に記載のマトリクス基板の製造方法。 20. The method of manufacturing a matrix substrate according to claim 10, wherein exposure using a photomask is not performed in the conductive film forming step.
  21. 　前記スイッチング素子が薄膜トランジスタであり、前記マトリクス回路の形成と、前記絶縁膜の形成と、前記導電膜の形成とを３枚のフォトマスクで行うことを特徴とする請求項１０～２０のいずれか１項に記載のマトリクス基板の製造方法。 The switching element is a thin film transistor, and the formation of the matrix circuit, the formation of the insulating film, and the formation of the conductive film are performed using three photomasks. The manufacturing method of the matrix board | substrate of description.
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